1 /*- 2 * Copyright (c) 2012 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _T4FW_INTERFACE_H_ 31 #define _T4FW_INTERFACE_H_ 32 33 /****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37 enum fw_retval { 38 FW_SUCCESS = 0, /* completed sucessfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_EINVAL = 22, /* invalid argument */ 49 FW_ENOSPC = 28, /* no space left on device */ 50 FW_ENOSYS = 38, /* functionality not implemented */ 51 FW_EPROTO = 71, /* protocol error */ 52 FW_EADDRINUSE = 98, /* address already in use */ 53 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 54 FW_ENETDOWN = 100, /* network is down */ 55 FW_ENETUNREACH = 101, /* network is unreachable */ 56 FW_ENOBUFS = 105, /* no buffer space available */ 57 FW_ETIMEDOUT = 110, /* timeout */ 58 FW_EINPROGRESS = 115, /* fw internal */ 59 FW_SCSI_ABORT_REQUESTED = 128, /* */ 60 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 61 FW_SCSI_ABORTED = 130, /* */ 62 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 63 FW_ERR_LINK_DOWN = 132, /* */ 64 FW_RDEV_NOT_READY = 133, /* */ 65 FW_ERR_RDEV_LOST = 134, /* */ 66 FW_ERR_RDEV_LOGO = 135, /* */ 67 FW_FCOE_NO_XCHG = 136, /* */ 68 FW_SCSI_RSP_ERR = 137, /* */ 69 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 70 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 71 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 72 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 73 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 74 }; 75 76 /****************************************************************************** 77 * W O R K R E Q U E S T s 78 ********************************/ 79 80 enum fw_wr_opcodes { 81 FW_FILTER_WR = 0x02, 82 FW_ULPTX_WR = 0x04, 83 FW_TP_WR = 0x05, 84 FW_ETH_TX_PKT_WR = 0x08, 85 FW_ETH_TX_PKTS_WR = 0x09, 86 FW_ETH_TX_UO_WR = 0x1c, 87 FW_EQ_FLUSH_WR = 0x1b, 88 FW_OFLD_CONNECTION_WR = 0x2f, 89 FW_FLOWC_WR = 0x0a, 90 FW_OFLD_TX_DATA_WR = 0x0b, 91 FW_CMD_WR = 0x10, 92 FW_ETH_TX_PKT_VM_WR = 0x11, 93 FW_RI_RES_WR = 0x0c, 94 FW_RI_RDMA_WRITE_WR = 0x14, 95 FW_RI_SEND_WR = 0x15, 96 FW_RI_RDMA_READ_WR = 0x16, 97 FW_RI_RECV_WR = 0x17, 98 FW_RI_BIND_MW_WR = 0x18, 99 FW_RI_FR_NSMR_WR = 0x19, 100 FW_RI_INV_LSTAG_WR = 0x1a, 101 FW_RI_SEND_IMMEDIATE_WR = 0x15, 102 FW_RI_ATOMIC_WR = 0x16, 103 FW_RI_WR = 0x0d, 104 FW_CHNET_IFCONF_WR = 0x6b, 105 FW_RDEV_WR = 0x38, 106 FW_FOISCSI_NODE_WR = 0x60, 107 FW_FOISCSI_CTRL_WR = 0x6a, 108 FW_FOISCSI_CHAP_WR = 0x6c, 109 FW_FCOE_ELS_CT_WR = 0x30, 110 FW_SCSI_WRITE_WR = 0x31, 111 FW_SCSI_READ_WR = 0x32, 112 FW_SCSI_CMD_WR = 0x33, 113 FW_SCSI_ABRT_CLS_WR = 0x34, 114 FW_SCSI_TGT_ACC_WR = 0x35, 115 FW_SCSI_TGT_XMIT_WR = 0x36, 116 FW_SCSI_TGT_RSP_WR = 0x37, 117 FW_LASTC2E_WR = 0x70 118 }; 119 120 /* 121 * Generic work request header flit0 122 */ 123 struct fw_wr_hdr { 124 __be32 hi; 125 __be32 lo; 126 }; 127 128 /* work request opcode (hi) 129 */ 130 #define S_FW_WR_OP 24 131 #define M_FW_WR_OP 0xff 132 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 133 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 134 135 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 136 */ 137 #define S_FW_WR_ATOMIC 23 138 #define M_FW_WR_ATOMIC 0x1 139 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 140 #define G_FW_WR_ATOMIC(x) \ 141 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 142 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 143 144 /* flush flag (hi) - firmware flushes flushable work request buffered 145 * in the flow context. 146 */ 147 #define S_FW_WR_FLUSH 22 148 #define M_FW_WR_FLUSH 0x1 149 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 150 #define G_FW_WR_FLUSH(x) \ 151 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 152 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 153 154 /* completion flag (hi) - firmware generates a cpl_fw6_ack 155 */ 156 #define S_FW_WR_COMPL 21 157 #define M_FW_WR_COMPL 0x1 158 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 159 #define G_FW_WR_COMPL(x) \ 160 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 161 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 162 163 164 /* work request immediate data lengh (hi) 165 */ 166 #define S_FW_WR_IMMDLEN 0 167 #define M_FW_WR_IMMDLEN 0xff 168 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 169 #define G_FW_WR_IMMDLEN(x) \ 170 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 171 172 /* egress queue status update to associated ingress queue entry (lo) 173 */ 174 #define S_FW_WR_EQUIQ 31 175 #define M_FW_WR_EQUIQ 0x1 176 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 177 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 178 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 179 180 /* egress queue status update to egress queue status entry (lo) 181 */ 182 #define S_FW_WR_EQUEQ 30 183 #define M_FW_WR_EQUEQ 0x1 184 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 185 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 186 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 187 188 /* flow context identifier (lo) 189 */ 190 #define S_FW_WR_FLOWID 8 191 #define M_FW_WR_FLOWID 0xfffff 192 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 193 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 194 195 /* length in units of 16-bytes (lo) 196 */ 197 #define S_FW_WR_LEN16 0 198 #define M_FW_WR_LEN16 0xff 199 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 200 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 201 202 /* valid filter configurations for compressed tuple 203 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 204 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 205 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 206 * OV - Outer VLAN/VNIC_ID, 207 */ 208 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 209 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 210 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 211 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 212 #define HW_TPL_FR_MT_E_PR_T 0x370 213 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 214 #define HW_TPL_FR_MT_E_T_P_FC 0X353 215 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 216 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 217 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 218 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 219 #define HW_TPL_FR_M_E_PR_FC 0X2E1 220 #define HW_TPL_FR_M_E_T_FC 0X2D1 221 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 222 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 223 #define HW_TPL_FR_M_T_IV_FC 0X299 224 #define HW_TPL_FR_M_T_OV_FC 0X295 225 #define HW_TPL_FR_E_PR_T_P 0X272 226 #define HW_TPL_FR_E_PR_T_FC 0X271 227 #define HW_TPL_FR_E_IV_FC 0X249 228 #define HW_TPL_FR_E_OV_FC 0X245 229 #define HW_TPL_FR_PR_T_IV_FC 0X239 230 #define HW_TPL_FR_PR_T_OV_FC 0X235 231 #define HW_TPL_FR_IV_OV_FC 0X20D 232 #define HW_TPL_MT_M_E_PR 0X1E0 233 #define HW_TPL_MT_M_E_T 0X1D0 234 #define HW_TPL_MT_E_PR_T_FC 0X171 235 #define HW_TPL_MT_E_IV 0X148 236 #define HW_TPL_MT_E_OV 0X144 237 #define HW_TPL_MT_PR_T_IV 0X138 238 #define HW_TPL_MT_PR_T_OV 0X134 239 #define HW_TPL_M_E_PR_P 0X0E2 240 #define HW_TPL_M_E_T_P 0X0D2 241 #define HW_TPL_E_PR_T_P_FC 0X073 242 #define HW_TPL_E_IV_P 0X04A 243 #define HW_TPL_E_OV_P 0X046 244 #define HW_TPL_PR_T_IV_P 0X03A 245 #define HW_TPL_PR_T_OV_P 0X036 246 247 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 248 enum fw_filter_wr_cookie { 249 FW_FILTER_WR_SUCCESS, 250 FW_FILTER_WR_FLT_ADDED, 251 FW_FILTER_WR_FLT_DELETED, 252 FW_FILTER_WR_SMT_TBL_FULL, 253 FW_FILTER_WR_EINVAL, 254 }; 255 256 struct fw_filter_wr { 257 __be32 op_pkd; 258 __be32 len16_pkd; 259 __be64 r3; 260 __be32 tid_to_iq; 261 __be32 del_filter_to_l2tix; 262 __be16 ethtype; 263 __be16 ethtypem; 264 __u8 frag_to_ovlan_vldm; 265 __u8 smac_sel; 266 __be16 rx_chan_rx_rpl_iq; 267 __be32 maci_to_matchtypem; 268 __u8 ptcl; 269 __u8 ptclm; 270 __u8 ttyp; 271 __u8 ttypm; 272 __be16 ivlan; 273 __be16 ivlanm; 274 __be16 ovlan; 275 __be16 ovlanm; 276 __u8 lip[16]; 277 __u8 lipm[16]; 278 __u8 fip[16]; 279 __u8 fipm[16]; 280 __be16 lp; 281 __be16 lpm; 282 __be16 fp; 283 __be16 fpm; 284 __be16 r7; 285 __u8 sma[6]; 286 }; 287 288 #define S_FW_FILTER_WR_TID 12 289 #define M_FW_FILTER_WR_TID 0xfffff 290 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 291 #define G_FW_FILTER_WR_TID(x) \ 292 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 293 294 #define S_FW_FILTER_WR_RQTYPE 11 295 #define M_FW_FILTER_WR_RQTYPE 0x1 296 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 297 #define G_FW_FILTER_WR_RQTYPE(x) \ 298 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 299 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 300 301 #define S_FW_FILTER_WR_NOREPLY 10 302 #define M_FW_FILTER_WR_NOREPLY 0x1 303 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 304 #define G_FW_FILTER_WR_NOREPLY(x) \ 305 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 306 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 307 308 #define S_FW_FILTER_WR_IQ 0 309 #define M_FW_FILTER_WR_IQ 0x3ff 310 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 311 #define G_FW_FILTER_WR_IQ(x) \ 312 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 313 314 #define S_FW_FILTER_WR_DEL_FILTER 31 315 #define M_FW_FILTER_WR_DEL_FILTER 0x1 316 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 317 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 318 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 319 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 320 321 #define S_FW_FILTER_WR_RPTTID 25 322 #define M_FW_FILTER_WR_RPTTID 0x1 323 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 324 #define G_FW_FILTER_WR_RPTTID(x) \ 325 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 326 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 327 328 #define S_FW_FILTER_WR_DROP 24 329 #define M_FW_FILTER_WR_DROP 0x1 330 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 331 #define G_FW_FILTER_WR_DROP(x) \ 332 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 333 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 334 335 #define S_FW_FILTER_WR_DIRSTEER 23 336 #define M_FW_FILTER_WR_DIRSTEER 0x1 337 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 338 #define G_FW_FILTER_WR_DIRSTEER(x) \ 339 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 340 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 341 342 #define S_FW_FILTER_WR_MASKHASH 22 343 #define M_FW_FILTER_WR_MASKHASH 0x1 344 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 345 #define G_FW_FILTER_WR_MASKHASH(x) \ 346 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 347 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 348 349 #define S_FW_FILTER_WR_DIRSTEERHASH 21 350 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 351 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 352 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 353 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 354 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 355 356 #define S_FW_FILTER_WR_LPBK 20 357 #define M_FW_FILTER_WR_LPBK 0x1 358 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 359 #define G_FW_FILTER_WR_LPBK(x) \ 360 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 361 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 362 363 #define S_FW_FILTER_WR_DMAC 19 364 #define M_FW_FILTER_WR_DMAC 0x1 365 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 366 #define G_FW_FILTER_WR_DMAC(x) \ 367 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 368 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 369 370 #define S_FW_FILTER_WR_SMAC 18 371 #define M_FW_FILTER_WR_SMAC 0x1 372 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 373 #define G_FW_FILTER_WR_SMAC(x) \ 374 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 375 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 376 377 #define S_FW_FILTER_WR_INSVLAN 17 378 #define M_FW_FILTER_WR_INSVLAN 0x1 379 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 380 #define G_FW_FILTER_WR_INSVLAN(x) \ 381 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 382 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 383 384 #define S_FW_FILTER_WR_RMVLAN 16 385 #define M_FW_FILTER_WR_RMVLAN 0x1 386 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 387 #define G_FW_FILTER_WR_RMVLAN(x) \ 388 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 389 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 390 391 #define S_FW_FILTER_WR_HITCNTS 15 392 #define M_FW_FILTER_WR_HITCNTS 0x1 393 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 394 #define G_FW_FILTER_WR_HITCNTS(x) \ 395 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 396 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 397 398 #define S_FW_FILTER_WR_TXCHAN 13 399 #define M_FW_FILTER_WR_TXCHAN 0x3 400 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 401 #define G_FW_FILTER_WR_TXCHAN(x) \ 402 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 403 404 #define S_FW_FILTER_WR_PRIO 12 405 #define M_FW_FILTER_WR_PRIO 0x1 406 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 407 #define G_FW_FILTER_WR_PRIO(x) \ 408 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 409 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 410 411 #define S_FW_FILTER_WR_L2TIX 0 412 #define M_FW_FILTER_WR_L2TIX 0xfff 413 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 414 #define G_FW_FILTER_WR_L2TIX(x) \ 415 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 416 417 #define S_FW_FILTER_WR_FRAG 7 418 #define M_FW_FILTER_WR_FRAG 0x1 419 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 420 #define G_FW_FILTER_WR_FRAG(x) \ 421 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 422 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 423 424 #define S_FW_FILTER_WR_FRAGM 6 425 #define M_FW_FILTER_WR_FRAGM 0x1 426 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 427 #define G_FW_FILTER_WR_FRAGM(x) \ 428 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 429 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 430 431 #define S_FW_FILTER_WR_IVLAN_VLD 5 432 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 433 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 434 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 435 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 436 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 437 438 #define S_FW_FILTER_WR_OVLAN_VLD 4 439 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 440 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 441 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 442 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 443 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 444 445 #define S_FW_FILTER_WR_IVLAN_VLDM 3 446 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 447 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 448 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 449 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 450 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 451 452 #define S_FW_FILTER_WR_OVLAN_VLDM 2 453 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 454 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 455 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 456 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 457 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 458 459 #define S_FW_FILTER_WR_RX_CHAN 15 460 #define M_FW_FILTER_WR_RX_CHAN 0x1 461 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 462 #define G_FW_FILTER_WR_RX_CHAN(x) \ 463 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 464 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 465 466 #define S_FW_FILTER_WR_RX_RPL_IQ 0 467 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 468 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 469 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 470 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 471 472 #define S_FW_FILTER_WR_MACI 23 473 #define M_FW_FILTER_WR_MACI 0x1ff 474 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 475 #define G_FW_FILTER_WR_MACI(x) \ 476 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 477 478 #define S_FW_FILTER_WR_MACIM 14 479 #define M_FW_FILTER_WR_MACIM 0x1ff 480 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 481 #define G_FW_FILTER_WR_MACIM(x) \ 482 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 483 484 #define S_FW_FILTER_WR_FCOE 13 485 #define M_FW_FILTER_WR_FCOE 0x1 486 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 487 #define G_FW_FILTER_WR_FCOE(x) \ 488 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 489 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 490 491 #define S_FW_FILTER_WR_FCOEM 12 492 #define M_FW_FILTER_WR_FCOEM 0x1 493 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 494 #define G_FW_FILTER_WR_FCOEM(x) \ 495 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 496 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 497 498 #define S_FW_FILTER_WR_PORT 9 499 #define M_FW_FILTER_WR_PORT 0x7 500 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 501 #define G_FW_FILTER_WR_PORT(x) \ 502 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 503 504 #define S_FW_FILTER_WR_PORTM 6 505 #define M_FW_FILTER_WR_PORTM 0x7 506 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 507 #define G_FW_FILTER_WR_PORTM(x) \ 508 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 509 510 #define S_FW_FILTER_WR_MATCHTYPE 3 511 #define M_FW_FILTER_WR_MATCHTYPE 0x7 512 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 513 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 514 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 515 516 #define S_FW_FILTER_WR_MATCHTYPEM 0 517 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 518 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 519 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 520 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 521 522 struct fw_ulptx_wr { 523 __be32 op_to_compl; 524 __be32 flowid_len16; 525 __u64 cookie; 526 }; 527 528 struct fw_tp_wr { 529 __be32 op_to_immdlen; 530 __be32 flowid_len16; 531 __u64 cookie; 532 }; 533 534 struct fw_eth_tx_pkt_wr { 535 __be32 op_immdlen; 536 __be32 equiq_to_len16; 537 __be64 r3; 538 }; 539 540 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 541 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 542 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 543 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 544 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 545 546 struct fw_eth_tx_pkts_wr { 547 __be32 op_pkd; 548 __be32 equiq_to_len16; 549 __be32 r3; 550 __be16 plen; 551 __u8 npkt; 552 __u8 type; 553 }; 554 555 struct fw_eth_tx_uo_wr { 556 __be32 op_immdlen; 557 __be32 equiq_to_len16; 558 __be64 r3; 559 __be16 ethlen; 560 __be16 iplen; 561 __be16 udplen; 562 __be16 mss; 563 __be32 length; 564 __be32 r4; 565 }; 566 567 struct fw_eq_flush_wr { 568 __u8 opcode; 569 __u8 r1[3]; 570 __be32 equiq_to_len16; 571 __be64 r3; 572 }; 573 574 struct fw_ofld_connection_wr { 575 __be32 op_compl; 576 __be32 len16_pkd; 577 __u64 cookie; 578 __be64 r2; 579 __be64 r3; 580 struct fw_ofld_connection_le { 581 __be32 version_cpl; 582 __be32 filter; 583 __be32 r1; 584 __be16 lport; 585 __be16 pport; 586 union fw_ofld_connection_leip { 587 struct fw_ofld_connection_le_ipv4 { 588 __be32 pip; 589 __be32 lip; 590 __be64 r0; 591 __be64 r1; 592 __be64 r2; 593 } ipv4; 594 struct fw_ofld_connection_le_ipv6 { 595 __be64 pip_hi; 596 __be64 pip_lo; 597 __be64 lip_hi; 598 __be64 lip_lo; 599 } ipv6; 600 } u; 601 } le; 602 struct fw_ofld_connection_tcb { 603 __be32 t_state_to_astid; 604 __be16 cplrxdataack_cplpassacceptrpl; 605 __be16 rcv_adv; 606 __be32 rcv_nxt; 607 __be32 tx_max; 608 __be64 opt0; 609 __be32 opt2; 610 __be32 r1; 611 __be64 r2; 612 __be64 r3; 613 } tcb; 614 }; 615 616 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 617 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 618 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 619 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 620 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 621 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 622 M_FW_OFLD_CONNECTION_WR_VERSION) 623 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 624 625 #define S_FW_OFLD_CONNECTION_WR_CPL 30 626 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 627 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 628 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 629 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 630 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 631 632 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 633 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 634 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 635 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 636 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 637 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 638 M_FW_OFLD_CONNECTION_WR_T_STATE) 639 640 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 641 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 642 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 643 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 644 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 645 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 646 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 647 648 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 649 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 650 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 651 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 652 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 653 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 654 655 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 656 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 657 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 658 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 659 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 660 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 661 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 662 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 663 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 664 665 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 666 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 667 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 668 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 669 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 670 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 671 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 672 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 673 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 674 675 enum fw_flowc_mnem_tcpstate { 676 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 677 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 678 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 679 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 680 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 681 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 682 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 683 * will resend FIN - equiv ESTAB 684 */ 685 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 686 * will resend FIN but have 687 * received FIN 688 */ 689 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 690 * will resend FIN but have 691 * received FIN 692 */ 693 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 694 * waiting for FIN 695 */ 696 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 697 }; 698 699 enum fw_flowc_mnem_uostate { 700 FW_FLOWC_MNEM_UOSTATE_CLOSED = 0, /* illegal */ 701 FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1, /* default */ 702 FW_FLOWC_MNEM_UOSTATE_CLOSING = 2, /* graceful close, after sending 703 * outstanding payload 704 */ 705 FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, /* immediate close, after 706 * discarding outstanding payload 707 */ 708 }; 709 710 enum fw_flowc_mnem { 711 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 712 FW_FLOWC_MNEM_CH, 713 FW_FLOWC_MNEM_PORT, 714 FW_FLOWC_MNEM_IQID, 715 FW_FLOWC_MNEM_SNDNXT, 716 FW_FLOWC_MNEM_RCVNXT, 717 FW_FLOWC_MNEM_SNDBUF, 718 FW_FLOWC_MNEM_MSS, 719 FW_FLOWC_MNEM_TXDATAPLEN_MAX, 720 FW_FLOWC_MNEM_TCPSTATE, 721 FW_FLOWC_MNEM_UOSTATE, 722 FW_FLOWC_MNEM_SCHEDCLASS, 723 }; 724 725 struct fw_flowc_mnemval { 726 __u8 mnemonic; 727 __u8 r4[3]; 728 __be32 val; 729 }; 730 731 struct fw_flowc_wr { 732 __be32 op_to_nparams; 733 __be32 flowid_len16; 734 #ifndef C99_NOT_SUPPORTED 735 struct fw_flowc_mnemval mnemval[0]; 736 #endif 737 }; 738 739 #define S_FW_FLOWC_WR_NPARAMS 0 740 #define M_FW_FLOWC_WR_NPARAMS 0xff 741 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 742 #define G_FW_FLOWC_WR_NPARAMS(x) \ 743 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 744 745 struct fw_ofld_tx_data_wr { 746 __be32 op_to_immdlen; 747 __be32 flowid_len16; 748 __be32 plen; 749 __be32 tunnel_to_proxy; 750 }; 751 752 #define S_FW_OFLD_TX_DATA_WR_TUNNEL 19 753 #define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1 754 #define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL) 755 #define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \ 756 (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL) 757 #define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U) 758 759 #define S_FW_OFLD_TX_DATA_WR_SAVE 18 760 #define M_FW_OFLD_TX_DATA_WR_SAVE 0x1 761 #define V_FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SAVE) 762 #define G_FW_OFLD_TX_DATA_WR_SAVE(x) \ 763 (((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE) 764 #define F_FW_OFLD_TX_DATA_WR_SAVE V_FW_OFLD_TX_DATA_WR_SAVE(1U) 765 766 #define S_FW_OFLD_TX_DATA_WR_FLUSH 17 767 #define M_FW_OFLD_TX_DATA_WR_FLUSH 0x1 768 #define V_FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLUSH) 769 #define G_FW_OFLD_TX_DATA_WR_FLUSH(x) \ 770 (((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH) 771 #define F_FW_OFLD_TX_DATA_WR_FLUSH V_FW_OFLD_TX_DATA_WR_FLUSH(1U) 772 773 #define S_FW_OFLD_TX_DATA_WR_URGENT 16 774 #define M_FW_OFLD_TX_DATA_WR_URGENT 0x1 775 #define V_FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << S_FW_OFLD_TX_DATA_WR_URGENT) 776 #define G_FW_OFLD_TX_DATA_WR_URGENT(x) \ 777 (((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT) 778 #define F_FW_OFLD_TX_DATA_WR_URGENT V_FW_OFLD_TX_DATA_WR_URGENT(1U) 779 780 #define S_FW_OFLD_TX_DATA_WR_MORE 15 781 #define M_FW_OFLD_TX_DATA_WR_MORE 0x1 782 #define V_FW_OFLD_TX_DATA_WR_MORE(x) ((x) << S_FW_OFLD_TX_DATA_WR_MORE) 783 #define G_FW_OFLD_TX_DATA_WR_MORE(x) \ 784 (((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE) 785 #define F_FW_OFLD_TX_DATA_WR_MORE V_FW_OFLD_TX_DATA_WR_MORE(1U) 786 787 #define S_FW_OFLD_TX_DATA_WR_SHOVE 14 788 #define M_FW_OFLD_TX_DATA_WR_SHOVE 0x1 789 #define V_FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SHOVE) 790 #define G_FW_OFLD_TX_DATA_WR_SHOVE(x) \ 791 (((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE) 792 #define F_FW_OFLD_TX_DATA_WR_SHOVE V_FW_OFLD_TX_DATA_WR_SHOVE(1U) 793 794 #define S_FW_OFLD_TX_DATA_WR_ULPMODE 10 795 #define M_FW_OFLD_TX_DATA_WR_ULPMODE 0xf 796 #define V_FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE) 797 #define G_FW_OFLD_TX_DATA_WR_ULPMODE(x) \ 798 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE) 799 800 #define S_FW_OFLD_TX_DATA_WR_ULPSUBMODE 6 801 #define M_FW_OFLD_TX_DATA_WR_ULPSUBMODE 0xf 802 #define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 803 ((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 804 #define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 805 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \ 806 M_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 807 808 #define S_FW_OFLD_TX_DATA_WR_PROXY 5 809 #define M_FW_OFLD_TX_DATA_WR_PROXY 0x1 810 #define V_FW_OFLD_TX_DATA_WR_PROXY(x) ((x) << S_FW_OFLD_TX_DATA_WR_PROXY) 811 #define G_FW_OFLD_TX_DATA_WR_PROXY(x) \ 812 (((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY) 813 #define F_FW_OFLD_TX_DATA_WR_PROXY V_FW_OFLD_TX_DATA_WR_PROXY(1U) 814 815 struct fw_cmd_wr { 816 __be32 op_dma; 817 __be32 len16_pkd; 818 __be64 cookie_daddr; 819 }; 820 821 #define S_FW_CMD_WR_DMA 17 822 #define M_FW_CMD_WR_DMA 0x1 823 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 824 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 825 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 826 827 struct fw_eth_tx_pkt_vm_wr { 828 __be32 op_immdlen; 829 __be32 equiq_to_len16; 830 __be32 r3[2]; 831 __u8 ethmacdst[6]; 832 __u8 ethmacsrc[6]; 833 __be16 ethtype; 834 __be16 vlantci; 835 }; 836 837 /****************************************************************************** 838 * R I W O R K R E Q U E S T s 839 **************************************/ 840 841 enum fw_ri_wr_opcode { 842 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 843 FW_RI_READ_REQ = 0x1, 844 FW_RI_READ_RESP = 0x2, 845 FW_RI_SEND = 0x3, 846 FW_RI_SEND_WITH_INV = 0x4, 847 FW_RI_SEND_WITH_SE = 0x5, 848 FW_RI_SEND_WITH_SE_INV = 0x6, 849 FW_RI_TERMINATE = 0x7, 850 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 851 FW_RI_BIND_MW = 0x9, 852 FW_RI_FAST_REGISTER = 0xa, 853 FW_RI_LOCAL_INV = 0xb, 854 FW_RI_QP_MODIFY = 0xc, 855 FW_RI_BYPASS = 0xd, 856 FW_RI_RECEIVE = 0xe, 857 #if 0 858 FW_RI_SEND_IMMEDIATE = 0x8, 859 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 860 FW_RI_ATOMIC_REQUEST = 0xa, 861 FW_RI_ATOMIC_RESPONSE = 0xb, 862 863 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 864 FW_RI_FAST_REGISTER = 0xd, 865 FW_RI_LOCAL_INV = 0xe, 866 #endif 867 FW_RI_SGE_EC_CR_RETURN = 0xf 868 }; 869 870 enum fw_ri_wr_flags { 871 FW_RI_COMPLETION_FLAG = 0x01, 872 FW_RI_NOTIFICATION_FLAG = 0x02, 873 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 874 FW_RI_READ_FENCE_FLAG = 0x08, 875 FW_RI_LOCAL_FENCE_FLAG = 0x10, 876 FW_RI_RDMA_READ_INVALIDATE = 0x20 877 }; 878 879 enum fw_ri_mpa_attrs { 880 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 881 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 882 FW_RI_MPA_CRC_ENABLE = 0x04, 883 FW_RI_MPA_IETF_ENABLE = 0x08 884 }; 885 886 enum fw_ri_qp_caps { 887 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 888 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 889 FW_RI_QP_BIND_ENABLE = 0x04, 890 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 891 FW_RI_QP_STAG0_ENABLE = 0x10, 892 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 893 }; 894 895 enum fw_ri_addr_type { 896 FW_RI_ZERO_BASED_TO = 0x00, 897 FW_RI_VA_BASED_TO = 0x01 898 }; 899 900 enum fw_ri_mem_perms { 901 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 902 FW_RI_MEM_ACCESS_REM_READ = 0x02, 903 FW_RI_MEM_ACCESS_REM = 0x03, 904 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 905 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 906 FW_RI_MEM_ACCESS_LOCAL = 0x0C 907 }; 908 909 enum fw_ri_stag_type { 910 FW_RI_STAG_NSMR = 0x00, 911 FW_RI_STAG_SMR = 0x01, 912 FW_RI_STAG_MW = 0x02, 913 FW_RI_STAG_MW_RELAXED = 0x03 914 }; 915 916 enum fw_ri_data_op { 917 FW_RI_DATA_IMMD = 0x81, 918 FW_RI_DATA_DSGL = 0x82, 919 FW_RI_DATA_ISGL = 0x83 920 }; 921 922 enum fw_ri_sgl_depth { 923 FW_RI_SGL_DEPTH_MAX_SQ = 16, 924 FW_RI_SGL_DEPTH_MAX_RQ = 4 925 }; 926 927 enum fw_ri_cqe_err { 928 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 929 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 930 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 931 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 932 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 933 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 934 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 935 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 936 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 937 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 938 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 939 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 940 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 941 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 942 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 943 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 944 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 945 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 946 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 947 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 948 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 949 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 950 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 951 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 952 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 953 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 954 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 955 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 956 957 }; 958 959 struct fw_ri_dsge_pair { 960 __be32 len[2]; 961 __be64 addr[2]; 962 }; 963 964 struct fw_ri_dsgl { 965 __u8 op; 966 __u8 r1; 967 __be16 nsge; 968 __be32 len0; 969 __be64 addr0; 970 #ifndef C99_NOT_SUPPORTED 971 struct fw_ri_dsge_pair sge[0]; 972 #endif 973 }; 974 975 struct fw_ri_sge { 976 __be32 stag; 977 __be32 len; 978 __be64 to; 979 }; 980 981 struct fw_ri_isgl { 982 __u8 op; 983 __u8 r1; 984 __be16 nsge; 985 __be32 r2; 986 #ifndef C99_NOT_SUPPORTED 987 struct fw_ri_sge sge[0]; 988 #endif 989 }; 990 991 struct fw_ri_immd { 992 __u8 op; 993 __u8 r1; 994 __be16 r2; 995 __be32 immdlen; 996 #ifndef C99_NOT_SUPPORTED 997 __u8 data[0]; 998 #endif 999 }; 1000 1001 struct fw_ri_tpte { 1002 __be32 valid_to_pdid; 1003 __be32 locread_to_qpid; 1004 __be32 nosnoop_pbladdr; 1005 __be32 len_lo; 1006 __be32 va_hi; 1007 __be32 va_lo_fbo; 1008 __be32 dca_mwbcnt_pstag; 1009 __be32 len_hi; 1010 }; 1011 1012 #define S_FW_RI_TPTE_VALID 31 1013 #define M_FW_RI_TPTE_VALID 0x1 1014 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1015 #define G_FW_RI_TPTE_VALID(x) \ 1016 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1017 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1018 1019 #define S_FW_RI_TPTE_STAGKEY 23 1020 #define M_FW_RI_TPTE_STAGKEY 0xff 1021 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1022 #define G_FW_RI_TPTE_STAGKEY(x) \ 1023 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1024 1025 #define S_FW_RI_TPTE_STAGSTATE 22 1026 #define M_FW_RI_TPTE_STAGSTATE 0x1 1027 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1028 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1029 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1030 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1031 1032 #define S_FW_RI_TPTE_STAGTYPE 20 1033 #define M_FW_RI_TPTE_STAGTYPE 0x3 1034 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1035 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1036 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1037 1038 #define S_FW_RI_TPTE_PDID 0 1039 #define M_FW_RI_TPTE_PDID 0xfffff 1040 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1041 #define G_FW_RI_TPTE_PDID(x) \ 1042 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1043 1044 #define S_FW_RI_TPTE_PERM 28 1045 #define M_FW_RI_TPTE_PERM 0xf 1046 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1047 #define G_FW_RI_TPTE_PERM(x) \ 1048 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1049 1050 #define S_FW_RI_TPTE_REMINVDIS 27 1051 #define M_FW_RI_TPTE_REMINVDIS 0x1 1052 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1053 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1054 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1055 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1056 1057 #define S_FW_RI_TPTE_ADDRTYPE 26 1058 #define M_FW_RI_TPTE_ADDRTYPE 1 1059 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1060 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1061 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1062 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1063 1064 #define S_FW_RI_TPTE_MWBINDEN 25 1065 #define M_FW_RI_TPTE_MWBINDEN 0x1 1066 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1067 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1068 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1069 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1070 1071 #define S_FW_RI_TPTE_PS 20 1072 #define M_FW_RI_TPTE_PS 0x1f 1073 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1074 #define G_FW_RI_TPTE_PS(x) \ 1075 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1076 1077 #define S_FW_RI_TPTE_QPID 0 1078 #define M_FW_RI_TPTE_QPID 0xfffff 1079 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1080 #define G_FW_RI_TPTE_QPID(x) \ 1081 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1082 1083 #define S_FW_RI_TPTE_NOSNOOP 31 1084 #define M_FW_RI_TPTE_NOSNOOP 0x1 1085 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1086 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1087 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1088 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1089 1090 #define S_FW_RI_TPTE_PBLADDR 0 1091 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1092 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1093 #define G_FW_RI_TPTE_PBLADDR(x) \ 1094 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1095 1096 #define S_FW_RI_TPTE_DCA 24 1097 #define M_FW_RI_TPTE_DCA 0x1f 1098 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1099 #define G_FW_RI_TPTE_DCA(x) \ 1100 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1101 1102 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1103 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1104 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1105 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1106 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1107 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1108 1109 enum fw_ri_cqe_rxtx { 1110 FW_RI_CQE_RXTX_RX = 0x0, 1111 FW_RI_CQE_RXTX_TX = 0x1, 1112 }; 1113 1114 struct fw_ri_cqe { 1115 union fw_ri_rxtx { 1116 struct fw_ri_scqe { 1117 __be32 qpid_n_stat_rxtx_type; 1118 __be32 plen; 1119 __be32 reserved; 1120 __be32 wrid; 1121 } scqe; 1122 struct fw_ri_rcqe { 1123 __be32 qpid_n_stat_rxtx_type; 1124 __be32 plen; 1125 __be32 stag; 1126 __be32 msn; 1127 } rcqe; 1128 } u; 1129 }; 1130 1131 #define S_FW_RI_CQE_QPID 12 1132 #define M_FW_RI_CQE_QPID 0xfffff 1133 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1134 #define G_FW_RI_CQE_QPID(x) \ 1135 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1136 1137 #define S_FW_RI_CQE_NOTIFY 10 1138 #define M_FW_RI_CQE_NOTIFY 0x1 1139 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1140 #define G_FW_RI_CQE_NOTIFY(x) \ 1141 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1142 1143 #define S_FW_RI_CQE_STATUS 5 1144 #define M_FW_RI_CQE_STATUS 0x1f 1145 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1146 #define G_FW_RI_CQE_STATUS(x) \ 1147 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1148 1149 1150 #define S_FW_RI_CQE_RXTX 4 1151 #define M_FW_RI_CQE_RXTX 0x1 1152 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1153 #define G_FW_RI_CQE_RXTX(x) \ 1154 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1155 1156 #define S_FW_RI_CQE_TYPE 0 1157 #define M_FW_RI_CQE_TYPE 0xf 1158 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1159 #define G_FW_RI_CQE_TYPE(x) \ 1160 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1161 1162 enum fw_ri_res_type { 1163 FW_RI_RES_TYPE_SQ, 1164 FW_RI_RES_TYPE_RQ, 1165 FW_RI_RES_TYPE_CQ, 1166 }; 1167 1168 enum fw_ri_res_op { 1169 FW_RI_RES_OP_WRITE, 1170 FW_RI_RES_OP_RESET, 1171 }; 1172 1173 struct fw_ri_res { 1174 union fw_ri_restype { 1175 struct fw_ri_res_sqrq { 1176 __u8 restype; 1177 __u8 op; 1178 __be16 r3; 1179 __be32 eqid; 1180 __be32 r4[2]; 1181 __be32 fetchszm_to_iqid; 1182 __be32 dcaen_to_eqsize; 1183 __be64 eqaddr; 1184 } sqrq; 1185 struct fw_ri_res_cq { 1186 __u8 restype; 1187 __u8 op; 1188 __be16 r3; 1189 __be32 iqid; 1190 __be32 r4[2]; 1191 __be32 iqandst_to_iqandstindex; 1192 __be16 iqdroprss_to_iqesize; 1193 __be16 iqsize; 1194 __be64 iqaddr; 1195 __be32 iqns_iqro; 1196 __be32 r6_lo; 1197 __be64 r7; 1198 } cq; 1199 } u; 1200 }; 1201 1202 struct fw_ri_res_wr { 1203 __be32 op_nres; 1204 __be32 len16_pkd; 1205 __u64 cookie; 1206 #ifndef C99_NOT_SUPPORTED 1207 struct fw_ri_res res[0]; 1208 #endif 1209 }; 1210 1211 #define S_FW_RI_RES_WR_NRES 0 1212 #define M_FW_RI_RES_WR_NRES 0xff 1213 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1214 #define G_FW_RI_RES_WR_NRES(x) \ 1215 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1216 1217 #define S_FW_RI_RES_WR_FETCHSZM 26 1218 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1219 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1220 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1221 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1222 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1223 1224 #define S_FW_RI_RES_WR_STATUSPGNS 25 1225 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1226 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1227 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1228 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1229 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1230 1231 #define S_FW_RI_RES_WR_STATUSPGRO 24 1232 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1233 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1234 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1235 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1236 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1237 1238 #define S_FW_RI_RES_WR_FETCHNS 23 1239 #define M_FW_RI_RES_WR_FETCHNS 0x1 1240 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1241 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1242 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1243 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1244 1245 #define S_FW_RI_RES_WR_FETCHRO 22 1246 #define M_FW_RI_RES_WR_FETCHRO 0x1 1247 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1248 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1249 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1250 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1251 1252 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1253 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1254 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1255 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1256 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1257 1258 #define S_FW_RI_RES_WR_CPRIO 19 1259 #define M_FW_RI_RES_WR_CPRIO 0x1 1260 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1261 #define G_FW_RI_RES_WR_CPRIO(x) \ 1262 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1263 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1264 1265 #define S_FW_RI_RES_WR_ONCHIP 18 1266 #define M_FW_RI_RES_WR_ONCHIP 0x1 1267 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1268 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1269 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1270 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1271 1272 #define S_FW_RI_RES_WR_PCIECHN 16 1273 #define M_FW_RI_RES_WR_PCIECHN 0x3 1274 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1275 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1276 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1277 1278 #define S_FW_RI_RES_WR_IQID 0 1279 #define M_FW_RI_RES_WR_IQID 0xffff 1280 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1281 #define G_FW_RI_RES_WR_IQID(x) \ 1282 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1283 1284 #define S_FW_RI_RES_WR_DCAEN 31 1285 #define M_FW_RI_RES_WR_DCAEN 0x1 1286 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1287 #define G_FW_RI_RES_WR_DCAEN(x) \ 1288 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1289 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1290 1291 #define S_FW_RI_RES_WR_DCACPU 26 1292 #define M_FW_RI_RES_WR_DCACPU 0x1f 1293 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1294 #define G_FW_RI_RES_WR_DCACPU(x) \ 1295 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1296 1297 #define S_FW_RI_RES_WR_FBMIN 23 1298 #define M_FW_RI_RES_WR_FBMIN 0x7 1299 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1300 #define G_FW_RI_RES_WR_FBMIN(x) \ 1301 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1302 1303 #define S_FW_RI_RES_WR_FBMAX 20 1304 #define M_FW_RI_RES_WR_FBMAX 0x7 1305 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1306 #define G_FW_RI_RES_WR_FBMAX(x) \ 1307 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1308 1309 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1310 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1311 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1312 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1313 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1314 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1315 1316 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1317 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1318 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1319 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1320 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1321 1322 #define S_FW_RI_RES_WR_EQSIZE 0 1323 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1324 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1325 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1326 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1327 1328 #define S_FW_RI_RES_WR_IQANDST 15 1329 #define M_FW_RI_RES_WR_IQANDST 0x1 1330 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1331 #define G_FW_RI_RES_WR_IQANDST(x) \ 1332 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1333 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1334 1335 #define S_FW_RI_RES_WR_IQANUS 14 1336 #define M_FW_RI_RES_WR_IQANUS 0x1 1337 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1338 #define G_FW_RI_RES_WR_IQANUS(x) \ 1339 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1340 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1341 1342 #define S_FW_RI_RES_WR_IQANUD 12 1343 #define M_FW_RI_RES_WR_IQANUD 0x3 1344 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1345 #define G_FW_RI_RES_WR_IQANUD(x) \ 1346 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1347 1348 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1349 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1350 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1351 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1352 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1353 1354 #define S_FW_RI_RES_WR_IQDROPRSS 15 1355 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1356 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1357 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1358 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1359 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1360 1361 #define S_FW_RI_RES_WR_IQGTSMODE 14 1362 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1363 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1364 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1365 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1366 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1367 1368 #define S_FW_RI_RES_WR_IQPCIECH 12 1369 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1370 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1371 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1372 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1373 1374 #define S_FW_RI_RES_WR_IQDCAEN 11 1375 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1376 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1377 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1378 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1379 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1380 1381 #define S_FW_RI_RES_WR_IQDCACPU 6 1382 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1383 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1384 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1385 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1386 1387 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1388 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1389 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1390 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1391 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1392 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1393 1394 #define S_FW_RI_RES_WR_IQO 3 1395 #define M_FW_RI_RES_WR_IQO 0x1 1396 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1397 #define G_FW_RI_RES_WR_IQO(x) \ 1398 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1399 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1400 1401 #define S_FW_RI_RES_WR_IQCPRIO 2 1402 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1403 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1404 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1405 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1406 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1407 1408 #define S_FW_RI_RES_WR_IQESIZE 0 1409 #define M_FW_RI_RES_WR_IQESIZE 0x3 1410 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1411 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1412 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1413 1414 #define S_FW_RI_RES_WR_IQNS 31 1415 #define M_FW_RI_RES_WR_IQNS 0x1 1416 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1417 #define G_FW_RI_RES_WR_IQNS(x) \ 1418 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1419 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1420 1421 #define S_FW_RI_RES_WR_IQRO 30 1422 #define M_FW_RI_RES_WR_IQRO 0x1 1423 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1424 #define G_FW_RI_RES_WR_IQRO(x) \ 1425 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1426 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1427 1428 struct fw_ri_rdma_write_wr { 1429 __u8 opcode; 1430 __u8 flags; 1431 __u16 wrid; 1432 __u8 r1[3]; 1433 __u8 len16; 1434 __be64 r2; 1435 __be32 plen; 1436 __be32 stag_sink; 1437 __be64 to_sink; 1438 #ifndef C99_NOT_SUPPORTED 1439 union { 1440 struct fw_ri_immd immd_src[0]; 1441 struct fw_ri_isgl isgl_src[0]; 1442 } u; 1443 #endif 1444 }; 1445 1446 struct fw_ri_send_wr { 1447 __u8 opcode; 1448 __u8 flags; 1449 __u16 wrid; 1450 __u8 r1[3]; 1451 __u8 len16; 1452 __be32 sendop_pkd; 1453 __be32 stag_inv; 1454 __be32 plen; 1455 __be32 r3; 1456 __be64 r4; 1457 #ifndef C99_NOT_SUPPORTED 1458 union { 1459 struct fw_ri_immd immd_src[0]; 1460 struct fw_ri_isgl isgl_src[0]; 1461 } u; 1462 #endif 1463 }; 1464 1465 #define S_FW_RI_SEND_WR_SENDOP 0 1466 #define M_FW_RI_SEND_WR_SENDOP 0xf 1467 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1468 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1469 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1470 1471 struct fw_ri_rdma_read_wr { 1472 __u8 opcode; 1473 __u8 flags; 1474 __u16 wrid; 1475 __u8 r1[3]; 1476 __u8 len16; 1477 __be64 r2; 1478 __be32 stag_sink; 1479 __be32 to_sink_hi; 1480 __be32 to_sink_lo; 1481 __be32 plen; 1482 __be32 stag_src; 1483 __be32 to_src_hi; 1484 __be32 to_src_lo; 1485 __be32 r5; 1486 }; 1487 1488 struct fw_ri_recv_wr { 1489 __u8 opcode; 1490 __u8 r1; 1491 __u16 wrid; 1492 __u8 r2[3]; 1493 __u8 len16; 1494 struct fw_ri_isgl isgl; 1495 }; 1496 1497 struct fw_ri_bind_mw_wr { 1498 __u8 opcode; 1499 __u8 flags; 1500 __u16 wrid; 1501 __u8 r1[3]; 1502 __u8 len16; 1503 __u8 qpbinde_to_dcacpu; 1504 __u8 pgsz_shift; 1505 __u8 addr_type; 1506 __u8 mem_perms; 1507 __be32 stag_mr; 1508 __be32 stag_mw; 1509 __be32 r3; 1510 __be64 len_mw; 1511 __be64 va_fbo; 1512 __be64 r4; 1513 }; 1514 1515 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1516 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1517 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1518 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1519 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1520 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1521 1522 #define S_FW_RI_BIND_MW_WR_NS 5 1523 #define M_FW_RI_BIND_MW_WR_NS 0x1 1524 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1525 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1526 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1527 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1528 1529 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1530 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1531 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1532 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1533 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1534 1535 struct fw_ri_fr_nsmr_wr { 1536 __u8 opcode; 1537 __u8 flags; 1538 __u16 wrid; 1539 __u8 r1[3]; 1540 __u8 len16; 1541 __u8 qpbinde_to_dcacpu; 1542 __u8 pgsz_shift; 1543 __u8 addr_type; 1544 __u8 mem_perms; 1545 __be32 stag; 1546 __be32 len_hi; 1547 __be32 len_lo; 1548 __be32 va_hi; 1549 __be32 va_lo_fbo; 1550 }; 1551 1552 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1553 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1554 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1555 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1556 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1557 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1558 1559 #define S_FW_RI_FR_NSMR_WR_NS 5 1560 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1561 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1562 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1563 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1564 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1565 1566 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1567 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1568 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1569 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1570 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1571 1572 struct fw_ri_inv_lstag_wr { 1573 __u8 opcode; 1574 __u8 flags; 1575 __u16 wrid; 1576 __u8 r1[3]; 1577 __u8 len16; 1578 __be32 r2; 1579 __be32 stag_inv; 1580 }; 1581 1582 struct fw_ri_send_immediate_wr { 1583 __u8 opcode; 1584 __u8 flags; 1585 __u16 wrid; 1586 __u8 r1[3]; 1587 __u8 len16; 1588 __be32 sendimmop_pkd; 1589 __be32 r3; 1590 __be32 plen; 1591 __be32 r4; 1592 __be64 r5; 1593 #ifndef C99_NOT_SUPPORTED 1594 struct fw_ri_immd immd_src[0]; 1595 #endif 1596 }; 1597 1598 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1599 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1600 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1601 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1602 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1603 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1604 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1605 1606 enum fw_ri_atomic_op { 1607 FW_RI_ATOMIC_OP_FETCHADD, 1608 FW_RI_ATOMIC_OP_SWAP, 1609 FW_RI_ATOMIC_OP_CMDSWAP, 1610 }; 1611 1612 struct fw_ri_atomic_wr { 1613 __u8 opcode; 1614 __u8 flags; 1615 __u16 wrid; 1616 __u8 r1[3]; 1617 __u8 len16; 1618 __be32 atomicop_pkd; 1619 __be64 r3; 1620 __be32 aopcode_pkd; 1621 __be32 reqid; 1622 __be32 stag; 1623 __be32 to_hi; 1624 __be32 to_lo; 1625 __be32 addswap_data_hi; 1626 __be32 addswap_data_lo; 1627 __be32 addswap_mask_hi; 1628 __be32 addswap_mask_lo; 1629 __be32 compare_data_hi; 1630 __be32 compare_data_lo; 1631 __be32 compare_mask_hi; 1632 __be32 compare_mask_lo; 1633 __be32 r5; 1634 }; 1635 1636 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1637 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1638 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1639 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1640 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 1641 1642 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 1643 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1644 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1645 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1646 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 1647 1648 enum fw_ri_type { 1649 FW_RI_TYPE_INIT, 1650 FW_RI_TYPE_FINI, 1651 FW_RI_TYPE_TERMINATE 1652 }; 1653 1654 enum fw_ri_init_p2ptype { 1655 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 1656 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 1657 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 1658 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 1659 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 1660 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 1661 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 1662 }; 1663 1664 struct fw_ri_wr { 1665 __be32 op_compl; 1666 __be32 flowid_len16; 1667 __u64 cookie; 1668 union fw_ri { 1669 struct fw_ri_init { 1670 __u8 type; 1671 __u8 mpareqbit_p2ptype; 1672 __u8 r4[2]; 1673 __u8 mpa_attrs; 1674 __u8 qp_caps; 1675 __be16 nrqe; 1676 __be32 pdid; 1677 __be32 qpid; 1678 __be32 sq_eqid; 1679 __be32 rq_eqid; 1680 __be32 scqid; 1681 __be32 rcqid; 1682 __be32 ord_max; 1683 __be32 ird_max; 1684 __be32 iss; 1685 __be32 irs; 1686 __be32 hwrqsize; 1687 __be32 hwrqaddr; 1688 __be64 r5; 1689 union fw_ri_init_p2p { 1690 struct fw_ri_rdma_write_wr write; 1691 struct fw_ri_rdma_read_wr read; 1692 struct fw_ri_send_wr send; 1693 } u; 1694 } init; 1695 struct fw_ri_fini { 1696 __u8 type; 1697 __u8 r3[7]; 1698 __be64 r4; 1699 } fini; 1700 struct fw_ri_terminate { 1701 __u8 type; 1702 __u8 r3[3]; 1703 __be32 immdlen; 1704 __u8 termmsg[40]; 1705 } terminate; 1706 } u; 1707 }; 1708 1709 #define S_FW_RI_WR_MPAREQBIT 7 1710 #define M_FW_RI_WR_MPAREQBIT 0x1 1711 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 1712 #define G_FW_RI_WR_MPAREQBIT(x) \ 1713 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 1714 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 1715 1716 #define S_FW_RI_WR_0BRRBIT 6 1717 #define M_FW_RI_WR_0BRRBIT 0x1 1718 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 1719 #define G_FW_RI_WR_0BRRBIT(x) \ 1720 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 1721 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 1722 1723 #define S_FW_RI_WR_P2PTYPE 0 1724 #define M_FW_RI_WR_P2PTYPE 0xf 1725 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1726 #define G_FW_RI_WR_P2PTYPE(x) \ 1727 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1728 1729 /****************************************************************************** 1730 * F O i S C S I W O R K R E Q U E S T s 1731 *********************************************/ 1732 1733 #define FW_FOISCSI_NAME_MAX_LEN 224 1734 #define FW_FOISCSI_ALIAS_MAX_LEN 224 1735 #define FW_FOISCSI_MAX_CHAP_NAME_LEN 64 1736 #define FW_FOISCSI_INIT_NODE_MAX 8 1737 1738 enum fw_chnet_ifconf_wr_subop { 1739 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 1740 1741 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 1742 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 1743 1744 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 1745 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 1746 1747 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 1748 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 1749 1750 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 1751 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 1752 1753 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 1754 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 1755 1756 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 1757 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 1758 1759 FW_CHNET_IFCONF_WR_SUBOP_MAX, 1760 }; 1761 1762 struct fw_chnet_ifconf_wr { 1763 __be32 op_compl; 1764 __be32 flowid_len16; 1765 __be64 cookie; 1766 __be32 if_flowid; 1767 __u8 idx; 1768 __u8 subop; 1769 __u8 retval; 1770 __u8 r2; 1771 __be64 r3; 1772 struct fw_chnet_ifconf_params { 1773 __be32 r0; 1774 __be16 vlanid; 1775 __be16 mtu; 1776 union fw_chnet_ifconf_addr_type { 1777 struct fw_chnet_ifconf_ipv4 { 1778 __be32 addr; 1779 __be32 mask; 1780 __be32 router; 1781 __be32 r0; 1782 __be64 r1; 1783 } ipv4; 1784 struct fw_chnet_ifconf_ipv6 { 1785 __be64 linklocal_lo; 1786 __be64 linklocal_hi; 1787 __be64 router_hi; 1788 __be64 router_lo; 1789 __be64 aconf_hi; 1790 __be64 aconf_lo; 1791 __be64 linklocal_aconf_hi; 1792 __be64 linklocal_aconf_lo; 1793 __be64 router_aconf_hi; 1794 __be64 router_aconf_lo; 1795 __be64 r0; 1796 } ipv6; 1797 } in_attr; 1798 } param; 1799 }; 1800 1801 enum fw_foiscsi_session_type { 1802 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 1803 FW_FOISCSI_SESSION_TYPE_NORMAL, 1804 }; 1805 1806 enum fw_foiscsi_auth_policy { 1807 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 1808 FW_FOISCSI_AUTH_POLICY_MUTUAL, 1809 }; 1810 1811 enum fw_foiscsi_auth_method { 1812 FW_FOISCSI_AUTH_METHOD_NONE = 0, 1813 FW_FOISCSI_AUTH_METHOD_CHAP, 1814 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 1815 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 1816 }; 1817 1818 enum fw_foiscsi_digest_type { 1819 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 1820 FW_FOISCSI_DIGEST_TYPE_CRC32, 1821 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 1822 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 1823 }; 1824 1825 enum fw_foiscsi_wr_subop { 1826 FW_FOISCSI_WR_SUBOP_ADD = 1, 1827 FW_FOISCSI_WR_SUBOP_DEL = 2, 1828 FW_FOISCSI_WR_SUBOP_MOD = 4, 1829 }; 1830 1831 enum fw_foiscsi_ctrl_state { 1832 FW_FOISCSI_CTRL_STATE_FREE = 0, 1833 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 1834 FW_FOISCSI_CTRL_STATE_FAILED, 1835 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 1836 FW_FOISCSI_CTRL_STATE_REDIRECT, 1837 }; 1838 1839 struct fw_rdev_wr { 1840 __be32 op_to_immdlen; 1841 __be32 alloc_to_len16; 1842 __be64 cookie; 1843 __u8 protocol; 1844 __u8 event_cause; 1845 __u8 cur_state; 1846 __u8 prev_state; 1847 __be32 flags_to_assoc_flowid; 1848 union rdev_entry { 1849 struct fcoe_rdev_entry { 1850 __be32 flowid; 1851 __u8 protocol; 1852 __u8 event_cause; 1853 __u8 flags; 1854 __u8 rjt_reason; 1855 __u8 cur_login_st; 1856 __u8 prev_login_st; 1857 __be16 rcv_fr_sz; 1858 __u8 rd_xfer_rdy_to_rport_type; 1859 __u8 vft_to_qos; 1860 __u8 org_proc_assoc_to_acc_rsp_code; 1861 __u8 enh_disc_to_tgt; 1862 __u8 wwnn[8]; 1863 __u8 wwpn[8]; 1864 __be16 iqid; 1865 __u8 fc_oui[3]; 1866 __u8 r_id[3]; 1867 } fcoe_rdev; 1868 struct iscsi_rdev_entry { 1869 __be32 flowid; 1870 __u8 protocol; 1871 __u8 event_cause; 1872 __u8 flags; 1873 __u8 r3; 1874 __be16 iscsi_opts; 1875 __be16 tcp_opts; 1876 __be16 ip_opts; 1877 __be16 max_rcv_len; 1878 __be16 max_snd_len; 1879 __be16 first_brst_len; 1880 __be16 max_brst_len; 1881 __be16 r4; 1882 __be16 def_time2wait; 1883 __be16 def_time2ret; 1884 __be16 nop_out_intrvl; 1885 __be16 non_scsi_to; 1886 __be16 isid; 1887 __be16 tsid; 1888 __be16 port; 1889 __be16 tpgt; 1890 __u8 r5[6]; 1891 __be16 iqid; 1892 } iscsi_rdev; 1893 } u; 1894 }; 1895 1896 #define S_FW_RDEV_WR_IMMDLEN 0 1897 #define M_FW_RDEV_WR_IMMDLEN 0xff 1898 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 1899 #define G_FW_RDEV_WR_IMMDLEN(x) \ 1900 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 1901 1902 #define S_FW_RDEV_WR_ALLOC 31 1903 #define M_FW_RDEV_WR_ALLOC 0x1 1904 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 1905 #define G_FW_RDEV_WR_ALLOC(x) \ 1906 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 1907 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 1908 1909 #define S_FW_RDEV_WR_FREE 30 1910 #define M_FW_RDEV_WR_FREE 0x1 1911 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 1912 #define G_FW_RDEV_WR_FREE(x) \ 1913 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 1914 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 1915 1916 #define S_FW_RDEV_WR_MODIFY 29 1917 #define M_FW_RDEV_WR_MODIFY 0x1 1918 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 1919 #define G_FW_RDEV_WR_MODIFY(x) \ 1920 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 1921 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 1922 1923 #define S_FW_RDEV_WR_FLOWID 8 1924 #define M_FW_RDEV_WR_FLOWID 0xfffff 1925 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 1926 #define G_FW_RDEV_WR_FLOWID(x) \ 1927 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 1928 1929 #define S_FW_RDEV_WR_LEN16 0 1930 #define M_FW_RDEV_WR_LEN16 0xff 1931 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 1932 #define G_FW_RDEV_WR_LEN16(x) \ 1933 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 1934 1935 #define S_FW_RDEV_WR_FLAGS 24 1936 #define M_FW_RDEV_WR_FLAGS 0xff 1937 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 1938 #define G_FW_RDEV_WR_FLAGS(x) \ 1939 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 1940 1941 #define S_FW_RDEV_WR_GET_NEXT 20 1942 #define M_FW_RDEV_WR_GET_NEXT 0xf 1943 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 1944 #define G_FW_RDEV_WR_GET_NEXT(x) \ 1945 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 1946 1947 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 1948 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 1949 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 1950 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 1951 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 1952 1953 #define S_FW_RDEV_WR_RJT 7 1954 #define M_FW_RDEV_WR_RJT 0x1 1955 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 1956 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 1957 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 1958 1959 #define S_FW_RDEV_WR_REASON 0 1960 #define M_FW_RDEV_WR_REASON 0x7f 1961 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 1962 #define G_FW_RDEV_WR_REASON(x) \ 1963 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 1964 1965 #define S_FW_RDEV_WR_RD_XFER_RDY 7 1966 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 1967 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 1968 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 1969 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 1970 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 1971 1972 #define S_FW_RDEV_WR_WR_XFER_RDY 6 1973 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 1974 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 1975 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 1976 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 1977 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 1978 1979 #define S_FW_RDEV_WR_FC_SP 5 1980 #define M_FW_RDEV_WR_FC_SP 0x1 1981 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 1982 #define G_FW_RDEV_WR_FC_SP(x) \ 1983 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 1984 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 1985 1986 #define S_FW_RDEV_WR_RPORT_TYPE 0 1987 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 1988 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 1989 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 1990 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 1991 1992 #define S_FW_RDEV_WR_VFT 7 1993 #define M_FW_RDEV_WR_VFT 0x1 1994 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 1995 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 1996 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 1997 1998 #define S_FW_RDEV_WR_NPIV 6 1999 #define M_FW_RDEV_WR_NPIV 0x1 2000 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2001 #define G_FW_RDEV_WR_NPIV(x) \ 2002 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2003 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2004 2005 #define S_FW_RDEV_WR_CLASS 4 2006 #define M_FW_RDEV_WR_CLASS 0x3 2007 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2008 #define G_FW_RDEV_WR_CLASS(x) \ 2009 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2010 2011 #define S_FW_RDEV_WR_SEQ_DEL 3 2012 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2013 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2014 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2015 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2016 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2017 2018 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2019 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2020 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2021 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2022 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2023 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2024 2025 #define S_FW_RDEV_WR_PREF 1 2026 #define M_FW_RDEV_WR_PREF 0x1 2027 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2028 #define G_FW_RDEV_WR_PREF(x) \ 2029 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2030 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2031 2032 #define S_FW_RDEV_WR_QOS 0 2033 #define M_FW_RDEV_WR_QOS 0x1 2034 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2035 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2036 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2037 2038 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2039 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2040 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2041 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2042 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2043 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2044 2045 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2046 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2047 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2048 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2049 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2050 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2051 2052 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2053 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2054 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2055 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2056 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2057 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2058 2059 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2060 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2061 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2062 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2063 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2064 2065 #define S_FW_RDEV_WR_ENH_DISC 7 2066 #define M_FW_RDEV_WR_ENH_DISC 0x1 2067 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2068 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2069 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2070 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2071 2072 #define S_FW_RDEV_WR_REC 6 2073 #define M_FW_RDEV_WR_REC 0x1 2074 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2075 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2076 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2077 2078 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2079 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2080 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2081 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2082 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2083 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2084 2085 #define S_FW_RDEV_WR_RETRY 4 2086 #define M_FW_RDEV_WR_RETRY 0x1 2087 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2088 #define G_FW_RDEV_WR_RETRY(x) \ 2089 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2090 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2091 2092 #define S_FW_RDEV_WR_CONF_CMPL 3 2093 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2094 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2095 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2096 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2097 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2098 2099 #define S_FW_RDEV_WR_DATA_OVLY 2 2100 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2101 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2102 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2103 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2104 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2105 2106 #define S_FW_RDEV_WR_INI 1 2107 #define M_FW_RDEV_WR_INI 0x1 2108 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2109 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2110 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2111 2112 #define S_FW_RDEV_WR_TGT 0 2113 #define M_FW_RDEV_WR_TGT 0x1 2114 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2115 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2116 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2117 2118 struct fw_foiscsi_node_wr { 2119 __be32 op_to_immdlen; 2120 __be32 flowid_len16; 2121 __u64 cookie; 2122 __u8 subop; 2123 __u8 status; 2124 __u8 alias_len; 2125 __u8 iqn_len; 2126 __be32 node_flowid; 2127 __be16 nodeid; 2128 __be16 login_retry; 2129 __be16 retry_timeout; 2130 __be16 r3; 2131 __u8 iqn[224]; 2132 __u8 alias[224]; 2133 }; 2134 2135 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2136 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2137 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2138 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2139 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2140 2141 struct fw_foiscsi_ctrl_wr { 2142 __be32 op_compl; 2143 __be32 flowid_len16; 2144 __u64 cookie; 2145 __u8 subop; 2146 __u8 status; 2147 __u8 ctrl_state; 2148 __u8 io_state; 2149 __be32 node_id; 2150 __be32 ctrl_id; 2151 __be32 io_id; 2152 struct fw_foiscsi_sess_attr { 2153 __be32 sess_type_to_erl; 2154 __be16 max_conn; 2155 __be16 max_r2t; 2156 __be16 time2wait; 2157 __be16 time2retain; 2158 __be32 max_burst; 2159 __be32 first_burst; 2160 __be32 r1; 2161 } sess_attr; 2162 struct fw_foiscsi_conn_attr { 2163 __be32 hdigest_to_auth_policy; 2164 __be32 max_rcv_dsl; 2165 __be32 ping_tmo; 2166 __be16 dst_port; 2167 __be16 src_port; 2168 union fw_foiscsi_conn_attr_addr { 2169 struct fw_foiscsi_conn_attr_ipv6 { 2170 __be64 dst_addr[2]; 2171 __be64 src_addr[2]; 2172 } ipv6_addr; 2173 struct fw_foiscsi_conn_attr_ipv4 { 2174 __be32 dst_addr; 2175 __be32 src_addr; 2176 } ipv4_addr; 2177 } u; 2178 } conn_attr; 2179 __u8 tgt_name_len; 2180 __u8 r3[7]; 2181 __u8 tgt_name[224]; 2182 }; 2183 2184 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2185 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2186 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2187 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2188 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2189 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2190 2191 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2192 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2193 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2194 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2195 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2196 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2197 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2198 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2199 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2200 2201 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2202 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2203 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2204 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2205 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2206 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2207 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2208 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2209 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2210 2211 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2212 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2213 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2214 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2215 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2216 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2217 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2218 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2219 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2220 2221 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2222 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2223 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2224 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2225 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2226 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2227 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2228 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2229 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2230 2231 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2232 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2233 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2234 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2235 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2236 2237 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2238 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2239 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2240 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2241 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2242 2243 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2244 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2245 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2246 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2247 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2248 2249 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2250 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2251 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2252 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2253 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2254 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2255 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2256 2257 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2258 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2259 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2260 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2261 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2262 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2263 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2264 2265 struct fw_foiscsi_chap_wr { 2266 __be32 op_compl; 2267 __be32 flowid_len16; 2268 __u64 cookie; 2269 __u8 status; 2270 __u8 id_len; 2271 __u8 sec_len; 2272 __u8 tgt_id_len; 2273 __u8 tgt_sec_len; 2274 __be16 node_id; 2275 __u8 r2; 2276 __u8 chap_id[64]; 2277 __u8 chap_sec[16]; 2278 __u8 tgt_id[64]; 2279 __u8 tgt_sec[16]; 2280 }; 2281 2282 /****************************************************************************** 2283 * F O F C O E W O R K R E Q U E S T s 2284 *******************************************/ 2285 2286 struct fw_fcoe_els_ct_wr { 2287 __be32 op_immdlen; 2288 __be32 flowid_len16; 2289 __be64 cookie; 2290 __be16 iqid; 2291 __u8 tmo_val; 2292 __u8 els_ct_type; 2293 __u8 ctl_pri; 2294 __u8 cp_en_class; 2295 __be16 xfer_cnt; 2296 __u8 fl_to_sp; 2297 __u8 l_id[3]; 2298 __u8 r5; 2299 __u8 r_id[3]; 2300 __be64 rsp_dmaaddr; 2301 __be32 rsp_dmalen; 2302 __be32 r6; 2303 }; 2304 2305 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2306 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2307 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2308 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2309 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2310 2311 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2312 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2313 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2314 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2315 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2316 2317 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2318 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2319 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2320 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2321 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2322 2323 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 2324 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2325 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2326 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2327 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2328 2329 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2330 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2331 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2332 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2333 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2334 2335 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 2336 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2337 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2338 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2339 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2340 2341 #define S_FW_FCOE_ELS_CT_WR_FL 2 2342 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 2343 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2344 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2345 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2346 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2347 2348 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 2349 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2350 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2351 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2352 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2353 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2354 2355 #define S_FW_FCOE_ELS_CT_WR_SP 0 2356 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 2357 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2358 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2359 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2360 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2361 2362 /****************************************************************************** 2363 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2364 *****************************************************************************/ 2365 2366 struct fw_scsi_write_wr { 2367 __be32 op_immdlen; 2368 __be32 flowid_len16; 2369 __be64 cookie; 2370 __be16 iqid; 2371 __u8 tmo_val; 2372 __u8 use_xfer_cnt; 2373 union fw_scsi_write_priv { 2374 struct fcoe_write_priv { 2375 __u8 ctl_pri; 2376 __u8 cp_en_class; 2377 __u8 r3_lo[2]; 2378 } fcoe; 2379 struct iscsi_write_priv { 2380 __u8 r3[4]; 2381 } iscsi; 2382 } u; 2383 __be32 xfer_cnt; 2384 __be32 ini_xfer_cnt; 2385 __be64 rsp_dmaaddr; 2386 __be32 rsp_dmalen; 2387 __be32 r4; 2388 }; 2389 2390 #define S_FW_SCSI_WRITE_WR_OPCODE 24 2391 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2392 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2393 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2394 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2395 2396 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2397 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2398 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2399 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2400 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2401 2402 #define S_FW_SCSI_WRITE_WR_FLOWID 8 2403 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2404 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2405 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2406 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2407 2408 #define S_FW_SCSI_WRITE_WR_LEN16 0 2409 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 2410 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2411 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2412 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2413 2414 #define S_FW_SCSI_WRITE_WR_CP_EN 6 2415 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2416 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2417 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2418 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2419 2420 #define S_FW_SCSI_WRITE_WR_CLASS 4 2421 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 2422 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2423 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2424 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 2425 2426 struct fw_scsi_read_wr { 2427 __be32 op_immdlen; 2428 __be32 flowid_len16; 2429 __be64 cookie; 2430 __be16 iqid; 2431 __u8 tmo_val; 2432 __u8 use_xfer_cnt; 2433 union fw_scsi_read_priv { 2434 struct fcoe_read_priv { 2435 __u8 ctl_pri; 2436 __u8 cp_en_class; 2437 __u8 r3_lo[2]; 2438 } fcoe; 2439 struct iscsi_read_priv { 2440 __u8 r3[4]; 2441 } iscsi; 2442 } u; 2443 __be32 xfer_cnt; 2444 __be32 ini_xfer_cnt; 2445 __be64 rsp_dmaaddr; 2446 __be32 rsp_dmalen; 2447 __be32 r4; 2448 }; 2449 2450 #define S_FW_SCSI_READ_WR_OPCODE 24 2451 #define M_FW_SCSI_READ_WR_OPCODE 0xff 2452 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2453 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 2454 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2455 2456 #define S_FW_SCSI_READ_WR_IMMDLEN 0 2457 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2458 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2459 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2460 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2461 2462 #define S_FW_SCSI_READ_WR_FLOWID 8 2463 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2464 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2465 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 2466 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2467 2468 #define S_FW_SCSI_READ_WR_LEN16 0 2469 #define M_FW_SCSI_READ_WR_LEN16 0xff 2470 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2471 #define G_FW_SCSI_READ_WR_LEN16(x) \ 2472 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2473 2474 #define S_FW_SCSI_READ_WR_CP_EN 6 2475 #define M_FW_SCSI_READ_WR_CP_EN 0x3 2476 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2477 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 2478 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 2479 2480 #define S_FW_SCSI_READ_WR_CLASS 4 2481 #define M_FW_SCSI_READ_WR_CLASS 0x3 2482 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 2483 #define G_FW_SCSI_READ_WR_CLASS(x) \ 2484 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 2485 2486 struct fw_scsi_cmd_wr { 2487 __be32 op_immdlen; 2488 __be32 flowid_len16; 2489 __be64 cookie; 2490 __be16 iqid; 2491 __u8 tmo_val; 2492 __u8 r3; 2493 union fw_scsi_cmd_priv { 2494 struct fcoe_cmd_priv { 2495 __u8 ctl_pri; 2496 __u8 cp_en_class; 2497 __u8 r4_lo[2]; 2498 } fcoe; 2499 struct iscsi_cmd_priv { 2500 __u8 r4[4]; 2501 } iscsi; 2502 } u; 2503 __u8 r5[8]; 2504 __be64 rsp_dmaaddr; 2505 __be32 rsp_dmalen; 2506 __be32 r6; 2507 }; 2508 2509 #define S_FW_SCSI_CMD_WR_OPCODE 24 2510 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 2511 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 2512 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 2513 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 2514 2515 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 2516 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 2517 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 2518 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 2519 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 2520 2521 #define S_FW_SCSI_CMD_WR_FLOWID 8 2522 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 2523 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 2524 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 2525 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 2526 2527 #define S_FW_SCSI_CMD_WR_LEN16 0 2528 #define M_FW_SCSI_CMD_WR_LEN16 0xff 2529 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 2530 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 2531 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 2532 2533 #define S_FW_SCSI_CMD_WR_CP_EN 6 2534 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 2535 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 2536 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 2537 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 2538 2539 #define S_FW_SCSI_CMD_WR_CLASS 4 2540 #define M_FW_SCSI_CMD_WR_CLASS 0x3 2541 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 2542 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 2543 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 2544 2545 struct fw_scsi_abrt_cls_wr { 2546 __be32 op_immdlen; 2547 __be32 flowid_len16; 2548 __be64 cookie; 2549 __be16 iqid; 2550 __u8 tmo_val; 2551 __u8 sub_opcode_to_chk_all_io; 2552 __u8 r3[4]; 2553 __be64 t_cookie; 2554 }; 2555 2556 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 2557 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 2558 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 2559 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 2560 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 2561 2562 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 2563 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 2564 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2565 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2566 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2567 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2568 2569 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 2570 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 2571 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 2572 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 2573 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 2574 2575 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 2576 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 2577 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 2578 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 2579 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 2580 2581 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 2582 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 2583 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2584 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2585 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2586 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 2587 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2588 2589 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 2590 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 2591 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 2592 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 2593 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 2594 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 2595 2596 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 2597 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 2598 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2599 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2600 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2601 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 2602 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2603 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 2604 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 2605 2606 struct fw_scsi_tgt_acc_wr { 2607 __be32 op_immdlen; 2608 __be32 flowid_len16; 2609 __be64 cookie; 2610 __be16 iqid; 2611 __u8 r3; 2612 __u8 use_burst_len; 2613 union fw_scsi_tgt_acc_priv { 2614 struct fcoe_tgt_acc_priv { 2615 __u8 ctl_pri; 2616 __u8 cp_en_class; 2617 __u8 r4_lo[2]; 2618 } fcoe; 2619 struct iscsi_tgt_acc_priv { 2620 __u8 r4[4]; 2621 } iscsi; 2622 } u; 2623 __be32 burst_len; 2624 __be32 rel_off; 2625 __be64 r5; 2626 __be32 r6; 2627 __be32 tot_xfer_len; 2628 }; 2629 2630 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 2631 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 2632 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 2633 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 2634 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 2635 2636 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 2637 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 2638 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2639 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 2640 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2641 2642 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 2643 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 2644 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 2645 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 2646 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 2647 2648 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 2649 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 2650 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 2651 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 2652 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 2653 2654 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 2655 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 2656 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 2657 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 2658 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 2659 2660 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 2661 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 2662 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 2663 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 2664 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 2665 2666 struct fw_scsi_tgt_xmit_wr { 2667 __be32 op_immdlen; 2668 __be32 flowid_len16; 2669 __be64 cookie; 2670 __be16 iqid; 2671 __u8 auto_rsp; 2672 __u8 use_xfer_cnt; 2673 union fw_scsi_tgt_xmit_priv { 2674 struct fcoe_tgt_xmit_priv { 2675 __u8 ctl_pri; 2676 __u8 cp_en_class; 2677 __u8 r3_lo[2]; 2678 } fcoe; 2679 struct iscsi_tgt_xmit_priv { 2680 __u8 r3[4]; 2681 } iscsi; 2682 } u; 2683 __be32 xfer_cnt; 2684 __be32 r4; 2685 __be64 r5; 2686 __be32 r6; 2687 __be32 tot_xfer_len; 2688 }; 2689 2690 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 2691 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 2692 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 2693 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 2694 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 2695 2696 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 2697 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 2698 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2699 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2700 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2701 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2702 2703 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 2704 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 2705 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 2706 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 2707 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 2708 2709 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 2710 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 2711 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 2712 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 2713 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 2714 2715 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 2716 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 2717 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 2718 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 2719 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 2720 2721 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 2722 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 2723 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 2724 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 2725 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 2726 2727 struct fw_scsi_tgt_rsp_wr { 2728 __be32 op_immdlen; 2729 __be32 flowid_len16; 2730 __be64 cookie; 2731 __be16 iqid; 2732 __u8 r3[2]; 2733 union fw_scsi_tgt_rsp_priv { 2734 struct fcoe_tgt_rsp_priv { 2735 __u8 ctl_pri; 2736 __u8 cp_en_class; 2737 __u8 r4_lo[2]; 2738 } fcoe; 2739 struct iscsi_tgt_rsp_priv { 2740 __u8 r4[4]; 2741 } iscsi; 2742 } u; 2743 __u8 r5[8]; 2744 }; 2745 2746 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 2747 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 2748 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 2749 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 2750 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 2751 2752 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 2753 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 2754 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2755 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 2756 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2757 2758 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 2759 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 2760 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 2761 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 2762 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 2763 2764 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 2765 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 2766 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 2767 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 2768 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 2769 2770 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 2771 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 2772 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 2773 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 2774 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 2775 2776 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 2777 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 2778 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 2779 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 2780 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 2781 2782 /****************************************************************************** 2783 * C O M M A N D s 2784 *********************/ 2785 2786 /* 2787 * The maximum length of time, in miliseconds, that we expect any firmware 2788 * command to take to execute and return a reply to the host. The RESET 2789 * and INITIALIZE commands can take a fair amount of time to execute but 2790 * most execute in far less time than this maximum. This constant is used 2791 * by host software to determine how long to wait for a firmware command 2792 * reply before declaring the firmware as dead/unreachable ... 2793 */ 2794 #define FW_CMD_MAX_TIMEOUT 10000 2795 2796 /* 2797 * If a host driver does a HELLO and discovers that there's already a MASTER 2798 * selected, we may have to wait for that MASTER to finish issuing RESET, 2799 * configuration and INITIALIZE commands. Also, there's a possibility that 2800 * our own HELLO may get lost if it happens right as the MASTER is issuign a 2801 * RESET command, so we need to be willing to make a few retries of our HELLO. 2802 */ 2803 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 2804 #define FW_CMD_HELLO_RETRIES 3 2805 2806 enum fw_cmd_opcodes { 2807 FW_LDST_CMD = 0x01, 2808 FW_RESET_CMD = 0x03, 2809 FW_HELLO_CMD = 0x04, 2810 FW_BYE_CMD = 0x05, 2811 FW_INITIALIZE_CMD = 0x06, 2812 FW_CAPS_CONFIG_CMD = 0x07, 2813 FW_PARAMS_CMD = 0x08, 2814 FW_PFVF_CMD = 0x09, 2815 FW_IQ_CMD = 0x10, 2816 FW_EQ_MNGT_CMD = 0x11, 2817 FW_EQ_ETH_CMD = 0x12, 2818 FW_EQ_CTRL_CMD = 0x13, 2819 FW_EQ_OFLD_CMD = 0x21, 2820 FW_VI_CMD = 0x14, 2821 FW_VI_MAC_CMD = 0x15, 2822 FW_VI_RXMODE_CMD = 0x16, 2823 FW_VI_ENABLE_CMD = 0x17, 2824 FW_VI_STATS_CMD = 0x1a, 2825 FW_ACL_MAC_CMD = 0x18, 2826 FW_ACL_VLAN_CMD = 0x19, 2827 FW_PORT_CMD = 0x1b, 2828 FW_PORT_STATS_CMD = 0x1c, 2829 FW_PORT_LB_STATS_CMD = 0x1d, 2830 FW_PORT_TRACE_CMD = 0x1e, 2831 FW_PORT_TRACE_MMAP_CMD = 0x1f, 2832 FW_RSS_IND_TBL_CMD = 0x20, 2833 FW_RSS_GLB_CONFIG_CMD = 0x22, 2834 FW_RSS_VI_CONFIG_CMD = 0x23, 2835 FW_SCHED_CMD = 0x24, 2836 FW_DEVLOG_CMD = 0x25, 2837 FW_WATCHDOG_CMD = 0x27, 2838 FW_CLIP_CMD = 0x28, 2839 FW_CHNET_IFACE_CMD = 0x26, 2840 FW_FCOE_RES_INFO_CMD = 0x31, 2841 FW_FCOE_LINK_CMD = 0x32, 2842 FW_FCOE_VNP_CMD = 0x33, 2843 FW_FCOE_SPARAMS_CMD = 0x35, 2844 FW_FCOE_STATS_CMD = 0x37, 2845 FW_FCOE_FCF_CMD = 0x38, 2846 FW_LASTC2E_CMD = 0x40, 2847 FW_ERROR_CMD = 0x80, 2848 FW_DEBUG_CMD = 0x81, 2849 }; 2850 2851 enum fw_cmd_cap { 2852 FW_CMD_CAP_PF = 0x01, 2853 FW_CMD_CAP_DMAQ = 0x02, 2854 FW_CMD_CAP_PORT = 0x04, 2855 FW_CMD_CAP_PORTPROMISC = 0x08, 2856 FW_CMD_CAP_PORTSTATS = 0x10, 2857 FW_CMD_CAP_VF = 0x80, 2858 }; 2859 2860 /* 2861 * Generic command header flit0 2862 */ 2863 struct fw_cmd_hdr { 2864 __be32 hi; 2865 __be32 lo; 2866 }; 2867 2868 #define S_FW_CMD_OP 24 2869 #define M_FW_CMD_OP 0xff 2870 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 2871 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 2872 2873 #define S_FW_CMD_REQUEST 23 2874 #define M_FW_CMD_REQUEST 0x1 2875 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 2876 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 2877 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 2878 2879 #define S_FW_CMD_READ 22 2880 #define M_FW_CMD_READ 0x1 2881 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 2882 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 2883 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 2884 2885 #define S_FW_CMD_WRITE 21 2886 #define M_FW_CMD_WRITE 0x1 2887 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 2888 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 2889 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 2890 2891 #define S_FW_CMD_EXEC 20 2892 #define M_FW_CMD_EXEC 0x1 2893 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 2894 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 2895 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 2896 2897 #define S_FW_CMD_RAMASK 20 2898 #define M_FW_CMD_RAMASK 0xf 2899 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 2900 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 2901 2902 #define S_FW_CMD_RETVAL 8 2903 #define M_FW_CMD_RETVAL 0xff 2904 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 2905 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 2906 2907 #define S_FW_CMD_LEN16 0 2908 #define M_FW_CMD_LEN16 0xff 2909 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 2910 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 2911 2912 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 2913 2914 /* 2915 * address spaces 2916 */ 2917 enum fw_ldst_addrspc { 2918 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 2919 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 2920 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 2921 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 2922 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 2923 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 2924 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 2925 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 2926 FW_LDST_ADDRSPC_MDIO = 0x0018, 2927 FW_LDST_ADDRSPC_MPS = 0x0020, 2928 FW_LDST_ADDRSPC_FUNC = 0x0028, 2929 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 2930 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, 2931 FW_LDST_ADDRSPC_LE = 0x0030, 2932 }; 2933 2934 /* 2935 * MDIO VSC8634 register access control field 2936 */ 2937 enum fw_ldst_mdio_vsc8634_aid { 2938 FW_LDST_MDIO_VS_STANDARD, 2939 FW_LDST_MDIO_VS_EXTENDED, 2940 FW_LDST_MDIO_VS_GPIO 2941 }; 2942 2943 enum fw_ldst_mps_fid { 2944 FW_LDST_MPS_ATRB, 2945 FW_LDST_MPS_RPLC 2946 }; 2947 2948 enum fw_ldst_func_access_ctl { 2949 FW_LDST_FUNC_ACC_CTL_VIID, 2950 FW_LDST_FUNC_ACC_CTL_FID 2951 }; 2952 2953 enum fw_ldst_func_mod_index { 2954 FW_LDST_FUNC_MPS 2955 }; 2956 2957 struct fw_ldst_cmd { 2958 __be32 op_to_addrspace; 2959 __be32 cycles_to_len16; 2960 union fw_ldst { 2961 struct fw_ldst_addrval { 2962 __be32 addr; 2963 __be32 val; 2964 } addrval; 2965 struct fw_ldst_idctxt { 2966 __be32 physid; 2967 __be32 msg_ctxtflush; 2968 __be32 ctxt_data7; 2969 __be32 ctxt_data6; 2970 __be32 ctxt_data5; 2971 __be32 ctxt_data4; 2972 __be32 ctxt_data3; 2973 __be32 ctxt_data2; 2974 __be32 ctxt_data1; 2975 __be32 ctxt_data0; 2976 } idctxt; 2977 struct fw_ldst_mdio { 2978 __be16 paddr_mmd; 2979 __be16 raddr; 2980 __be16 vctl; 2981 __be16 rval; 2982 } mdio; 2983 struct fw_ldst_mps { 2984 __be16 fid_ctl; 2985 __be16 rplcpf_pkd; 2986 __be32 rplc127_96; 2987 __be32 rplc95_64; 2988 __be32 rplc63_32; 2989 __be32 rplc31_0; 2990 __be32 atrb; 2991 __be16 vlan[16]; 2992 } mps; 2993 struct fw_ldst_func { 2994 __u8 access_ctl; 2995 __u8 mod_index; 2996 __be16 ctl_id; 2997 __be32 offset; 2998 __be64 data0; 2999 __be64 data1; 3000 } func; 3001 struct fw_ldst_pcie { 3002 __u8 ctrl_to_fn; 3003 __u8 bnum; 3004 __u8 r; 3005 __u8 ext_r; 3006 __u8 select_naccess; 3007 __u8 pcie_fn; 3008 __be16 nset_pkd; 3009 __be32 data[12]; 3010 } pcie; 3011 struct fw_ldst_i2c { 3012 __u8 pid_pkd; 3013 __u8 base; 3014 __u8 boffset; 3015 __u8 data; 3016 __be32 r9; 3017 } i2c; 3018 struct fw_ldst_le { 3019 __be16 region; 3020 __be16 nval; 3021 __u32 val[12]; 3022 } le; 3023 } u; 3024 }; 3025 3026 #define S_FW_LDST_CMD_ADDRSPACE 0 3027 #define M_FW_LDST_CMD_ADDRSPACE 0xff 3028 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3029 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 3030 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 3031 3032 #define S_FW_LDST_CMD_CYCLES 16 3033 #define M_FW_LDST_CMD_CYCLES 0xffff 3034 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 3035 #define G_FW_LDST_CMD_CYCLES(x) \ 3036 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 3037 3038 #define S_FW_LDST_CMD_MSG 31 3039 #define M_FW_LDST_CMD_MSG 0x1 3040 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 3041 #define G_FW_LDST_CMD_MSG(x) \ 3042 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 3043 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 3044 3045 #define S_FW_LDST_CMD_CTXTFLUSH 30 3046 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 3047 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 3048 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 3049 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 3050 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 3051 3052 #define S_FW_LDST_CMD_PADDR 8 3053 #define M_FW_LDST_CMD_PADDR 0x1f 3054 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 3055 #define G_FW_LDST_CMD_PADDR(x) \ 3056 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 3057 3058 #define S_FW_LDST_CMD_MMD 0 3059 #define M_FW_LDST_CMD_MMD 0x1f 3060 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 3061 #define G_FW_LDST_CMD_MMD(x) \ 3062 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 3063 3064 #define S_FW_LDST_CMD_FID 15 3065 #define M_FW_LDST_CMD_FID 0x1 3066 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 3067 #define G_FW_LDST_CMD_FID(x) \ 3068 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 3069 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 3070 3071 #define S_FW_LDST_CMD_CTL 0 3072 #define M_FW_LDST_CMD_CTL 0x7fff 3073 #define V_FW_LDST_CMD_CTL(x) ((x) << S_FW_LDST_CMD_CTL) 3074 #define G_FW_LDST_CMD_CTL(x) \ 3075 (((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL) 3076 3077 #define S_FW_LDST_CMD_RPLCPF 0 3078 #define M_FW_LDST_CMD_RPLCPF 0xff 3079 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 3080 #define G_FW_LDST_CMD_RPLCPF(x) \ 3081 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 3082 3083 #define S_FW_LDST_CMD_CTRL 7 3084 #define M_FW_LDST_CMD_CTRL 0x1 3085 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 3086 #define G_FW_LDST_CMD_CTRL(x) \ 3087 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 3088 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 3089 3090 #define S_FW_LDST_CMD_LC 4 3091 #define M_FW_LDST_CMD_LC 0x1 3092 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 3093 #define G_FW_LDST_CMD_LC(x) (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 3094 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 3095 3096 #define S_FW_LDST_CMD_AI 3 3097 #define M_FW_LDST_CMD_AI 0x1 3098 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 3099 #define G_FW_LDST_CMD_AI(x) (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 3100 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 3101 3102 #define S_FW_LDST_CMD_FN 0 3103 #define M_FW_LDST_CMD_FN 0x7 3104 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 3105 #define G_FW_LDST_CMD_FN(x) (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 3106 3107 #define S_FW_LDST_CMD_SELECT 4 3108 #define M_FW_LDST_CMD_SELECT 0xf 3109 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 3110 #define G_FW_LDST_CMD_SELECT(x) \ 3111 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 3112 3113 #define S_FW_LDST_CMD_NACCESS 0 3114 #define M_FW_LDST_CMD_NACCESS 0xf 3115 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 3116 #define G_FW_LDST_CMD_NACCESS(x) \ 3117 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 3118 3119 #define S_FW_LDST_CMD_NSET 14 3120 #define M_FW_LDST_CMD_NSET 0x3 3121 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 3122 #define G_FW_LDST_CMD_NSET(x) \ 3123 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 3124 3125 #define S_FW_LDST_CMD_PID 6 3126 #define M_FW_LDST_CMD_PID 0x3 3127 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 3128 #define G_FW_LDST_CMD_PID(x) \ 3129 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 3130 3131 struct fw_reset_cmd { 3132 __be32 op_to_write; 3133 __be32 retval_len16; 3134 __be32 val; 3135 __be32 halt_pkd; 3136 }; 3137 3138 #define S_FW_RESET_CMD_HALT 31 3139 #define M_FW_RESET_CMD_HALT 0x1 3140 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 3141 #define G_FW_RESET_CMD_HALT(x) \ 3142 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 3143 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 3144 3145 enum { 3146 FW_HELLO_CMD_STAGE_OS = 0, 3147 FW_HELLO_CMD_STAGE_PREOS0 = 1, 3148 FW_HELLO_CMD_STAGE_PREOS1 = 2, 3149 FW_HELLO_CMD_STAGE_POSTOS = 3, 3150 }; 3151 3152 struct fw_hello_cmd { 3153 __be32 op_to_write; 3154 __be32 retval_len16; 3155 __be32 err_to_clearinit; 3156 __be32 fwrev; 3157 }; 3158 3159 #define S_FW_HELLO_CMD_ERR 31 3160 #define M_FW_HELLO_CMD_ERR 0x1 3161 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 3162 #define G_FW_HELLO_CMD_ERR(x) \ 3163 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 3164 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 3165 3166 #define S_FW_HELLO_CMD_INIT 30 3167 #define M_FW_HELLO_CMD_INIT 0x1 3168 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 3169 #define G_FW_HELLO_CMD_INIT(x) \ 3170 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 3171 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 3172 3173 #define S_FW_HELLO_CMD_MASTERDIS 29 3174 #define M_FW_HELLO_CMD_MASTERDIS 0x1 3175 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 3176 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 3177 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 3178 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 3179 3180 #define S_FW_HELLO_CMD_MASTERFORCE 28 3181 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 3182 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 3183 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 3184 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 3185 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 3186 3187 #define S_FW_HELLO_CMD_MBMASTER 24 3188 #define M_FW_HELLO_CMD_MBMASTER 0xf 3189 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 3190 #define G_FW_HELLO_CMD_MBMASTER(x) \ 3191 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 3192 3193 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 3194 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 3195 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 3196 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 3197 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 3198 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 3199 3200 #define S_FW_HELLO_CMD_MBASYNCNOT 20 3201 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 3202 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 3203 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 3204 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 3205 3206 #define S_FW_HELLO_CMD_STAGE 17 3207 #define M_FW_HELLO_CMD_STAGE 0x7 3208 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 3209 #define G_FW_HELLO_CMD_STAGE(x) \ 3210 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 3211 3212 #define S_FW_HELLO_CMD_CLEARINIT 16 3213 #define M_FW_HELLO_CMD_CLEARINIT 0x1 3214 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 3215 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 3216 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 3217 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 3218 3219 struct fw_bye_cmd { 3220 __be32 op_to_write; 3221 __be32 retval_len16; 3222 __be64 r3; 3223 }; 3224 3225 struct fw_initialize_cmd { 3226 __be32 op_to_write; 3227 __be32 retval_len16; 3228 __be64 r3; 3229 }; 3230 3231 enum fw_caps_config_hm { 3232 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 3233 FW_CAPS_CONFIG_HM_PL = 0x00000002, 3234 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 3235 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 3236 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 3237 FW_CAPS_CONFIG_HM_TP = 0x00000020, 3238 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 3239 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 3240 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 3241 FW_CAPS_CONFIG_HM_MC = 0x00000200, 3242 FW_CAPS_CONFIG_HM_LE = 0x00000400, 3243 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 3244 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 3245 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 3246 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 3247 FW_CAPS_CONFIG_HM_MI = 0x00008000, 3248 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 3249 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 3250 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 3251 FW_CAPS_CONFIG_HM_MA = 0x00080000, 3252 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 3253 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 3254 FW_CAPS_CONFIG_HM_UART = 0x00400000, 3255 FW_CAPS_CONFIG_HM_SF = 0x00800000, 3256 }; 3257 3258 /* 3259 * The VF Register Map. 3260 * 3261 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 3262 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 3263 * the Slice to Module Map Table (see below) in the Physical Function Register 3264 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 3265 * and Offset registers in the PF Register Map. The MBDATA base address is 3266 * quite constrained as it determines the Mailbox Data addresses for both PFs 3267 * and VFs, and therefore must fit in both the VF and PF Register Maps without 3268 * overlapping other registers. 3269 */ 3270 #define FW_T4VF_SGE_BASE_ADDR 0x0000 3271 #define FW_T4VF_MPS_BASE_ADDR 0x0100 3272 #define FW_T4VF_PL_BASE_ADDR 0x0200 3273 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 3274 #define FW_T4VF_CIM_BASE_ADDR 0x0300 3275 3276 #define FW_T4VF_REGMAP_START 0x0000 3277 #define FW_T4VF_REGMAP_SIZE 0x0400 3278 3279 enum fw_caps_config_nbm { 3280 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 3281 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 3282 }; 3283 3284 enum fw_caps_config_link { 3285 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 3286 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 3287 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 3288 }; 3289 3290 enum fw_caps_config_switch { 3291 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 3292 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 3293 }; 3294 3295 enum fw_caps_config_nic { 3296 FW_CAPS_CONFIG_NIC = 0x00000001, 3297 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 3298 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 3299 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 3300 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 3301 }; 3302 3303 enum fw_caps_config_toe { 3304 FW_CAPS_CONFIG_TOE = 0x00000001, 3305 }; 3306 3307 enum fw_caps_config_rdma { 3308 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 3309 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 3310 }; 3311 3312 enum fw_caps_config_iscsi { 3313 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 3314 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 3315 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 3316 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 3317 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 3318 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 3319 }; 3320 3321 enum fw_caps_config_fcoe { 3322 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 3323 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 3324 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 3325 }; 3326 3327 enum fw_memtype_cf { 3328 FW_MEMTYPE_CF_EDC0 = 0x0, 3329 FW_MEMTYPE_CF_EDC1 = 0x1, 3330 FW_MEMTYPE_CF_EXTMEM = 0x2, 3331 FW_MEMTYPE_CF_FLASH = 0x4, 3332 FW_MEMTYPE_CF_INTERNAL = 0x5, 3333 }; 3334 3335 struct fw_caps_config_cmd { 3336 __be32 op_to_write; 3337 __be32 cfvalid_to_len16; 3338 __be32 r2; 3339 __be32 hwmbitmap; 3340 __be16 nbmcaps; 3341 __be16 linkcaps; 3342 __be16 switchcaps; 3343 __be16 r3; 3344 __be16 niccaps; 3345 __be16 toecaps; 3346 __be16 rdmacaps; 3347 __be16 r4; 3348 __be16 iscsicaps; 3349 __be16 fcoecaps; 3350 __be32 cfcsum; 3351 __be32 finiver; 3352 __be32 finicsum; 3353 }; 3354 3355 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 3356 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 3357 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 3358 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 3359 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 3360 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 3361 3362 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 3363 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 3364 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3365 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3366 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3367 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 3368 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3369 3370 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 3371 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 3372 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3373 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3374 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3375 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 3376 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3377 3378 /* 3379 * params command mnemonics 3380 */ 3381 enum fw_params_mnem { 3382 FW_PARAMS_MNEM_DEV = 1, /* device params */ 3383 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 3384 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 3385 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 3386 FW_PARAMS_MNEM_LAST 3387 }; 3388 3389 /* 3390 * device parameters 3391 */ 3392 enum fw_params_param_dev { 3393 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 3394 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 3395 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 3396 * allocated by the device's 3397 * Lookup Engine 3398 */ 3399 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 3400 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 3401 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 3402 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 3403 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 3404 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 3405 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 3406 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 3407 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 3408 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 3409 FW_PARAMS_PARAM_DEV_CF = 0x0D, 3410 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 3411 }; 3412 3413 /* 3414 * physical and virtual function parameters 3415 */ 3416 enum fw_params_param_pfvf { 3417 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 3418 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 3419 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 3420 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 3421 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 3422 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 3423 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 3424 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 3425 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 3426 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 3427 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 3428 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 3429 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 3430 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 3431 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 3432 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 3433 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 3434 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 3435 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 3436 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 3437 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 3438 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 3439 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 3440 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 3441 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 3442 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 3443 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 3444 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 3445 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 3446 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 3447 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 3448 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 3449 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 3450 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 3451 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 3452 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 3453 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 3454 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 3455 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30 3456 }; 3457 3458 /* 3459 * dma queue parameters 3460 */ 3461 enum fw_params_param_dmaq { 3462 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 3463 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 3464 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 3465 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 3466 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 3467 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13 3468 }; 3469 3470 /* 3471 * dev bypass parameters; actions and modes 3472 */ 3473 enum fw_params_param_dev_bypass { 3474 3475 /* actions 3476 */ 3477 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 3478 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 3479 3480 /* modes 3481 */ 3482 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 3483 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 3484 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 3485 }; 3486 3487 #define S_FW_PARAMS_MNEM 24 3488 #define M_FW_PARAMS_MNEM 0xff 3489 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 3490 #define G_FW_PARAMS_MNEM(x) \ 3491 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 3492 3493 #define S_FW_PARAMS_PARAM_X 16 3494 #define M_FW_PARAMS_PARAM_X 0xff 3495 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 3496 #define G_FW_PARAMS_PARAM_X(x) \ 3497 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 3498 3499 #define S_FW_PARAMS_PARAM_Y 8 3500 #define M_FW_PARAMS_PARAM_Y 0xff 3501 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 3502 #define G_FW_PARAMS_PARAM_Y(x) \ 3503 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 3504 3505 #define S_FW_PARAMS_PARAM_Z 0 3506 #define M_FW_PARAMS_PARAM_Z 0xff 3507 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 3508 #define G_FW_PARAMS_PARAM_Z(x) \ 3509 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 3510 3511 #define S_FW_PARAMS_PARAM_XYZ 0 3512 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 3513 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 3514 #define G_FW_PARAMS_PARAM_XYZ(x) \ 3515 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 3516 3517 #define S_FW_PARAMS_PARAM_YZ 0 3518 #define M_FW_PARAMS_PARAM_YZ 0xffff 3519 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 3520 #define G_FW_PARAMS_PARAM_YZ(x) \ 3521 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 3522 3523 struct fw_params_cmd { 3524 __be32 op_to_vfn; 3525 __be32 retval_len16; 3526 struct fw_params_param { 3527 __be32 mnem; 3528 __be32 val; 3529 } param[7]; 3530 }; 3531 3532 #define S_FW_PARAMS_CMD_PFN 8 3533 #define M_FW_PARAMS_CMD_PFN 0x7 3534 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 3535 #define G_FW_PARAMS_CMD_PFN(x) \ 3536 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 3537 3538 #define S_FW_PARAMS_CMD_VFN 0 3539 #define M_FW_PARAMS_CMD_VFN 0xff 3540 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 3541 #define G_FW_PARAMS_CMD_VFN(x) \ 3542 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 3543 3544 struct fw_pfvf_cmd { 3545 __be32 op_to_vfn; 3546 __be32 retval_len16; 3547 __be32 niqflint_niq; 3548 __be32 type_to_neq; 3549 __be32 tc_to_nexactf; 3550 __be32 r_caps_to_nethctrl; 3551 __be16 nricq; 3552 __be16 nriqp; 3553 __be32 r4; 3554 }; 3555 3556 #define S_FW_PFVF_CMD_PFN 8 3557 #define M_FW_PFVF_CMD_PFN 0x7 3558 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 3559 #define G_FW_PFVF_CMD_PFN(x) \ 3560 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 3561 3562 #define S_FW_PFVF_CMD_VFN 0 3563 #define M_FW_PFVF_CMD_VFN 0xff 3564 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 3565 #define G_FW_PFVF_CMD_VFN(x) \ 3566 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 3567 3568 #define S_FW_PFVF_CMD_NIQFLINT 20 3569 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 3570 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 3571 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 3572 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 3573 3574 #define S_FW_PFVF_CMD_NIQ 0 3575 #define M_FW_PFVF_CMD_NIQ 0xfffff 3576 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 3577 #define G_FW_PFVF_CMD_NIQ(x) \ 3578 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 3579 3580 #define S_FW_PFVF_CMD_TYPE 31 3581 #define M_FW_PFVF_CMD_TYPE 0x1 3582 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 3583 #define G_FW_PFVF_CMD_TYPE(x) \ 3584 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 3585 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 3586 3587 #define S_FW_PFVF_CMD_CMASK 24 3588 #define M_FW_PFVF_CMD_CMASK 0xf 3589 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 3590 #define G_FW_PFVF_CMD_CMASK(x) \ 3591 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 3592 3593 #define S_FW_PFVF_CMD_PMASK 20 3594 #define M_FW_PFVF_CMD_PMASK 0xf 3595 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 3596 #define G_FW_PFVF_CMD_PMASK(x) \ 3597 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 3598 3599 #define S_FW_PFVF_CMD_NEQ 0 3600 #define M_FW_PFVF_CMD_NEQ 0xfffff 3601 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 3602 #define G_FW_PFVF_CMD_NEQ(x) \ 3603 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 3604 3605 #define S_FW_PFVF_CMD_TC 24 3606 #define M_FW_PFVF_CMD_TC 0xff 3607 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 3608 #define G_FW_PFVF_CMD_TC(x) (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 3609 3610 #define S_FW_PFVF_CMD_NVI 16 3611 #define M_FW_PFVF_CMD_NVI 0xff 3612 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 3613 #define G_FW_PFVF_CMD_NVI(x) \ 3614 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 3615 3616 #define S_FW_PFVF_CMD_NEXACTF 0 3617 #define M_FW_PFVF_CMD_NEXACTF 0xffff 3618 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 3619 #define G_FW_PFVF_CMD_NEXACTF(x) \ 3620 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 3621 3622 #define S_FW_PFVF_CMD_R_CAPS 24 3623 #define M_FW_PFVF_CMD_R_CAPS 0xff 3624 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 3625 #define G_FW_PFVF_CMD_R_CAPS(x) \ 3626 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 3627 3628 #define S_FW_PFVF_CMD_WX_CAPS 16 3629 #define M_FW_PFVF_CMD_WX_CAPS 0xff 3630 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 3631 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 3632 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 3633 3634 #define S_FW_PFVF_CMD_NETHCTRL 0 3635 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 3636 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 3637 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 3638 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 3639 3640 /* 3641 * ingress queue type; the first 1K ingress queues can have associated 0, 3642 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 3643 * capabilities 3644 */ 3645 enum fw_iq_type { 3646 FW_IQ_TYPE_FL_INT_CAP, 3647 FW_IQ_TYPE_NO_FL_INT_CAP 3648 }; 3649 3650 struct fw_iq_cmd { 3651 __be32 op_to_vfn; 3652 __be32 alloc_to_len16; 3653 __be16 physiqid; 3654 __be16 iqid; 3655 __be16 fl0id; 3656 __be16 fl1id; 3657 __be32 type_to_iqandstindex; 3658 __be16 iqdroprss_to_iqesize; 3659 __be16 iqsize; 3660 __be64 iqaddr; 3661 __be32 iqns_to_fl0congen; 3662 __be16 fl0dcaen_to_fl0cidxfthresh; 3663 __be16 fl0size; 3664 __be64 fl0addr; 3665 __be32 fl1cngchmap_to_fl1congen; 3666 __be16 fl1dcaen_to_fl1cidxfthresh; 3667 __be16 fl1size; 3668 __be64 fl1addr; 3669 }; 3670 3671 #define S_FW_IQ_CMD_PFN 8 3672 #define M_FW_IQ_CMD_PFN 0x7 3673 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 3674 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 3675 3676 #define S_FW_IQ_CMD_VFN 0 3677 #define M_FW_IQ_CMD_VFN 0xff 3678 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 3679 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 3680 3681 #define S_FW_IQ_CMD_ALLOC 31 3682 #define M_FW_IQ_CMD_ALLOC 0x1 3683 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 3684 #define G_FW_IQ_CMD_ALLOC(x) \ 3685 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 3686 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 3687 3688 #define S_FW_IQ_CMD_FREE 30 3689 #define M_FW_IQ_CMD_FREE 0x1 3690 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 3691 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 3692 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 3693 3694 #define S_FW_IQ_CMD_MODIFY 29 3695 #define M_FW_IQ_CMD_MODIFY 0x1 3696 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 3697 #define G_FW_IQ_CMD_MODIFY(x) \ 3698 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 3699 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 3700 3701 #define S_FW_IQ_CMD_IQSTART 28 3702 #define M_FW_IQ_CMD_IQSTART 0x1 3703 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 3704 #define G_FW_IQ_CMD_IQSTART(x) \ 3705 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 3706 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 3707 3708 #define S_FW_IQ_CMD_IQSTOP 27 3709 #define M_FW_IQ_CMD_IQSTOP 0x1 3710 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 3711 #define G_FW_IQ_CMD_IQSTOP(x) \ 3712 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 3713 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 3714 3715 #define S_FW_IQ_CMD_TYPE 29 3716 #define M_FW_IQ_CMD_TYPE 0x7 3717 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 3718 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 3719 3720 #define S_FW_IQ_CMD_IQASYNCH 28 3721 #define M_FW_IQ_CMD_IQASYNCH 0x1 3722 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 3723 #define G_FW_IQ_CMD_IQASYNCH(x) \ 3724 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 3725 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 3726 3727 #define S_FW_IQ_CMD_VIID 16 3728 #define M_FW_IQ_CMD_VIID 0xfff 3729 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 3730 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 3731 3732 #define S_FW_IQ_CMD_IQANDST 15 3733 #define M_FW_IQ_CMD_IQANDST 0x1 3734 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 3735 #define G_FW_IQ_CMD_IQANDST(x) \ 3736 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 3737 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 3738 3739 #define S_FW_IQ_CMD_IQANUS 14 3740 #define M_FW_IQ_CMD_IQANUS 0x1 3741 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 3742 #define G_FW_IQ_CMD_IQANUS(x) \ 3743 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 3744 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 3745 3746 #define S_FW_IQ_CMD_IQANUD 12 3747 #define M_FW_IQ_CMD_IQANUD 0x3 3748 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 3749 #define G_FW_IQ_CMD_IQANUD(x) \ 3750 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 3751 3752 #define S_FW_IQ_CMD_IQANDSTINDEX 0 3753 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 3754 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 3755 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 3756 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 3757 3758 #define S_FW_IQ_CMD_IQDROPRSS 15 3759 #define M_FW_IQ_CMD_IQDROPRSS 0x1 3760 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 3761 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 3762 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 3763 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 3764 3765 #define S_FW_IQ_CMD_IQGTSMODE 14 3766 #define M_FW_IQ_CMD_IQGTSMODE 0x1 3767 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 3768 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 3769 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 3770 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 3771 3772 #define S_FW_IQ_CMD_IQPCIECH 12 3773 #define M_FW_IQ_CMD_IQPCIECH 0x3 3774 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 3775 #define G_FW_IQ_CMD_IQPCIECH(x) \ 3776 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 3777 3778 #define S_FW_IQ_CMD_IQDCAEN 11 3779 #define M_FW_IQ_CMD_IQDCAEN 0x1 3780 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 3781 #define G_FW_IQ_CMD_IQDCAEN(x) \ 3782 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 3783 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 3784 3785 #define S_FW_IQ_CMD_IQDCACPU 6 3786 #define M_FW_IQ_CMD_IQDCACPU 0x1f 3787 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 3788 #define G_FW_IQ_CMD_IQDCACPU(x) \ 3789 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 3790 3791 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 3792 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 3793 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 3794 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 3795 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 3796 3797 #define S_FW_IQ_CMD_IQO 3 3798 #define M_FW_IQ_CMD_IQO 0x1 3799 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 3800 #define G_FW_IQ_CMD_IQO(x) (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 3801 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 3802 3803 #define S_FW_IQ_CMD_IQCPRIO 2 3804 #define M_FW_IQ_CMD_IQCPRIO 0x1 3805 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 3806 #define G_FW_IQ_CMD_IQCPRIO(x) \ 3807 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 3808 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 3809 3810 #define S_FW_IQ_CMD_IQESIZE 0 3811 #define M_FW_IQ_CMD_IQESIZE 0x3 3812 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 3813 #define G_FW_IQ_CMD_IQESIZE(x) \ 3814 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 3815 3816 #define S_FW_IQ_CMD_IQNS 31 3817 #define M_FW_IQ_CMD_IQNS 0x1 3818 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 3819 #define G_FW_IQ_CMD_IQNS(x) (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 3820 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 3821 3822 #define S_FW_IQ_CMD_IQRO 30 3823 #define M_FW_IQ_CMD_IQRO 0x1 3824 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 3825 #define G_FW_IQ_CMD_IQRO(x) (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 3826 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 3827 3828 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 3829 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 3830 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 3831 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 3832 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 3833 3834 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 3835 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 3836 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 3837 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 3838 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 3839 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 3840 3841 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 3842 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 3843 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 3844 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 3845 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 3846 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 3847 3848 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 3849 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 3850 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 3851 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 3852 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 3853 3854 #define S_FW_IQ_CMD_FL0CACHELOCK 15 3855 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 3856 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 3857 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 3858 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 3859 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 3860 3861 #define S_FW_IQ_CMD_FL0DBP 14 3862 #define M_FW_IQ_CMD_FL0DBP 0x1 3863 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 3864 #define G_FW_IQ_CMD_FL0DBP(x) \ 3865 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 3866 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 3867 3868 #define S_FW_IQ_CMD_FL0DATANS 13 3869 #define M_FW_IQ_CMD_FL0DATANS 0x1 3870 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 3871 #define G_FW_IQ_CMD_FL0DATANS(x) \ 3872 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 3873 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 3874 3875 #define S_FW_IQ_CMD_FL0DATARO 12 3876 #define M_FW_IQ_CMD_FL0DATARO 0x1 3877 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 3878 #define G_FW_IQ_CMD_FL0DATARO(x) \ 3879 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 3880 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 3881 3882 #define S_FW_IQ_CMD_FL0CONGCIF 11 3883 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 3884 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 3885 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 3886 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 3887 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 3888 3889 #define S_FW_IQ_CMD_FL0ONCHIP 10 3890 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 3891 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 3892 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 3893 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 3894 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 3895 3896 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 3897 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 3898 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 3899 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 3900 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 3901 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 3902 3903 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 3904 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 3905 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 3906 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 3907 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 3908 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 3909 3910 #define S_FW_IQ_CMD_FL0FETCHNS 7 3911 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 3912 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 3913 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 3914 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 3915 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 3916 3917 #define S_FW_IQ_CMD_FL0FETCHRO 6 3918 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 3919 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 3920 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 3921 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 3922 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 3923 3924 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 3925 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 3926 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 3927 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 3928 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 3929 3930 #define S_FW_IQ_CMD_FL0CPRIO 3 3931 #define M_FW_IQ_CMD_FL0CPRIO 0x1 3932 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 3933 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 3934 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 3935 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 3936 3937 #define S_FW_IQ_CMD_FL0PADEN 2 3938 #define M_FW_IQ_CMD_FL0PADEN 0x1 3939 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 3940 #define G_FW_IQ_CMD_FL0PADEN(x) \ 3941 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 3942 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 3943 3944 #define S_FW_IQ_CMD_FL0PACKEN 1 3945 #define M_FW_IQ_CMD_FL0PACKEN 0x1 3946 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 3947 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 3948 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 3949 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 3950 3951 #define S_FW_IQ_CMD_FL0CONGEN 0 3952 #define M_FW_IQ_CMD_FL0CONGEN 0x1 3953 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 3954 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 3955 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 3956 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 3957 3958 #define S_FW_IQ_CMD_FL0DCAEN 15 3959 #define M_FW_IQ_CMD_FL0DCAEN 0x1 3960 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 3961 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 3962 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 3963 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 3964 3965 #define S_FW_IQ_CMD_FL0DCACPU 10 3966 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 3967 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 3968 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 3969 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 3970 3971 #define S_FW_IQ_CMD_FL0FBMIN 7 3972 #define M_FW_IQ_CMD_FL0FBMIN 0x7 3973 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 3974 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 3975 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 3976 3977 #define S_FW_IQ_CMD_FL0FBMAX 4 3978 #define M_FW_IQ_CMD_FL0FBMAX 0x7 3979 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 3980 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 3981 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 3982 3983 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 3984 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 3985 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 3986 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 3987 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 3988 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 3989 3990 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 3991 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 3992 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 3993 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 3994 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 3995 3996 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 3997 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 3998 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 3999 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 4000 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 4001 4002 #define S_FW_IQ_CMD_FL1CACHELOCK 15 4003 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 4004 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 4005 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 4006 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 4007 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 4008 4009 #define S_FW_IQ_CMD_FL1DBP 14 4010 #define M_FW_IQ_CMD_FL1DBP 0x1 4011 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 4012 #define G_FW_IQ_CMD_FL1DBP(x) \ 4013 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 4014 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 4015 4016 #define S_FW_IQ_CMD_FL1DATANS 13 4017 #define M_FW_IQ_CMD_FL1DATANS 0x1 4018 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 4019 #define G_FW_IQ_CMD_FL1DATANS(x) \ 4020 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 4021 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 4022 4023 #define S_FW_IQ_CMD_FL1DATARO 12 4024 #define M_FW_IQ_CMD_FL1DATARO 0x1 4025 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 4026 #define G_FW_IQ_CMD_FL1DATARO(x) \ 4027 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 4028 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 4029 4030 #define S_FW_IQ_CMD_FL1CONGCIF 11 4031 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 4032 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 4033 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 4034 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 4035 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 4036 4037 #define S_FW_IQ_CMD_FL1ONCHIP 10 4038 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 4039 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 4040 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 4041 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 4042 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 4043 4044 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 4045 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 4046 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 4047 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 4048 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 4049 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 4050 4051 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 4052 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 4053 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 4054 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 4055 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 4056 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 4057 4058 #define S_FW_IQ_CMD_FL1FETCHNS 7 4059 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 4060 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 4061 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 4062 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 4063 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 4064 4065 #define S_FW_IQ_CMD_FL1FETCHRO 6 4066 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 4067 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 4068 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 4069 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 4070 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 4071 4072 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 4073 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 4074 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 4075 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 4076 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 4077 4078 #define S_FW_IQ_CMD_FL1CPRIO 3 4079 #define M_FW_IQ_CMD_FL1CPRIO 0x1 4080 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 4081 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 4082 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 4083 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 4084 4085 #define S_FW_IQ_CMD_FL1PADEN 2 4086 #define M_FW_IQ_CMD_FL1PADEN 0x1 4087 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 4088 #define G_FW_IQ_CMD_FL1PADEN(x) \ 4089 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 4090 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 4091 4092 #define S_FW_IQ_CMD_FL1PACKEN 1 4093 #define M_FW_IQ_CMD_FL1PACKEN 0x1 4094 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 4095 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 4096 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 4097 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 4098 4099 #define S_FW_IQ_CMD_FL1CONGEN 0 4100 #define M_FW_IQ_CMD_FL1CONGEN 0x1 4101 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 4102 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 4103 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 4104 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 4105 4106 #define S_FW_IQ_CMD_FL1DCAEN 15 4107 #define M_FW_IQ_CMD_FL1DCAEN 0x1 4108 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 4109 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 4110 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 4111 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 4112 4113 #define S_FW_IQ_CMD_FL1DCACPU 10 4114 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 4115 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 4116 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 4117 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 4118 4119 #define S_FW_IQ_CMD_FL1FBMIN 7 4120 #define M_FW_IQ_CMD_FL1FBMIN 0x7 4121 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 4122 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 4123 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 4124 4125 #define S_FW_IQ_CMD_FL1FBMAX 4 4126 #define M_FW_IQ_CMD_FL1FBMAX 0x7 4127 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 4128 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 4129 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 4130 4131 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 4132 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 4133 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 4134 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 4135 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 4136 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 4137 4138 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 4139 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 4140 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 4141 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 4142 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 4143 4144 struct fw_eq_mngt_cmd { 4145 __be32 op_to_vfn; 4146 __be32 alloc_to_len16; 4147 __be32 cmpliqid_eqid; 4148 __be32 physeqid_pkd; 4149 __be32 fetchszm_to_iqid; 4150 __be32 dcaen_to_eqsize; 4151 __be64 eqaddr; 4152 }; 4153 4154 #define S_FW_EQ_MNGT_CMD_PFN 8 4155 #define M_FW_EQ_MNGT_CMD_PFN 0x7 4156 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 4157 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 4158 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 4159 4160 #define S_FW_EQ_MNGT_CMD_VFN 0 4161 #define M_FW_EQ_MNGT_CMD_VFN 0xff 4162 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 4163 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 4164 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 4165 4166 #define S_FW_EQ_MNGT_CMD_ALLOC 31 4167 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 4168 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 4169 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 4170 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 4171 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 4172 4173 #define S_FW_EQ_MNGT_CMD_FREE 30 4174 #define M_FW_EQ_MNGT_CMD_FREE 0x1 4175 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 4176 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 4177 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 4178 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 4179 4180 #define S_FW_EQ_MNGT_CMD_MODIFY 29 4181 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 4182 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 4183 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 4184 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 4185 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 4186 4187 #define S_FW_EQ_MNGT_CMD_EQSTART 28 4188 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 4189 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 4190 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 4191 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 4192 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 4193 4194 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 4195 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 4196 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 4197 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 4198 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 4199 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 4200 4201 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 4202 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 4203 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 4204 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 4205 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 4206 4207 #define S_FW_EQ_MNGT_CMD_EQID 0 4208 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 4209 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 4210 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 4211 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 4212 4213 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 4214 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 4215 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 4216 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 4217 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 4218 4219 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 4220 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 4221 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 4222 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 4223 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 4224 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 4225 4226 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 4227 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 4228 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 4229 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 4230 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 4231 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 4232 4233 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 4234 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 4235 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 4236 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 4237 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 4238 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 4239 4240 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 4241 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 4242 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 4243 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 4244 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 4245 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 4246 4247 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 4248 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 4249 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 4250 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 4251 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 4252 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 4253 4254 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 4255 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 4256 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 4257 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 4258 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 4259 4260 #define S_FW_EQ_MNGT_CMD_CPRIO 19 4261 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 4262 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 4263 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 4264 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 4265 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 4266 4267 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 4268 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 4269 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 4270 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 4271 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 4272 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 4273 4274 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 4275 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 4276 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 4277 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 4278 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 4279 4280 #define S_FW_EQ_MNGT_CMD_IQID 0 4281 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 4282 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 4283 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 4284 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 4285 4286 #define S_FW_EQ_MNGT_CMD_DCAEN 31 4287 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 4288 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 4289 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 4290 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 4291 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 4292 4293 #define S_FW_EQ_MNGT_CMD_DCACPU 26 4294 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 4295 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 4296 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 4297 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 4298 4299 #define S_FW_EQ_MNGT_CMD_FBMIN 23 4300 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 4301 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 4302 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 4303 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 4304 4305 #define S_FW_EQ_MNGT_CMD_FBMAX 20 4306 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 4307 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 4308 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 4309 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 4310 4311 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 4312 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 4313 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4314 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4315 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4316 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4317 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 4318 4319 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 4320 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 4321 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4322 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 4323 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4324 4325 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 4326 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 4327 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 4328 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 4329 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 4330 4331 struct fw_eq_eth_cmd { 4332 __be32 op_to_vfn; 4333 __be32 alloc_to_len16; 4334 __be32 eqid_pkd; 4335 __be32 physeqid_pkd; 4336 __be32 fetchszm_to_iqid; 4337 __be32 dcaen_to_eqsize; 4338 __be64 eqaddr; 4339 __be32 viid_pkd; 4340 __be32 r8_lo; 4341 __be64 r9; 4342 }; 4343 4344 #define S_FW_EQ_ETH_CMD_PFN 8 4345 #define M_FW_EQ_ETH_CMD_PFN 0x7 4346 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 4347 #define G_FW_EQ_ETH_CMD_PFN(x) \ 4348 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 4349 4350 #define S_FW_EQ_ETH_CMD_VFN 0 4351 #define M_FW_EQ_ETH_CMD_VFN 0xff 4352 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 4353 #define G_FW_EQ_ETH_CMD_VFN(x) \ 4354 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 4355 4356 #define S_FW_EQ_ETH_CMD_ALLOC 31 4357 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 4358 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 4359 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 4360 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 4361 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 4362 4363 #define S_FW_EQ_ETH_CMD_FREE 30 4364 #define M_FW_EQ_ETH_CMD_FREE 0x1 4365 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 4366 #define G_FW_EQ_ETH_CMD_FREE(x) \ 4367 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 4368 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 4369 4370 #define S_FW_EQ_ETH_CMD_MODIFY 29 4371 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 4372 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 4373 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 4374 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 4375 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 4376 4377 #define S_FW_EQ_ETH_CMD_EQSTART 28 4378 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 4379 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 4380 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 4381 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 4382 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 4383 4384 #define S_FW_EQ_ETH_CMD_EQSTOP 27 4385 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 4386 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 4387 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 4388 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 4389 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 4390 4391 #define S_FW_EQ_ETH_CMD_EQID 0 4392 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 4393 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 4394 #define G_FW_EQ_ETH_CMD_EQID(x) \ 4395 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 4396 4397 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 4398 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 4399 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 4400 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 4401 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 4402 4403 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 4404 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 4405 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 4406 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 4407 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 4408 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 4409 4410 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 4411 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 4412 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 4413 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 4414 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 4415 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 4416 4417 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 4418 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 4419 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 4420 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 4421 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 4422 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 4423 4424 #define S_FW_EQ_ETH_CMD_FETCHNS 23 4425 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 4426 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 4427 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 4428 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 4429 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 4430 4431 #define S_FW_EQ_ETH_CMD_FETCHRO 22 4432 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 4433 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 4434 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 4435 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 4436 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 4437 4438 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 4439 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 4440 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 4441 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 4442 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 4443 4444 #define S_FW_EQ_ETH_CMD_CPRIO 19 4445 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 4446 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 4447 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 4448 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 4449 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 4450 4451 #define S_FW_EQ_ETH_CMD_ONCHIP 18 4452 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 4453 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 4454 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 4455 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 4456 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 4457 4458 #define S_FW_EQ_ETH_CMD_PCIECHN 16 4459 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 4460 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 4461 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 4462 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 4463 4464 #define S_FW_EQ_ETH_CMD_IQID 0 4465 #define M_FW_EQ_ETH_CMD_IQID 0xffff 4466 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 4467 #define G_FW_EQ_ETH_CMD_IQID(x) \ 4468 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 4469 4470 #define S_FW_EQ_ETH_CMD_DCAEN 31 4471 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 4472 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 4473 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 4474 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 4475 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 4476 4477 #define S_FW_EQ_ETH_CMD_DCACPU 26 4478 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 4479 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 4480 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 4481 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 4482 4483 #define S_FW_EQ_ETH_CMD_FBMIN 23 4484 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 4485 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 4486 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 4487 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 4488 4489 #define S_FW_EQ_ETH_CMD_FBMAX 20 4490 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 4491 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 4492 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 4493 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 4494 4495 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 4496 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 4497 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4498 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 4499 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4500 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 4501 4502 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 4503 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 4504 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 4505 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 4506 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 4507 4508 #define S_FW_EQ_ETH_CMD_EQSIZE 0 4509 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 4510 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 4511 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 4512 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 4513 4514 #define S_FW_EQ_ETH_CMD_VIID 16 4515 #define M_FW_EQ_ETH_CMD_VIID 0xfff 4516 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 4517 #define G_FW_EQ_ETH_CMD_VIID(x) \ 4518 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 4519 4520 struct fw_eq_ctrl_cmd { 4521 __be32 op_to_vfn; 4522 __be32 alloc_to_len16; 4523 __be32 cmpliqid_eqid; 4524 __be32 physeqid_pkd; 4525 __be32 fetchszm_to_iqid; 4526 __be32 dcaen_to_eqsize; 4527 __be64 eqaddr; 4528 }; 4529 4530 #define S_FW_EQ_CTRL_CMD_PFN 8 4531 #define M_FW_EQ_CTRL_CMD_PFN 0x7 4532 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 4533 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 4534 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 4535 4536 #define S_FW_EQ_CTRL_CMD_VFN 0 4537 #define M_FW_EQ_CTRL_CMD_VFN 0xff 4538 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 4539 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 4540 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 4541 4542 #define S_FW_EQ_CTRL_CMD_ALLOC 31 4543 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 4544 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 4545 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 4546 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 4547 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 4548 4549 #define S_FW_EQ_CTRL_CMD_FREE 30 4550 #define M_FW_EQ_CTRL_CMD_FREE 0x1 4551 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 4552 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 4553 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 4554 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 4555 4556 #define S_FW_EQ_CTRL_CMD_MODIFY 29 4557 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 4558 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 4559 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 4560 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 4561 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 4562 4563 #define S_FW_EQ_CTRL_CMD_EQSTART 28 4564 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 4565 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 4566 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 4567 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 4568 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 4569 4570 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 4571 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 4572 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 4573 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 4574 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 4575 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 4576 4577 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 4578 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 4579 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 4580 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 4581 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 4582 4583 #define S_FW_EQ_CTRL_CMD_EQID 0 4584 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 4585 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 4586 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 4587 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 4588 4589 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 4590 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 4591 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 4592 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 4593 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 4594 4595 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 4596 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 4597 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 4598 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 4599 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 4600 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 4601 4602 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 4603 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 4604 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 4605 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 4606 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 4607 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 4608 4609 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 4610 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 4611 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 4612 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 4613 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 4614 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 4615 4616 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 4617 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 4618 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 4619 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 4620 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 4621 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 4622 4623 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 4624 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 4625 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 4626 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 4627 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 4628 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 4629 4630 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 4631 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 4632 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 4633 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 4634 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 4635 4636 #define S_FW_EQ_CTRL_CMD_CPRIO 19 4637 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 4638 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 4639 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 4640 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 4641 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 4642 4643 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 4644 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 4645 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 4646 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 4647 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 4648 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 4649 4650 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 4651 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 4652 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 4653 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 4654 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 4655 4656 #define S_FW_EQ_CTRL_CMD_IQID 0 4657 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 4658 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 4659 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 4660 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 4661 4662 #define S_FW_EQ_CTRL_CMD_DCAEN 31 4663 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 4664 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 4665 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 4666 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 4667 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 4668 4669 #define S_FW_EQ_CTRL_CMD_DCACPU 26 4670 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 4671 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 4672 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 4673 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 4674 4675 #define S_FW_EQ_CTRL_CMD_FBMIN 23 4676 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 4677 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 4678 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 4679 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 4680 4681 #define S_FW_EQ_CTRL_CMD_FBMAX 20 4682 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 4683 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 4684 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 4685 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 4686 4687 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 4688 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 4689 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4690 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4691 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4692 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4693 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 4694 4695 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 4696 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 4697 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4698 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 4699 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4700 4701 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 4702 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 4703 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 4704 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 4705 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 4706 4707 struct fw_eq_ofld_cmd { 4708 __be32 op_to_vfn; 4709 __be32 alloc_to_len16; 4710 __be32 eqid_pkd; 4711 __be32 physeqid_pkd; 4712 __be32 fetchszm_to_iqid; 4713 __be32 dcaen_to_eqsize; 4714 __be64 eqaddr; 4715 }; 4716 4717 #define S_FW_EQ_OFLD_CMD_PFN 8 4718 #define M_FW_EQ_OFLD_CMD_PFN 0x7 4719 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 4720 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 4721 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 4722 4723 #define S_FW_EQ_OFLD_CMD_VFN 0 4724 #define M_FW_EQ_OFLD_CMD_VFN 0xff 4725 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 4726 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 4727 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 4728 4729 #define S_FW_EQ_OFLD_CMD_ALLOC 31 4730 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 4731 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 4732 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 4733 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 4734 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 4735 4736 #define S_FW_EQ_OFLD_CMD_FREE 30 4737 #define M_FW_EQ_OFLD_CMD_FREE 0x1 4738 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 4739 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 4740 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 4741 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 4742 4743 #define S_FW_EQ_OFLD_CMD_MODIFY 29 4744 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 4745 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 4746 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 4747 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 4748 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 4749 4750 #define S_FW_EQ_OFLD_CMD_EQSTART 28 4751 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 4752 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 4753 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 4754 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 4755 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 4756 4757 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 4758 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 4759 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 4760 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 4761 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 4762 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 4763 4764 #define S_FW_EQ_OFLD_CMD_EQID 0 4765 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 4766 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 4767 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 4768 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 4769 4770 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 4771 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 4772 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 4773 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 4774 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 4775 4776 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 4777 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 4778 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 4779 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 4780 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 4781 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 4782 4783 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 4784 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 4785 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 4786 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 4787 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 4788 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 4789 4790 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 4791 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 4792 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 4793 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 4794 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 4795 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 4796 4797 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 4798 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 4799 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 4800 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 4801 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 4802 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 4803 4804 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 4805 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 4806 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 4807 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 4808 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 4809 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 4810 4811 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 4812 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 4813 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 4814 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 4815 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 4816 4817 #define S_FW_EQ_OFLD_CMD_CPRIO 19 4818 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 4819 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 4820 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 4821 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 4822 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 4823 4824 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 4825 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 4826 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 4827 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 4828 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 4829 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 4830 4831 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 4832 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 4833 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 4834 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 4835 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 4836 4837 #define S_FW_EQ_OFLD_CMD_IQID 0 4838 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 4839 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 4840 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 4841 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 4842 4843 #define S_FW_EQ_OFLD_CMD_DCAEN 31 4844 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 4845 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 4846 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 4847 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 4848 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 4849 4850 #define S_FW_EQ_OFLD_CMD_DCACPU 26 4851 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 4852 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 4853 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 4854 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 4855 4856 #define S_FW_EQ_OFLD_CMD_FBMIN 23 4857 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 4858 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 4859 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 4860 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 4861 4862 #define S_FW_EQ_OFLD_CMD_FBMAX 20 4863 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 4864 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 4865 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 4866 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 4867 4868 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 4869 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 4870 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 4871 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 4872 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 4873 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 4874 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 4875 4876 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 4877 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 4878 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 4879 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 4880 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 4881 4882 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 4883 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 4884 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 4885 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 4886 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 4887 4888 /* Macros for VIID parsing: 4889 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 4890 #define S_FW_VIID_PFN 8 4891 #define M_FW_VIID_PFN 0x7 4892 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 4893 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 4894 4895 #define S_FW_VIID_VIVLD 7 4896 #define M_FW_VIID_VIVLD 0x1 4897 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 4898 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 4899 4900 #define S_FW_VIID_VIN 0 4901 #define M_FW_VIID_VIN 0x7F 4902 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 4903 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 4904 4905 enum fw_vi_func { 4906 FW_VI_FUNC_ETH, 4907 FW_VI_FUNC_OFLD, 4908 FW_VI_FUNC_IWARP, 4909 FW_VI_FUNC_OPENISCSI, 4910 FW_VI_FUNC_OPENFCOE, 4911 FW_VI_FUNC_FOISCSI, 4912 FW_VI_FUNC_FOFCOE, 4913 FW_VI_FUNC_FW, 4914 }; 4915 4916 struct fw_vi_cmd { 4917 __be32 op_to_vfn; 4918 __be32 alloc_to_len16; 4919 __be16 type_to_viid; 4920 __u8 mac[6]; 4921 __u8 portid_pkd; 4922 __u8 nmac; 4923 __u8 nmac0[6]; 4924 __be16 rsssize_pkd; 4925 __u8 nmac1[6]; 4926 __be16 idsiiq_pkd; 4927 __u8 nmac2[6]; 4928 __be16 idseiq_pkd; 4929 __u8 nmac3[6]; 4930 __be64 r9; 4931 __be64 r10; 4932 }; 4933 4934 #define S_FW_VI_CMD_PFN 8 4935 #define M_FW_VI_CMD_PFN 0x7 4936 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 4937 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 4938 4939 #define S_FW_VI_CMD_VFN 0 4940 #define M_FW_VI_CMD_VFN 0xff 4941 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 4942 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 4943 4944 #define S_FW_VI_CMD_ALLOC 31 4945 #define M_FW_VI_CMD_ALLOC 0x1 4946 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 4947 #define G_FW_VI_CMD_ALLOC(x) \ 4948 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 4949 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 4950 4951 #define S_FW_VI_CMD_FREE 30 4952 #define M_FW_VI_CMD_FREE 0x1 4953 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 4954 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 4955 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 4956 4957 #define S_FW_VI_CMD_TYPE 15 4958 #define M_FW_VI_CMD_TYPE 0x1 4959 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 4960 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 4961 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 4962 4963 #define S_FW_VI_CMD_FUNC 12 4964 #define M_FW_VI_CMD_FUNC 0x7 4965 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 4966 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 4967 4968 #define S_FW_VI_CMD_VIID 0 4969 #define M_FW_VI_CMD_VIID 0xfff 4970 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 4971 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 4972 4973 #define S_FW_VI_CMD_PORTID 4 4974 #define M_FW_VI_CMD_PORTID 0xf 4975 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 4976 #define G_FW_VI_CMD_PORTID(x) \ 4977 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 4978 4979 #define S_FW_VI_CMD_RSSSIZE 0 4980 #define M_FW_VI_CMD_RSSSIZE 0x7ff 4981 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 4982 #define G_FW_VI_CMD_RSSSIZE(x) \ 4983 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 4984 4985 #define S_FW_VI_CMD_IDSIIQ 0 4986 #define M_FW_VI_CMD_IDSIIQ 0x3ff 4987 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 4988 #define G_FW_VI_CMD_IDSIIQ(x) \ 4989 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 4990 4991 #define S_FW_VI_CMD_IDSEIQ 0 4992 #define M_FW_VI_CMD_IDSEIQ 0x3ff 4993 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 4994 #define G_FW_VI_CMD_IDSEIQ(x) \ 4995 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 4996 4997 /* Special VI_MAC command index ids */ 4998 #define FW_VI_MAC_ADD_MAC 0x3FF 4999 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 5000 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 5001 5002 enum fw_vi_mac_smac { 5003 FW_VI_MAC_MPS_TCAM_ENTRY, 5004 FW_VI_MAC_MPS_TCAM_ONLY, 5005 FW_VI_MAC_SMT_ONLY, 5006 FW_VI_MAC_SMT_AND_MPSTCAM 5007 }; 5008 5009 enum fw_vi_mac_result { 5010 FW_VI_MAC_R_SUCCESS, 5011 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 5012 FW_VI_MAC_R_SMAC_FAIL, 5013 FW_VI_MAC_R_F_ACL_CHECK 5014 }; 5015 5016 struct fw_vi_mac_cmd { 5017 __be32 op_to_viid; 5018 __be32 freemacs_to_len16; 5019 union fw_vi_mac { 5020 struct fw_vi_mac_exact { 5021 __be16 valid_to_idx; 5022 __u8 macaddr[6]; 5023 } exact[7]; 5024 struct fw_vi_mac_hash { 5025 __be64 hashvec; 5026 } hash; 5027 } u; 5028 }; 5029 5030 #define S_FW_VI_MAC_CMD_VIID 0 5031 #define M_FW_VI_MAC_CMD_VIID 0xfff 5032 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 5033 #define G_FW_VI_MAC_CMD_VIID(x) \ 5034 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 5035 5036 #define S_FW_VI_MAC_CMD_FREEMACS 31 5037 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 5038 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 5039 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 5040 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 5041 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 5042 5043 #define S_FW_VI_MAC_CMD_HASHVECEN 23 5044 #define M_FW_VI_MAC_CMD_HASHVECEN 0x1 5045 #define V_FW_VI_MAC_CMD_HASHVECEN(x) ((x) << S_FW_VI_MAC_CMD_HASHVECEN) 5046 #define G_FW_VI_MAC_CMD_HASHVECEN(x) \ 5047 (((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN) 5048 #define F_FW_VI_MAC_CMD_HASHVECEN V_FW_VI_MAC_CMD_HASHVECEN(1U) 5049 5050 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 5051 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 5052 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 5053 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 5054 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 5055 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 5056 5057 #define S_FW_VI_MAC_CMD_VALID 15 5058 #define M_FW_VI_MAC_CMD_VALID 0x1 5059 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 5060 #define G_FW_VI_MAC_CMD_VALID(x) \ 5061 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 5062 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 5063 5064 #define S_FW_VI_MAC_CMD_PRIO 12 5065 #define M_FW_VI_MAC_CMD_PRIO 0x7 5066 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 5067 #define G_FW_VI_MAC_CMD_PRIO(x) \ 5068 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 5069 5070 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 5071 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 5072 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 5073 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 5074 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 5075 5076 #define S_FW_VI_MAC_CMD_IDX 0 5077 #define M_FW_VI_MAC_CMD_IDX 0x3ff 5078 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 5079 #define G_FW_VI_MAC_CMD_IDX(x) \ 5080 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 5081 5082 /* T4 max MTU supported */ 5083 #define T4_MAX_MTU_SUPPORTED 9600 5084 #define FW_RXMODE_MTU_NO_CHG 65535 5085 5086 struct fw_vi_rxmode_cmd { 5087 __be32 op_to_viid; 5088 __be32 retval_len16; 5089 __be32 mtu_to_vlanexen; 5090 __be32 r4_lo; 5091 }; 5092 5093 #define S_FW_VI_RXMODE_CMD_VIID 0 5094 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 5095 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 5096 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 5097 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 5098 5099 #define S_FW_VI_RXMODE_CMD_MTU 16 5100 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 5101 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 5102 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 5103 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 5104 5105 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 5106 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 5107 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 5108 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 5109 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 5110 5111 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 5112 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 5113 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5114 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 5115 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5116 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 5117 5118 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 5119 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 5120 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5121 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 5122 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5123 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 5124 5125 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 5126 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 5127 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 5128 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 5129 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 5130 5131 struct fw_vi_enable_cmd { 5132 __be32 op_to_viid; 5133 __be32 ien_to_len16; 5134 __be16 blinkdur; 5135 __be16 r3; 5136 __be32 r4; 5137 }; 5138 5139 #define S_FW_VI_ENABLE_CMD_VIID 0 5140 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 5141 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 5142 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 5143 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 5144 5145 #define S_FW_VI_ENABLE_CMD_IEN 31 5146 #define M_FW_VI_ENABLE_CMD_IEN 0x1 5147 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 5148 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 5149 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 5150 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 5151 5152 #define S_FW_VI_ENABLE_CMD_EEN 30 5153 #define M_FW_VI_ENABLE_CMD_EEN 0x1 5154 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 5155 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 5156 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 5157 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 5158 5159 #define S_FW_VI_ENABLE_CMD_LED 29 5160 #define M_FW_VI_ENABLE_CMD_LED 0x1 5161 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 5162 #define G_FW_VI_ENABLE_CMD_LED(x) \ 5163 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 5164 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 5165 5166 /* VI VF stats offset definitions */ 5167 #define VI_VF_NUM_STATS 16 5168 enum fw_vi_stats_vf_index { 5169 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 5170 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 5171 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 5172 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 5173 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 5174 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 5175 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 5176 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 5177 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 5178 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 5179 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 5180 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 5181 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 5182 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 5183 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 5184 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 5185 }; 5186 5187 /* VI PF stats offset definitions */ 5188 #define VI_PF_NUM_STATS 17 5189 enum fw_vi_stats_pf_index { 5190 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 5191 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 5192 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 5193 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 5194 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 5195 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 5196 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 5197 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 5198 FW_VI_PF_STAT_RX_BYTES_IX, 5199 FW_VI_PF_STAT_RX_FRAMES_IX, 5200 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 5201 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 5202 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 5203 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 5204 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 5205 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 5206 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 5207 }; 5208 5209 struct fw_vi_stats_cmd { 5210 __be32 op_to_viid; 5211 __be32 retval_len16; 5212 union fw_vi_stats { 5213 struct fw_vi_stats_ctl { 5214 __be16 nstats_ix; 5215 __be16 r6; 5216 __be32 r7; 5217 __be64 stat0; 5218 __be64 stat1; 5219 __be64 stat2; 5220 __be64 stat3; 5221 __be64 stat4; 5222 __be64 stat5; 5223 } ctl; 5224 struct fw_vi_stats_pf { 5225 __be64 tx_bcast_bytes; 5226 __be64 tx_bcast_frames; 5227 __be64 tx_mcast_bytes; 5228 __be64 tx_mcast_frames; 5229 __be64 tx_ucast_bytes; 5230 __be64 tx_ucast_frames; 5231 __be64 tx_offload_bytes; 5232 __be64 tx_offload_frames; 5233 __be64 rx_pf_bytes; 5234 __be64 rx_pf_frames; 5235 __be64 rx_bcast_bytes; 5236 __be64 rx_bcast_frames; 5237 __be64 rx_mcast_bytes; 5238 __be64 rx_mcast_frames; 5239 __be64 rx_ucast_bytes; 5240 __be64 rx_ucast_frames; 5241 __be64 rx_err_frames; 5242 } pf; 5243 struct fw_vi_stats_vf { 5244 __be64 tx_bcast_bytes; 5245 __be64 tx_bcast_frames; 5246 __be64 tx_mcast_bytes; 5247 __be64 tx_mcast_frames; 5248 __be64 tx_ucast_bytes; 5249 __be64 tx_ucast_frames; 5250 __be64 tx_drop_frames; 5251 __be64 tx_offload_bytes; 5252 __be64 tx_offload_frames; 5253 __be64 rx_bcast_bytes; 5254 __be64 rx_bcast_frames; 5255 __be64 rx_mcast_bytes; 5256 __be64 rx_mcast_frames; 5257 __be64 rx_ucast_bytes; 5258 __be64 rx_ucast_frames; 5259 __be64 rx_err_frames; 5260 } vf; 5261 } u; 5262 }; 5263 5264 #define S_FW_VI_STATS_CMD_VIID 0 5265 #define M_FW_VI_STATS_CMD_VIID 0xfff 5266 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 5267 #define G_FW_VI_STATS_CMD_VIID(x) \ 5268 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 5269 5270 #define S_FW_VI_STATS_CMD_NSTATS 12 5271 #define M_FW_VI_STATS_CMD_NSTATS 0x7 5272 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 5273 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 5274 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 5275 5276 #define S_FW_VI_STATS_CMD_IX 0 5277 #define M_FW_VI_STATS_CMD_IX 0x1f 5278 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 5279 #define G_FW_VI_STATS_CMD_IX(x) \ 5280 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 5281 5282 struct fw_acl_mac_cmd { 5283 __be32 op_to_vfn; 5284 __be32 en_to_len16; 5285 __u8 nmac; 5286 __u8 r3[7]; 5287 __be16 r4; 5288 __u8 macaddr0[6]; 5289 __be16 r5; 5290 __u8 macaddr1[6]; 5291 __be16 r6; 5292 __u8 macaddr2[6]; 5293 __be16 r7; 5294 __u8 macaddr3[6]; 5295 }; 5296 5297 #define S_FW_ACL_MAC_CMD_PFN 8 5298 #define M_FW_ACL_MAC_CMD_PFN 0x7 5299 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 5300 #define G_FW_ACL_MAC_CMD_PFN(x) \ 5301 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 5302 5303 #define S_FW_ACL_MAC_CMD_VFN 0 5304 #define M_FW_ACL_MAC_CMD_VFN 0xff 5305 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 5306 #define G_FW_ACL_MAC_CMD_VFN(x) \ 5307 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 5308 5309 #define S_FW_ACL_MAC_CMD_EN 31 5310 #define M_FW_ACL_MAC_CMD_EN 0x1 5311 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 5312 #define G_FW_ACL_MAC_CMD_EN(x) \ 5313 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 5314 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 5315 5316 struct fw_acl_vlan_cmd { 5317 __be32 op_to_vfn; 5318 __be32 en_to_len16; 5319 __u8 nvlan; 5320 __u8 dropnovlan_fm; 5321 __u8 r3_lo[6]; 5322 __be16 vlanid[16]; 5323 }; 5324 5325 #define S_FW_ACL_VLAN_CMD_PFN 8 5326 #define M_FW_ACL_VLAN_CMD_PFN 0x7 5327 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 5328 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 5329 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 5330 5331 #define S_FW_ACL_VLAN_CMD_VFN 0 5332 #define M_FW_ACL_VLAN_CMD_VFN 0xff 5333 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 5334 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 5335 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 5336 5337 #define S_FW_ACL_VLAN_CMD_EN 31 5338 #define M_FW_ACL_VLAN_CMD_EN 0x1 5339 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 5340 #define G_FW_ACL_VLAN_CMD_EN(x) \ 5341 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 5342 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 5343 5344 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 5345 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 5346 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 5347 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 5348 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 5349 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 5350 5351 #define S_FW_ACL_VLAN_CMD_FM 6 5352 #define M_FW_ACL_VLAN_CMD_FM 0x1 5353 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 5354 #define G_FW_ACL_VLAN_CMD_FM(x) \ 5355 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 5356 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 5357 5358 /* port capabilities bitmap */ 5359 enum fw_port_cap { 5360 FW_PORT_CAP_SPEED_100M = 0x0001, 5361 FW_PORT_CAP_SPEED_1G = 0x0002, 5362 FW_PORT_CAP_SPEED_2_5G = 0x0004, 5363 FW_PORT_CAP_SPEED_10G = 0x0008, 5364 FW_PORT_CAP_SPEED_40G = 0x0010, 5365 FW_PORT_CAP_SPEED_100G = 0x0020, 5366 FW_PORT_CAP_FC_RX = 0x0040, 5367 FW_PORT_CAP_FC_TX = 0x0080, 5368 FW_PORT_CAP_ANEG = 0x0100, 5369 FW_PORT_CAP_MDIX = 0x0200, 5370 FW_PORT_CAP_MDIAUTO = 0x0400, 5371 FW_PORT_CAP_FEC = 0x0800, 5372 FW_PORT_CAP_TECHKR = 0x1000, 5373 FW_PORT_CAP_TECHKX4 = 0x2000, 5374 }; 5375 5376 #define S_FW_PORT_AUXLINFO_MDI 3 5377 #define M_FW_PORT_AUXLINFO_MDI 0x3 5378 #define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI) 5379 #define G_FW_PORT_AUXLINFO_MDI(x) \ 5380 (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI) 5381 5382 #define S_FW_PORT_AUXLINFO_KX4 2 5383 #define M_FW_PORT_AUXLINFO_KX4 0x1 5384 #define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4) 5385 #define G_FW_PORT_AUXLINFO_KX4(x) \ 5386 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 5387 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 5388 5389 #define S_FW_PORT_AUXLINFO_KR 1 5390 #define M_FW_PORT_AUXLINFO_KR 0x1 5391 #define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR) 5392 #define G_FW_PORT_AUXLINFO_KR(x) \ 5393 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 5394 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 5395 5396 #define S_FW_PORT_AUXLINFO_FEC 0 5397 #define M_FW_PORT_AUXLINFO_FEC 0x1 5398 #define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) 5399 #define G_FW_PORT_AUXLINFO_FEC(x) \ 5400 (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) 5401 #define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) 5402 5403 #define S_FW_PORT_RCAP_AUX 11 5404 #define M_FW_PORT_RCAP_AUX 0x7 5405 #define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX) 5406 #define G_FW_PORT_RCAP_AUX(x) \ 5407 (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX) 5408 5409 #define S_FW_PORT_CAP_SPEED 0 5410 #define M_FW_PORT_CAP_SPEED 0x3f 5411 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 5412 #define G_FW_PORT_CAP_SPEED(x) \ 5413 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 5414 5415 #define S_FW_PORT_CAP_FC 6 5416 #define M_FW_PORT_CAP_FC 0x3 5417 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 5418 #define G_FW_PORT_CAP_FC(x) \ 5419 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 5420 5421 #define S_FW_PORT_CAP_ANEG 8 5422 #define M_FW_PORT_CAP_ANEG 0x1 5423 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 5424 #define G_FW_PORT_CAP_ANEG(x) \ 5425 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 5426 5427 enum fw_port_mdi { 5428 FW_PORT_CAP_MDI_UNCHANGED, 5429 FW_PORT_CAP_MDI_AUTO, 5430 FW_PORT_CAP_MDI_F_STRAIGHT, 5431 FW_PORT_CAP_MDI_F_CROSSOVER 5432 }; 5433 5434 #define S_FW_PORT_CAP_MDI 9 5435 #define M_FW_PORT_CAP_MDI 3 5436 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 5437 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 5438 5439 enum fw_port_action { 5440 FW_PORT_ACTION_L1_CFG = 0x0001, 5441 FW_PORT_ACTION_L2_CFG = 0x0002, 5442 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 5443 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 5444 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 5445 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 5446 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 5447 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 5448 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 5449 FW_PORT_ACTION_L1_SS_LPBK_ASIC = 0x0021, 5450 FW_PORT_ACTION_MAC_LPBK = 0x0022, 5451 FW_PORT_ACTION_L1_WS_LPBK_ASIC = 0x0023, 5452 FW_PORT_ACTION_L1_EXT_LPBK = 0x0026, 5453 FW_PORT_ACTION_PCS_LPBK = 0x0028, 5454 FW_PORT_ACTION_PHY_RESET = 0x0040, 5455 FW_PORT_ACTION_PMA_RESET = 0x0041, 5456 FW_PORT_ACTION_PCS_RESET = 0x0042, 5457 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 5458 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 5459 FW_PORT_ACTION_AN_RESET = 0x0045 5460 }; 5461 5462 enum fw_port_l2cfg_ctlbf { 5463 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 5464 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 5465 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 5466 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 5467 FW_PORT_L2_CTLBF_IVLAN = 0x10, 5468 FW_PORT_L2_CTLBF_TXIPG = 0x20, 5469 FW_PORT_L2_CTLBF_MTU = 0x40 5470 }; 5471 5472 enum fw_port_dcb_cfg { 5473 FW_PORT_DCB_CFG_PG = 0x01, 5474 FW_PORT_DCB_CFG_PFC = 0x02, 5475 FW_PORT_DCB_CFG_APPL = 0x04 5476 }; 5477 5478 enum fw_port_dcb_cfg_rc { 5479 FW_PORT_DCB_CFG_SUCCESS = 0x0, 5480 FW_PORT_DCB_CFG_ERROR = 0x1 5481 }; 5482 5483 enum fw_port_dcb_type { 5484 FW_PORT_DCB_TYPE_PGID = 0x00, 5485 FW_PORT_DCB_TYPE_PGRATE = 0x01, 5486 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 5487 FW_PORT_DCB_TYPE_PFC = 0x03, 5488 FW_PORT_DCB_TYPE_APP_ID = 0x04, 5489 }; 5490 5491 struct fw_port_cmd { 5492 __be32 op_to_portid; 5493 __be32 action_to_len16; 5494 union fw_port { 5495 struct fw_port_l1cfg { 5496 __be32 rcap; 5497 __be32 r; 5498 } l1cfg; 5499 struct fw_port_l2cfg { 5500 __u8 ctlbf; 5501 __u8 ovlan3_to_ivlan0; 5502 __be16 ivlantype; 5503 __be16 txipg_force_pinfo; 5504 __be16 mtu; 5505 __be16 ovlan0mask; 5506 __be16 ovlan0type; 5507 __be16 ovlan1mask; 5508 __be16 ovlan1type; 5509 __be16 ovlan2mask; 5510 __be16 ovlan2type; 5511 __be16 ovlan3mask; 5512 __be16 ovlan3type; 5513 } l2cfg; 5514 struct fw_port_info { 5515 __be32 lstatus_to_modtype; 5516 __be16 pcap; 5517 __be16 acap; 5518 __be16 mtu; 5519 __u8 cbllen; 5520 __u8 auxlinfo; 5521 __be32 r8; 5522 __be64 r9; 5523 } info; 5524 union fw_port_dcb { 5525 struct fw_port_dcb_pgid { 5526 __u8 type; 5527 __u8 apply_pkd; 5528 __u8 r10_lo[2]; 5529 __be32 pgid; 5530 __be64 r11; 5531 } pgid; 5532 struct fw_port_dcb_pgrate { 5533 __u8 type; 5534 __u8 apply_pkd; 5535 __u8 r10_lo[5]; 5536 __u8 num_tcs_supported; 5537 __u8 pgrate[8]; 5538 } pgrate; 5539 struct fw_port_dcb_priorate { 5540 __u8 type; 5541 __u8 apply_pkd; 5542 __u8 r10_lo[6]; 5543 __u8 strict_priorate[8]; 5544 } priorate; 5545 struct fw_port_dcb_pfc { 5546 __u8 type; 5547 __u8 pfcen; 5548 __be16 r10[3]; 5549 __be64 r11; 5550 } pfc; 5551 struct fw_port_app_priority { 5552 __u8 type; 5553 __u8 r10[2]; 5554 __u8 idx; 5555 __u8 user_prio_map; 5556 __u8 sel_field; 5557 __be16 protocolid; 5558 __be64 r12; 5559 } app_priority; 5560 } dcb; 5561 } u; 5562 }; 5563 5564 #define S_FW_PORT_CMD_READ 22 5565 #define M_FW_PORT_CMD_READ 0x1 5566 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 5567 #define G_FW_PORT_CMD_READ(x) \ 5568 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 5569 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 5570 5571 #define S_FW_PORT_CMD_PORTID 0 5572 #define M_FW_PORT_CMD_PORTID 0xf 5573 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 5574 #define G_FW_PORT_CMD_PORTID(x) \ 5575 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 5576 5577 #define S_FW_PORT_CMD_ACTION 16 5578 #define M_FW_PORT_CMD_ACTION 0xffff 5579 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 5580 #define G_FW_PORT_CMD_ACTION(x) \ 5581 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 5582 5583 #define S_FW_PORT_CMD_OVLAN3 7 5584 #define M_FW_PORT_CMD_OVLAN3 0x1 5585 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 5586 #define G_FW_PORT_CMD_OVLAN3(x) \ 5587 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 5588 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 5589 5590 #define S_FW_PORT_CMD_OVLAN2 6 5591 #define M_FW_PORT_CMD_OVLAN2 0x1 5592 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 5593 #define G_FW_PORT_CMD_OVLAN2(x) \ 5594 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 5595 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 5596 5597 #define S_FW_PORT_CMD_OVLAN1 5 5598 #define M_FW_PORT_CMD_OVLAN1 0x1 5599 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 5600 #define G_FW_PORT_CMD_OVLAN1(x) \ 5601 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 5602 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 5603 5604 #define S_FW_PORT_CMD_OVLAN0 4 5605 #define M_FW_PORT_CMD_OVLAN0 0x1 5606 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 5607 #define G_FW_PORT_CMD_OVLAN0(x) \ 5608 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 5609 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 5610 5611 #define S_FW_PORT_CMD_IVLAN0 3 5612 #define M_FW_PORT_CMD_IVLAN0 0x1 5613 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 5614 #define G_FW_PORT_CMD_IVLAN0(x) \ 5615 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 5616 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 5617 5618 #define S_FW_PORT_CMD_TXIPG 3 5619 #define M_FW_PORT_CMD_TXIPG 0x1fff 5620 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 5621 #define G_FW_PORT_CMD_TXIPG(x) \ 5622 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 5623 5624 #define S_FW_PORT_CMD_FORCE_PINFO 0 5625 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 5626 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 5627 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 5628 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 5629 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 5630 5631 #define S_FW_PORT_CMD_LSTATUS 31 5632 #define M_FW_PORT_CMD_LSTATUS 0x1 5633 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 5634 #define G_FW_PORT_CMD_LSTATUS(x) \ 5635 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 5636 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 5637 5638 #define S_FW_PORT_CMD_LSPEED 24 5639 #define M_FW_PORT_CMD_LSPEED 0x3f 5640 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 5641 #define G_FW_PORT_CMD_LSPEED(x) \ 5642 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 5643 5644 #define S_FW_PORT_CMD_TXPAUSE 23 5645 #define M_FW_PORT_CMD_TXPAUSE 0x1 5646 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 5647 #define G_FW_PORT_CMD_TXPAUSE(x) \ 5648 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 5649 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 5650 5651 #define S_FW_PORT_CMD_RXPAUSE 22 5652 #define M_FW_PORT_CMD_RXPAUSE 0x1 5653 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 5654 #define G_FW_PORT_CMD_RXPAUSE(x) \ 5655 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 5656 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 5657 5658 #define S_FW_PORT_CMD_MDIOCAP 21 5659 #define M_FW_PORT_CMD_MDIOCAP 0x1 5660 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 5661 #define G_FW_PORT_CMD_MDIOCAP(x) \ 5662 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 5663 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 5664 5665 #define S_FW_PORT_CMD_MDIOADDR 16 5666 #define M_FW_PORT_CMD_MDIOADDR 0x1f 5667 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 5668 #define G_FW_PORT_CMD_MDIOADDR(x) \ 5669 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 5670 5671 #define S_FW_PORT_CMD_LPTXPAUSE 15 5672 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 5673 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 5674 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 5675 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 5676 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 5677 5678 #define S_FW_PORT_CMD_LPRXPAUSE 14 5679 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 5680 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 5681 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 5682 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 5683 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 5684 5685 #define S_FW_PORT_CMD_PTYPE 8 5686 #define M_FW_PORT_CMD_PTYPE 0x1f 5687 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 5688 #define G_FW_PORT_CMD_PTYPE(x) \ 5689 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 5690 5691 #define S_FW_PORT_CMD_LINKDNRC 5 5692 #define M_FW_PORT_CMD_LINKDNRC 0x7 5693 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 5694 #define G_FW_PORT_CMD_LINKDNRC(x) \ 5695 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 5696 5697 #define S_FW_PORT_CMD_MODTYPE 0 5698 #define M_FW_PORT_CMD_MODTYPE 0x1f 5699 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 5700 #define G_FW_PORT_CMD_MODTYPE(x) \ 5701 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 5702 5703 #define S_FW_PORT_CMD_APPLY 7 5704 #define M_FW_PORT_CMD_APPLY 0x1 5705 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 5706 #define G_FW_PORT_CMD_APPLY(x) \ 5707 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 5708 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 5709 5710 /* 5711 * These are configured into the VPD and hence tools that generate 5712 * VPD may use this enumeration. 5713 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 5714 */ 5715 enum fw_port_type { 5716 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 5717 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 5718 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 5719 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ 5720 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ 5721 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 5722 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 5723 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 5724 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 5725 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 5726 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 5727 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 5728 5729 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 5730 }; 5731 5732 /* These are read from module's EEPROM and determined once the 5733 module is inserted. */ 5734 enum fw_port_module_type { 5735 FW_PORT_MOD_TYPE_NA = 0x0, 5736 FW_PORT_MOD_TYPE_LR = 0x1, 5737 FW_PORT_MOD_TYPE_SR = 0x2, 5738 FW_PORT_MOD_TYPE_ER = 0x3, 5739 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 5740 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 5741 FW_PORT_MOD_TYPE_LRM = 0x6, 5742 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 5743 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 5744 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 5745 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 5746 }; 5747 5748 /* used by FW and tools may use this to generate VPD */ 5749 enum fw_port_mod_sub_type { 5750 FW_PORT_MOD_SUB_TYPE_NA, 5751 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 5752 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 5753 5754 /* 5755 * The following will never been in the VPD. They are TWINAX cable 5756 * lengths decoded from SFP+ module i2c PROMs. These should almost 5757 * certainly go somewhere else ... 5758 */ 5759 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 5760 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 5761 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 5762 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 5763 }; 5764 5765 /* link down reason codes (3b) */ 5766 enum fw_port_link_dn_rc { 5767 FW_PORT_LINK_DN_RC_NONE, 5768 FW_PORT_LINK_DN_RC_REMFLT, 5769 FW_PORT_LINK_DN_ANEG_F, 5770 FW_PORT_LINK_DN_MS_RES_F, 5771 FW_PORT_LINK_DN_UNKNOWN 5772 }; 5773 5774 /* port stats */ 5775 #define FW_NUM_PORT_STATS 50 5776 #define FW_NUM_PORT_TX_STATS 23 5777 #define FW_NUM_PORT_RX_STATS 27 5778 5779 enum fw_port_stats_tx_index { 5780 FW_STAT_TX_PORT_BYTES_IX, 5781 FW_STAT_TX_PORT_FRAMES_IX, 5782 FW_STAT_TX_PORT_BCAST_IX, 5783 FW_STAT_TX_PORT_MCAST_IX, 5784 FW_STAT_TX_PORT_UCAST_IX, 5785 FW_STAT_TX_PORT_ERROR_IX, 5786 FW_STAT_TX_PORT_64B_IX, 5787 FW_STAT_TX_PORT_65B_127B_IX, 5788 FW_STAT_TX_PORT_128B_255B_IX, 5789 FW_STAT_TX_PORT_256B_511B_IX, 5790 FW_STAT_TX_PORT_512B_1023B_IX, 5791 FW_STAT_TX_PORT_1024B_1518B_IX, 5792 FW_STAT_TX_PORT_1519B_MAX_IX, 5793 FW_STAT_TX_PORT_DROP_IX, 5794 FW_STAT_TX_PORT_PAUSE_IX, 5795 FW_STAT_TX_PORT_PPP0_IX, 5796 FW_STAT_TX_PORT_PPP1_IX, 5797 FW_STAT_TX_PORT_PPP2_IX, 5798 FW_STAT_TX_PORT_PPP3_IX, 5799 FW_STAT_TX_PORT_PPP4_IX, 5800 FW_STAT_TX_PORT_PPP5_IX, 5801 FW_STAT_TX_PORT_PPP6_IX, 5802 FW_STAT_TX_PORT_PPP7_IX 5803 }; 5804 5805 enum fw_port_stat_rx_index { 5806 FW_STAT_RX_PORT_BYTES_IX, 5807 FW_STAT_RX_PORT_FRAMES_IX, 5808 FW_STAT_RX_PORT_BCAST_IX, 5809 FW_STAT_RX_PORT_MCAST_IX, 5810 FW_STAT_RX_PORT_UCAST_IX, 5811 FW_STAT_RX_PORT_MTU_ERROR_IX, 5812 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 5813 FW_STAT_RX_PORT_CRC_ERROR_IX, 5814 FW_STAT_RX_PORT_LEN_ERROR_IX, 5815 FW_STAT_RX_PORT_SYM_ERROR_IX, 5816 FW_STAT_RX_PORT_64B_IX, 5817 FW_STAT_RX_PORT_65B_127B_IX, 5818 FW_STAT_RX_PORT_128B_255B_IX, 5819 FW_STAT_RX_PORT_256B_511B_IX, 5820 FW_STAT_RX_PORT_512B_1023B_IX, 5821 FW_STAT_RX_PORT_1024B_1518B_IX, 5822 FW_STAT_RX_PORT_1519B_MAX_IX, 5823 FW_STAT_RX_PORT_PAUSE_IX, 5824 FW_STAT_RX_PORT_PPP0_IX, 5825 FW_STAT_RX_PORT_PPP1_IX, 5826 FW_STAT_RX_PORT_PPP2_IX, 5827 FW_STAT_RX_PORT_PPP3_IX, 5828 FW_STAT_RX_PORT_PPP4_IX, 5829 FW_STAT_RX_PORT_PPP5_IX, 5830 FW_STAT_RX_PORT_PPP6_IX, 5831 FW_STAT_RX_PORT_PPP7_IX, 5832 FW_STAT_RX_PORT_LESS_64B_IX 5833 }; 5834 5835 struct fw_port_stats_cmd { 5836 __be32 op_to_portid; 5837 __be32 retval_len16; 5838 union fw_port_stats { 5839 struct fw_port_stats_ctl { 5840 __u8 nstats_bg_bm; 5841 __u8 tx_ix; 5842 __be16 r6; 5843 __be32 r7; 5844 __be64 stat0; 5845 __be64 stat1; 5846 __be64 stat2; 5847 __be64 stat3; 5848 __be64 stat4; 5849 __be64 stat5; 5850 } ctl; 5851 struct fw_port_stats_all { 5852 __be64 tx_bytes; 5853 __be64 tx_frames; 5854 __be64 tx_bcast; 5855 __be64 tx_mcast; 5856 __be64 tx_ucast; 5857 __be64 tx_error; 5858 __be64 tx_64b; 5859 __be64 tx_65b_127b; 5860 __be64 tx_128b_255b; 5861 __be64 tx_256b_511b; 5862 __be64 tx_512b_1023b; 5863 __be64 tx_1024b_1518b; 5864 __be64 tx_1519b_max; 5865 __be64 tx_drop; 5866 __be64 tx_pause; 5867 __be64 tx_ppp0; 5868 __be64 tx_ppp1; 5869 __be64 tx_ppp2; 5870 __be64 tx_ppp3; 5871 __be64 tx_ppp4; 5872 __be64 tx_ppp5; 5873 __be64 tx_ppp6; 5874 __be64 tx_ppp7; 5875 __be64 rx_bytes; 5876 __be64 rx_frames; 5877 __be64 rx_bcast; 5878 __be64 rx_mcast; 5879 __be64 rx_ucast; 5880 __be64 rx_mtu_error; 5881 __be64 rx_mtu_crc_error; 5882 __be64 rx_crc_error; 5883 __be64 rx_len_error; 5884 __be64 rx_sym_error; 5885 __be64 rx_64b; 5886 __be64 rx_65b_127b; 5887 __be64 rx_128b_255b; 5888 __be64 rx_256b_511b; 5889 __be64 rx_512b_1023b; 5890 __be64 rx_1024b_1518b; 5891 __be64 rx_1519b_max; 5892 __be64 rx_pause; 5893 __be64 rx_ppp0; 5894 __be64 rx_ppp1; 5895 __be64 rx_ppp2; 5896 __be64 rx_ppp3; 5897 __be64 rx_ppp4; 5898 __be64 rx_ppp5; 5899 __be64 rx_ppp6; 5900 __be64 rx_ppp7; 5901 __be64 rx_less_64b; 5902 __be64 rx_bg_drop; 5903 __be64 rx_bg_trunc; 5904 } all; 5905 } u; 5906 }; 5907 5908 #define S_FW_PORT_STATS_CMD_NSTATS 4 5909 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 5910 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 5911 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 5912 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 5913 5914 #define S_FW_PORT_STATS_CMD_BG_BM 0 5915 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 5916 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 5917 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 5918 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 5919 5920 #define S_FW_PORT_STATS_CMD_TX 7 5921 #define M_FW_PORT_STATS_CMD_TX 0x1 5922 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 5923 #define G_FW_PORT_STATS_CMD_TX(x) \ 5924 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 5925 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 5926 5927 #define S_FW_PORT_STATS_CMD_IX 0 5928 #define M_FW_PORT_STATS_CMD_IX 0x3f 5929 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 5930 #define G_FW_PORT_STATS_CMD_IX(x) \ 5931 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 5932 5933 /* port loopback stats */ 5934 #define FW_NUM_LB_STATS 14 5935 enum fw_port_lb_stats_index { 5936 FW_STAT_LB_PORT_BYTES_IX, 5937 FW_STAT_LB_PORT_FRAMES_IX, 5938 FW_STAT_LB_PORT_BCAST_IX, 5939 FW_STAT_LB_PORT_MCAST_IX, 5940 FW_STAT_LB_PORT_UCAST_IX, 5941 FW_STAT_LB_PORT_ERROR_IX, 5942 FW_STAT_LB_PORT_64B_IX, 5943 FW_STAT_LB_PORT_65B_127B_IX, 5944 FW_STAT_LB_PORT_128B_255B_IX, 5945 FW_STAT_LB_PORT_256B_511B_IX, 5946 FW_STAT_LB_PORT_512B_1023B_IX, 5947 FW_STAT_LB_PORT_1024B_1518B_IX, 5948 FW_STAT_LB_PORT_1519B_MAX_IX, 5949 FW_STAT_LB_PORT_DROP_FRAMES_IX 5950 }; 5951 5952 struct fw_port_lb_stats_cmd { 5953 __be32 op_to_lbport; 5954 __be32 retval_len16; 5955 union fw_port_lb_stats { 5956 struct fw_port_lb_stats_ctl { 5957 __u8 nstats_bg_bm; 5958 __u8 ix_pkd; 5959 __be16 r6; 5960 __be32 r7; 5961 __be64 stat0; 5962 __be64 stat1; 5963 __be64 stat2; 5964 __be64 stat3; 5965 __be64 stat4; 5966 __be64 stat5; 5967 } ctl; 5968 struct fw_port_lb_stats_all { 5969 __be64 tx_bytes; 5970 __be64 tx_frames; 5971 __be64 tx_bcast; 5972 __be64 tx_mcast; 5973 __be64 tx_ucast; 5974 __be64 tx_error; 5975 __be64 tx_64b; 5976 __be64 tx_65b_127b; 5977 __be64 tx_128b_255b; 5978 __be64 tx_256b_511b; 5979 __be64 tx_512b_1023b; 5980 __be64 tx_1024b_1518b; 5981 __be64 tx_1519b_max; 5982 __be64 rx_lb_drop; 5983 __be64 rx_lb_trunc; 5984 } all; 5985 } u; 5986 }; 5987 5988 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 5989 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 5990 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 5991 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 5992 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 5993 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 5994 5995 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 5996 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 5997 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 5998 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 5999 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6000 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 6001 6002 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 6003 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 6004 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 6005 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 6006 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 6007 6008 #define S_FW_PORT_LB_STATS_CMD_IX 0 6009 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 6010 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 6011 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 6012 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 6013 6014 /* Trace related defines */ 6015 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 6016 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 6017 6018 struct fw_port_trace_cmd { 6019 __be32 op_to_portid; 6020 __be32 retval_len16; 6021 __be16 traceen_to_pciech; 6022 __be16 qnum; 6023 __be32 r5; 6024 }; 6025 6026 #define S_FW_PORT_TRACE_CMD_PORTID 0 6027 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 6028 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 6029 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 6030 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 6031 6032 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 6033 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 6034 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 6035 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 6036 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 6037 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 6038 6039 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 6040 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 6041 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 6042 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 6043 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 6044 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 6045 6046 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 6047 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 6048 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 6049 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 6050 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 6051 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 6052 6053 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 6054 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 6055 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6056 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6057 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6058 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 6059 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6060 6061 #define S_FW_PORT_TRACE_CMD_PCIECH 6 6062 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 6063 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 6064 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 6065 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 6066 6067 struct fw_port_trace_mmap_cmd { 6068 __be32 op_to_portid; 6069 __be32 retval_len16; 6070 __be32 fid_to_skipoffset; 6071 __be32 minpktsize_capturemax; 6072 __u8 map[224]; 6073 }; 6074 6075 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 6076 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 6077 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6078 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 6079 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6080 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 6081 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 6082 6083 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 6084 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 6085 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 6086 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 6087 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 6088 6089 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 6090 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 6091 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6092 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6093 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6094 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 6095 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6096 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 6097 6098 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 6099 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 6100 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6101 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6102 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6103 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 6104 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6105 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN \ 6106 V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 6107 6108 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 6109 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 6110 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6111 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6112 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6113 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 6114 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6115 6116 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 6117 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 6118 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6119 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6120 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6121 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 6122 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6123 6124 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 6125 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 6126 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6127 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6128 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6129 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 6130 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6131 6132 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 6133 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 6134 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6135 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6136 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6137 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 6138 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6139 6140 struct fw_rss_ind_tbl_cmd { 6141 __be32 op_to_viid; 6142 __be32 retval_len16; 6143 __be16 niqid; 6144 __be16 startidx; 6145 __be32 r3; 6146 __be32 iq0_to_iq2; 6147 __be32 iq3_to_iq5; 6148 __be32 iq6_to_iq8; 6149 __be32 iq9_to_iq11; 6150 __be32 iq12_to_iq14; 6151 __be32 iq15_to_iq17; 6152 __be32 iq18_to_iq20; 6153 __be32 iq21_to_iq23; 6154 __be32 iq24_to_iq26; 6155 __be32 iq27_to_iq29; 6156 __be32 iq30_iq31; 6157 __be32 r15_lo; 6158 }; 6159 6160 #define S_FW_RSS_IND_TBL_CMD_VIID 0 6161 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 6162 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 6163 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 6164 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 6165 6166 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 6167 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 6168 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 6169 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 6170 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 6171 6172 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 6173 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 6174 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 6175 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 6176 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 6177 6178 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 6179 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 6180 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 6181 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 6182 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 6183 6184 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 6185 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 6186 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 6187 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 6188 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 6189 6190 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 6191 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 6192 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 6193 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 6194 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 6195 6196 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 6197 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 6198 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 6199 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 6200 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 6201 6202 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 6203 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 6204 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 6205 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 6206 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 6207 6208 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 6209 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 6210 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 6211 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 6212 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 6213 6214 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 6215 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 6216 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 6217 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 6218 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 6219 6220 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 6221 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 6222 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 6223 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 6224 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 6225 6226 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 6227 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 6228 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 6229 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 6230 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 6231 6232 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 6233 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 6234 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 6235 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 6236 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 6237 6238 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 6239 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 6240 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 6241 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 6242 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 6243 6244 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 6245 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 6246 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 6247 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 6248 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 6249 6250 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 6251 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 6252 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 6253 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 6254 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 6255 6256 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 6257 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 6258 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 6259 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 6260 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 6261 6262 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 6263 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 6264 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 6265 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 6266 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 6267 6268 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 6269 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 6270 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 6271 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 6272 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 6273 6274 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 6275 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 6276 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 6277 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 6278 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 6279 6280 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 6281 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 6282 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 6283 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 6284 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 6285 6286 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 6287 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 6288 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 6289 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 6290 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 6291 6292 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 6293 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 6294 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 6295 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 6296 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 6297 6298 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 6299 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 6300 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 6301 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 6302 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 6303 6304 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 6305 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 6306 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 6307 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 6308 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 6309 6310 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 6311 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 6312 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 6313 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 6314 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 6315 6316 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 6317 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 6318 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 6319 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 6320 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 6321 6322 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 6323 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 6324 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 6325 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 6326 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 6327 6328 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 6329 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 6330 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 6331 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 6332 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 6333 6334 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 6335 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 6336 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 6337 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 6338 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 6339 6340 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 6341 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 6342 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 6343 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 6344 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 6345 6346 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 6347 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 6348 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 6349 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 6350 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 6351 6352 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 6353 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 6354 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 6355 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 6356 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 6357 6358 struct fw_rss_glb_config_cmd { 6359 __be32 op_to_write; 6360 __be32 retval_len16; 6361 union fw_rss_glb_config { 6362 struct fw_rss_glb_config_manual { 6363 __be32 mode_pkd; 6364 __be32 r3; 6365 __be64 r4; 6366 __be64 r5; 6367 } manual; 6368 struct fw_rss_glb_config_basicvirtual { 6369 __be32 mode_pkd; 6370 __be32 synmapen_to_hashtoeplitz; 6371 __be64 r8; 6372 __be64 r9; 6373 } basicvirtual; 6374 } u; 6375 }; 6376 6377 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 6378 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 6379 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 6380 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 6381 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 6382 6383 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 6384 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 6385 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 6386 6387 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 6388 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 6389 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6390 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6391 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6392 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 6393 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6394 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN \ 6395 V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 6396 6397 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 6398 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 6399 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6400 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6401 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6402 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 6403 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6404 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 6405 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 6406 6407 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 6408 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 6409 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6410 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6411 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6412 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 6413 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6414 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 6415 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 6416 6417 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 6418 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 6419 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6420 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6421 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6422 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 6423 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6424 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 6425 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 6426 6427 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 6428 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 6429 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6430 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6431 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6432 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 6433 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6434 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 6435 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 6436 6437 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 6438 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 6439 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6440 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6441 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6442 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 6443 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6444 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN \ 6445 V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 6446 6447 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 6448 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 6449 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6450 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6451 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6452 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 6453 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6454 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN \ 6455 V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 6456 6457 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 6458 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 6459 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6460 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6461 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6462 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 6463 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6464 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 6465 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 6466 6467 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 6468 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 6469 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6470 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6471 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6472 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 6473 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6474 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 6475 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 6476 6477 struct fw_rss_vi_config_cmd { 6478 __be32 op_to_viid; 6479 __be32 retval_len16; 6480 union fw_rss_vi_config { 6481 struct fw_rss_vi_config_manual { 6482 __be64 r3; 6483 __be64 r4; 6484 __be64 r5; 6485 } manual; 6486 struct fw_rss_vi_config_basicvirtual { 6487 __be32 r6; 6488 __be32 defaultq_to_udpen; 6489 __be64 r9; 6490 __be64 r10; 6491 } basicvirtual; 6492 } u; 6493 }; 6494 6495 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 6496 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 6497 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 6498 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 6499 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 6500 6501 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 6502 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 6503 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6504 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6505 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6506 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 6507 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6508 6509 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 6510 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 6511 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6512 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6513 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6514 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 6515 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6516 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 6517 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 6518 6519 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 6520 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 6521 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6522 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6523 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6524 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 6525 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6526 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 6527 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 6528 6529 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 6530 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 6531 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6532 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6533 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6534 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 6535 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6536 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 6537 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 6538 6539 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 6540 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 6541 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6542 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6543 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6544 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 6545 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6546 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 6547 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 6548 6549 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 6550 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 6551 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 6552 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 6553 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 6554 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 6555 6556 enum fw_sched_sc { 6557 FW_SCHED_SC_CONFIG = 0, 6558 FW_SCHED_SC_PARAMS = 1, 6559 }; 6560 6561 enum fw_sched_type { 6562 FW_SCHED_TYPE_PKTSCHED = 0, 6563 FW_SCHED_TYPE_STREAMSCHED = 1, 6564 }; 6565 6566 enum fw_sched_params_level { 6567 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 6568 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 6569 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 6570 FW_SCHED_PARAMS_LEVEL_CH_WRR = 3, 6571 }; 6572 6573 enum fw_sched_params_mode { 6574 FW_SCHED_PARAMS_MODE_CLASS = 0, 6575 FW_SCHED_PARAMS_MODE_FLOW = 1, 6576 }; 6577 6578 enum fw_sched_params_unit { 6579 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 6580 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 6581 }; 6582 6583 enum fw_sched_params_rate { 6584 FW_SCHED_PARAMS_RATE_REL = 0, 6585 FW_SCHED_PARAMS_RATE_ABS = 1, 6586 }; 6587 6588 struct fw_sched_cmd { 6589 __be32 op_to_write; 6590 __be32 retval_len16; 6591 union fw_sched { 6592 struct fw_sched_config { 6593 __u8 sc; 6594 __u8 type; 6595 __u8 minmaxen; 6596 __u8 r3[5]; 6597 } config; 6598 struct fw_sched_params { 6599 __u8 sc; 6600 __u8 type; 6601 __u8 level; 6602 __u8 mode; 6603 __u8 unit; 6604 __u8 rate; 6605 __u8 ch; 6606 __u8 cl; 6607 __be32 min; 6608 __be32 max; 6609 __be16 weight; 6610 __be16 pktsize; 6611 __be32 r4; 6612 } params; 6613 } u; 6614 }; 6615 6616 /* 6617 * length of the formatting string 6618 */ 6619 #define FW_DEVLOG_FMT_LEN 192 6620 6621 /* 6622 * maximum number of the formatting string parameters 6623 */ 6624 #define FW_DEVLOG_FMT_PARAMS_NUM 8 6625 6626 /* 6627 * priority levels 6628 */ 6629 enum fw_devlog_level { 6630 FW_DEVLOG_LEVEL_EMERG = 0x0, 6631 FW_DEVLOG_LEVEL_CRIT = 0x1, 6632 FW_DEVLOG_LEVEL_ERR = 0x2, 6633 FW_DEVLOG_LEVEL_NOTICE = 0x3, 6634 FW_DEVLOG_LEVEL_INFO = 0x4, 6635 FW_DEVLOG_LEVEL_DEBUG = 0x5, 6636 FW_DEVLOG_LEVEL_MAX = 0x5, 6637 }; 6638 6639 /* 6640 * facilities that may send a log message 6641 */ 6642 enum fw_devlog_facility { 6643 FW_DEVLOG_FACILITY_CORE = 0x00, 6644 FW_DEVLOG_FACILITY_SCHED = 0x02, 6645 FW_DEVLOG_FACILITY_TIMER = 0x04, 6646 FW_DEVLOG_FACILITY_RES = 0x06, 6647 FW_DEVLOG_FACILITY_HW = 0x08, 6648 FW_DEVLOG_FACILITY_FLR = 0x10, 6649 FW_DEVLOG_FACILITY_DMAQ = 0x12, 6650 FW_DEVLOG_FACILITY_PHY = 0x14, 6651 FW_DEVLOG_FACILITY_MAC = 0x16, 6652 FW_DEVLOG_FACILITY_PORT = 0x18, 6653 FW_DEVLOG_FACILITY_VI = 0x1A, 6654 FW_DEVLOG_FACILITY_FILTER = 0x1C, 6655 FW_DEVLOG_FACILITY_ACL = 0x1E, 6656 FW_DEVLOG_FACILITY_TM = 0x20, 6657 FW_DEVLOG_FACILITY_QFC = 0x22, 6658 FW_DEVLOG_FACILITY_DCB = 0x24, 6659 FW_DEVLOG_FACILITY_ETH = 0x26, 6660 FW_DEVLOG_FACILITY_OFLD = 0x28, 6661 FW_DEVLOG_FACILITY_RI = 0x2A, 6662 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 6663 FW_DEVLOG_FACILITY_FCOE = 0x2E, 6664 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 6665 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 6666 FW_DEVLOG_FACILITY_MAX = 0x32, 6667 }; 6668 6669 /* 6670 * log message format 6671 */ 6672 struct fw_devlog_e { 6673 __be64 timestamp; 6674 __be32 seqno; 6675 __be16 reserved1; 6676 __u8 level; 6677 __u8 facility; 6678 __u8 fmt[FW_DEVLOG_FMT_LEN]; 6679 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 6680 __be32 reserved3[4]; 6681 }; 6682 6683 struct fw_devlog_cmd { 6684 __be32 op_to_write; 6685 __be32 retval_len16; 6686 __u8 level; 6687 __u8 r2[7]; 6688 __be32 memtype_devlog_memaddr16_devlog; 6689 __be32 memsize_devlog; 6690 __be32 r3[2]; 6691 }; 6692 6693 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 6694 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 6695 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 6696 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 6697 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 6698 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 6699 6700 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 6701 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 6702 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 6703 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 6704 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 6705 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 6706 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 6707 6708 enum fw_watchdog_actions { 6709 FW_WATCHDOG_ACTION_FLR = 0x1, 6710 FW_WATCHDOG_ACTION_BYPASS = 0x2, 6711 }; 6712 6713 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 6714 6715 struct fw_watchdog_cmd { 6716 __be32 op_to_write; 6717 __be32 retval_len16; 6718 __be32 timeout; 6719 __be32 actions; 6720 }; 6721 6722 struct fw_clip_cmd { 6723 __be32 op_to_write; 6724 __be32 alloc_to_len16; 6725 __be64 ip_hi; 6726 __be64 ip_lo; 6727 __be32 r4[2]; 6728 }; 6729 6730 #define S_FW_CLIP_CMD_ALLOC 31 6731 #define M_FW_CLIP_CMD_ALLOC 0x1 6732 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 6733 #define G_FW_CLIP_CMD_ALLOC(x) \ 6734 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 6735 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 6736 6737 #define S_FW_CLIP_CMD_FREE 30 6738 #define M_FW_CLIP_CMD_FREE 0x1 6739 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 6740 #define G_FW_CLIP_CMD_FREE(x) \ 6741 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 6742 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 6743 6744 /****************************************************************************** 6745 * F O i S C S I C O M M A N D s 6746 **************************************/ 6747 6748 #define FW_CHNET_IFACE_ADDR_MAX 3 6749 6750 enum fw_chnet_iface_cmd_subop { 6751 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 6752 6753 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 6754 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 6755 6756 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 6757 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 6758 6759 FW_CHNET_IFACE_CMD_SUBOP_MAX, 6760 }; 6761 6762 struct fw_chnet_iface_cmd { 6763 __be32 op_to_portid; 6764 __be32 retval_len16; 6765 __u8 subop; 6766 __u8 r2[3]; 6767 __be32 ifid_ifstate; 6768 __be16 mtu; 6769 __be16 vlanid; 6770 __be32 r3; 6771 __be16 r4; 6772 __u8 mac[6]; 6773 }; 6774 6775 #define S_FW_CHNET_IFACE_CMD_PORTID 0 6776 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 6777 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 6778 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 6779 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 6780 6781 #define S_FW_CHNET_IFACE_CMD_IFID 8 6782 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 6783 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 6784 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 6785 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 6786 6787 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 6788 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 6789 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 6790 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 6791 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 6792 6793 /****************************************************************************** 6794 * F O F C O E C O M M A N D s 6795 ************************************/ 6796 6797 struct fw_fcoe_res_info_cmd { 6798 __be32 op_to_read; 6799 __be32 retval_len16; 6800 __be16 e_d_tov; 6801 __be16 r_a_tov_seq; 6802 __be16 r_a_tov_els; 6803 __be16 r_r_tov; 6804 __be32 max_xchgs; 6805 __be32 max_ssns; 6806 __be32 used_xchgs; 6807 __be32 used_ssns; 6808 __be32 max_fcfs; 6809 __be32 max_vnps; 6810 __be32 used_fcfs; 6811 __be32 used_vnps; 6812 }; 6813 6814 struct fw_fcoe_link_cmd { 6815 __be32 op_to_portid; 6816 __be32 retval_len16; 6817 __be32 sub_opcode_fcfi; 6818 __u8 r3; 6819 __u8 lstatus; 6820 __be16 flags; 6821 __u8 r4; 6822 __u8 set_vlan; 6823 __be16 vlan_id; 6824 __be32 vnpi_pkd; 6825 __be16 r6; 6826 __u8 phy_mac[6]; 6827 __u8 vnport_wwnn[8]; 6828 __u8 vnport_wwpn[8]; 6829 }; 6830 6831 #define S_FW_FCOE_LINK_CMD_PORTID 0 6832 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 6833 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 6834 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 6835 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 6836 6837 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 6838 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 6839 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 6840 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 6841 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 6842 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 6843 6844 #define S_FW_FCOE_LINK_CMD_FCFI 0 6845 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 6846 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 6847 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 6848 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 6849 6850 #define S_FW_FCOE_LINK_CMD_VNPI 0 6851 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 6852 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 6853 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 6854 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 6855 6856 struct fw_fcoe_vnp_cmd { 6857 __be32 op_to_fcfi; 6858 __be32 alloc_to_len16; 6859 __be32 gen_wwn_to_vnpi; 6860 __be32 vf_id; 6861 __be16 iqid; 6862 __u8 vnport_mac[6]; 6863 __u8 vnport_wwnn[8]; 6864 __u8 vnport_wwpn[8]; 6865 __u8 cmn_srv_parms[16]; 6866 __u8 clsp_word_0_1[8]; 6867 }; 6868 6869 #define S_FW_FCOE_VNP_CMD_FCFI 0 6870 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 6871 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 6872 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 6873 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 6874 6875 #define S_FW_FCOE_VNP_CMD_ALLOC 31 6876 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 6877 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 6878 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 6879 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 6880 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 6881 6882 #define S_FW_FCOE_VNP_CMD_FREE 30 6883 #define M_FW_FCOE_VNP_CMD_FREE 0x1 6884 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 6885 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 6886 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 6887 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 6888 6889 #define S_FW_FCOE_VNP_CMD_MODIFY 29 6890 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 6891 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 6892 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 6893 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 6894 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 6895 6896 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 6897 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 6898 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 6899 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 6900 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 6901 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 6902 6903 #define S_FW_FCOE_VNP_CMD_PERSIST 21 6904 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 6905 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 6906 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 6907 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 6908 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 6909 6910 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 6911 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 6912 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 6913 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 6914 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 6915 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 6916 6917 #define S_FW_FCOE_VNP_CMD_VNPI 0 6918 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 6919 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 6920 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 6921 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 6922 6923 struct fw_fcoe_sparams_cmd { 6924 __be32 op_to_portid; 6925 __be32 retval_len16; 6926 __u8 r3[7]; 6927 __u8 cos; 6928 __u8 lport_wwnn[8]; 6929 __u8 lport_wwpn[8]; 6930 __u8 cmn_srv_parms[16]; 6931 __u8 cls_srv_parms[16]; 6932 }; 6933 6934 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 6935 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 6936 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 6937 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 6938 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 6939 6940 struct fw_fcoe_stats_cmd { 6941 __be32 op_to_flowid; 6942 __be32 free_to_len16; 6943 union fw_fcoe_stats { 6944 struct fw_fcoe_stats_ctl { 6945 __u8 nstats_port; 6946 __u8 port_valid_ix; 6947 __be16 r6; 6948 __be32 r7; 6949 __be64 stat0; 6950 __be64 stat1; 6951 __be64 stat2; 6952 __be64 stat3; 6953 __be64 stat4; 6954 __be64 stat5; 6955 } ctl; 6956 struct fw_fcoe_port_stats { 6957 __be64 tx_bcast_bytes; 6958 __be64 tx_bcast_frames; 6959 __be64 tx_mcast_bytes; 6960 __be64 tx_mcast_frames; 6961 __be64 tx_ucast_bytes; 6962 __be64 tx_ucast_frames; 6963 __be64 tx_drop_frames; 6964 __be64 tx_offload_bytes; 6965 __be64 tx_offload_frames; 6966 __be64 rx_bcast_bytes; 6967 __be64 rx_bcast_frames; 6968 __be64 rx_mcast_bytes; 6969 __be64 rx_mcast_frames; 6970 __be64 rx_ucast_bytes; 6971 __be64 rx_ucast_frames; 6972 __be64 rx_err_frames; 6973 } port_stats; 6974 struct fw_fcoe_fcf_stats { 6975 __be32 fip_tx_bytes; 6976 __be32 fip_tx_fr; 6977 __be64 fcf_ka; 6978 __be64 mcast_adv_rcvd; 6979 __be16 ucast_adv_rcvd; 6980 __be16 sol_sent; 6981 __be16 vlan_req; 6982 __be16 vlan_rpl; 6983 __be16 clr_vlink; 6984 __be16 link_down; 6985 __be16 link_up; 6986 __be16 logo; 6987 __be16 flogi_req; 6988 __be16 flogi_rpl; 6989 __be16 fdisc_req; 6990 __be16 fdisc_rpl; 6991 __be16 fka_prd_chg; 6992 __be16 fc_map_chg; 6993 __be16 vfid_chg; 6994 __u8 no_fka_req; 6995 __u8 no_vnp; 6996 } fcf_stats; 6997 struct fw_fcoe_pcb_stats { 6998 __be64 tx_bytes; 6999 __be64 tx_frames; 7000 __be64 rx_bytes; 7001 __be64 rx_frames; 7002 __be32 vnp_ka; 7003 __be32 unsol_els_rcvd; 7004 __be64 unsol_cmd_rcvd; 7005 __be16 implicit_logo; 7006 __be16 flogi_inv_sparm; 7007 __be16 fdisc_inv_sparm; 7008 __be16 flogi_rjt; 7009 __be16 fdisc_rjt; 7010 __be16 no_ssn; 7011 __be16 mac_flt_fail; 7012 __be16 inv_fr_rcvd; 7013 } pcb_stats; 7014 struct fw_fcoe_scb_stats { 7015 __be64 tx_bytes; 7016 __be64 tx_frames; 7017 __be64 rx_bytes; 7018 __be64 rx_frames; 7019 __be32 host_abrt_req; 7020 __be32 adap_auto_abrt; 7021 __be32 adap_abrt_rsp; 7022 __be32 host_ios_req; 7023 __be16 ssn_offl_ios; 7024 __be16 ssn_not_rdy_ios; 7025 __u8 rx_data_ddp_err; 7026 __u8 ddp_flt_set_err; 7027 __be16 rx_data_fr_err; 7028 __u8 bad_st_abrt_req; 7029 __u8 no_io_abrt_req; 7030 __u8 abort_tmo; 7031 __u8 abort_tmo_2; 7032 __be32 abort_req; 7033 __u8 no_ppod_res_tmo; 7034 __u8 bp_tmo; 7035 __u8 adap_auto_cls; 7036 __u8 no_io_cls_req; 7037 __be32 host_cls_req; 7038 __be64 unsol_cmd_rcvd; 7039 __be32 plogi_req_rcvd; 7040 __be32 prli_req_rcvd; 7041 __be16 logo_req_rcvd; 7042 __be16 prlo_req_rcvd; 7043 __be16 plogi_rjt_rcvd; 7044 __be16 prli_rjt_rcvd; 7045 __be32 adisc_req_rcvd; 7046 __be32 rscn_rcvd; 7047 __be32 rrq_req_rcvd; 7048 __be32 unsol_els_rcvd; 7049 __u8 adisc_rjt_rcvd; 7050 __u8 scr_rjt; 7051 __u8 ct_rjt; 7052 __u8 inval_bls_rcvd; 7053 __be32 ba_rjt_rcvd; 7054 } scb_stats; 7055 } u; 7056 }; 7057 7058 #define S_FW_FCOE_STATS_CMD_FLOWID 0 7059 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 7060 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 7061 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 7062 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 7063 7064 #define S_FW_FCOE_STATS_CMD_FREE 30 7065 #define M_FW_FCOE_STATS_CMD_FREE 0x1 7066 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 7067 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 7068 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 7069 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 7070 7071 #define S_FW_FCOE_STATS_CMD_NSTATS 4 7072 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 7073 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 7074 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 7075 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 7076 7077 #define S_FW_FCOE_STATS_CMD_PORT 0 7078 #define M_FW_FCOE_STATS_CMD_PORT 0x3 7079 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 7080 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 7081 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 7082 7083 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 7084 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 7085 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7086 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 7087 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7088 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 7089 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 7090 7091 #define S_FW_FCOE_STATS_CMD_IX 0 7092 #define M_FW_FCOE_STATS_CMD_IX 0x3f 7093 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 7094 #define G_FW_FCOE_STATS_CMD_IX(x) \ 7095 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 7096 7097 struct fw_fcoe_fcf_cmd { 7098 __be32 op_to_fcfi; 7099 __be32 retval_len16; 7100 __be16 priority_pkd; 7101 __u8 mac[6]; 7102 __u8 name_id[8]; 7103 __u8 fabric[8]; 7104 __be16 vf_id; 7105 __be16 max_fcoe_size; 7106 __u8 vlan_id; 7107 __u8 fc_map[3]; 7108 __be32 fka_adv; 7109 __be32 r6; 7110 __u8 r7_hi; 7111 __u8 fpma_to_portid; 7112 __u8 spma_mac[6]; 7113 __be64 r8; 7114 }; 7115 7116 #define S_FW_FCOE_FCF_CMD_FCFI 0 7117 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 7118 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 7119 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 7120 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 7121 7122 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 7123 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 7124 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 7125 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 7126 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 7127 7128 #define S_FW_FCOE_FCF_CMD_FPMA 6 7129 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 7130 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 7131 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 7132 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 7133 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 7134 7135 #define S_FW_FCOE_FCF_CMD_SPMA 5 7136 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 7137 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 7138 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 7139 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 7140 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 7141 7142 #define S_FW_FCOE_FCF_CMD_LOGIN 4 7143 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 7144 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 7145 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 7146 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 7147 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 7148 7149 #define S_FW_FCOE_FCF_CMD_PORTID 0 7150 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 7151 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 7152 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 7153 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 7154 7155 /****************************************************************************** 7156 * E R R O R a n d D E B U G C O M M A N D s 7157 ******************************************************/ 7158 7159 enum fw_error_type { 7160 FW_ERROR_TYPE_EXCEPTION = 0x0, 7161 FW_ERROR_TYPE_HWMODULE = 0x1, 7162 FW_ERROR_TYPE_WR = 0x2, 7163 FW_ERROR_TYPE_ACL = 0x3, 7164 }; 7165 7166 struct fw_error_cmd { 7167 __be32 op_to_type; 7168 __be32 len16_pkd; 7169 union fw_error { 7170 struct fw_error_exception { 7171 __be32 info[6]; 7172 } exception; 7173 struct fw_error_hwmodule { 7174 __be32 regaddr; 7175 __be32 regval; 7176 } hwmodule; 7177 struct fw_error_wr { 7178 __be16 cidx; 7179 __be16 pfn_vfn; 7180 __be32 eqid; 7181 __u8 wrhdr[16]; 7182 } wr; 7183 struct fw_error_acl { 7184 __be16 cidx; 7185 __be16 pfn_vfn; 7186 __be32 eqid; 7187 __be16 mv_pkd; 7188 __u8 val[6]; 7189 __be64 r4; 7190 } acl; 7191 } u; 7192 }; 7193 7194 #define S_FW_ERROR_CMD_FATAL 4 7195 #define M_FW_ERROR_CMD_FATAL 0x1 7196 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 7197 #define G_FW_ERROR_CMD_FATAL(x) \ 7198 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 7199 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 7200 7201 #define S_FW_ERROR_CMD_TYPE 0 7202 #define M_FW_ERROR_CMD_TYPE 0xf 7203 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 7204 #define G_FW_ERROR_CMD_TYPE(x) \ 7205 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 7206 7207 #define S_FW_ERROR_CMD_PFN 8 7208 #define M_FW_ERROR_CMD_PFN 0x7 7209 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7210 #define G_FW_ERROR_CMD_PFN(x) \ 7211 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7212 7213 #define S_FW_ERROR_CMD_VFN 0 7214 #define M_FW_ERROR_CMD_VFN 0xff 7215 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7216 #define G_FW_ERROR_CMD_VFN(x) \ 7217 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7218 7219 #define S_FW_ERROR_CMD_PFN 8 7220 #define M_FW_ERROR_CMD_PFN 0x7 7221 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7222 #define G_FW_ERROR_CMD_PFN(x) \ 7223 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7224 7225 #define S_FW_ERROR_CMD_VFN 0 7226 #define M_FW_ERROR_CMD_VFN 0xff 7227 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7228 #define G_FW_ERROR_CMD_VFN(x) \ 7229 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7230 7231 #define S_FW_ERROR_CMD_MV 15 7232 #define M_FW_ERROR_CMD_MV 0x1 7233 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 7234 #define G_FW_ERROR_CMD_MV(x) \ 7235 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 7236 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 7237 7238 struct fw_debug_cmd { 7239 __be32 op_type; 7240 __be32 len16_pkd; 7241 union fw_debug { 7242 struct fw_debug_assert { 7243 __be32 fcid; 7244 __be32 line; 7245 __be32 x; 7246 __be32 y; 7247 __u8 filename_0_7[8]; 7248 __u8 filename_8_15[8]; 7249 __be64 r3; 7250 } assert; 7251 struct fw_debug_prt { 7252 __be16 dprtstridx; 7253 __be16 r3[3]; 7254 __be32 dprtstrparam0; 7255 __be32 dprtstrparam1; 7256 __be32 dprtstrparam2; 7257 __be32 dprtstrparam3; 7258 } prt; 7259 } u; 7260 }; 7261 7262 #define S_FW_DEBUG_CMD_TYPE 0 7263 #define M_FW_DEBUG_CMD_TYPE 0xff 7264 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 7265 #define G_FW_DEBUG_CMD_TYPE(x) \ 7266 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 7267 7268 /****************************************************************************** 7269 * P C I E F W R E G I S T E R 7270 **************************************/ 7271 7272 /** 7273 * Register definitions for the PCIE_FW register which the firmware uses 7274 * to retain status across RESETs. This register should be considered 7275 * as a READ-ONLY register for Host Software and only to be used to 7276 * track firmware initialization/error state, etc. 7277 */ 7278 #define S_PCIE_FW_ERR 31 7279 #define M_PCIE_FW_ERR 0x1 7280 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 7281 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 7282 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 7283 7284 #define S_PCIE_FW_INIT 30 7285 #define M_PCIE_FW_INIT 0x1 7286 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 7287 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 7288 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 7289 7290 #define S_PCIE_FW_HALT 29 7291 #define M_PCIE_FW_HALT 0x1 7292 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 7293 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 7294 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 7295 7296 #define S_PCIE_FW_STAGE 21 7297 #define M_PCIE_FW_STAGE 0x7 7298 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 7299 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 7300 7301 #define S_PCIE_FW_ASYNCNOT_VLD 20 7302 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 7303 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 7304 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 7305 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 7306 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 7307 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 7308 7309 #define S_PCIE_FW_ASYNCNOTINT 19 7310 #define M_PCIE_FW_ASYNCNOTINT 0x1 7311 #define V_PCIE_FW_ASYNCNOTINT(x) \ 7312 ((x) << S_PCIE_FW_ASYNCNOTINT) 7313 #define G_PCIE_FW_ASYNCNOTINT(x) \ 7314 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 7315 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 7316 7317 #define S_PCIE_FW_ASYNCNOT 16 7318 #define M_PCIE_FW_ASYNCNOT 0x7 7319 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 7320 #define G_PCIE_FW_ASYNCNOT(x) \ 7321 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 7322 7323 #define S_PCIE_FW_MASTER_VLD 15 7324 #define M_PCIE_FW_MASTER_VLD 0x1 7325 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 7326 #define G_PCIE_FW_MASTER_VLD(x) \ 7327 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 7328 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 7329 7330 #define S_PCIE_FW_MASTER 12 7331 #define M_PCIE_FW_MASTER 0x7 7332 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 7333 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 7334 7335 #define S_PCIE_FW_RESET_VLD 11 7336 #define M_PCIE_FW_RESET_VLD 0x1 7337 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 7338 #define G_PCIE_FW_RESET_VLD(x) \ 7339 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 7340 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 7341 7342 #define S_PCIE_FW_RESET 8 7343 #define M_PCIE_FW_RESET 0x7 7344 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 7345 #define G_PCIE_FW_RESET(x) \ 7346 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 7347 7348 #define S_PCIE_FW_REGISTERED 0 7349 #define M_PCIE_FW_REGISTERED 0xff 7350 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 7351 #define G_PCIE_FW_REGISTERED(x) \ 7352 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 7353 7354 7355 /****************************************************************************** 7356 * B I N A R Y H E A D E R F O R M A T 7357 **********************************************/ 7358 7359 /* 7360 * firmware binary header format 7361 */ 7362 struct fw_hdr { 7363 __u8 ver; 7364 __u8 chip; /* terminator chip family */ 7365 __be16 len512; /* bin length in units of 512-bytes */ 7366 __be32 fw_ver; /* firmware version */ 7367 __be32 tp_microcode_ver; /* tcp processor microcode version */ 7368 __u8 intfver_nic; 7369 __u8 intfver_vnic; 7370 __u8 intfver_ofld; 7371 __u8 intfver_ri; 7372 __u8 intfver_iscsipdu; 7373 __u8 intfver_iscsi; 7374 __u8 intfver_fcoe; 7375 __u8 reserved2; 7376 __u32 reserved3; 7377 __u32 reserved4; 7378 __u32 reserved5; 7379 __be32 flags; 7380 __be32 reserved6[23]; 7381 }; 7382 7383 enum fw_hdr_chip { 7384 FW_HDR_CHIP_T4, 7385 FW_HDR_CHIP_T5 7386 }; 7387 7388 #define S_FW_HDR_FW_VER_MAJOR 24 7389 #define M_FW_HDR_FW_VER_MAJOR 0xff 7390 #define V_FW_HDR_FW_VER_MAJOR(x) \ 7391 ((x) << S_FW_HDR_FW_VER_MAJOR) 7392 #define G_FW_HDR_FW_VER_MAJOR(x) \ 7393 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 7394 7395 #define S_FW_HDR_FW_VER_MINOR 16 7396 #define M_FW_HDR_FW_VER_MINOR 0xff 7397 #define V_FW_HDR_FW_VER_MINOR(x) \ 7398 ((x) << S_FW_HDR_FW_VER_MINOR) 7399 #define G_FW_HDR_FW_VER_MINOR(x) \ 7400 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 7401 7402 #define S_FW_HDR_FW_VER_MICRO 8 7403 #define M_FW_HDR_FW_VER_MICRO 0xff 7404 #define V_FW_HDR_FW_VER_MICRO(x) \ 7405 ((x) << S_FW_HDR_FW_VER_MICRO) 7406 #define G_FW_HDR_FW_VER_MICRO(x) \ 7407 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 7408 7409 #define S_FW_HDR_FW_VER_BUILD 0 7410 #define M_FW_HDR_FW_VER_BUILD 0xff 7411 #define V_FW_HDR_FW_VER_BUILD(x) \ 7412 ((x) << S_FW_HDR_FW_VER_BUILD) 7413 #define G_FW_HDR_FW_VER_BUILD(x) \ 7414 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 7415 7416 enum { 7417 FW_HDR_INTFVER_NIC = 0x00, 7418 FW_HDR_INTFVER_VNIC = 0x00, 7419 FW_HDR_INTFVER_OFLD = 0x00, 7420 FW_HDR_INTFVER_RI = 0x00, 7421 FW_HDR_INTFVER_ISCSIPDU = 0x00, 7422 FW_HDR_INTFVER_ISCSI = 0x00, 7423 FW_HDR_INTFVER_FCOE = 0x00, 7424 }; 7425 7426 enum fw_hdr_flags { 7427 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 7428 }; 7429 7430 #endif /* _T4FW_INTERFACE_H_ */ 7431