1 /*- 2 * Copyright (c) 2012 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _T4FW_INTERFACE_H_ 31 #define _T4FW_INTERFACE_H_ 32 33 /****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37 enum fw_retval { 38 FW_SUCCESS = 0, /* completed sucessfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_ENODEV = 19, /* no such device */ 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ 52 FW_ENODATA = 61, /* no data available */ 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ 61 FW_SCSI_ABORT_REQUESTED = 128, /* */ 62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 63 FW_SCSI_ABORTED = 130, /* */ 64 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 65 FW_ERR_LINK_DOWN = 132, /* */ 66 FW_RDEV_NOT_READY = 133, /* */ 67 FW_ERR_RDEV_LOST = 134, /* */ 68 FW_ERR_RDEV_LOGO = 135, /* */ 69 FW_FCOE_NO_XCHG = 136, /* */ 70 FW_SCSI_RSP_ERR = 137, /* */ 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76 }; 77 78 /****************************************************************************** 79 * W O R K R E Q U E S T s 80 ********************************/ 81 82 enum fw_wr_opcodes { 83 FW_FILTER_WR = 0x02, 84 FW_ULPTX_WR = 0x04, 85 FW_TP_WR = 0x05, 86 FW_ETH_TX_PKT_WR = 0x08, 87 FW_ETH_TX_PKTS_WR = 0x09, 88 FW_ETH_TX_UO_WR = 0x1c, 89 FW_EQ_FLUSH_WR = 0x1b, 90 FW_OFLD_CONNECTION_WR = 0x2f, 91 FW_FLOWC_WR = 0x0a, 92 FW_OFLD_TX_DATA_WR = 0x0b, 93 FW_CMD_WR = 0x10, 94 FW_ETH_TX_PKT_VM_WR = 0x11, 95 FW_RI_RES_WR = 0x0c, 96 FW_RI_RDMA_WRITE_WR = 0x14, 97 FW_RI_SEND_WR = 0x15, 98 FW_RI_RDMA_READ_WR = 0x16, 99 FW_RI_RECV_WR = 0x17, 100 FW_RI_BIND_MW_WR = 0x18, 101 FW_RI_FR_NSMR_WR = 0x19, 102 FW_RI_INV_LSTAG_WR = 0x1a, 103 FW_RI_SEND_IMMEDIATE_WR = 0x15, 104 FW_RI_ATOMIC_WR = 0x16, 105 FW_RI_WR = 0x0d, 106 FW_CHNET_IFCONF_WR = 0x6b, 107 FW_RDEV_WR = 0x38, 108 FW_FOISCSI_NODE_WR = 0x60, 109 FW_FOISCSI_CTRL_WR = 0x6a, 110 FW_FOISCSI_CHAP_WR = 0x6c, 111 FW_FCOE_ELS_CT_WR = 0x30, 112 FW_SCSI_WRITE_WR = 0x31, 113 FW_SCSI_READ_WR = 0x32, 114 FW_SCSI_CMD_WR = 0x33, 115 FW_SCSI_ABRT_CLS_WR = 0x34, 116 FW_SCSI_TGT_ACC_WR = 0x35, 117 FW_SCSI_TGT_XMIT_WR = 0x36, 118 FW_SCSI_TGT_RSP_WR = 0x37, 119 FW_POFCOE_TCB_WR = 0x42, 120 FW_POFCOE_ULPTX_WR = 0x43, 121 FW_LASTC2E_WR = 0x70 122 }; 123 124 /* 125 * Generic work request header flit0 126 */ 127 struct fw_wr_hdr { 128 __be32 hi; 129 __be32 lo; 130 }; 131 132 /* work request opcode (hi) 133 */ 134 #define S_FW_WR_OP 24 135 #define M_FW_WR_OP 0xff 136 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 137 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 138 139 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 140 */ 141 #define S_FW_WR_ATOMIC 23 142 #define M_FW_WR_ATOMIC 0x1 143 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 144 #define G_FW_WR_ATOMIC(x) \ 145 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 146 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 147 148 /* flush flag (hi) - firmware flushes flushable work request buffered 149 * in the flow context. 150 */ 151 #define S_FW_WR_FLUSH 22 152 #define M_FW_WR_FLUSH 0x1 153 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 154 #define G_FW_WR_FLUSH(x) \ 155 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 156 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 157 158 /* completion flag (hi) - firmware generates a cpl_fw6_ack 159 */ 160 #define S_FW_WR_COMPL 21 161 #define M_FW_WR_COMPL 0x1 162 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 163 #define G_FW_WR_COMPL(x) \ 164 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 165 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 166 167 168 /* work request immediate data lengh (hi) 169 */ 170 #define S_FW_WR_IMMDLEN 0 171 #define M_FW_WR_IMMDLEN 0xff 172 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 173 #define G_FW_WR_IMMDLEN(x) \ 174 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 175 176 /* egress queue status update to associated ingress queue entry (lo) 177 */ 178 #define S_FW_WR_EQUIQ 31 179 #define M_FW_WR_EQUIQ 0x1 180 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 181 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 182 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 183 184 /* egress queue status update to egress queue status entry (lo) 185 */ 186 #define S_FW_WR_EQUEQ 30 187 #define M_FW_WR_EQUEQ 0x1 188 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 189 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 190 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 191 192 /* flow context identifier (lo) 193 */ 194 #define S_FW_WR_FLOWID 8 195 #define M_FW_WR_FLOWID 0xfffff 196 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 197 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 198 199 /* length in units of 16-bytes (lo) 200 */ 201 #define S_FW_WR_LEN16 0 202 #define M_FW_WR_LEN16 0xff 203 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 204 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 205 206 /* valid filter configurations for compressed tuple 207 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 208 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 209 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 210 * OV - Outer VLAN/VNIC_ID, 211 */ 212 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 213 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 214 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 215 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 216 #define HW_TPL_FR_MT_E_PR_T 0x370 217 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 218 #define HW_TPL_FR_MT_E_T_P_FC 0X353 219 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 220 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 221 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 222 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 223 #define HW_TPL_FR_M_E_PR_FC 0X2E1 224 #define HW_TPL_FR_M_E_T_FC 0X2D1 225 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 226 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 227 #define HW_TPL_FR_M_T_IV_FC 0X299 228 #define HW_TPL_FR_M_T_OV_FC 0X295 229 #define HW_TPL_FR_E_PR_T_P 0X272 230 #define HW_TPL_FR_E_PR_T_FC 0X271 231 #define HW_TPL_FR_E_IV_FC 0X249 232 #define HW_TPL_FR_E_OV_FC 0X245 233 #define HW_TPL_FR_PR_T_IV_FC 0X239 234 #define HW_TPL_FR_PR_T_OV_FC 0X235 235 #define HW_TPL_FR_IV_OV_FC 0X20D 236 #define HW_TPL_MT_M_E_PR 0X1E0 237 #define HW_TPL_MT_M_E_T 0X1D0 238 #define HW_TPL_MT_E_PR_T_FC 0X171 239 #define HW_TPL_MT_E_IV 0X148 240 #define HW_TPL_MT_E_OV 0X144 241 #define HW_TPL_MT_PR_T_IV 0X138 242 #define HW_TPL_MT_PR_T_OV 0X134 243 #define HW_TPL_M_E_PR_P 0X0E2 244 #define HW_TPL_M_E_T_P 0X0D2 245 #define HW_TPL_E_PR_T_P_FC 0X073 246 #define HW_TPL_E_IV_P 0X04A 247 #define HW_TPL_E_OV_P 0X046 248 #define HW_TPL_PR_T_IV_P 0X03A 249 #define HW_TPL_PR_T_OV_P 0X036 250 251 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 252 enum fw_filter_wr_cookie { 253 FW_FILTER_WR_SUCCESS, 254 FW_FILTER_WR_FLT_ADDED, 255 FW_FILTER_WR_FLT_DELETED, 256 FW_FILTER_WR_SMT_TBL_FULL, 257 FW_FILTER_WR_EINVAL, 258 }; 259 260 struct fw_filter_wr { 261 __be32 op_pkd; 262 __be32 len16_pkd; 263 __be64 r3; 264 __be32 tid_to_iq; 265 __be32 del_filter_to_l2tix; 266 __be16 ethtype; 267 __be16 ethtypem; 268 __u8 frag_to_ovlan_vldm; 269 __u8 smac_sel; 270 __be16 rx_chan_rx_rpl_iq; 271 __be32 maci_to_matchtypem; 272 __u8 ptcl; 273 __u8 ptclm; 274 __u8 ttyp; 275 __u8 ttypm; 276 __be16 ivlan; 277 __be16 ivlanm; 278 __be16 ovlan; 279 __be16 ovlanm; 280 __u8 lip[16]; 281 __u8 lipm[16]; 282 __u8 fip[16]; 283 __u8 fipm[16]; 284 __be16 lp; 285 __be16 lpm; 286 __be16 fp; 287 __be16 fpm; 288 __be16 r7; 289 __u8 sma[6]; 290 }; 291 292 #define S_FW_FILTER_WR_TID 12 293 #define M_FW_FILTER_WR_TID 0xfffff 294 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 295 #define G_FW_FILTER_WR_TID(x) \ 296 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 297 298 #define S_FW_FILTER_WR_RQTYPE 11 299 #define M_FW_FILTER_WR_RQTYPE 0x1 300 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 301 #define G_FW_FILTER_WR_RQTYPE(x) \ 302 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 303 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 304 305 #define S_FW_FILTER_WR_NOREPLY 10 306 #define M_FW_FILTER_WR_NOREPLY 0x1 307 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 308 #define G_FW_FILTER_WR_NOREPLY(x) \ 309 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 310 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 311 312 #define S_FW_FILTER_WR_IQ 0 313 #define M_FW_FILTER_WR_IQ 0x3ff 314 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 315 #define G_FW_FILTER_WR_IQ(x) \ 316 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 317 318 #define S_FW_FILTER_WR_DEL_FILTER 31 319 #define M_FW_FILTER_WR_DEL_FILTER 0x1 320 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 321 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 322 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 323 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 324 325 #define S_FW_FILTER_WR_RPTTID 25 326 #define M_FW_FILTER_WR_RPTTID 0x1 327 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 328 #define G_FW_FILTER_WR_RPTTID(x) \ 329 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 330 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 331 332 #define S_FW_FILTER_WR_DROP 24 333 #define M_FW_FILTER_WR_DROP 0x1 334 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 335 #define G_FW_FILTER_WR_DROP(x) \ 336 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 337 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 338 339 #define S_FW_FILTER_WR_DIRSTEER 23 340 #define M_FW_FILTER_WR_DIRSTEER 0x1 341 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 342 #define G_FW_FILTER_WR_DIRSTEER(x) \ 343 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 344 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 345 346 #define S_FW_FILTER_WR_MASKHASH 22 347 #define M_FW_FILTER_WR_MASKHASH 0x1 348 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 349 #define G_FW_FILTER_WR_MASKHASH(x) \ 350 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 351 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 352 353 #define S_FW_FILTER_WR_DIRSTEERHASH 21 354 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 355 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 356 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 357 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 358 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 359 360 #define S_FW_FILTER_WR_LPBK 20 361 #define M_FW_FILTER_WR_LPBK 0x1 362 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 363 #define G_FW_FILTER_WR_LPBK(x) \ 364 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 365 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 366 367 #define S_FW_FILTER_WR_DMAC 19 368 #define M_FW_FILTER_WR_DMAC 0x1 369 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 370 #define G_FW_FILTER_WR_DMAC(x) \ 371 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 372 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 373 374 #define S_FW_FILTER_WR_SMAC 18 375 #define M_FW_FILTER_WR_SMAC 0x1 376 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 377 #define G_FW_FILTER_WR_SMAC(x) \ 378 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 379 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 380 381 #define S_FW_FILTER_WR_INSVLAN 17 382 #define M_FW_FILTER_WR_INSVLAN 0x1 383 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 384 #define G_FW_FILTER_WR_INSVLAN(x) \ 385 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 386 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 387 388 #define S_FW_FILTER_WR_RMVLAN 16 389 #define M_FW_FILTER_WR_RMVLAN 0x1 390 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 391 #define G_FW_FILTER_WR_RMVLAN(x) \ 392 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 393 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 394 395 #define S_FW_FILTER_WR_HITCNTS 15 396 #define M_FW_FILTER_WR_HITCNTS 0x1 397 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 398 #define G_FW_FILTER_WR_HITCNTS(x) \ 399 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 400 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 401 402 #define S_FW_FILTER_WR_TXCHAN 13 403 #define M_FW_FILTER_WR_TXCHAN 0x3 404 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 405 #define G_FW_FILTER_WR_TXCHAN(x) \ 406 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 407 408 #define S_FW_FILTER_WR_PRIO 12 409 #define M_FW_FILTER_WR_PRIO 0x1 410 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 411 #define G_FW_FILTER_WR_PRIO(x) \ 412 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 413 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 414 415 #define S_FW_FILTER_WR_L2TIX 0 416 #define M_FW_FILTER_WR_L2TIX 0xfff 417 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 418 #define G_FW_FILTER_WR_L2TIX(x) \ 419 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 420 421 #define S_FW_FILTER_WR_FRAG 7 422 #define M_FW_FILTER_WR_FRAG 0x1 423 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 424 #define G_FW_FILTER_WR_FRAG(x) \ 425 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 426 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 427 428 #define S_FW_FILTER_WR_FRAGM 6 429 #define M_FW_FILTER_WR_FRAGM 0x1 430 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 431 #define G_FW_FILTER_WR_FRAGM(x) \ 432 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 433 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 434 435 #define S_FW_FILTER_WR_IVLAN_VLD 5 436 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 437 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 438 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 439 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 440 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 441 442 #define S_FW_FILTER_WR_OVLAN_VLD 4 443 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 444 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 445 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 446 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 447 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 448 449 #define S_FW_FILTER_WR_IVLAN_VLDM 3 450 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 451 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 452 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 453 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 454 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 455 456 #define S_FW_FILTER_WR_OVLAN_VLDM 2 457 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 458 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 459 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 460 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 461 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 462 463 #define S_FW_FILTER_WR_RX_CHAN 15 464 #define M_FW_FILTER_WR_RX_CHAN 0x1 465 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 466 #define G_FW_FILTER_WR_RX_CHAN(x) \ 467 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 468 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 469 470 #define S_FW_FILTER_WR_RX_RPL_IQ 0 471 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 472 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 473 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 474 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 475 476 #define S_FW_FILTER_WR_MACI 23 477 #define M_FW_FILTER_WR_MACI 0x1ff 478 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 479 #define G_FW_FILTER_WR_MACI(x) \ 480 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 481 482 #define S_FW_FILTER_WR_MACIM 14 483 #define M_FW_FILTER_WR_MACIM 0x1ff 484 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 485 #define G_FW_FILTER_WR_MACIM(x) \ 486 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 487 488 #define S_FW_FILTER_WR_FCOE 13 489 #define M_FW_FILTER_WR_FCOE 0x1 490 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 491 #define G_FW_FILTER_WR_FCOE(x) \ 492 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 493 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 494 495 #define S_FW_FILTER_WR_FCOEM 12 496 #define M_FW_FILTER_WR_FCOEM 0x1 497 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 498 #define G_FW_FILTER_WR_FCOEM(x) \ 499 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 500 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 501 502 #define S_FW_FILTER_WR_PORT 9 503 #define M_FW_FILTER_WR_PORT 0x7 504 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 505 #define G_FW_FILTER_WR_PORT(x) \ 506 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 507 508 #define S_FW_FILTER_WR_PORTM 6 509 #define M_FW_FILTER_WR_PORTM 0x7 510 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 511 #define G_FW_FILTER_WR_PORTM(x) \ 512 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 513 514 #define S_FW_FILTER_WR_MATCHTYPE 3 515 #define M_FW_FILTER_WR_MATCHTYPE 0x7 516 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 517 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 518 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 519 520 #define S_FW_FILTER_WR_MATCHTYPEM 0 521 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 522 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 523 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 524 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 525 526 struct fw_ulptx_wr { 527 __be32 op_to_compl; 528 __be32 flowid_len16; 529 __u64 cookie; 530 }; 531 532 struct fw_tp_wr { 533 __be32 op_to_immdlen; 534 __be32 flowid_len16; 535 __u64 cookie; 536 }; 537 538 struct fw_eth_tx_pkt_wr { 539 __be32 op_immdlen; 540 __be32 equiq_to_len16; 541 __be64 r3; 542 }; 543 544 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 545 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 546 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 547 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 548 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 549 550 struct fw_eth_tx_pkts_wr { 551 __be32 op_pkd; 552 __be32 equiq_to_len16; 553 __be32 r3; 554 __be16 plen; 555 __u8 npkt; 556 __u8 type; 557 }; 558 559 struct fw_eth_tx_uo_wr { 560 __be32 op_immdlen; 561 __be32 equiq_to_len16; 562 __be64 r3; 563 __u8 r4; 564 __u8 ethlen; 565 __be16 iplen; 566 __u8 udplen; 567 __u8 rtplen; 568 __be16 r5; 569 __be16 mss; 570 __be16 schedpktsize; 571 __be32 length; 572 }; 573 574 struct fw_eq_flush_wr { 575 __u8 opcode; 576 __u8 r1[3]; 577 __be32 equiq_to_len16; 578 __be64 r3; 579 }; 580 581 struct fw_ofld_connection_wr { 582 __be32 op_compl; 583 __be32 len16_pkd; 584 __u64 cookie; 585 __be64 r2; 586 __be64 r3; 587 struct fw_ofld_connection_le { 588 __be32 version_cpl; 589 __be32 filter; 590 __be32 r1; 591 __be16 lport; 592 __be16 pport; 593 union fw_ofld_connection_leip { 594 struct fw_ofld_connection_le_ipv4 { 595 __be32 pip; 596 __be32 lip; 597 __be64 r0; 598 __be64 r1; 599 __be64 r2; 600 } ipv4; 601 struct fw_ofld_connection_le_ipv6 { 602 __be64 pip_hi; 603 __be64 pip_lo; 604 __be64 lip_hi; 605 __be64 lip_lo; 606 } ipv6; 607 } u; 608 } le; 609 struct fw_ofld_connection_tcb { 610 __be32 t_state_to_astid; 611 __be16 cplrxdataack_cplpassacceptrpl; 612 __be16 rcv_adv; 613 __be32 rcv_nxt; 614 __be32 tx_max; 615 __be64 opt0; 616 __be32 opt2; 617 __be32 r1; 618 __be64 r2; 619 __be64 r3; 620 } tcb; 621 }; 622 623 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 624 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 625 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 626 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 627 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 628 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 629 M_FW_OFLD_CONNECTION_WR_VERSION) 630 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 631 632 #define S_FW_OFLD_CONNECTION_WR_CPL 30 633 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 634 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 635 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 636 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 637 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 638 639 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 640 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 641 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 642 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 643 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 644 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 645 M_FW_OFLD_CONNECTION_WR_T_STATE) 646 647 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 648 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 649 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 650 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 651 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 652 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 653 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 654 655 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 656 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 657 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 658 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 659 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 660 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 661 662 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 663 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 664 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 665 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 666 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 667 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 668 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 669 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 670 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 671 672 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 673 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 674 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 675 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 676 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 677 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 678 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 679 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 680 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 681 682 enum fw_flowc_mnem_tcpstate { 683 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 684 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 685 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 686 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 687 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 688 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 689 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 690 * will resend FIN - equiv ESTAB 691 */ 692 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 693 * will resend FIN but have 694 * received FIN 695 */ 696 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 697 * will resend FIN but have 698 * received FIN 699 */ 700 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 701 * waiting for FIN 702 */ 703 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 704 }; 705 706 enum fw_flowc_mnem_uostate { 707 FW_FLOWC_MNEM_UOSTATE_CLOSED = 0, /* illegal */ 708 FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1, /* default */ 709 FW_FLOWC_MNEM_UOSTATE_CLOSING = 2, /* graceful close, after sending 710 * outstanding payload 711 */ 712 FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, /* immediate close, after 713 * discarding outstanding payload 714 */ 715 }; 716 717 enum fw_flowc_mnem { 718 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 719 FW_FLOWC_MNEM_CH = 1, 720 FW_FLOWC_MNEM_PORT = 2, 721 FW_FLOWC_MNEM_IQID = 3, 722 FW_FLOWC_MNEM_SNDNXT = 4, 723 FW_FLOWC_MNEM_RCVNXT = 5, 724 FW_FLOWC_MNEM_SNDBUF = 6, 725 FW_FLOWC_MNEM_MSS = 7, 726 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 727 FW_FLOWC_MNEM_TCPSTATE = 9, 728 FW_FLOWC_MNEM_UOSTATE = 10, 729 FW_FLOWC_MNEM_SCHEDCLASS = 11, 730 FW_FLOWC_MNEM_DCBPRIO = 12, 731 }; 732 733 struct fw_flowc_mnemval { 734 __u8 mnemonic; 735 __u8 r4[3]; 736 __be32 val; 737 }; 738 739 struct fw_flowc_wr { 740 __be32 op_to_nparams; 741 __be32 flowid_len16; 742 #ifndef C99_NOT_SUPPORTED 743 struct fw_flowc_mnemval mnemval[0]; 744 #endif 745 }; 746 747 #define S_FW_FLOWC_WR_NPARAMS 0 748 #define M_FW_FLOWC_WR_NPARAMS 0xff 749 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 750 #define G_FW_FLOWC_WR_NPARAMS(x) \ 751 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 752 753 struct fw_ofld_tx_data_wr { 754 __be32 op_to_immdlen; 755 __be32 flowid_len16; 756 __be32 plen; 757 __be32 tunnel_to_proxy; 758 }; 759 760 #define S_FW_OFLD_TX_DATA_WR_TUNNEL 19 761 #define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1 762 #define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL) 763 #define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \ 764 (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL) 765 #define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U) 766 767 #define S_FW_OFLD_TX_DATA_WR_SAVE 18 768 #define M_FW_OFLD_TX_DATA_WR_SAVE 0x1 769 #define V_FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SAVE) 770 #define G_FW_OFLD_TX_DATA_WR_SAVE(x) \ 771 (((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE) 772 #define F_FW_OFLD_TX_DATA_WR_SAVE V_FW_OFLD_TX_DATA_WR_SAVE(1U) 773 774 #define S_FW_OFLD_TX_DATA_WR_FLUSH 17 775 #define M_FW_OFLD_TX_DATA_WR_FLUSH 0x1 776 #define V_FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLUSH) 777 #define G_FW_OFLD_TX_DATA_WR_FLUSH(x) \ 778 (((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH) 779 #define F_FW_OFLD_TX_DATA_WR_FLUSH V_FW_OFLD_TX_DATA_WR_FLUSH(1U) 780 781 #define S_FW_OFLD_TX_DATA_WR_URGENT 16 782 #define M_FW_OFLD_TX_DATA_WR_URGENT 0x1 783 #define V_FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << S_FW_OFLD_TX_DATA_WR_URGENT) 784 #define G_FW_OFLD_TX_DATA_WR_URGENT(x) \ 785 (((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT) 786 #define F_FW_OFLD_TX_DATA_WR_URGENT V_FW_OFLD_TX_DATA_WR_URGENT(1U) 787 788 #define S_FW_OFLD_TX_DATA_WR_MORE 15 789 #define M_FW_OFLD_TX_DATA_WR_MORE 0x1 790 #define V_FW_OFLD_TX_DATA_WR_MORE(x) ((x) << S_FW_OFLD_TX_DATA_WR_MORE) 791 #define G_FW_OFLD_TX_DATA_WR_MORE(x) \ 792 (((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE) 793 #define F_FW_OFLD_TX_DATA_WR_MORE V_FW_OFLD_TX_DATA_WR_MORE(1U) 794 795 #define S_FW_OFLD_TX_DATA_WR_SHOVE 14 796 #define M_FW_OFLD_TX_DATA_WR_SHOVE 0x1 797 #define V_FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SHOVE) 798 #define G_FW_OFLD_TX_DATA_WR_SHOVE(x) \ 799 (((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE) 800 #define F_FW_OFLD_TX_DATA_WR_SHOVE V_FW_OFLD_TX_DATA_WR_SHOVE(1U) 801 802 #define S_FW_OFLD_TX_DATA_WR_ULPMODE 10 803 #define M_FW_OFLD_TX_DATA_WR_ULPMODE 0xf 804 #define V_FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE) 805 #define G_FW_OFLD_TX_DATA_WR_ULPMODE(x) \ 806 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE) 807 808 #define S_FW_OFLD_TX_DATA_WR_ULPSUBMODE 6 809 #define M_FW_OFLD_TX_DATA_WR_ULPSUBMODE 0xf 810 #define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 811 ((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 812 #define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 813 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \ 814 M_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 815 816 #define S_FW_OFLD_TX_DATA_WR_PROXY 5 817 #define M_FW_OFLD_TX_DATA_WR_PROXY 0x1 818 #define V_FW_OFLD_TX_DATA_WR_PROXY(x) ((x) << S_FW_OFLD_TX_DATA_WR_PROXY) 819 #define G_FW_OFLD_TX_DATA_WR_PROXY(x) \ 820 (((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY) 821 #define F_FW_OFLD_TX_DATA_WR_PROXY V_FW_OFLD_TX_DATA_WR_PROXY(1U) 822 823 struct fw_cmd_wr { 824 __be32 op_dma; 825 __be32 len16_pkd; 826 __be64 cookie_daddr; 827 }; 828 829 #define S_FW_CMD_WR_DMA 17 830 #define M_FW_CMD_WR_DMA 0x1 831 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 832 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 833 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 834 835 struct fw_eth_tx_pkt_vm_wr { 836 __be32 op_immdlen; 837 __be32 equiq_to_len16; 838 __be32 r3[2]; 839 __u8 ethmacdst[6]; 840 __u8 ethmacsrc[6]; 841 __be16 ethtype; 842 __be16 vlantci; 843 }; 844 845 /****************************************************************************** 846 * R I W O R K R E Q U E S T s 847 **************************************/ 848 849 enum fw_ri_wr_opcode { 850 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 851 FW_RI_READ_REQ = 0x1, 852 FW_RI_READ_RESP = 0x2, 853 FW_RI_SEND = 0x3, 854 FW_RI_SEND_WITH_INV = 0x4, 855 FW_RI_SEND_WITH_SE = 0x5, 856 FW_RI_SEND_WITH_SE_INV = 0x6, 857 FW_RI_TERMINATE = 0x7, 858 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 859 FW_RI_BIND_MW = 0x9, 860 FW_RI_FAST_REGISTER = 0xa, 861 FW_RI_LOCAL_INV = 0xb, 862 FW_RI_QP_MODIFY = 0xc, 863 FW_RI_BYPASS = 0xd, 864 FW_RI_RECEIVE = 0xe, 865 #if 0 866 FW_RI_SEND_IMMEDIATE = 0x8, 867 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 868 FW_RI_ATOMIC_REQUEST = 0xa, 869 FW_RI_ATOMIC_RESPONSE = 0xb, 870 871 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 872 FW_RI_FAST_REGISTER = 0xd, 873 FW_RI_LOCAL_INV = 0xe, 874 #endif 875 FW_RI_SGE_EC_CR_RETURN = 0xf 876 }; 877 878 enum fw_ri_wr_flags { 879 FW_RI_COMPLETION_FLAG = 0x01, 880 FW_RI_NOTIFICATION_FLAG = 0x02, 881 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 882 FW_RI_READ_FENCE_FLAG = 0x08, 883 FW_RI_LOCAL_FENCE_FLAG = 0x10, 884 FW_RI_RDMA_READ_INVALIDATE = 0x20 885 }; 886 887 enum fw_ri_mpa_attrs { 888 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 889 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 890 FW_RI_MPA_CRC_ENABLE = 0x04, 891 FW_RI_MPA_IETF_ENABLE = 0x08 892 }; 893 894 enum fw_ri_qp_caps { 895 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 896 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 897 FW_RI_QP_BIND_ENABLE = 0x04, 898 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 899 FW_RI_QP_STAG0_ENABLE = 0x10, 900 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 901 }; 902 903 enum fw_ri_addr_type { 904 FW_RI_ZERO_BASED_TO = 0x00, 905 FW_RI_VA_BASED_TO = 0x01 906 }; 907 908 enum fw_ri_mem_perms { 909 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 910 FW_RI_MEM_ACCESS_REM_READ = 0x02, 911 FW_RI_MEM_ACCESS_REM = 0x03, 912 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 913 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 914 FW_RI_MEM_ACCESS_LOCAL = 0x0C 915 }; 916 917 enum fw_ri_stag_type { 918 FW_RI_STAG_NSMR = 0x00, 919 FW_RI_STAG_SMR = 0x01, 920 FW_RI_STAG_MW = 0x02, 921 FW_RI_STAG_MW_RELAXED = 0x03 922 }; 923 924 enum fw_ri_data_op { 925 FW_RI_DATA_IMMD = 0x81, 926 FW_RI_DATA_DSGL = 0x82, 927 FW_RI_DATA_ISGL = 0x83 928 }; 929 930 enum fw_ri_sgl_depth { 931 FW_RI_SGL_DEPTH_MAX_SQ = 16, 932 FW_RI_SGL_DEPTH_MAX_RQ = 4 933 }; 934 935 enum fw_ri_cqe_err { 936 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 937 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 938 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 939 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 940 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 941 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 942 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 943 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 944 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 945 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 946 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 947 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 948 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 949 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 950 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 951 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 952 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 953 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 954 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 955 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 956 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 957 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 958 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 959 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 960 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 961 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 962 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 963 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 964 965 }; 966 967 struct fw_ri_dsge_pair { 968 __be32 len[2]; 969 __be64 addr[2]; 970 }; 971 972 struct fw_ri_dsgl { 973 __u8 op; 974 __u8 r1; 975 __be16 nsge; 976 __be32 len0; 977 __be64 addr0; 978 #ifndef C99_NOT_SUPPORTED 979 struct fw_ri_dsge_pair sge[0]; 980 #endif 981 }; 982 983 struct fw_ri_sge { 984 __be32 stag; 985 __be32 len; 986 __be64 to; 987 }; 988 989 struct fw_ri_isgl { 990 __u8 op; 991 __u8 r1; 992 __be16 nsge; 993 __be32 r2; 994 #ifndef C99_NOT_SUPPORTED 995 struct fw_ri_sge sge[0]; 996 #endif 997 }; 998 999 struct fw_ri_immd { 1000 __u8 op; 1001 __u8 r1; 1002 __be16 r2; 1003 __be32 immdlen; 1004 #ifndef C99_NOT_SUPPORTED 1005 __u8 data[0]; 1006 #endif 1007 }; 1008 1009 struct fw_ri_tpte { 1010 __be32 valid_to_pdid; 1011 __be32 locread_to_qpid; 1012 __be32 nosnoop_pbladdr; 1013 __be32 len_lo; 1014 __be32 va_hi; 1015 __be32 va_lo_fbo; 1016 __be32 dca_mwbcnt_pstag; 1017 __be32 len_hi; 1018 }; 1019 1020 #define S_FW_RI_TPTE_VALID 31 1021 #define M_FW_RI_TPTE_VALID 0x1 1022 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1023 #define G_FW_RI_TPTE_VALID(x) \ 1024 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1025 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1026 1027 #define S_FW_RI_TPTE_STAGKEY 23 1028 #define M_FW_RI_TPTE_STAGKEY 0xff 1029 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1030 #define G_FW_RI_TPTE_STAGKEY(x) \ 1031 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1032 1033 #define S_FW_RI_TPTE_STAGSTATE 22 1034 #define M_FW_RI_TPTE_STAGSTATE 0x1 1035 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1036 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1037 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1038 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1039 1040 #define S_FW_RI_TPTE_STAGTYPE 20 1041 #define M_FW_RI_TPTE_STAGTYPE 0x3 1042 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1043 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1044 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1045 1046 #define S_FW_RI_TPTE_PDID 0 1047 #define M_FW_RI_TPTE_PDID 0xfffff 1048 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1049 #define G_FW_RI_TPTE_PDID(x) \ 1050 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1051 1052 #define S_FW_RI_TPTE_PERM 28 1053 #define M_FW_RI_TPTE_PERM 0xf 1054 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1055 #define G_FW_RI_TPTE_PERM(x) \ 1056 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1057 1058 #define S_FW_RI_TPTE_REMINVDIS 27 1059 #define M_FW_RI_TPTE_REMINVDIS 0x1 1060 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1061 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1062 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1063 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1064 1065 #define S_FW_RI_TPTE_ADDRTYPE 26 1066 #define M_FW_RI_TPTE_ADDRTYPE 1 1067 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1068 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1069 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1070 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1071 1072 #define S_FW_RI_TPTE_MWBINDEN 25 1073 #define M_FW_RI_TPTE_MWBINDEN 0x1 1074 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1075 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1076 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1077 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1078 1079 #define S_FW_RI_TPTE_PS 20 1080 #define M_FW_RI_TPTE_PS 0x1f 1081 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1082 #define G_FW_RI_TPTE_PS(x) \ 1083 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1084 1085 #define S_FW_RI_TPTE_QPID 0 1086 #define M_FW_RI_TPTE_QPID 0xfffff 1087 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1088 #define G_FW_RI_TPTE_QPID(x) \ 1089 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1090 1091 #define S_FW_RI_TPTE_NOSNOOP 31 1092 #define M_FW_RI_TPTE_NOSNOOP 0x1 1093 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1094 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1095 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1096 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1097 1098 #define S_FW_RI_TPTE_PBLADDR 0 1099 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1100 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1101 #define G_FW_RI_TPTE_PBLADDR(x) \ 1102 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1103 1104 #define S_FW_RI_TPTE_DCA 24 1105 #define M_FW_RI_TPTE_DCA 0x1f 1106 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1107 #define G_FW_RI_TPTE_DCA(x) \ 1108 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1109 1110 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1111 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1112 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1113 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1114 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1115 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1116 1117 enum fw_ri_cqe_rxtx { 1118 FW_RI_CQE_RXTX_RX = 0x0, 1119 FW_RI_CQE_RXTX_TX = 0x1, 1120 }; 1121 1122 struct fw_ri_cqe { 1123 union fw_ri_rxtx { 1124 struct fw_ri_scqe { 1125 __be32 qpid_n_stat_rxtx_type; 1126 __be32 plen; 1127 __be32 reserved; 1128 __be32 wrid; 1129 } scqe; 1130 struct fw_ri_rcqe { 1131 __be32 qpid_n_stat_rxtx_type; 1132 __be32 plen; 1133 __be32 stag; 1134 __be32 msn; 1135 } rcqe; 1136 } u; 1137 }; 1138 1139 #define S_FW_RI_CQE_QPID 12 1140 #define M_FW_RI_CQE_QPID 0xfffff 1141 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1142 #define G_FW_RI_CQE_QPID(x) \ 1143 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1144 1145 #define S_FW_RI_CQE_NOTIFY 10 1146 #define M_FW_RI_CQE_NOTIFY 0x1 1147 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1148 #define G_FW_RI_CQE_NOTIFY(x) \ 1149 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1150 1151 #define S_FW_RI_CQE_STATUS 5 1152 #define M_FW_RI_CQE_STATUS 0x1f 1153 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1154 #define G_FW_RI_CQE_STATUS(x) \ 1155 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1156 1157 1158 #define S_FW_RI_CQE_RXTX 4 1159 #define M_FW_RI_CQE_RXTX 0x1 1160 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1161 #define G_FW_RI_CQE_RXTX(x) \ 1162 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1163 1164 #define S_FW_RI_CQE_TYPE 0 1165 #define M_FW_RI_CQE_TYPE 0xf 1166 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1167 #define G_FW_RI_CQE_TYPE(x) \ 1168 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1169 1170 enum fw_ri_res_type { 1171 FW_RI_RES_TYPE_SQ, 1172 FW_RI_RES_TYPE_RQ, 1173 FW_RI_RES_TYPE_CQ, 1174 }; 1175 1176 enum fw_ri_res_op { 1177 FW_RI_RES_OP_WRITE, 1178 FW_RI_RES_OP_RESET, 1179 }; 1180 1181 struct fw_ri_res { 1182 union fw_ri_restype { 1183 struct fw_ri_res_sqrq { 1184 __u8 restype; 1185 __u8 op; 1186 __be16 r3; 1187 __be32 eqid; 1188 __be32 r4[2]; 1189 __be32 fetchszm_to_iqid; 1190 __be32 dcaen_to_eqsize; 1191 __be64 eqaddr; 1192 } sqrq; 1193 struct fw_ri_res_cq { 1194 __u8 restype; 1195 __u8 op; 1196 __be16 r3; 1197 __be32 iqid; 1198 __be32 r4[2]; 1199 __be32 iqandst_to_iqandstindex; 1200 __be16 iqdroprss_to_iqesize; 1201 __be16 iqsize; 1202 __be64 iqaddr; 1203 __be32 iqns_iqro; 1204 __be32 r6_lo; 1205 __be64 r7; 1206 } cq; 1207 } u; 1208 }; 1209 1210 struct fw_ri_res_wr { 1211 __be32 op_nres; 1212 __be32 len16_pkd; 1213 __u64 cookie; 1214 #ifndef C99_NOT_SUPPORTED 1215 struct fw_ri_res res[0]; 1216 #endif 1217 }; 1218 1219 #define S_FW_RI_RES_WR_NRES 0 1220 #define M_FW_RI_RES_WR_NRES 0xff 1221 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1222 #define G_FW_RI_RES_WR_NRES(x) \ 1223 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1224 1225 #define S_FW_RI_RES_WR_FETCHSZM 26 1226 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1227 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1228 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1229 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1230 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1231 1232 #define S_FW_RI_RES_WR_STATUSPGNS 25 1233 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1234 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1235 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1236 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1237 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1238 1239 #define S_FW_RI_RES_WR_STATUSPGRO 24 1240 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1241 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1242 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1243 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1244 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1245 1246 #define S_FW_RI_RES_WR_FETCHNS 23 1247 #define M_FW_RI_RES_WR_FETCHNS 0x1 1248 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1249 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1250 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1251 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1252 1253 #define S_FW_RI_RES_WR_FETCHRO 22 1254 #define M_FW_RI_RES_WR_FETCHRO 0x1 1255 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1256 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1257 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1258 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1259 1260 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1261 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1262 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1263 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1264 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1265 1266 #define S_FW_RI_RES_WR_CPRIO 19 1267 #define M_FW_RI_RES_WR_CPRIO 0x1 1268 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1269 #define G_FW_RI_RES_WR_CPRIO(x) \ 1270 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1271 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1272 1273 #define S_FW_RI_RES_WR_ONCHIP 18 1274 #define M_FW_RI_RES_WR_ONCHIP 0x1 1275 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1276 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1277 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1278 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1279 1280 #define S_FW_RI_RES_WR_PCIECHN 16 1281 #define M_FW_RI_RES_WR_PCIECHN 0x3 1282 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1283 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1284 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1285 1286 #define S_FW_RI_RES_WR_IQID 0 1287 #define M_FW_RI_RES_WR_IQID 0xffff 1288 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1289 #define G_FW_RI_RES_WR_IQID(x) \ 1290 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1291 1292 #define S_FW_RI_RES_WR_DCAEN 31 1293 #define M_FW_RI_RES_WR_DCAEN 0x1 1294 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1295 #define G_FW_RI_RES_WR_DCAEN(x) \ 1296 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1297 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1298 1299 #define S_FW_RI_RES_WR_DCACPU 26 1300 #define M_FW_RI_RES_WR_DCACPU 0x1f 1301 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1302 #define G_FW_RI_RES_WR_DCACPU(x) \ 1303 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1304 1305 #define S_FW_RI_RES_WR_FBMIN 23 1306 #define M_FW_RI_RES_WR_FBMIN 0x7 1307 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1308 #define G_FW_RI_RES_WR_FBMIN(x) \ 1309 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1310 1311 #define S_FW_RI_RES_WR_FBMAX 20 1312 #define M_FW_RI_RES_WR_FBMAX 0x7 1313 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1314 #define G_FW_RI_RES_WR_FBMAX(x) \ 1315 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1316 1317 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1318 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1319 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1320 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1321 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1322 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1323 1324 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1325 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1326 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1327 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1328 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1329 1330 #define S_FW_RI_RES_WR_EQSIZE 0 1331 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1332 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1333 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1334 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1335 1336 #define S_FW_RI_RES_WR_IQANDST 15 1337 #define M_FW_RI_RES_WR_IQANDST 0x1 1338 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1339 #define G_FW_RI_RES_WR_IQANDST(x) \ 1340 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1341 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1342 1343 #define S_FW_RI_RES_WR_IQANUS 14 1344 #define M_FW_RI_RES_WR_IQANUS 0x1 1345 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1346 #define G_FW_RI_RES_WR_IQANUS(x) \ 1347 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1348 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1349 1350 #define S_FW_RI_RES_WR_IQANUD 12 1351 #define M_FW_RI_RES_WR_IQANUD 0x3 1352 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1353 #define G_FW_RI_RES_WR_IQANUD(x) \ 1354 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1355 1356 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1357 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1358 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1359 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1360 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1361 1362 #define S_FW_RI_RES_WR_IQDROPRSS 15 1363 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1364 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1365 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1366 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1367 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1368 1369 #define S_FW_RI_RES_WR_IQGTSMODE 14 1370 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1371 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1372 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1373 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1374 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1375 1376 #define S_FW_RI_RES_WR_IQPCIECH 12 1377 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1378 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1379 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1380 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1381 1382 #define S_FW_RI_RES_WR_IQDCAEN 11 1383 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1384 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1385 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1386 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1387 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1388 1389 #define S_FW_RI_RES_WR_IQDCACPU 6 1390 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1391 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1392 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1393 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1394 1395 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1396 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1397 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1398 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1399 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1400 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1401 1402 #define S_FW_RI_RES_WR_IQO 3 1403 #define M_FW_RI_RES_WR_IQO 0x1 1404 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1405 #define G_FW_RI_RES_WR_IQO(x) \ 1406 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1407 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1408 1409 #define S_FW_RI_RES_WR_IQCPRIO 2 1410 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1411 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1412 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1413 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1414 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1415 1416 #define S_FW_RI_RES_WR_IQESIZE 0 1417 #define M_FW_RI_RES_WR_IQESIZE 0x3 1418 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1419 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1420 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1421 1422 #define S_FW_RI_RES_WR_IQNS 31 1423 #define M_FW_RI_RES_WR_IQNS 0x1 1424 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1425 #define G_FW_RI_RES_WR_IQNS(x) \ 1426 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1427 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1428 1429 #define S_FW_RI_RES_WR_IQRO 30 1430 #define M_FW_RI_RES_WR_IQRO 0x1 1431 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1432 #define G_FW_RI_RES_WR_IQRO(x) \ 1433 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1434 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1435 1436 struct fw_ri_rdma_write_wr { 1437 __u8 opcode; 1438 __u8 flags; 1439 __u16 wrid; 1440 __u8 r1[3]; 1441 __u8 len16; 1442 __be64 r2; 1443 __be32 plen; 1444 __be32 stag_sink; 1445 __be64 to_sink; 1446 #ifndef C99_NOT_SUPPORTED 1447 union { 1448 struct fw_ri_immd immd_src[0]; 1449 struct fw_ri_isgl isgl_src[0]; 1450 } u; 1451 #endif 1452 }; 1453 1454 struct fw_ri_send_wr { 1455 __u8 opcode; 1456 __u8 flags; 1457 __u16 wrid; 1458 __u8 r1[3]; 1459 __u8 len16; 1460 __be32 sendop_pkd; 1461 __be32 stag_inv; 1462 __be32 plen; 1463 __be32 r3; 1464 __be64 r4; 1465 #ifndef C99_NOT_SUPPORTED 1466 union { 1467 struct fw_ri_immd immd_src[0]; 1468 struct fw_ri_isgl isgl_src[0]; 1469 } u; 1470 #endif 1471 }; 1472 1473 #define S_FW_RI_SEND_WR_SENDOP 0 1474 #define M_FW_RI_SEND_WR_SENDOP 0xf 1475 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1476 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1477 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1478 1479 struct fw_ri_rdma_read_wr { 1480 __u8 opcode; 1481 __u8 flags; 1482 __u16 wrid; 1483 __u8 r1[3]; 1484 __u8 len16; 1485 __be64 r2; 1486 __be32 stag_sink; 1487 __be32 to_sink_hi; 1488 __be32 to_sink_lo; 1489 __be32 plen; 1490 __be32 stag_src; 1491 __be32 to_src_hi; 1492 __be32 to_src_lo; 1493 __be32 r5; 1494 }; 1495 1496 struct fw_ri_recv_wr { 1497 __u8 opcode; 1498 __u8 r1; 1499 __u16 wrid; 1500 __u8 r2[3]; 1501 __u8 len16; 1502 struct fw_ri_isgl isgl; 1503 }; 1504 1505 struct fw_ri_bind_mw_wr { 1506 __u8 opcode; 1507 __u8 flags; 1508 __u16 wrid; 1509 __u8 r1[3]; 1510 __u8 len16; 1511 __u8 qpbinde_to_dcacpu; 1512 __u8 pgsz_shift; 1513 __u8 addr_type; 1514 __u8 mem_perms; 1515 __be32 stag_mr; 1516 __be32 stag_mw; 1517 __be32 r3; 1518 __be64 len_mw; 1519 __be64 va_fbo; 1520 __be64 r4; 1521 }; 1522 1523 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1524 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1525 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1526 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1527 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1528 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1529 1530 #define S_FW_RI_BIND_MW_WR_NS 5 1531 #define M_FW_RI_BIND_MW_WR_NS 0x1 1532 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1533 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1534 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1535 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1536 1537 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1538 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1539 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1540 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1541 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1542 1543 struct fw_ri_fr_nsmr_wr { 1544 __u8 opcode; 1545 __u8 flags; 1546 __u16 wrid; 1547 __u8 r1[3]; 1548 __u8 len16; 1549 __u8 qpbinde_to_dcacpu; 1550 __u8 pgsz_shift; 1551 __u8 addr_type; 1552 __u8 mem_perms; 1553 __be32 stag; 1554 __be32 len_hi; 1555 __be32 len_lo; 1556 __be32 va_hi; 1557 __be32 va_lo_fbo; 1558 }; 1559 1560 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1561 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1562 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1563 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1564 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1565 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1566 1567 #define S_FW_RI_FR_NSMR_WR_NS 5 1568 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1569 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1570 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1571 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1572 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1573 1574 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1575 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1576 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1577 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1578 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1579 1580 struct fw_ri_inv_lstag_wr { 1581 __u8 opcode; 1582 __u8 flags; 1583 __u16 wrid; 1584 __u8 r1[3]; 1585 __u8 len16; 1586 __be32 r2; 1587 __be32 stag_inv; 1588 }; 1589 1590 struct fw_ri_send_immediate_wr { 1591 __u8 opcode; 1592 __u8 flags; 1593 __u16 wrid; 1594 __u8 r1[3]; 1595 __u8 len16; 1596 __be32 sendimmop_pkd; 1597 __be32 r3; 1598 __be32 plen; 1599 __be32 r4; 1600 __be64 r5; 1601 #ifndef C99_NOT_SUPPORTED 1602 struct fw_ri_immd immd_src[0]; 1603 #endif 1604 }; 1605 1606 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1607 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1608 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1609 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1610 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1611 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1612 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1613 1614 enum fw_ri_atomic_op { 1615 FW_RI_ATOMIC_OP_FETCHADD, 1616 FW_RI_ATOMIC_OP_SWAP, 1617 FW_RI_ATOMIC_OP_CMDSWAP, 1618 }; 1619 1620 struct fw_ri_atomic_wr { 1621 __u8 opcode; 1622 __u8 flags; 1623 __u16 wrid; 1624 __u8 r1[3]; 1625 __u8 len16; 1626 __be32 atomicop_pkd; 1627 __be64 r3; 1628 __be32 aopcode_pkd; 1629 __be32 reqid; 1630 __be32 stag; 1631 __be32 to_hi; 1632 __be32 to_lo; 1633 __be32 addswap_data_hi; 1634 __be32 addswap_data_lo; 1635 __be32 addswap_mask_hi; 1636 __be32 addswap_mask_lo; 1637 __be32 compare_data_hi; 1638 __be32 compare_data_lo; 1639 __be32 compare_mask_hi; 1640 __be32 compare_mask_lo; 1641 __be32 r5; 1642 }; 1643 1644 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1645 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1646 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1647 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1648 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 1649 1650 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 1651 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1652 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1653 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1654 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 1655 1656 enum fw_ri_type { 1657 FW_RI_TYPE_INIT, 1658 FW_RI_TYPE_FINI, 1659 FW_RI_TYPE_TERMINATE 1660 }; 1661 1662 enum fw_ri_init_p2ptype { 1663 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 1664 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 1665 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 1666 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 1667 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 1668 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 1669 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 1670 }; 1671 1672 struct fw_ri_wr { 1673 __be32 op_compl; 1674 __be32 flowid_len16; 1675 __u64 cookie; 1676 union fw_ri { 1677 struct fw_ri_init { 1678 __u8 type; 1679 __u8 mpareqbit_p2ptype; 1680 __u8 r4[2]; 1681 __u8 mpa_attrs; 1682 __u8 qp_caps; 1683 __be16 nrqe; 1684 __be32 pdid; 1685 __be32 qpid; 1686 __be32 sq_eqid; 1687 __be32 rq_eqid; 1688 __be32 scqid; 1689 __be32 rcqid; 1690 __be32 ord_max; 1691 __be32 ird_max; 1692 __be32 iss; 1693 __be32 irs; 1694 __be32 hwrqsize; 1695 __be32 hwrqaddr; 1696 __be64 r5; 1697 union fw_ri_init_p2p { 1698 struct fw_ri_rdma_write_wr write; 1699 struct fw_ri_rdma_read_wr read; 1700 struct fw_ri_send_wr send; 1701 } u; 1702 } init; 1703 struct fw_ri_fini { 1704 __u8 type; 1705 __u8 r3[7]; 1706 __be64 r4; 1707 } fini; 1708 struct fw_ri_terminate { 1709 __u8 type; 1710 __u8 r3[3]; 1711 __be32 immdlen; 1712 __u8 termmsg[40]; 1713 } terminate; 1714 } u; 1715 }; 1716 1717 #define S_FW_RI_WR_MPAREQBIT 7 1718 #define M_FW_RI_WR_MPAREQBIT 0x1 1719 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 1720 #define G_FW_RI_WR_MPAREQBIT(x) \ 1721 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 1722 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 1723 1724 #define S_FW_RI_WR_0BRRBIT 6 1725 #define M_FW_RI_WR_0BRRBIT 0x1 1726 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 1727 #define G_FW_RI_WR_0BRRBIT(x) \ 1728 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 1729 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 1730 1731 #define S_FW_RI_WR_P2PTYPE 0 1732 #define M_FW_RI_WR_P2PTYPE 0xf 1733 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1734 #define G_FW_RI_WR_P2PTYPE(x) \ 1735 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1736 1737 /****************************************************************************** 1738 * F O i S C S I W O R K R E Q U E S T s 1739 *********************************************/ 1740 1741 #define FW_FOISCSI_NAME_MAX_LEN 224 1742 #define FW_FOISCSI_ALIAS_MAX_LEN 224 1743 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 1744 #define FW_FOISCSI_INIT_NODE_MAX 8 1745 1746 enum fw_chnet_ifconf_wr_subop { 1747 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 1748 1749 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 1750 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 1751 1752 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 1753 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 1754 1755 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 1756 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 1757 1758 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 1759 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 1760 1761 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 1762 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 1763 1764 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 1765 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 1766 1767 FW_CHNET_IFCONF_WR_SUBOP_MAX, 1768 }; 1769 1770 struct fw_chnet_ifconf_wr { 1771 __be32 op_compl; 1772 __be32 flowid_len16; 1773 __be64 cookie; 1774 __be32 if_flowid; 1775 __u8 idx; 1776 __u8 subop; 1777 __u8 retval; 1778 __u8 r2; 1779 __be64 r3; 1780 struct fw_chnet_ifconf_params { 1781 __be32 r0; 1782 __be16 vlanid; 1783 __be16 mtu; 1784 union fw_chnet_ifconf_addr_type { 1785 struct fw_chnet_ifconf_ipv4 { 1786 __be32 addr; 1787 __be32 mask; 1788 __be32 router; 1789 __be32 r0; 1790 __be64 r1; 1791 } ipv4; 1792 struct fw_chnet_ifconf_ipv6 { 1793 __be64 linklocal_lo; 1794 __be64 linklocal_hi; 1795 __be64 router_hi; 1796 __be64 router_lo; 1797 __be64 aconf_hi; 1798 __be64 aconf_lo; 1799 __be64 linklocal_aconf_hi; 1800 __be64 linklocal_aconf_lo; 1801 __be64 router_aconf_hi; 1802 __be64 router_aconf_lo; 1803 __be64 r0; 1804 } ipv6; 1805 } in_attr; 1806 } param; 1807 }; 1808 1809 enum fw_foiscsi_node_type { 1810 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 1811 FW_FOISCSI_NODE_TYPE_TARGET, 1812 }; 1813 1814 enum fw_foiscsi_session_type { 1815 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 1816 FW_FOISCSI_SESSION_TYPE_NORMAL, 1817 }; 1818 1819 enum fw_foiscsi_auth_policy { 1820 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 1821 FW_FOISCSI_AUTH_POLICY_MUTUAL, 1822 }; 1823 1824 enum fw_foiscsi_auth_method { 1825 FW_FOISCSI_AUTH_METHOD_NONE = 0, 1826 FW_FOISCSI_AUTH_METHOD_CHAP, 1827 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 1828 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 1829 }; 1830 1831 enum fw_foiscsi_digest_type { 1832 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 1833 FW_FOISCSI_DIGEST_TYPE_CRC32, 1834 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 1835 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 1836 }; 1837 1838 enum fw_foiscsi_wr_subop { 1839 FW_FOISCSI_WR_SUBOP_ADD = 1, 1840 FW_FOISCSI_WR_SUBOP_DEL = 2, 1841 FW_FOISCSI_WR_SUBOP_MOD = 4, 1842 }; 1843 1844 enum fw_foiscsi_ctrl_state { 1845 FW_FOISCSI_CTRL_STATE_FREE = 0, 1846 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 1847 FW_FOISCSI_CTRL_STATE_FAILED, 1848 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 1849 FW_FOISCSI_CTRL_STATE_REDIRECT, 1850 }; 1851 1852 struct fw_rdev_wr { 1853 __be32 op_to_immdlen; 1854 __be32 alloc_to_len16; 1855 __be64 cookie; 1856 __u8 protocol; 1857 __u8 event_cause; 1858 __u8 cur_state; 1859 __u8 prev_state; 1860 __be32 flags_to_assoc_flowid; 1861 union rdev_entry { 1862 struct fcoe_rdev_entry { 1863 __be32 flowid; 1864 __u8 protocol; 1865 __u8 event_cause; 1866 __u8 flags; 1867 __u8 rjt_reason; 1868 __u8 cur_login_st; 1869 __u8 prev_login_st; 1870 __be16 rcv_fr_sz; 1871 __u8 rd_xfer_rdy_to_rport_type; 1872 __u8 vft_to_qos; 1873 __u8 org_proc_assoc_to_acc_rsp_code; 1874 __u8 enh_disc_to_tgt; 1875 __u8 wwnn[8]; 1876 __u8 wwpn[8]; 1877 __be16 iqid; 1878 __u8 fc_oui[3]; 1879 __u8 r_id[3]; 1880 } fcoe_rdev; 1881 struct iscsi_rdev_entry { 1882 __be32 flowid; 1883 __u8 protocol; 1884 __u8 event_cause; 1885 __u8 flags; 1886 __u8 r3; 1887 __be16 iscsi_opts; 1888 __be16 tcp_opts; 1889 __be16 ip_opts; 1890 __be16 max_rcv_len; 1891 __be16 max_snd_len; 1892 __be16 first_brst_len; 1893 __be16 max_brst_len; 1894 __be16 r4; 1895 __be16 def_time2wait; 1896 __be16 def_time2ret; 1897 __be16 nop_out_intrvl; 1898 __be16 non_scsi_to; 1899 __be16 isid; 1900 __be16 tsid; 1901 __be16 port; 1902 __be16 tpgt; 1903 __u8 r5[6]; 1904 __be16 iqid; 1905 } iscsi_rdev; 1906 } u; 1907 }; 1908 1909 #define S_FW_RDEV_WR_IMMDLEN 0 1910 #define M_FW_RDEV_WR_IMMDLEN 0xff 1911 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 1912 #define G_FW_RDEV_WR_IMMDLEN(x) \ 1913 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 1914 1915 #define S_FW_RDEV_WR_ALLOC 31 1916 #define M_FW_RDEV_WR_ALLOC 0x1 1917 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 1918 #define G_FW_RDEV_WR_ALLOC(x) \ 1919 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 1920 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 1921 1922 #define S_FW_RDEV_WR_FREE 30 1923 #define M_FW_RDEV_WR_FREE 0x1 1924 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 1925 #define G_FW_RDEV_WR_FREE(x) \ 1926 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 1927 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 1928 1929 #define S_FW_RDEV_WR_MODIFY 29 1930 #define M_FW_RDEV_WR_MODIFY 0x1 1931 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 1932 #define G_FW_RDEV_WR_MODIFY(x) \ 1933 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 1934 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 1935 1936 #define S_FW_RDEV_WR_FLOWID 8 1937 #define M_FW_RDEV_WR_FLOWID 0xfffff 1938 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 1939 #define G_FW_RDEV_WR_FLOWID(x) \ 1940 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 1941 1942 #define S_FW_RDEV_WR_LEN16 0 1943 #define M_FW_RDEV_WR_LEN16 0xff 1944 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 1945 #define G_FW_RDEV_WR_LEN16(x) \ 1946 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 1947 1948 #define S_FW_RDEV_WR_FLAGS 24 1949 #define M_FW_RDEV_WR_FLAGS 0xff 1950 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 1951 #define G_FW_RDEV_WR_FLAGS(x) \ 1952 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 1953 1954 #define S_FW_RDEV_WR_GET_NEXT 20 1955 #define M_FW_RDEV_WR_GET_NEXT 0xf 1956 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 1957 #define G_FW_RDEV_WR_GET_NEXT(x) \ 1958 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 1959 1960 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 1961 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 1962 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 1963 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 1964 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 1965 1966 #define S_FW_RDEV_WR_RJT 7 1967 #define M_FW_RDEV_WR_RJT 0x1 1968 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 1969 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 1970 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 1971 1972 #define S_FW_RDEV_WR_REASON 0 1973 #define M_FW_RDEV_WR_REASON 0x7f 1974 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 1975 #define G_FW_RDEV_WR_REASON(x) \ 1976 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 1977 1978 #define S_FW_RDEV_WR_RD_XFER_RDY 7 1979 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 1980 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 1981 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 1982 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 1983 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 1984 1985 #define S_FW_RDEV_WR_WR_XFER_RDY 6 1986 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 1987 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 1988 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 1989 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 1990 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 1991 1992 #define S_FW_RDEV_WR_FC_SP 5 1993 #define M_FW_RDEV_WR_FC_SP 0x1 1994 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 1995 #define G_FW_RDEV_WR_FC_SP(x) \ 1996 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 1997 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 1998 1999 #define S_FW_RDEV_WR_RPORT_TYPE 0 2000 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2001 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2002 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2003 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2004 2005 #define S_FW_RDEV_WR_VFT 7 2006 #define M_FW_RDEV_WR_VFT 0x1 2007 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2008 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2009 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2010 2011 #define S_FW_RDEV_WR_NPIV 6 2012 #define M_FW_RDEV_WR_NPIV 0x1 2013 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2014 #define G_FW_RDEV_WR_NPIV(x) \ 2015 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2016 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2017 2018 #define S_FW_RDEV_WR_CLASS 4 2019 #define M_FW_RDEV_WR_CLASS 0x3 2020 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2021 #define G_FW_RDEV_WR_CLASS(x) \ 2022 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2023 2024 #define S_FW_RDEV_WR_SEQ_DEL 3 2025 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2026 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2027 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2028 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2029 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2030 2031 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2032 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2033 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2034 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2035 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2036 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2037 2038 #define S_FW_RDEV_WR_PREF 1 2039 #define M_FW_RDEV_WR_PREF 0x1 2040 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2041 #define G_FW_RDEV_WR_PREF(x) \ 2042 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2043 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2044 2045 #define S_FW_RDEV_WR_QOS 0 2046 #define M_FW_RDEV_WR_QOS 0x1 2047 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2048 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2049 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2050 2051 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2052 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2053 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2054 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2055 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2056 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2057 2058 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2059 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2060 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2061 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2062 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2063 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2064 2065 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2066 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2067 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2068 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2069 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2070 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2071 2072 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2073 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2074 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2075 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2076 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2077 2078 #define S_FW_RDEV_WR_ENH_DISC 7 2079 #define M_FW_RDEV_WR_ENH_DISC 0x1 2080 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2081 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2082 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2083 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2084 2085 #define S_FW_RDEV_WR_REC 6 2086 #define M_FW_RDEV_WR_REC 0x1 2087 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2088 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2089 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2090 2091 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2092 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2093 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2094 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2095 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2096 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2097 2098 #define S_FW_RDEV_WR_RETRY 4 2099 #define M_FW_RDEV_WR_RETRY 0x1 2100 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2101 #define G_FW_RDEV_WR_RETRY(x) \ 2102 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2103 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2104 2105 #define S_FW_RDEV_WR_CONF_CMPL 3 2106 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2107 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2108 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2109 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2110 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2111 2112 #define S_FW_RDEV_WR_DATA_OVLY 2 2113 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2114 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2115 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2116 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2117 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2118 2119 #define S_FW_RDEV_WR_INI 1 2120 #define M_FW_RDEV_WR_INI 0x1 2121 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2122 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2123 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2124 2125 #define S_FW_RDEV_WR_TGT 0 2126 #define M_FW_RDEV_WR_TGT 0x1 2127 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2128 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2129 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2130 2131 struct fw_foiscsi_node_wr { 2132 __be32 op_to_immdlen; 2133 __be32 flowid_len16; 2134 __u64 cookie; 2135 __u8 subop; 2136 __u8 status; 2137 __u8 alias_len; 2138 __u8 iqn_len; 2139 __be32 node_flowid; 2140 __be16 nodeid; 2141 __be16 login_retry; 2142 __be16 retry_timeout; 2143 __be16 r3; 2144 __u8 iqn[224]; 2145 __u8 alias[224]; 2146 }; 2147 2148 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2149 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2150 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2151 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2152 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2153 2154 struct fw_foiscsi_ctrl_wr { 2155 __be32 op_compl; 2156 __be32 flowid_len16; 2157 __u64 cookie; 2158 __u8 subop; 2159 __u8 status; 2160 __u8 ctrl_state; 2161 __u8 io_state; 2162 __be32 node_id; 2163 __be32 ctrl_id; 2164 __be32 io_id; 2165 struct fw_foiscsi_sess_attr { 2166 __be32 sess_type_to_erl; 2167 __be16 max_conn; 2168 __be16 max_r2t; 2169 __be16 time2wait; 2170 __be16 time2retain; 2171 __be32 max_burst; 2172 __be32 first_burst; 2173 __be32 r1; 2174 } sess_attr; 2175 struct fw_foiscsi_conn_attr { 2176 __be32 hdigest_to_ddp_pgsz; 2177 __be32 max_rcv_dsl; 2178 __be32 ping_tmo; 2179 __be16 dst_port; 2180 __be16 src_port; 2181 union fw_foiscsi_conn_attr_addr { 2182 struct fw_foiscsi_conn_attr_ipv6 { 2183 __be64 dst_addr[2]; 2184 __be64 src_addr[2]; 2185 } ipv6_addr; 2186 struct fw_foiscsi_conn_attr_ipv4 { 2187 __be32 dst_addr; 2188 __be32 src_addr; 2189 } ipv4_addr; 2190 } u; 2191 } conn_attr; 2192 __u8 tgt_name_len; 2193 __u8 r3[7]; 2194 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2195 }; 2196 2197 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2198 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2199 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2200 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2201 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2202 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2203 2204 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2205 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2206 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2207 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2208 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2209 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2210 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2211 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2212 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2213 2214 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2215 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2216 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2217 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2218 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2219 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2220 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2221 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2222 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2223 2224 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2225 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2226 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2227 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2228 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2229 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2230 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2231 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2232 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2233 2234 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2235 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2236 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2237 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2238 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2239 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2240 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2241 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2242 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2243 2244 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2245 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2246 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2247 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2248 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2249 2250 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2251 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2252 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2253 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2254 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2255 2256 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2257 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2258 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2259 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2260 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2261 2262 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2263 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2264 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2265 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2266 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2267 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2268 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2269 2270 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2271 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2272 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2273 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2274 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2275 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2276 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2277 2278 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2279 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2280 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2281 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2282 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2283 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2284 2285 struct fw_foiscsi_chap_wr { 2286 __be32 op_compl; 2287 __be32 flowid_len16; 2288 __u64 cookie; 2289 __u8 status; 2290 __u8 id_len; 2291 __u8 sec_len; 2292 __u8 node_type; 2293 __be16 node_id; 2294 __u8 r3[2]; 2295 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2296 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 2297 }; 2298 2299 /****************************************************************************** 2300 * F O F C O E W O R K R E Q U E S T s 2301 *******************************************/ 2302 2303 struct fw_fcoe_els_ct_wr { 2304 __be32 op_immdlen; 2305 __be32 flowid_len16; 2306 __be64 cookie; 2307 __be16 iqid; 2308 __u8 tmo_val; 2309 __u8 els_ct_type; 2310 __u8 ctl_pri; 2311 __u8 cp_en_class; 2312 __be16 xfer_cnt; 2313 __u8 fl_to_sp; 2314 __u8 l_id[3]; 2315 __u8 r5; 2316 __u8 r_id[3]; 2317 __be64 rsp_dmaaddr; 2318 __be32 rsp_dmalen; 2319 __be32 r6; 2320 }; 2321 2322 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2323 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2324 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2325 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2326 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2327 2328 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2329 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2330 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2331 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2332 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2333 2334 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2335 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2336 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2337 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2338 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2339 2340 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 2341 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2342 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2343 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2344 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2345 2346 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2347 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2348 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2349 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2350 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2351 2352 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 2353 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2354 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2355 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2356 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2357 2358 #define S_FW_FCOE_ELS_CT_WR_FL 2 2359 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 2360 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2361 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2362 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2363 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2364 2365 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 2366 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2367 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2368 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2369 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2370 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2371 2372 #define S_FW_FCOE_ELS_CT_WR_SP 0 2373 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 2374 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2375 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2376 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2377 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2378 2379 /****************************************************************************** 2380 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2381 *****************************************************************************/ 2382 2383 struct fw_scsi_write_wr { 2384 __be32 op_immdlen; 2385 __be32 flowid_len16; 2386 __be64 cookie; 2387 __be16 iqid; 2388 __u8 tmo_val; 2389 __u8 use_xfer_cnt; 2390 union fw_scsi_write_priv { 2391 struct fcoe_write_priv { 2392 __u8 ctl_pri; 2393 __u8 cp_en_class; 2394 __u8 r3_lo[2]; 2395 } fcoe; 2396 struct iscsi_write_priv { 2397 __u8 r3[4]; 2398 } iscsi; 2399 } u; 2400 __be32 xfer_cnt; 2401 __be32 ini_xfer_cnt; 2402 __be64 rsp_dmaaddr; 2403 __be32 rsp_dmalen; 2404 __be32 r4; 2405 }; 2406 2407 #define S_FW_SCSI_WRITE_WR_OPCODE 24 2408 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2409 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2410 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2411 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2412 2413 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2414 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2415 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2416 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2417 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2418 2419 #define S_FW_SCSI_WRITE_WR_FLOWID 8 2420 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2421 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2422 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2423 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2424 2425 #define S_FW_SCSI_WRITE_WR_LEN16 0 2426 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 2427 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2428 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2429 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2430 2431 #define S_FW_SCSI_WRITE_WR_CP_EN 6 2432 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2433 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2434 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2435 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2436 2437 #define S_FW_SCSI_WRITE_WR_CLASS 4 2438 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 2439 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2440 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2441 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 2442 2443 struct fw_scsi_read_wr { 2444 __be32 op_immdlen; 2445 __be32 flowid_len16; 2446 __be64 cookie; 2447 __be16 iqid; 2448 __u8 tmo_val; 2449 __u8 use_xfer_cnt; 2450 union fw_scsi_read_priv { 2451 struct fcoe_read_priv { 2452 __u8 ctl_pri; 2453 __u8 cp_en_class; 2454 __u8 r3_lo[2]; 2455 } fcoe; 2456 struct iscsi_read_priv { 2457 __u8 r3[4]; 2458 } iscsi; 2459 } u; 2460 __be32 xfer_cnt; 2461 __be32 ini_xfer_cnt; 2462 __be64 rsp_dmaaddr; 2463 __be32 rsp_dmalen; 2464 __be32 r4; 2465 }; 2466 2467 #define S_FW_SCSI_READ_WR_OPCODE 24 2468 #define M_FW_SCSI_READ_WR_OPCODE 0xff 2469 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2470 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 2471 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2472 2473 #define S_FW_SCSI_READ_WR_IMMDLEN 0 2474 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2475 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2476 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2477 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2478 2479 #define S_FW_SCSI_READ_WR_FLOWID 8 2480 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2481 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2482 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 2483 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2484 2485 #define S_FW_SCSI_READ_WR_LEN16 0 2486 #define M_FW_SCSI_READ_WR_LEN16 0xff 2487 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2488 #define G_FW_SCSI_READ_WR_LEN16(x) \ 2489 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2490 2491 #define S_FW_SCSI_READ_WR_CP_EN 6 2492 #define M_FW_SCSI_READ_WR_CP_EN 0x3 2493 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2494 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 2495 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 2496 2497 #define S_FW_SCSI_READ_WR_CLASS 4 2498 #define M_FW_SCSI_READ_WR_CLASS 0x3 2499 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 2500 #define G_FW_SCSI_READ_WR_CLASS(x) \ 2501 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 2502 2503 struct fw_scsi_cmd_wr { 2504 __be32 op_immdlen; 2505 __be32 flowid_len16; 2506 __be64 cookie; 2507 __be16 iqid; 2508 __u8 tmo_val; 2509 __u8 r3; 2510 union fw_scsi_cmd_priv { 2511 struct fcoe_cmd_priv { 2512 __u8 ctl_pri; 2513 __u8 cp_en_class; 2514 __u8 r4_lo[2]; 2515 } fcoe; 2516 struct iscsi_cmd_priv { 2517 __u8 r4[4]; 2518 } iscsi; 2519 } u; 2520 __u8 r5[8]; 2521 __be64 rsp_dmaaddr; 2522 __be32 rsp_dmalen; 2523 __be32 r6; 2524 }; 2525 2526 #define S_FW_SCSI_CMD_WR_OPCODE 24 2527 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 2528 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 2529 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 2530 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 2531 2532 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 2533 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 2534 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 2535 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 2536 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 2537 2538 #define S_FW_SCSI_CMD_WR_FLOWID 8 2539 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 2540 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 2541 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 2542 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 2543 2544 #define S_FW_SCSI_CMD_WR_LEN16 0 2545 #define M_FW_SCSI_CMD_WR_LEN16 0xff 2546 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 2547 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 2548 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 2549 2550 #define S_FW_SCSI_CMD_WR_CP_EN 6 2551 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 2552 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 2553 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 2554 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 2555 2556 #define S_FW_SCSI_CMD_WR_CLASS 4 2557 #define M_FW_SCSI_CMD_WR_CLASS 0x3 2558 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 2559 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 2560 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 2561 2562 struct fw_scsi_abrt_cls_wr { 2563 __be32 op_immdlen; 2564 __be32 flowid_len16; 2565 __be64 cookie; 2566 __be16 iqid; 2567 __u8 tmo_val; 2568 __u8 sub_opcode_to_chk_all_io; 2569 __u8 r3[4]; 2570 __be64 t_cookie; 2571 }; 2572 2573 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 2574 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 2575 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 2576 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 2577 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 2578 2579 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 2580 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 2581 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2582 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2583 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2584 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2585 2586 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 2587 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 2588 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 2589 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 2590 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 2591 2592 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 2593 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 2594 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 2595 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 2596 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 2597 2598 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 2599 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 2600 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2601 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2602 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2603 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 2604 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2605 2606 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 2607 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 2608 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 2609 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 2610 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 2611 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 2612 2613 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 2614 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 2615 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2616 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2617 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2618 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 2619 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2620 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 2621 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 2622 2623 struct fw_scsi_tgt_acc_wr { 2624 __be32 op_immdlen; 2625 __be32 flowid_len16; 2626 __be64 cookie; 2627 __be16 iqid; 2628 __u8 r3; 2629 __u8 use_burst_len; 2630 union fw_scsi_tgt_acc_priv { 2631 struct fcoe_tgt_acc_priv { 2632 __u8 ctl_pri; 2633 __u8 cp_en_class; 2634 __u8 r4_lo[2]; 2635 } fcoe; 2636 struct iscsi_tgt_acc_priv { 2637 __u8 r4[4]; 2638 } iscsi; 2639 } u; 2640 __be32 burst_len; 2641 __be32 rel_off; 2642 __be64 r5; 2643 __be32 r6; 2644 __be32 tot_xfer_len; 2645 }; 2646 2647 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 2648 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 2649 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 2650 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 2651 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 2652 2653 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 2654 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 2655 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2656 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 2657 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2658 2659 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 2660 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 2661 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 2662 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 2663 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 2664 2665 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 2666 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 2667 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 2668 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 2669 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 2670 2671 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 2672 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 2673 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 2674 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 2675 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 2676 2677 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 2678 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 2679 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 2680 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 2681 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 2682 2683 struct fw_scsi_tgt_xmit_wr { 2684 __be32 op_immdlen; 2685 __be32 flowid_len16; 2686 __be64 cookie; 2687 __be16 iqid; 2688 __u8 auto_rsp; 2689 __u8 use_xfer_cnt; 2690 union fw_scsi_tgt_xmit_priv { 2691 struct fcoe_tgt_xmit_priv { 2692 __u8 ctl_pri; 2693 __u8 cp_en_class; 2694 __u8 r3_lo[2]; 2695 } fcoe; 2696 struct iscsi_tgt_xmit_priv { 2697 __u8 r3[4]; 2698 } iscsi; 2699 } u; 2700 __be32 xfer_cnt; 2701 __be32 r4; 2702 __be64 r5; 2703 __be32 r6; 2704 __be32 tot_xfer_len; 2705 }; 2706 2707 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 2708 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 2709 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 2710 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 2711 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 2712 2713 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 2714 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 2715 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2716 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2717 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2718 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2719 2720 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 2721 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 2722 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 2723 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 2724 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 2725 2726 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 2727 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 2728 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 2729 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 2730 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 2731 2732 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 2733 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 2734 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 2735 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 2736 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 2737 2738 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 2739 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 2740 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 2741 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 2742 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 2743 2744 struct fw_scsi_tgt_rsp_wr { 2745 __be32 op_immdlen; 2746 __be32 flowid_len16; 2747 __be64 cookie; 2748 __be16 iqid; 2749 __u8 r3[2]; 2750 union fw_scsi_tgt_rsp_priv { 2751 struct fcoe_tgt_rsp_priv { 2752 __u8 ctl_pri; 2753 __u8 cp_en_class; 2754 __u8 r4_lo[2]; 2755 } fcoe; 2756 struct iscsi_tgt_rsp_priv { 2757 __u8 r4[4]; 2758 } iscsi; 2759 } u; 2760 __u8 r5[8]; 2761 }; 2762 2763 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 2764 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 2765 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 2766 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 2767 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 2768 2769 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 2770 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 2771 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2772 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 2773 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2774 2775 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 2776 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 2777 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 2778 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 2779 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 2780 2781 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 2782 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 2783 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 2784 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 2785 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 2786 2787 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 2788 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 2789 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 2790 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 2791 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 2792 2793 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 2794 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 2795 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 2796 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 2797 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 2798 2799 struct fw_pofcoe_tcb_wr { 2800 __be32 op_compl; 2801 __be32 equiq_to_len16; 2802 __be64 cookie; 2803 __be32 tid_to_port; 2804 __be16 x_id; 2805 __be16 vlan_id; 2806 __be32 s_id; 2807 __be32 d_id; 2808 __be32 tag; 2809 __be32 xfer_len; 2810 __be32 r4; 2811 __be16 r5; 2812 __be16 iqid; 2813 }; 2814 2815 #define S_FW_POFCOE_TCB_WR_TID 12 2816 #define M_FW_POFCOE_TCB_WR_TID 0xfffff 2817 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 2818 #define G_FW_POFCOE_TCB_WR_TID(x) \ 2819 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 2820 2821 #define S_FW_POFCOE_TCB_WR_ALLOC 4 2822 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 2823 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 2824 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 2825 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 2826 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 2827 2828 #define S_FW_POFCOE_TCB_WR_FREE 3 2829 #define M_FW_POFCOE_TCB_WR_FREE 0x1 2830 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 2831 #define G_FW_POFCOE_TCB_WR_FREE(x) \ 2832 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 2833 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 2834 2835 #define S_FW_POFCOE_TCB_WR_PORT 0 2836 #define M_FW_POFCOE_TCB_WR_PORT 0x7 2837 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 2838 #define G_FW_POFCOE_TCB_WR_PORT(x) \ 2839 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 2840 2841 struct fw_pofcoe_ulptx_wr { 2842 __be32 op_pkd; 2843 __be32 equiq_to_len16; 2844 __u64 cookie; 2845 }; 2846 2847 2848 /****************************************************************************** 2849 * C O M M A N D s 2850 *********************/ 2851 2852 /* 2853 * The maximum length of time, in miliseconds, that we expect any firmware 2854 * command to take to execute and return a reply to the host. The RESET 2855 * and INITIALIZE commands can take a fair amount of time to execute but 2856 * most execute in far less time than this maximum. This constant is used 2857 * by host software to determine how long to wait for a firmware command 2858 * reply before declaring the firmware as dead/unreachable ... 2859 */ 2860 #define FW_CMD_MAX_TIMEOUT 10000 2861 2862 /* 2863 * If a host driver does a HELLO and discovers that there's already a MASTER 2864 * selected, we may have to wait for that MASTER to finish issuing RESET, 2865 * configuration and INITIALIZE commands. Also, there's a possibility that 2866 * our own HELLO may get lost if it happens right as the MASTER is issuign a 2867 * RESET command, so we need to be willing to make a few retries of our HELLO. 2868 */ 2869 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 2870 #define FW_CMD_HELLO_RETRIES 3 2871 2872 enum fw_cmd_opcodes { 2873 FW_LDST_CMD = 0x01, 2874 FW_RESET_CMD = 0x03, 2875 FW_HELLO_CMD = 0x04, 2876 FW_BYE_CMD = 0x05, 2877 FW_INITIALIZE_CMD = 0x06, 2878 FW_CAPS_CONFIG_CMD = 0x07, 2879 FW_PARAMS_CMD = 0x08, 2880 FW_PFVF_CMD = 0x09, 2881 FW_IQ_CMD = 0x10, 2882 FW_EQ_MNGT_CMD = 0x11, 2883 FW_EQ_ETH_CMD = 0x12, 2884 FW_EQ_CTRL_CMD = 0x13, 2885 FW_EQ_OFLD_CMD = 0x21, 2886 FW_VI_CMD = 0x14, 2887 FW_VI_MAC_CMD = 0x15, 2888 FW_VI_RXMODE_CMD = 0x16, 2889 FW_VI_ENABLE_CMD = 0x17, 2890 FW_VI_STATS_CMD = 0x1a, 2891 FW_ACL_MAC_CMD = 0x18, 2892 FW_ACL_VLAN_CMD = 0x19, 2893 FW_PORT_CMD = 0x1b, 2894 FW_PORT_STATS_CMD = 0x1c, 2895 FW_PORT_LB_STATS_CMD = 0x1d, 2896 FW_PORT_TRACE_CMD = 0x1e, 2897 FW_PORT_TRACE_MMAP_CMD = 0x1f, 2898 FW_RSS_IND_TBL_CMD = 0x20, 2899 FW_RSS_GLB_CONFIG_CMD = 0x22, 2900 FW_RSS_VI_CONFIG_CMD = 0x23, 2901 FW_SCHED_CMD = 0x24, 2902 FW_DEVLOG_CMD = 0x25, 2903 FW_WATCHDOG_CMD = 0x27, 2904 FW_CLIP_CMD = 0x28, 2905 FW_CHNET_IFACE_CMD = 0x26, 2906 FW_FCOE_RES_INFO_CMD = 0x31, 2907 FW_FCOE_LINK_CMD = 0x32, 2908 FW_FCOE_VNP_CMD = 0x33, 2909 FW_FCOE_SPARAMS_CMD = 0x35, 2910 FW_FCOE_STATS_CMD = 0x37, 2911 FW_FCOE_FCF_CMD = 0x38, 2912 FW_LASTC2E_CMD = 0x40, 2913 FW_ERROR_CMD = 0x80, 2914 FW_DEBUG_CMD = 0x81, 2915 }; 2916 2917 enum fw_cmd_cap { 2918 FW_CMD_CAP_PF = 0x01, 2919 FW_CMD_CAP_DMAQ = 0x02, 2920 FW_CMD_CAP_PORT = 0x04, 2921 FW_CMD_CAP_PORTPROMISC = 0x08, 2922 FW_CMD_CAP_PORTSTATS = 0x10, 2923 FW_CMD_CAP_VF = 0x80, 2924 }; 2925 2926 /* 2927 * Generic command header flit0 2928 */ 2929 struct fw_cmd_hdr { 2930 __be32 hi; 2931 __be32 lo; 2932 }; 2933 2934 #define S_FW_CMD_OP 24 2935 #define M_FW_CMD_OP 0xff 2936 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 2937 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 2938 2939 #define S_FW_CMD_REQUEST 23 2940 #define M_FW_CMD_REQUEST 0x1 2941 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 2942 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 2943 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 2944 2945 #define S_FW_CMD_READ 22 2946 #define M_FW_CMD_READ 0x1 2947 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 2948 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 2949 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 2950 2951 #define S_FW_CMD_WRITE 21 2952 #define M_FW_CMD_WRITE 0x1 2953 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 2954 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 2955 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 2956 2957 #define S_FW_CMD_EXEC 20 2958 #define M_FW_CMD_EXEC 0x1 2959 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 2960 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 2961 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 2962 2963 #define S_FW_CMD_RAMASK 20 2964 #define M_FW_CMD_RAMASK 0xf 2965 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 2966 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 2967 2968 #define S_FW_CMD_RETVAL 8 2969 #define M_FW_CMD_RETVAL 0xff 2970 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 2971 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 2972 2973 #define S_FW_CMD_LEN16 0 2974 #define M_FW_CMD_LEN16 0xff 2975 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 2976 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 2977 2978 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 2979 2980 /* 2981 * address spaces 2982 */ 2983 enum fw_ldst_addrspc { 2984 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 2985 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 2986 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 2987 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 2988 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 2989 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 2990 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 2991 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 2992 FW_LDST_ADDRSPC_MDIO = 0x0018, 2993 FW_LDST_ADDRSPC_MPS = 0x0020, 2994 FW_LDST_ADDRSPC_FUNC = 0x0028, 2995 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 2996 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 2997 FW_LDST_ADDRSPC_LE = 0x0030, 2998 FW_LDST_ADDRSPC_I2C = 0x0038, 2999 }; 3000 3001 /* 3002 * MDIO VSC8634 register access control field 3003 */ 3004 enum fw_ldst_mdio_vsc8634_aid { 3005 FW_LDST_MDIO_VS_STANDARD, 3006 FW_LDST_MDIO_VS_EXTENDED, 3007 FW_LDST_MDIO_VS_GPIO 3008 }; 3009 3010 enum fw_ldst_mps_fid { 3011 FW_LDST_MPS_ATRB, 3012 FW_LDST_MPS_RPLC 3013 }; 3014 3015 enum fw_ldst_func_access_ctl { 3016 FW_LDST_FUNC_ACC_CTL_VIID, 3017 FW_LDST_FUNC_ACC_CTL_FID 3018 }; 3019 3020 enum fw_ldst_func_mod_index { 3021 FW_LDST_FUNC_MPS 3022 }; 3023 3024 struct fw_ldst_cmd { 3025 __be32 op_to_addrspace; 3026 __be32 cycles_to_len16; 3027 union fw_ldst { 3028 struct fw_ldst_addrval { 3029 __be32 addr; 3030 __be32 val; 3031 } addrval; 3032 struct fw_ldst_idctxt { 3033 __be32 physid; 3034 __be32 msg_ctxtflush; 3035 __be32 ctxt_data7; 3036 __be32 ctxt_data6; 3037 __be32 ctxt_data5; 3038 __be32 ctxt_data4; 3039 __be32 ctxt_data3; 3040 __be32 ctxt_data2; 3041 __be32 ctxt_data1; 3042 __be32 ctxt_data0; 3043 } idctxt; 3044 struct fw_ldst_mdio { 3045 __be16 paddr_mmd; 3046 __be16 raddr; 3047 __be16 vctl; 3048 __be16 rval; 3049 } mdio; 3050 struct fw_ldst_mps { 3051 __be16 fid_ctl; 3052 __be16 rplcpf_pkd; 3053 __be32 rplc127_96; 3054 __be32 rplc95_64; 3055 __be32 rplc63_32; 3056 __be32 rplc31_0; 3057 __be32 atrb; 3058 __be16 vlan[16]; 3059 } mps; 3060 struct fw_ldst_func { 3061 __u8 access_ctl; 3062 __u8 mod_index; 3063 __be16 ctl_id; 3064 __be32 offset; 3065 __be64 data0; 3066 __be64 data1; 3067 } func; 3068 struct fw_ldst_pcie { 3069 __u8 ctrl_to_fn; 3070 __u8 bnum; 3071 __u8 r; 3072 __u8 ext_r; 3073 __u8 select_naccess; 3074 __u8 pcie_fn; 3075 __be16 nset_pkd; 3076 __be32 data[12]; 3077 } pcie; 3078 struct fw_ldst_i2c_deprecated { 3079 __u8 pid_pkd; 3080 __u8 base; 3081 __u8 boffset; 3082 __u8 data; 3083 __be32 r9; 3084 } i2c_deprecated; 3085 struct fw_ldst_i2c { 3086 __u8 pid; 3087 __u8 did; 3088 __u8 boffset; 3089 __u8 blen; 3090 __be32 r9; 3091 __u8 data[48]; 3092 } i2c; 3093 struct fw_ldst_le { 3094 __be32 index; 3095 __be32 r9; 3096 __u8 val[33]; 3097 __u8 r11[7]; 3098 } le; 3099 } u; 3100 }; 3101 3102 #define S_FW_LDST_CMD_ADDRSPACE 0 3103 #define M_FW_LDST_CMD_ADDRSPACE 0xff 3104 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3105 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 3106 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 3107 3108 #define S_FW_LDST_CMD_CYCLES 16 3109 #define M_FW_LDST_CMD_CYCLES 0xffff 3110 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 3111 #define G_FW_LDST_CMD_CYCLES(x) \ 3112 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 3113 3114 #define S_FW_LDST_CMD_MSG 31 3115 #define M_FW_LDST_CMD_MSG 0x1 3116 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 3117 #define G_FW_LDST_CMD_MSG(x) \ 3118 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 3119 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 3120 3121 #define S_FW_LDST_CMD_CTXTFLUSH 30 3122 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 3123 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 3124 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 3125 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 3126 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 3127 3128 #define S_FW_LDST_CMD_PADDR 8 3129 #define M_FW_LDST_CMD_PADDR 0x1f 3130 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 3131 #define G_FW_LDST_CMD_PADDR(x) \ 3132 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 3133 3134 #define S_FW_LDST_CMD_MMD 0 3135 #define M_FW_LDST_CMD_MMD 0x1f 3136 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 3137 #define G_FW_LDST_CMD_MMD(x) \ 3138 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 3139 3140 #define S_FW_LDST_CMD_FID 15 3141 #define M_FW_LDST_CMD_FID 0x1 3142 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 3143 #define G_FW_LDST_CMD_FID(x) \ 3144 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 3145 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 3146 3147 #define S_FW_LDST_CMD_CTL 0 3148 #define M_FW_LDST_CMD_CTL 0x7fff 3149 #define V_FW_LDST_CMD_CTL(x) ((x) << S_FW_LDST_CMD_CTL) 3150 #define G_FW_LDST_CMD_CTL(x) \ 3151 (((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL) 3152 3153 #define S_FW_LDST_CMD_RPLCPF 0 3154 #define M_FW_LDST_CMD_RPLCPF 0xff 3155 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 3156 #define G_FW_LDST_CMD_RPLCPF(x) \ 3157 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 3158 3159 #define S_FW_LDST_CMD_CTRL 7 3160 #define M_FW_LDST_CMD_CTRL 0x1 3161 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 3162 #define G_FW_LDST_CMD_CTRL(x) \ 3163 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 3164 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 3165 3166 #define S_FW_LDST_CMD_LC 4 3167 #define M_FW_LDST_CMD_LC 0x1 3168 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 3169 #define G_FW_LDST_CMD_LC(x) (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 3170 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 3171 3172 #define S_FW_LDST_CMD_AI 3 3173 #define M_FW_LDST_CMD_AI 0x1 3174 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 3175 #define G_FW_LDST_CMD_AI(x) (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 3176 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 3177 3178 #define S_FW_LDST_CMD_FN 0 3179 #define M_FW_LDST_CMD_FN 0x7 3180 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 3181 #define G_FW_LDST_CMD_FN(x) (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 3182 3183 #define S_FW_LDST_CMD_SELECT 4 3184 #define M_FW_LDST_CMD_SELECT 0xf 3185 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 3186 #define G_FW_LDST_CMD_SELECT(x) \ 3187 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 3188 3189 #define S_FW_LDST_CMD_NACCESS 0 3190 #define M_FW_LDST_CMD_NACCESS 0xf 3191 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 3192 #define G_FW_LDST_CMD_NACCESS(x) \ 3193 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 3194 3195 #define S_FW_LDST_CMD_NSET 14 3196 #define M_FW_LDST_CMD_NSET 0x3 3197 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 3198 #define G_FW_LDST_CMD_NSET(x) \ 3199 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 3200 3201 #define S_FW_LDST_CMD_PID 6 3202 #define M_FW_LDST_CMD_PID 0x3 3203 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 3204 #define G_FW_LDST_CMD_PID(x) \ 3205 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 3206 3207 struct fw_reset_cmd { 3208 __be32 op_to_write; 3209 __be32 retval_len16; 3210 __be32 val; 3211 __be32 halt_pkd; 3212 }; 3213 3214 #define S_FW_RESET_CMD_HALT 31 3215 #define M_FW_RESET_CMD_HALT 0x1 3216 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 3217 #define G_FW_RESET_CMD_HALT(x) \ 3218 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 3219 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 3220 3221 enum { 3222 FW_HELLO_CMD_STAGE_OS = 0, 3223 FW_HELLO_CMD_STAGE_PREOS0 = 1, 3224 FW_HELLO_CMD_STAGE_PREOS1 = 2, 3225 FW_HELLO_CMD_STAGE_POSTOS = 3, 3226 }; 3227 3228 struct fw_hello_cmd { 3229 __be32 op_to_write; 3230 __be32 retval_len16; 3231 __be32 err_to_clearinit; 3232 __be32 fwrev; 3233 }; 3234 3235 #define S_FW_HELLO_CMD_ERR 31 3236 #define M_FW_HELLO_CMD_ERR 0x1 3237 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 3238 #define G_FW_HELLO_CMD_ERR(x) \ 3239 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 3240 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 3241 3242 #define S_FW_HELLO_CMD_INIT 30 3243 #define M_FW_HELLO_CMD_INIT 0x1 3244 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 3245 #define G_FW_HELLO_CMD_INIT(x) \ 3246 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 3247 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 3248 3249 #define S_FW_HELLO_CMD_MASTERDIS 29 3250 #define M_FW_HELLO_CMD_MASTERDIS 0x1 3251 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 3252 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 3253 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 3254 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 3255 3256 #define S_FW_HELLO_CMD_MASTERFORCE 28 3257 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 3258 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 3259 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 3260 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 3261 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 3262 3263 #define S_FW_HELLO_CMD_MBMASTER 24 3264 #define M_FW_HELLO_CMD_MBMASTER 0xf 3265 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 3266 #define G_FW_HELLO_CMD_MBMASTER(x) \ 3267 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 3268 3269 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 3270 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 3271 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 3272 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 3273 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 3274 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 3275 3276 #define S_FW_HELLO_CMD_MBASYNCNOT 20 3277 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 3278 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 3279 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 3280 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 3281 3282 #define S_FW_HELLO_CMD_STAGE 17 3283 #define M_FW_HELLO_CMD_STAGE 0x7 3284 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 3285 #define G_FW_HELLO_CMD_STAGE(x) \ 3286 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 3287 3288 #define S_FW_HELLO_CMD_CLEARINIT 16 3289 #define M_FW_HELLO_CMD_CLEARINIT 0x1 3290 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 3291 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 3292 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 3293 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 3294 3295 struct fw_bye_cmd { 3296 __be32 op_to_write; 3297 __be32 retval_len16; 3298 __be64 r3; 3299 }; 3300 3301 struct fw_initialize_cmd { 3302 __be32 op_to_write; 3303 __be32 retval_len16; 3304 __be64 r3; 3305 }; 3306 3307 enum fw_caps_config_hm { 3308 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 3309 FW_CAPS_CONFIG_HM_PL = 0x00000002, 3310 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 3311 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 3312 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 3313 FW_CAPS_CONFIG_HM_TP = 0x00000020, 3314 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 3315 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 3316 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 3317 FW_CAPS_CONFIG_HM_MC = 0x00000200, 3318 FW_CAPS_CONFIG_HM_LE = 0x00000400, 3319 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 3320 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 3321 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 3322 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 3323 FW_CAPS_CONFIG_HM_MI = 0x00008000, 3324 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 3325 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 3326 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 3327 FW_CAPS_CONFIG_HM_MA = 0x00080000, 3328 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 3329 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 3330 FW_CAPS_CONFIG_HM_UART = 0x00400000, 3331 FW_CAPS_CONFIG_HM_SF = 0x00800000, 3332 }; 3333 3334 /* 3335 * The VF Register Map. 3336 * 3337 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 3338 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 3339 * the Slice to Module Map Table (see below) in the Physical Function Register 3340 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 3341 * and Offset registers in the PF Register Map. The MBDATA base address is 3342 * quite constrained as it determines the Mailbox Data addresses for both PFs 3343 * and VFs, and therefore must fit in both the VF and PF Register Maps without 3344 * overlapping other registers. 3345 */ 3346 #define FW_T4VF_SGE_BASE_ADDR 0x0000 3347 #define FW_T4VF_MPS_BASE_ADDR 0x0100 3348 #define FW_T4VF_PL_BASE_ADDR 0x0200 3349 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 3350 #define FW_T4VF_CIM_BASE_ADDR 0x0300 3351 3352 #define FW_T4VF_REGMAP_START 0x0000 3353 #define FW_T4VF_REGMAP_SIZE 0x0400 3354 3355 enum fw_caps_config_nbm { 3356 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 3357 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 3358 }; 3359 3360 enum fw_caps_config_link { 3361 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 3362 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 3363 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 3364 }; 3365 3366 enum fw_caps_config_switch { 3367 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 3368 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 3369 }; 3370 3371 enum fw_caps_config_nic { 3372 FW_CAPS_CONFIG_NIC = 0x00000001, 3373 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 3374 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 3375 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 3376 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 3377 }; 3378 3379 enum fw_caps_config_toe { 3380 FW_CAPS_CONFIG_TOE = 0x00000001, 3381 }; 3382 3383 enum fw_caps_config_rdma { 3384 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 3385 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 3386 }; 3387 3388 enum fw_caps_config_iscsi { 3389 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 3390 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 3391 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 3392 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 3393 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 3394 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 3395 }; 3396 3397 enum fw_caps_config_fcoe { 3398 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 3399 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 3400 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 3401 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 3402 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 3403 }; 3404 3405 enum fw_memtype_cf { 3406 FW_MEMTYPE_CF_EDC0 = 0x0, 3407 FW_MEMTYPE_CF_EDC1 = 0x1, 3408 FW_MEMTYPE_CF_EXTMEM = 0x2, 3409 FW_MEMTYPE_CF_FLASH = 0x4, 3410 FW_MEMTYPE_CF_INTERNAL = 0x5, 3411 }; 3412 3413 struct fw_caps_config_cmd { 3414 __be32 op_to_write; 3415 __be32 cfvalid_to_len16; 3416 __be32 r2; 3417 __be32 hwmbitmap; 3418 __be16 nbmcaps; 3419 __be16 linkcaps; 3420 __be16 switchcaps; 3421 __be16 r3; 3422 __be16 niccaps; 3423 __be16 toecaps; 3424 __be16 rdmacaps; 3425 __be16 r4; 3426 __be16 iscsicaps; 3427 __be16 fcoecaps; 3428 __be32 cfcsum; 3429 __be32 finiver; 3430 __be32 finicsum; 3431 }; 3432 3433 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 3434 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 3435 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 3436 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 3437 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 3438 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 3439 3440 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 3441 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 3442 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3443 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3444 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3445 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 3446 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3447 3448 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 3449 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 3450 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3451 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3452 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3453 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 3454 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3455 3456 /* 3457 * params command mnemonics 3458 */ 3459 enum fw_params_mnem { 3460 FW_PARAMS_MNEM_DEV = 1, /* device params */ 3461 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 3462 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 3463 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 3464 FW_PARAMS_MNEM_LAST 3465 }; 3466 3467 /* 3468 * device parameters 3469 */ 3470 enum fw_params_param_dev { 3471 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 3472 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 3473 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 3474 * allocated by the device's 3475 * Lookup Engine 3476 */ 3477 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 3478 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 3479 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 3480 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 3481 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 3482 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 3483 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 3484 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 3485 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 3486 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 3487 FW_PARAMS_PARAM_DEV_CF = 0x0D, 3488 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 3489 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 3490 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 3491 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 3492 }; 3493 3494 /* 3495 * physical and virtual function parameters 3496 */ 3497 enum fw_params_param_pfvf { 3498 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 3499 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 3500 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 3501 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 3502 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 3503 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 3504 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 3505 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 3506 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 3507 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 3508 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 3509 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 3510 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 3511 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 3512 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 3513 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 3514 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 3515 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 3516 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 3517 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 3518 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 3519 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 3520 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 3521 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 3522 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 3523 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 3524 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 3525 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 3526 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 3527 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 3528 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 3529 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 3530 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 3531 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 3532 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 3533 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 3534 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 3535 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 3536 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 3537 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31 3538 }; 3539 3540 /* 3541 * dma queue parameters 3542 */ 3543 enum fw_params_param_dmaq { 3544 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 3545 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 3546 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 3547 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 3548 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 3549 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 3550 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13 3551 }; 3552 3553 /* 3554 * dev bypass parameters; actions and modes 3555 */ 3556 enum fw_params_param_dev_bypass { 3557 3558 /* actions 3559 */ 3560 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 3561 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 3562 3563 /* modes 3564 */ 3565 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 3566 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 3567 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 3568 }; 3569 3570 enum fw_params_phyfw_actions { 3571 FW_PARAMS_PARAM_PHYFW_DOWNLOAD = 0x00, 3572 FW_PARAMS_PARAM_PHYFW_VERSION = 0x01, 3573 }; 3574 3575 enum fw_params_param_dev_diag { 3576 FW_PARAM_DEV_DIAG_TMP = 0x00, 3577 }; 3578 3579 #define S_FW_PARAMS_MNEM 24 3580 #define M_FW_PARAMS_MNEM 0xff 3581 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 3582 #define G_FW_PARAMS_MNEM(x) \ 3583 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 3584 3585 #define S_FW_PARAMS_PARAM_X 16 3586 #define M_FW_PARAMS_PARAM_X 0xff 3587 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 3588 #define G_FW_PARAMS_PARAM_X(x) \ 3589 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 3590 3591 #define S_FW_PARAMS_PARAM_Y 8 3592 #define M_FW_PARAMS_PARAM_Y 0xff 3593 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 3594 #define G_FW_PARAMS_PARAM_Y(x) \ 3595 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 3596 3597 #define S_FW_PARAMS_PARAM_Z 0 3598 #define M_FW_PARAMS_PARAM_Z 0xff 3599 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 3600 #define G_FW_PARAMS_PARAM_Z(x) \ 3601 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 3602 3603 #define S_FW_PARAMS_PARAM_XYZ 0 3604 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 3605 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 3606 #define G_FW_PARAMS_PARAM_XYZ(x) \ 3607 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 3608 3609 #define S_FW_PARAMS_PARAM_YZ 0 3610 #define M_FW_PARAMS_PARAM_YZ 0xffff 3611 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 3612 #define G_FW_PARAMS_PARAM_YZ(x) \ 3613 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 3614 3615 struct fw_params_cmd { 3616 __be32 op_to_vfn; 3617 __be32 retval_len16; 3618 struct fw_params_param { 3619 __be32 mnem; 3620 __be32 val; 3621 } param[7]; 3622 }; 3623 3624 #define S_FW_PARAMS_CMD_PFN 8 3625 #define M_FW_PARAMS_CMD_PFN 0x7 3626 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 3627 #define G_FW_PARAMS_CMD_PFN(x) \ 3628 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 3629 3630 #define S_FW_PARAMS_CMD_VFN 0 3631 #define M_FW_PARAMS_CMD_VFN 0xff 3632 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 3633 #define G_FW_PARAMS_CMD_VFN(x) \ 3634 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 3635 3636 struct fw_pfvf_cmd { 3637 __be32 op_to_vfn; 3638 __be32 retval_len16; 3639 __be32 niqflint_niq; 3640 __be32 type_to_neq; 3641 __be32 tc_to_nexactf; 3642 __be32 r_caps_to_nethctrl; 3643 __be16 nricq; 3644 __be16 nriqp; 3645 __be32 r4; 3646 }; 3647 3648 #define S_FW_PFVF_CMD_PFN 8 3649 #define M_FW_PFVF_CMD_PFN 0x7 3650 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 3651 #define G_FW_PFVF_CMD_PFN(x) \ 3652 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 3653 3654 #define S_FW_PFVF_CMD_VFN 0 3655 #define M_FW_PFVF_CMD_VFN 0xff 3656 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 3657 #define G_FW_PFVF_CMD_VFN(x) \ 3658 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 3659 3660 #define S_FW_PFVF_CMD_NIQFLINT 20 3661 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 3662 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 3663 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 3664 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 3665 3666 #define S_FW_PFVF_CMD_NIQ 0 3667 #define M_FW_PFVF_CMD_NIQ 0xfffff 3668 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 3669 #define G_FW_PFVF_CMD_NIQ(x) \ 3670 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 3671 3672 #define S_FW_PFVF_CMD_TYPE 31 3673 #define M_FW_PFVF_CMD_TYPE 0x1 3674 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 3675 #define G_FW_PFVF_CMD_TYPE(x) \ 3676 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 3677 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 3678 3679 #define S_FW_PFVF_CMD_CMASK 24 3680 #define M_FW_PFVF_CMD_CMASK 0xf 3681 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 3682 #define G_FW_PFVF_CMD_CMASK(x) \ 3683 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 3684 3685 #define S_FW_PFVF_CMD_PMASK 20 3686 #define M_FW_PFVF_CMD_PMASK 0xf 3687 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 3688 #define G_FW_PFVF_CMD_PMASK(x) \ 3689 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 3690 3691 #define S_FW_PFVF_CMD_NEQ 0 3692 #define M_FW_PFVF_CMD_NEQ 0xfffff 3693 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 3694 #define G_FW_PFVF_CMD_NEQ(x) \ 3695 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 3696 3697 #define S_FW_PFVF_CMD_TC 24 3698 #define M_FW_PFVF_CMD_TC 0xff 3699 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 3700 #define G_FW_PFVF_CMD_TC(x) (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 3701 3702 #define S_FW_PFVF_CMD_NVI 16 3703 #define M_FW_PFVF_CMD_NVI 0xff 3704 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 3705 #define G_FW_PFVF_CMD_NVI(x) \ 3706 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 3707 3708 #define S_FW_PFVF_CMD_NEXACTF 0 3709 #define M_FW_PFVF_CMD_NEXACTF 0xffff 3710 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 3711 #define G_FW_PFVF_CMD_NEXACTF(x) \ 3712 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 3713 3714 #define S_FW_PFVF_CMD_R_CAPS 24 3715 #define M_FW_PFVF_CMD_R_CAPS 0xff 3716 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 3717 #define G_FW_PFVF_CMD_R_CAPS(x) \ 3718 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 3719 3720 #define S_FW_PFVF_CMD_WX_CAPS 16 3721 #define M_FW_PFVF_CMD_WX_CAPS 0xff 3722 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 3723 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 3724 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 3725 3726 #define S_FW_PFVF_CMD_NETHCTRL 0 3727 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 3728 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 3729 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 3730 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 3731 3732 /* 3733 * ingress queue type; the first 1K ingress queues can have associated 0, 3734 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 3735 * capabilities 3736 */ 3737 enum fw_iq_type { 3738 FW_IQ_TYPE_FL_INT_CAP, 3739 FW_IQ_TYPE_NO_FL_INT_CAP 3740 }; 3741 3742 struct fw_iq_cmd { 3743 __be32 op_to_vfn; 3744 __be32 alloc_to_len16; 3745 __be16 physiqid; 3746 __be16 iqid; 3747 __be16 fl0id; 3748 __be16 fl1id; 3749 __be32 type_to_iqandstindex; 3750 __be16 iqdroprss_to_iqesize; 3751 __be16 iqsize; 3752 __be64 iqaddr; 3753 __be32 iqns_to_fl0congen; 3754 __be16 fl0dcaen_to_fl0cidxfthresh; 3755 __be16 fl0size; 3756 __be64 fl0addr; 3757 __be32 fl1cngchmap_to_fl1congen; 3758 __be16 fl1dcaen_to_fl1cidxfthresh; 3759 __be16 fl1size; 3760 __be64 fl1addr; 3761 }; 3762 3763 #define S_FW_IQ_CMD_PFN 8 3764 #define M_FW_IQ_CMD_PFN 0x7 3765 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 3766 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 3767 3768 #define S_FW_IQ_CMD_VFN 0 3769 #define M_FW_IQ_CMD_VFN 0xff 3770 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 3771 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 3772 3773 #define S_FW_IQ_CMD_ALLOC 31 3774 #define M_FW_IQ_CMD_ALLOC 0x1 3775 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 3776 #define G_FW_IQ_CMD_ALLOC(x) \ 3777 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 3778 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 3779 3780 #define S_FW_IQ_CMD_FREE 30 3781 #define M_FW_IQ_CMD_FREE 0x1 3782 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 3783 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 3784 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 3785 3786 #define S_FW_IQ_CMD_MODIFY 29 3787 #define M_FW_IQ_CMD_MODIFY 0x1 3788 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 3789 #define G_FW_IQ_CMD_MODIFY(x) \ 3790 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 3791 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 3792 3793 #define S_FW_IQ_CMD_IQSTART 28 3794 #define M_FW_IQ_CMD_IQSTART 0x1 3795 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 3796 #define G_FW_IQ_CMD_IQSTART(x) \ 3797 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 3798 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 3799 3800 #define S_FW_IQ_CMD_IQSTOP 27 3801 #define M_FW_IQ_CMD_IQSTOP 0x1 3802 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 3803 #define G_FW_IQ_CMD_IQSTOP(x) \ 3804 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 3805 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 3806 3807 #define S_FW_IQ_CMD_TYPE 29 3808 #define M_FW_IQ_CMD_TYPE 0x7 3809 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 3810 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 3811 3812 #define S_FW_IQ_CMD_IQASYNCH 28 3813 #define M_FW_IQ_CMD_IQASYNCH 0x1 3814 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 3815 #define G_FW_IQ_CMD_IQASYNCH(x) \ 3816 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 3817 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 3818 3819 #define S_FW_IQ_CMD_VIID 16 3820 #define M_FW_IQ_CMD_VIID 0xfff 3821 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 3822 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 3823 3824 #define S_FW_IQ_CMD_IQANDST 15 3825 #define M_FW_IQ_CMD_IQANDST 0x1 3826 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 3827 #define G_FW_IQ_CMD_IQANDST(x) \ 3828 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 3829 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 3830 3831 #define S_FW_IQ_CMD_IQANUS 14 3832 #define M_FW_IQ_CMD_IQANUS 0x1 3833 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 3834 #define G_FW_IQ_CMD_IQANUS(x) \ 3835 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 3836 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 3837 3838 #define S_FW_IQ_CMD_IQANUD 12 3839 #define M_FW_IQ_CMD_IQANUD 0x3 3840 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 3841 #define G_FW_IQ_CMD_IQANUD(x) \ 3842 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 3843 3844 #define S_FW_IQ_CMD_IQANDSTINDEX 0 3845 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 3846 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 3847 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 3848 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 3849 3850 #define S_FW_IQ_CMD_IQDROPRSS 15 3851 #define M_FW_IQ_CMD_IQDROPRSS 0x1 3852 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 3853 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 3854 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 3855 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 3856 3857 #define S_FW_IQ_CMD_IQGTSMODE 14 3858 #define M_FW_IQ_CMD_IQGTSMODE 0x1 3859 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 3860 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 3861 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 3862 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 3863 3864 #define S_FW_IQ_CMD_IQPCIECH 12 3865 #define M_FW_IQ_CMD_IQPCIECH 0x3 3866 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 3867 #define G_FW_IQ_CMD_IQPCIECH(x) \ 3868 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 3869 3870 #define S_FW_IQ_CMD_IQDCAEN 11 3871 #define M_FW_IQ_CMD_IQDCAEN 0x1 3872 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 3873 #define G_FW_IQ_CMD_IQDCAEN(x) \ 3874 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 3875 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 3876 3877 #define S_FW_IQ_CMD_IQDCACPU 6 3878 #define M_FW_IQ_CMD_IQDCACPU 0x1f 3879 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 3880 #define G_FW_IQ_CMD_IQDCACPU(x) \ 3881 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 3882 3883 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 3884 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 3885 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 3886 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 3887 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 3888 3889 #define S_FW_IQ_CMD_IQO 3 3890 #define M_FW_IQ_CMD_IQO 0x1 3891 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 3892 #define G_FW_IQ_CMD_IQO(x) (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 3893 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 3894 3895 #define S_FW_IQ_CMD_IQCPRIO 2 3896 #define M_FW_IQ_CMD_IQCPRIO 0x1 3897 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 3898 #define G_FW_IQ_CMD_IQCPRIO(x) \ 3899 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 3900 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 3901 3902 #define S_FW_IQ_CMD_IQESIZE 0 3903 #define M_FW_IQ_CMD_IQESIZE 0x3 3904 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 3905 #define G_FW_IQ_CMD_IQESIZE(x) \ 3906 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 3907 3908 #define S_FW_IQ_CMD_IQNS 31 3909 #define M_FW_IQ_CMD_IQNS 0x1 3910 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 3911 #define G_FW_IQ_CMD_IQNS(x) (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 3912 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 3913 3914 #define S_FW_IQ_CMD_IQRO 30 3915 #define M_FW_IQ_CMD_IQRO 0x1 3916 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 3917 #define G_FW_IQ_CMD_IQRO(x) (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 3918 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 3919 3920 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 3921 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 3922 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 3923 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 3924 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 3925 3926 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 3927 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 3928 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 3929 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 3930 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 3931 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 3932 3933 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 3934 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 3935 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 3936 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 3937 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 3938 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 3939 3940 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 3941 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 3942 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 3943 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 3944 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 3945 3946 #define S_FW_IQ_CMD_FL0CACHELOCK 15 3947 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 3948 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 3949 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 3950 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 3951 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 3952 3953 #define S_FW_IQ_CMD_FL0DBP 14 3954 #define M_FW_IQ_CMD_FL0DBP 0x1 3955 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 3956 #define G_FW_IQ_CMD_FL0DBP(x) \ 3957 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 3958 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 3959 3960 #define S_FW_IQ_CMD_FL0DATANS 13 3961 #define M_FW_IQ_CMD_FL0DATANS 0x1 3962 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 3963 #define G_FW_IQ_CMD_FL0DATANS(x) \ 3964 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 3965 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 3966 3967 #define S_FW_IQ_CMD_FL0DATARO 12 3968 #define M_FW_IQ_CMD_FL0DATARO 0x1 3969 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 3970 #define G_FW_IQ_CMD_FL0DATARO(x) \ 3971 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 3972 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 3973 3974 #define S_FW_IQ_CMD_FL0CONGCIF 11 3975 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 3976 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 3977 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 3978 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 3979 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 3980 3981 #define S_FW_IQ_CMD_FL0ONCHIP 10 3982 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 3983 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 3984 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 3985 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 3986 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 3987 3988 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 3989 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 3990 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 3991 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 3992 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 3993 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 3994 3995 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 3996 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 3997 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 3998 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 3999 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 4000 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 4001 4002 #define S_FW_IQ_CMD_FL0FETCHNS 7 4003 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 4004 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 4005 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 4006 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 4007 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 4008 4009 #define S_FW_IQ_CMD_FL0FETCHRO 6 4010 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 4011 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 4012 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 4013 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 4014 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 4015 4016 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 4017 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 4018 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 4019 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 4020 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 4021 4022 #define S_FW_IQ_CMD_FL0CPRIO 3 4023 #define M_FW_IQ_CMD_FL0CPRIO 0x1 4024 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 4025 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 4026 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 4027 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 4028 4029 #define S_FW_IQ_CMD_FL0PADEN 2 4030 #define M_FW_IQ_CMD_FL0PADEN 0x1 4031 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 4032 #define G_FW_IQ_CMD_FL0PADEN(x) \ 4033 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 4034 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 4035 4036 #define S_FW_IQ_CMD_FL0PACKEN 1 4037 #define M_FW_IQ_CMD_FL0PACKEN 0x1 4038 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 4039 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 4040 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 4041 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 4042 4043 #define S_FW_IQ_CMD_FL0CONGEN 0 4044 #define M_FW_IQ_CMD_FL0CONGEN 0x1 4045 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 4046 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 4047 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 4048 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 4049 4050 #define S_FW_IQ_CMD_FL0DCAEN 15 4051 #define M_FW_IQ_CMD_FL0DCAEN 0x1 4052 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 4053 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 4054 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 4055 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 4056 4057 #define S_FW_IQ_CMD_FL0DCACPU 10 4058 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 4059 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 4060 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 4061 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 4062 4063 #define S_FW_IQ_CMD_FL0FBMIN 7 4064 #define M_FW_IQ_CMD_FL0FBMIN 0x7 4065 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 4066 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 4067 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 4068 4069 #define S_FW_IQ_CMD_FL0FBMAX 4 4070 #define M_FW_IQ_CMD_FL0FBMAX 0x7 4071 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 4072 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 4073 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 4074 4075 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 4076 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 4077 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 4078 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 4079 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 4080 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 4081 4082 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 4083 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 4084 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 4085 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 4086 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 4087 4088 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 4089 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 4090 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 4091 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 4092 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 4093 4094 #define S_FW_IQ_CMD_FL1CACHELOCK 15 4095 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 4096 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 4097 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 4098 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 4099 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 4100 4101 #define S_FW_IQ_CMD_FL1DBP 14 4102 #define M_FW_IQ_CMD_FL1DBP 0x1 4103 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 4104 #define G_FW_IQ_CMD_FL1DBP(x) \ 4105 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 4106 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 4107 4108 #define S_FW_IQ_CMD_FL1DATANS 13 4109 #define M_FW_IQ_CMD_FL1DATANS 0x1 4110 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 4111 #define G_FW_IQ_CMD_FL1DATANS(x) \ 4112 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 4113 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 4114 4115 #define S_FW_IQ_CMD_FL1DATARO 12 4116 #define M_FW_IQ_CMD_FL1DATARO 0x1 4117 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 4118 #define G_FW_IQ_CMD_FL1DATARO(x) \ 4119 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 4120 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 4121 4122 #define S_FW_IQ_CMD_FL1CONGCIF 11 4123 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 4124 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 4125 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 4126 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 4127 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 4128 4129 #define S_FW_IQ_CMD_FL1ONCHIP 10 4130 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 4131 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 4132 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 4133 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 4134 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 4135 4136 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 4137 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 4138 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 4139 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 4140 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 4141 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 4142 4143 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 4144 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 4145 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 4146 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 4147 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 4148 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 4149 4150 #define S_FW_IQ_CMD_FL1FETCHNS 7 4151 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 4152 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 4153 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 4154 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 4155 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 4156 4157 #define S_FW_IQ_CMD_FL1FETCHRO 6 4158 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 4159 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 4160 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 4161 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 4162 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 4163 4164 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 4165 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 4166 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 4167 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 4168 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 4169 4170 #define S_FW_IQ_CMD_FL1CPRIO 3 4171 #define M_FW_IQ_CMD_FL1CPRIO 0x1 4172 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 4173 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 4174 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 4175 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 4176 4177 #define S_FW_IQ_CMD_FL1PADEN 2 4178 #define M_FW_IQ_CMD_FL1PADEN 0x1 4179 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 4180 #define G_FW_IQ_CMD_FL1PADEN(x) \ 4181 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 4182 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 4183 4184 #define S_FW_IQ_CMD_FL1PACKEN 1 4185 #define M_FW_IQ_CMD_FL1PACKEN 0x1 4186 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 4187 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 4188 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 4189 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 4190 4191 #define S_FW_IQ_CMD_FL1CONGEN 0 4192 #define M_FW_IQ_CMD_FL1CONGEN 0x1 4193 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 4194 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 4195 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 4196 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 4197 4198 #define S_FW_IQ_CMD_FL1DCAEN 15 4199 #define M_FW_IQ_CMD_FL1DCAEN 0x1 4200 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 4201 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 4202 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 4203 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 4204 4205 #define S_FW_IQ_CMD_FL1DCACPU 10 4206 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 4207 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 4208 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 4209 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 4210 4211 #define S_FW_IQ_CMD_FL1FBMIN 7 4212 #define M_FW_IQ_CMD_FL1FBMIN 0x7 4213 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 4214 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 4215 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 4216 4217 #define S_FW_IQ_CMD_FL1FBMAX 4 4218 #define M_FW_IQ_CMD_FL1FBMAX 0x7 4219 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 4220 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 4221 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 4222 4223 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 4224 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 4225 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 4226 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 4227 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 4228 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 4229 4230 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 4231 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 4232 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 4233 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 4234 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 4235 4236 struct fw_eq_mngt_cmd { 4237 __be32 op_to_vfn; 4238 __be32 alloc_to_len16; 4239 __be32 cmpliqid_eqid; 4240 __be32 physeqid_pkd; 4241 __be32 fetchszm_to_iqid; 4242 __be32 dcaen_to_eqsize; 4243 __be64 eqaddr; 4244 }; 4245 4246 #define S_FW_EQ_MNGT_CMD_PFN 8 4247 #define M_FW_EQ_MNGT_CMD_PFN 0x7 4248 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 4249 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 4250 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 4251 4252 #define S_FW_EQ_MNGT_CMD_VFN 0 4253 #define M_FW_EQ_MNGT_CMD_VFN 0xff 4254 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 4255 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 4256 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 4257 4258 #define S_FW_EQ_MNGT_CMD_ALLOC 31 4259 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 4260 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 4261 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 4262 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 4263 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 4264 4265 #define S_FW_EQ_MNGT_CMD_FREE 30 4266 #define M_FW_EQ_MNGT_CMD_FREE 0x1 4267 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 4268 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 4269 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 4270 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 4271 4272 #define S_FW_EQ_MNGT_CMD_MODIFY 29 4273 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 4274 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 4275 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 4276 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 4277 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 4278 4279 #define S_FW_EQ_MNGT_CMD_EQSTART 28 4280 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 4281 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 4282 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 4283 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 4284 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 4285 4286 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 4287 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 4288 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 4289 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 4290 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 4291 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 4292 4293 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 4294 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 4295 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 4296 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 4297 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 4298 4299 #define S_FW_EQ_MNGT_CMD_EQID 0 4300 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 4301 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 4302 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 4303 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 4304 4305 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 4306 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 4307 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 4308 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 4309 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 4310 4311 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 4312 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 4313 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 4314 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 4315 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 4316 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 4317 4318 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 4319 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 4320 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 4321 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 4322 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 4323 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 4324 4325 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 4326 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 4327 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 4328 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 4329 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 4330 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 4331 4332 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 4333 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 4334 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 4335 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 4336 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 4337 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 4338 4339 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 4340 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 4341 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 4342 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 4343 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 4344 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 4345 4346 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 4347 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 4348 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 4349 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 4350 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 4351 4352 #define S_FW_EQ_MNGT_CMD_CPRIO 19 4353 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 4354 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 4355 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 4356 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 4357 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 4358 4359 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 4360 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 4361 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 4362 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 4363 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 4364 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 4365 4366 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 4367 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 4368 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 4369 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 4370 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 4371 4372 #define S_FW_EQ_MNGT_CMD_IQID 0 4373 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 4374 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 4375 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 4376 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 4377 4378 #define S_FW_EQ_MNGT_CMD_DCAEN 31 4379 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 4380 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 4381 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 4382 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 4383 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 4384 4385 #define S_FW_EQ_MNGT_CMD_DCACPU 26 4386 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 4387 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 4388 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 4389 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 4390 4391 #define S_FW_EQ_MNGT_CMD_FBMIN 23 4392 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 4393 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 4394 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 4395 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 4396 4397 #define S_FW_EQ_MNGT_CMD_FBMAX 20 4398 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 4399 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 4400 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 4401 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 4402 4403 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 4404 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 4405 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4406 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4407 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4408 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4409 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 4410 4411 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 4412 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 4413 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4414 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 4415 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4416 4417 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 4418 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 4419 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 4420 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 4421 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 4422 4423 struct fw_eq_eth_cmd { 4424 __be32 op_to_vfn; 4425 __be32 alloc_to_len16; 4426 __be32 eqid_pkd; 4427 __be32 physeqid_pkd; 4428 __be32 fetchszm_to_iqid; 4429 __be32 dcaen_to_eqsize; 4430 __be64 eqaddr; 4431 __be32 viid_pkd; 4432 __be32 r8_lo; 4433 __be64 r9; 4434 }; 4435 4436 #define S_FW_EQ_ETH_CMD_PFN 8 4437 #define M_FW_EQ_ETH_CMD_PFN 0x7 4438 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 4439 #define G_FW_EQ_ETH_CMD_PFN(x) \ 4440 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 4441 4442 #define S_FW_EQ_ETH_CMD_VFN 0 4443 #define M_FW_EQ_ETH_CMD_VFN 0xff 4444 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 4445 #define G_FW_EQ_ETH_CMD_VFN(x) \ 4446 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 4447 4448 #define S_FW_EQ_ETH_CMD_ALLOC 31 4449 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 4450 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 4451 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 4452 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 4453 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 4454 4455 #define S_FW_EQ_ETH_CMD_FREE 30 4456 #define M_FW_EQ_ETH_CMD_FREE 0x1 4457 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 4458 #define G_FW_EQ_ETH_CMD_FREE(x) \ 4459 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 4460 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 4461 4462 #define S_FW_EQ_ETH_CMD_MODIFY 29 4463 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 4464 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 4465 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 4466 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 4467 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 4468 4469 #define S_FW_EQ_ETH_CMD_EQSTART 28 4470 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 4471 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 4472 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 4473 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 4474 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 4475 4476 #define S_FW_EQ_ETH_CMD_EQSTOP 27 4477 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 4478 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 4479 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 4480 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 4481 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 4482 4483 #define S_FW_EQ_ETH_CMD_EQID 0 4484 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 4485 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 4486 #define G_FW_EQ_ETH_CMD_EQID(x) \ 4487 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 4488 4489 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 4490 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 4491 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 4492 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 4493 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 4494 4495 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 4496 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 4497 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 4498 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 4499 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 4500 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 4501 4502 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 4503 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 4504 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 4505 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 4506 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 4507 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 4508 4509 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 4510 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 4511 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 4512 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 4513 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 4514 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 4515 4516 #define S_FW_EQ_ETH_CMD_FETCHNS 23 4517 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 4518 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 4519 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 4520 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 4521 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 4522 4523 #define S_FW_EQ_ETH_CMD_FETCHRO 22 4524 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 4525 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 4526 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 4527 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 4528 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 4529 4530 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 4531 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 4532 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 4533 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 4534 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 4535 4536 #define S_FW_EQ_ETH_CMD_CPRIO 19 4537 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 4538 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 4539 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 4540 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 4541 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 4542 4543 #define S_FW_EQ_ETH_CMD_ONCHIP 18 4544 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 4545 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 4546 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 4547 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 4548 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 4549 4550 #define S_FW_EQ_ETH_CMD_PCIECHN 16 4551 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 4552 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 4553 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 4554 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 4555 4556 #define S_FW_EQ_ETH_CMD_IQID 0 4557 #define M_FW_EQ_ETH_CMD_IQID 0xffff 4558 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 4559 #define G_FW_EQ_ETH_CMD_IQID(x) \ 4560 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 4561 4562 #define S_FW_EQ_ETH_CMD_DCAEN 31 4563 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 4564 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 4565 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 4566 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 4567 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 4568 4569 #define S_FW_EQ_ETH_CMD_DCACPU 26 4570 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 4571 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 4572 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 4573 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 4574 4575 #define S_FW_EQ_ETH_CMD_FBMIN 23 4576 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 4577 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 4578 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 4579 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 4580 4581 #define S_FW_EQ_ETH_CMD_FBMAX 20 4582 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 4583 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 4584 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 4585 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 4586 4587 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 4588 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 4589 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4590 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 4591 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4592 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 4593 4594 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 4595 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 4596 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 4597 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 4598 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 4599 4600 #define S_FW_EQ_ETH_CMD_EQSIZE 0 4601 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 4602 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 4603 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 4604 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 4605 4606 #define S_FW_EQ_ETH_CMD_VIID 16 4607 #define M_FW_EQ_ETH_CMD_VIID 0xfff 4608 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 4609 #define G_FW_EQ_ETH_CMD_VIID(x) \ 4610 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 4611 4612 struct fw_eq_ctrl_cmd { 4613 __be32 op_to_vfn; 4614 __be32 alloc_to_len16; 4615 __be32 cmpliqid_eqid; 4616 __be32 physeqid_pkd; 4617 __be32 fetchszm_to_iqid; 4618 __be32 dcaen_to_eqsize; 4619 __be64 eqaddr; 4620 }; 4621 4622 #define S_FW_EQ_CTRL_CMD_PFN 8 4623 #define M_FW_EQ_CTRL_CMD_PFN 0x7 4624 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 4625 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 4626 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 4627 4628 #define S_FW_EQ_CTRL_CMD_VFN 0 4629 #define M_FW_EQ_CTRL_CMD_VFN 0xff 4630 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 4631 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 4632 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 4633 4634 #define S_FW_EQ_CTRL_CMD_ALLOC 31 4635 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 4636 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 4637 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 4638 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 4639 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 4640 4641 #define S_FW_EQ_CTRL_CMD_FREE 30 4642 #define M_FW_EQ_CTRL_CMD_FREE 0x1 4643 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 4644 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 4645 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 4646 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 4647 4648 #define S_FW_EQ_CTRL_CMD_MODIFY 29 4649 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 4650 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 4651 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 4652 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 4653 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 4654 4655 #define S_FW_EQ_CTRL_CMD_EQSTART 28 4656 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 4657 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 4658 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 4659 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 4660 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 4661 4662 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 4663 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 4664 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 4665 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 4666 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 4667 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 4668 4669 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 4670 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 4671 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 4672 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 4673 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 4674 4675 #define S_FW_EQ_CTRL_CMD_EQID 0 4676 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 4677 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 4678 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 4679 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 4680 4681 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 4682 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 4683 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 4684 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 4685 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 4686 4687 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 4688 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 4689 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 4690 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 4691 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 4692 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 4693 4694 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 4695 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 4696 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 4697 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 4698 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 4699 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 4700 4701 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 4702 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 4703 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 4704 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 4705 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 4706 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 4707 4708 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 4709 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 4710 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 4711 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 4712 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 4713 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 4714 4715 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 4716 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 4717 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 4718 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 4719 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 4720 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 4721 4722 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 4723 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 4724 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 4725 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 4726 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 4727 4728 #define S_FW_EQ_CTRL_CMD_CPRIO 19 4729 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 4730 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 4731 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 4732 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 4733 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 4734 4735 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 4736 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 4737 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 4738 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 4739 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 4740 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 4741 4742 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 4743 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 4744 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 4745 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 4746 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 4747 4748 #define S_FW_EQ_CTRL_CMD_IQID 0 4749 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 4750 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 4751 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 4752 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 4753 4754 #define S_FW_EQ_CTRL_CMD_DCAEN 31 4755 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 4756 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 4757 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 4758 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 4759 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 4760 4761 #define S_FW_EQ_CTRL_CMD_DCACPU 26 4762 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 4763 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 4764 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 4765 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 4766 4767 #define S_FW_EQ_CTRL_CMD_FBMIN 23 4768 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 4769 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 4770 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 4771 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 4772 4773 #define S_FW_EQ_CTRL_CMD_FBMAX 20 4774 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 4775 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 4776 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 4777 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 4778 4779 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 4780 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 4781 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4782 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4783 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4784 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4785 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 4786 4787 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 4788 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 4789 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4790 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 4791 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4792 4793 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 4794 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 4795 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 4796 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 4797 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 4798 4799 struct fw_eq_ofld_cmd { 4800 __be32 op_to_vfn; 4801 __be32 alloc_to_len16; 4802 __be32 eqid_pkd; 4803 __be32 physeqid_pkd; 4804 __be32 fetchszm_to_iqid; 4805 __be32 dcaen_to_eqsize; 4806 __be64 eqaddr; 4807 }; 4808 4809 #define S_FW_EQ_OFLD_CMD_PFN 8 4810 #define M_FW_EQ_OFLD_CMD_PFN 0x7 4811 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 4812 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 4813 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 4814 4815 #define S_FW_EQ_OFLD_CMD_VFN 0 4816 #define M_FW_EQ_OFLD_CMD_VFN 0xff 4817 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 4818 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 4819 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 4820 4821 #define S_FW_EQ_OFLD_CMD_ALLOC 31 4822 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 4823 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 4824 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 4825 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 4826 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 4827 4828 #define S_FW_EQ_OFLD_CMD_FREE 30 4829 #define M_FW_EQ_OFLD_CMD_FREE 0x1 4830 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 4831 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 4832 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 4833 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 4834 4835 #define S_FW_EQ_OFLD_CMD_MODIFY 29 4836 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 4837 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 4838 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 4839 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 4840 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 4841 4842 #define S_FW_EQ_OFLD_CMD_EQSTART 28 4843 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 4844 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 4845 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 4846 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 4847 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 4848 4849 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 4850 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 4851 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 4852 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 4853 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 4854 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 4855 4856 #define S_FW_EQ_OFLD_CMD_EQID 0 4857 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 4858 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 4859 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 4860 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 4861 4862 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 4863 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 4864 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 4865 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 4866 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 4867 4868 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 4869 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 4870 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 4871 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 4872 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 4873 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 4874 4875 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 4876 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 4877 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 4878 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 4879 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 4880 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 4881 4882 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 4883 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 4884 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 4885 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 4886 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 4887 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 4888 4889 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 4890 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 4891 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 4892 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 4893 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 4894 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 4895 4896 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 4897 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 4898 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 4899 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 4900 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 4901 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 4902 4903 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 4904 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 4905 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 4906 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 4907 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 4908 4909 #define S_FW_EQ_OFLD_CMD_CPRIO 19 4910 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 4911 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 4912 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 4913 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 4914 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 4915 4916 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 4917 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 4918 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 4919 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 4920 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 4921 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 4922 4923 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 4924 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 4925 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 4926 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 4927 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 4928 4929 #define S_FW_EQ_OFLD_CMD_IQID 0 4930 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 4931 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 4932 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 4933 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 4934 4935 #define S_FW_EQ_OFLD_CMD_DCAEN 31 4936 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 4937 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 4938 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 4939 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 4940 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 4941 4942 #define S_FW_EQ_OFLD_CMD_DCACPU 26 4943 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 4944 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 4945 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 4946 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 4947 4948 #define S_FW_EQ_OFLD_CMD_FBMIN 23 4949 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 4950 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 4951 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 4952 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 4953 4954 #define S_FW_EQ_OFLD_CMD_FBMAX 20 4955 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 4956 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 4957 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 4958 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 4959 4960 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 4961 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 4962 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 4963 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 4964 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 4965 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 4966 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 4967 4968 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 4969 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 4970 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 4971 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 4972 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 4973 4974 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 4975 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 4976 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 4977 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 4978 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 4979 4980 /* Macros for VIID parsing: 4981 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 4982 #define S_FW_VIID_PFN 8 4983 #define M_FW_VIID_PFN 0x7 4984 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 4985 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 4986 4987 #define S_FW_VIID_VIVLD 7 4988 #define M_FW_VIID_VIVLD 0x1 4989 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 4990 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 4991 4992 #define S_FW_VIID_VIN 0 4993 #define M_FW_VIID_VIN 0x7F 4994 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 4995 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 4996 4997 enum fw_vi_func { 4998 FW_VI_FUNC_ETH, 4999 FW_VI_FUNC_OFLD, 5000 FW_VI_FUNC_IWARP, 5001 FW_VI_FUNC_OPENISCSI, 5002 FW_VI_FUNC_OPENFCOE, 5003 FW_VI_FUNC_FOISCSI, 5004 FW_VI_FUNC_FOFCOE, 5005 FW_VI_FUNC_FW, 5006 }; 5007 5008 struct fw_vi_cmd { 5009 __be32 op_to_vfn; 5010 __be32 alloc_to_len16; 5011 __be16 type_to_viid; 5012 __u8 mac[6]; 5013 __u8 portid_pkd; 5014 __u8 nmac; 5015 __u8 nmac0[6]; 5016 __be16 norss_rsssize; 5017 __u8 nmac1[6]; 5018 __be16 idsiiq_pkd; 5019 __u8 nmac2[6]; 5020 __be16 idseiq_pkd; 5021 __u8 nmac3[6]; 5022 __be64 r9; 5023 __be64 r10; 5024 }; 5025 5026 #define S_FW_VI_CMD_PFN 8 5027 #define M_FW_VI_CMD_PFN 0x7 5028 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 5029 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 5030 5031 #define S_FW_VI_CMD_VFN 0 5032 #define M_FW_VI_CMD_VFN 0xff 5033 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 5034 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 5035 5036 #define S_FW_VI_CMD_ALLOC 31 5037 #define M_FW_VI_CMD_ALLOC 0x1 5038 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 5039 #define G_FW_VI_CMD_ALLOC(x) \ 5040 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 5041 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 5042 5043 #define S_FW_VI_CMD_FREE 30 5044 #define M_FW_VI_CMD_FREE 0x1 5045 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 5046 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 5047 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 5048 5049 #define S_FW_VI_CMD_TYPE 15 5050 #define M_FW_VI_CMD_TYPE 0x1 5051 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 5052 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 5053 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 5054 5055 #define S_FW_VI_CMD_FUNC 12 5056 #define M_FW_VI_CMD_FUNC 0x7 5057 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 5058 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 5059 5060 #define S_FW_VI_CMD_VIID 0 5061 #define M_FW_VI_CMD_VIID 0xfff 5062 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 5063 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 5064 5065 #define S_FW_VI_CMD_PORTID 4 5066 #define M_FW_VI_CMD_PORTID 0xf 5067 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 5068 #define G_FW_VI_CMD_PORTID(x) \ 5069 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 5070 5071 #define S_FW_VI_CMD_NORSS 11 5072 #define M_FW_VI_CMD_NORSS 0x1 5073 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 5074 #define G_FW_VI_CMD_NORSS(x) \ 5075 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 5076 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 5077 5078 #define S_FW_VI_CMD_RSSSIZE 0 5079 #define M_FW_VI_CMD_RSSSIZE 0x7ff 5080 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 5081 #define G_FW_VI_CMD_RSSSIZE(x) \ 5082 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 5083 5084 #define S_FW_VI_CMD_IDSIIQ 0 5085 #define M_FW_VI_CMD_IDSIIQ 0x3ff 5086 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 5087 #define G_FW_VI_CMD_IDSIIQ(x) \ 5088 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 5089 5090 #define S_FW_VI_CMD_IDSEIQ 0 5091 #define M_FW_VI_CMD_IDSEIQ 0x3ff 5092 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 5093 #define G_FW_VI_CMD_IDSEIQ(x) \ 5094 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 5095 5096 /* Special VI_MAC command index ids */ 5097 #define FW_VI_MAC_ADD_MAC 0x3FF 5098 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 5099 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 5100 5101 enum fw_vi_mac_smac { 5102 FW_VI_MAC_MPS_TCAM_ENTRY, 5103 FW_VI_MAC_MPS_TCAM_ONLY, 5104 FW_VI_MAC_SMT_ONLY, 5105 FW_VI_MAC_SMT_AND_MPSTCAM 5106 }; 5107 5108 enum fw_vi_mac_result { 5109 FW_VI_MAC_R_SUCCESS, 5110 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 5111 FW_VI_MAC_R_SMAC_FAIL, 5112 FW_VI_MAC_R_F_ACL_CHECK 5113 }; 5114 5115 struct fw_vi_mac_cmd { 5116 __be32 op_to_viid; 5117 __be32 freemacs_to_len16; 5118 union fw_vi_mac { 5119 struct fw_vi_mac_exact { 5120 __be16 valid_to_idx; 5121 __u8 macaddr[6]; 5122 } exact[7]; 5123 struct fw_vi_mac_hash { 5124 __be64 hashvec; 5125 } hash; 5126 } u; 5127 }; 5128 5129 #define S_FW_VI_MAC_CMD_VIID 0 5130 #define M_FW_VI_MAC_CMD_VIID 0xfff 5131 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 5132 #define G_FW_VI_MAC_CMD_VIID(x) \ 5133 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 5134 5135 #define S_FW_VI_MAC_CMD_FREEMACS 31 5136 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 5137 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 5138 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 5139 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 5140 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 5141 5142 #define S_FW_VI_MAC_CMD_HASHVECEN 23 5143 #define M_FW_VI_MAC_CMD_HASHVECEN 0x1 5144 #define V_FW_VI_MAC_CMD_HASHVECEN(x) ((x) << S_FW_VI_MAC_CMD_HASHVECEN) 5145 #define G_FW_VI_MAC_CMD_HASHVECEN(x) \ 5146 (((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN) 5147 #define F_FW_VI_MAC_CMD_HASHVECEN V_FW_VI_MAC_CMD_HASHVECEN(1U) 5148 5149 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 5150 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 5151 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 5152 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 5153 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 5154 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 5155 5156 #define S_FW_VI_MAC_CMD_VALID 15 5157 #define M_FW_VI_MAC_CMD_VALID 0x1 5158 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 5159 #define G_FW_VI_MAC_CMD_VALID(x) \ 5160 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 5161 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 5162 5163 #define S_FW_VI_MAC_CMD_PRIO 12 5164 #define M_FW_VI_MAC_CMD_PRIO 0x7 5165 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 5166 #define G_FW_VI_MAC_CMD_PRIO(x) \ 5167 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 5168 5169 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 5170 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 5171 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 5172 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 5173 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 5174 5175 #define S_FW_VI_MAC_CMD_IDX 0 5176 #define M_FW_VI_MAC_CMD_IDX 0x3ff 5177 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 5178 #define G_FW_VI_MAC_CMD_IDX(x) \ 5179 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 5180 5181 /* T4 max MTU supported */ 5182 #define T4_MAX_MTU_SUPPORTED 9600 5183 #define FW_RXMODE_MTU_NO_CHG 65535 5184 5185 struct fw_vi_rxmode_cmd { 5186 __be32 op_to_viid; 5187 __be32 retval_len16; 5188 __be32 mtu_to_vlanexen; 5189 __be32 r4_lo; 5190 }; 5191 5192 #define S_FW_VI_RXMODE_CMD_VIID 0 5193 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 5194 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 5195 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 5196 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 5197 5198 #define S_FW_VI_RXMODE_CMD_MTU 16 5199 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 5200 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 5201 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 5202 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 5203 5204 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 5205 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 5206 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 5207 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 5208 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 5209 5210 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 5211 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 5212 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5213 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 5214 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5215 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 5216 5217 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 5218 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 5219 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5220 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 5221 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5222 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 5223 5224 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 5225 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 5226 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 5227 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 5228 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 5229 5230 struct fw_vi_enable_cmd { 5231 __be32 op_to_viid; 5232 __be32 ien_to_len16; 5233 __be16 blinkdur; 5234 __be16 r3; 5235 __be32 r4; 5236 }; 5237 5238 #define S_FW_VI_ENABLE_CMD_VIID 0 5239 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 5240 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 5241 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 5242 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 5243 5244 #define S_FW_VI_ENABLE_CMD_IEN 31 5245 #define M_FW_VI_ENABLE_CMD_IEN 0x1 5246 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 5247 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 5248 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 5249 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 5250 5251 #define S_FW_VI_ENABLE_CMD_EEN 30 5252 #define M_FW_VI_ENABLE_CMD_EEN 0x1 5253 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 5254 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 5255 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 5256 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 5257 5258 #define S_FW_VI_ENABLE_CMD_LED 29 5259 #define M_FW_VI_ENABLE_CMD_LED 0x1 5260 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 5261 #define G_FW_VI_ENABLE_CMD_LED(x) \ 5262 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 5263 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 5264 5265 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 5266 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 5267 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 5268 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 5269 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 5270 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 5271 5272 /* VI VF stats offset definitions */ 5273 #define VI_VF_NUM_STATS 16 5274 enum fw_vi_stats_vf_index { 5275 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 5276 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 5277 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 5278 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 5279 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 5280 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 5281 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 5282 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 5283 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 5284 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 5285 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 5286 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 5287 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 5288 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 5289 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 5290 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 5291 }; 5292 5293 /* VI PF stats offset definitions */ 5294 #define VI_PF_NUM_STATS 17 5295 enum fw_vi_stats_pf_index { 5296 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 5297 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 5298 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 5299 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 5300 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 5301 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 5302 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 5303 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 5304 FW_VI_PF_STAT_RX_BYTES_IX, 5305 FW_VI_PF_STAT_RX_FRAMES_IX, 5306 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 5307 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 5308 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 5309 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 5310 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 5311 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 5312 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 5313 }; 5314 5315 struct fw_vi_stats_cmd { 5316 __be32 op_to_viid; 5317 __be32 retval_len16; 5318 union fw_vi_stats { 5319 struct fw_vi_stats_ctl { 5320 __be16 nstats_ix; 5321 __be16 r6; 5322 __be32 r7; 5323 __be64 stat0; 5324 __be64 stat1; 5325 __be64 stat2; 5326 __be64 stat3; 5327 __be64 stat4; 5328 __be64 stat5; 5329 } ctl; 5330 struct fw_vi_stats_pf { 5331 __be64 tx_bcast_bytes; 5332 __be64 tx_bcast_frames; 5333 __be64 tx_mcast_bytes; 5334 __be64 tx_mcast_frames; 5335 __be64 tx_ucast_bytes; 5336 __be64 tx_ucast_frames; 5337 __be64 tx_offload_bytes; 5338 __be64 tx_offload_frames; 5339 __be64 rx_pf_bytes; 5340 __be64 rx_pf_frames; 5341 __be64 rx_bcast_bytes; 5342 __be64 rx_bcast_frames; 5343 __be64 rx_mcast_bytes; 5344 __be64 rx_mcast_frames; 5345 __be64 rx_ucast_bytes; 5346 __be64 rx_ucast_frames; 5347 __be64 rx_err_frames; 5348 } pf; 5349 struct fw_vi_stats_vf { 5350 __be64 tx_bcast_bytes; 5351 __be64 tx_bcast_frames; 5352 __be64 tx_mcast_bytes; 5353 __be64 tx_mcast_frames; 5354 __be64 tx_ucast_bytes; 5355 __be64 tx_ucast_frames; 5356 __be64 tx_drop_frames; 5357 __be64 tx_offload_bytes; 5358 __be64 tx_offload_frames; 5359 __be64 rx_bcast_bytes; 5360 __be64 rx_bcast_frames; 5361 __be64 rx_mcast_bytes; 5362 __be64 rx_mcast_frames; 5363 __be64 rx_ucast_bytes; 5364 __be64 rx_ucast_frames; 5365 __be64 rx_err_frames; 5366 } vf; 5367 } u; 5368 }; 5369 5370 #define S_FW_VI_STATS_CMD_VIID 0 5371 #define M_FW_VI_STATS_CMD_VIID 0xfff 5372 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 5373 #define G_FW_VI_STATS_CMD_VIID(x) \ 5374 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 5375 5376 #define S_FW_VI_STATS_CMD_NSTATS 12 5377 #define M_FW_VI_STATS_CMD_NSTATS 0x7 5378 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 5379 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 5380 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 5381 5382 #define S_FW_VI_STATS_CMD_IX 0 5383 #define M_FW_VI_STATS_CMD_IX 0x1f 5384 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 5385 #define G_FW_VI_STATS_CMD_IX(x) \ 5386 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 5387 5388 struct fw_acl_mac_cmd { 5389 __be32 op_to_vfn; 5390 __be32 en_to_len16; 5391 __u8 nmac; 5392 __u8 r3[7]; 5393 __be16 r4; 5394 __u8 macaddr0[6]; 5395 __be16 r5; 5396 __u8 macaddr1[6]; 5397 __be16 r6; 5398 __u8 macaddr2[6]; 5399 __be16 r7; 5400 __u8 macaddr3[6]; 5401 }; 5402 5403 #define S_FW_ACL_MAC_CMD_PFN 8 5404 #define M_FW_ACL_MAC_CMD_PFN 0x7 5405 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 5406 #define G_FW_ACL_MAC_CMD_PFN(x) \ 5407 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 5408 5409 #define S_FW_ACL_MAC_CMD_VFN 0 5410 #define M_FW_ACL_MAC_CMD_VFN 0xff 5411 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 5412 #define G_FW_ACL_MAC_CMD_VFN(x) \ 5413 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 5414 5415 #define S_FW_ACL_MAC_CMD_EN 31 5416 #define M_FW_ACL_MAC_CMD_EN 0x1 5417 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 5418 #define G_FW_ACL_MAC_CMD_EN(x) \ 5419 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 5420 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 5421 5422 struct fw_acl_vlan_cmd { 5423 __be32 op_to_vfn; 5424 __be32 en_to_len16; 5425 __u8 nvlan; 5426 __u8 dropnovlan_fm; 5427 __u8 r3_lo[6]; 5428 __be16 vlanid[16]; 5429 }; 5430 5431 #define S_FW_ACL_VLAN_CMD_PFN 8 5432 #define M_FW_ACL_VLAN_CMD_PFN 0x7 5433 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 5434 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 5435 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 5436 5437 #define S_FW_ACL_VLAN_CMD_VFN 0 5438 #define M_FW_ACL_VLAN_CMD_VFN 0xff 5439 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 5440 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 5441 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 5442 5443 #define S_FW_ACL_VLAN_CMD_EN 31 5444 #define M_FW_ACL_VLAN_CMD_EN 0x1 5445 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 5446 #define G_FW_ACL_VLAN_CMD_EN(x) \ 5447 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 5448 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 5449 5450 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 5451 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 5452 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 5453 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 5454 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 5455 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 5456 5457 #define S_FW_ACL_VLAN_CMD_FM 6 5458 #define M_FW_ACL_VLAN_CMD_FM 0x1 5459 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 5460 #define G_FW_ACL_VLAN_CMD_FM(x) \ 5461 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 5462 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 5463 5464 /* port capabilities bitmap */ 5465 enum fw_port_cap { 5466 FW_PORT_CAP_SPEED_100M = 0x0001, 5467 FW_PORT_CAP_SPEED_1G = 0x0002, 5468 FW_PORT_CAP_SPEED_2_5G = 0x0004, 5469 FW_PORT_CAP_SPEED_10G = 0x0008, 5470 FW_PORT_CAP_SPEED_40G = 0x0010, 5471 FW_PORT_CAP_SPEED_100G = 0x0020, 5472 FW_PORT_CAP_FC_RX = 0x0040, 5473 FW_PORT_CAP_FC_TX = 0x0080, 5474 FW_PORT_CAP_ANEG = 0x0100, 5475 FW_PORT_CAP_MDIX = 0x0200, 5476 FW_PORT_CAP_MDIAUTO = 0x0400, 5477 FW_PORT_CAP_FEC = 0x0800, 5478 FW_PORT_CAP_TECHKR = 0x1000, 5479 FW_PORT_CAP_TECHKX4 = 0x2000, 5480 }; 5481 5482 #define S_FW_PORT_AUXLINFO_MDI 3 5483 #define M_FW_PORT_AUXLINFO_MDI 0x3 5484 #define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI) 5485 #define G_FW_PORT_AUXLINFO_MDI(x) \ 5486 (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI) 5487 5488 #define S_FW_PORT_AUXLINFO_KX4 2 5489 #define M_FW_PORT_AUXLINFO_KX4 0x1 5490 #define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4) 5491 #define G_FW_PORT_AUXLINFO_KX4(x) \ 5492 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 5493 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 5494 5495 #define S_FW_PORT_AUXLINFO_KR 1 5496 #define M_FW_PORT_AUXLINFO_KR 0x1 5497 #define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR) 5498 #define G_FW_PORT_AUXLINFO_KR(x) \ 5499 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 5500 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 5501 5502 #define S_FW_PORT_AUXLINFO_FEC 0 5503 #define M_FW_PORT_AUXLINFO_FEC 0x1 5504 #define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) 5505 #define G_FW_PORT_AUXLINFO_FEC(x) \ 5506 (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) 5507 #define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) 5508 5509 #define S_FW_PORT_RCAP_AUX 11 5510 #define M_FW_PORT_RCAP_AUX 0x7 5511 #define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX) 5512 #define G_FW_PORT_RCAP_AUX(x) \ 5513 (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX) 5514 5515 #define S_FW_PORT_CAP_SPEED 0 5516 #define M_FW_PORT_CAP_SPEED 0x3f 5517 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 5518 #define G_FW_PORT_CAP_SPEED(x) \ 5519 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 5520 5521 #define S_FW_PORT_CAP_FC 6 5522 #define M_FW_PORT_CAP_FC 0x3 5523 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 5524 #define G_FW_PORT_CAP_FC(x) \ 5525 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 5526 5527 #define S_FW_PORT_CAP_ANEG 8 5528 #define M_FW_PORT_CAP_ANEG 0x1 5529 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 5530 #define G_FW_PORT_CAP_ANEG(x) \ 5531 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 5532 5533 enum fw_port_mdi { 5534 FW_PORT_CAP_MDI_UNCHANGED, 5535 FW_PORT_CAP_MDI_AUTO, 5536 FW_PORT_CAP_MDI_F_STRAIGHT, 5537 FW_PORT_CAP_MDI_F_CROSSOVER 5538 }; 5539 5540 #define S_FW_PORT_CAP_MDI 9 5541 #define M_FW_PORT_CAP_MDI 3 5542 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 5543 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 5544 5545 enum fw_port_action { 5546 FW_PORT_ACTION_L1_CFG = 0x0001, 5547 FW_PORT_ACTION_L2_CFG = 0x0002, 5548 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 5549 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 5550 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 5551 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 5552 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 5553 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 5554 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 5555 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 5556 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 5557 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 5558 FW_PORT_ACTION_L1_SS_LPBK_ASIC = 0x0021, 5559 FW_PORT_ACTION_MAC_LPBK = 0x0022, 5560 FW_PORT_ACTION_L1_WS_LPBK_ASIC = 0x0023, 5561 FW_PORT_ACTION_L1_EXT_LPBK = 0x0026, 5562 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 5563 FW_PORT_ACTION_PCS_LPBK = 0x0028, 5564 FW_PORT_ACTION_PHY_RESET = 0x0040, 5565 FW_PORT_ACTION_PMA_RESET = 0x0041, 5566 FW_PORT_ACTION_PCS_RESET = 0x0042, 5567 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 5568 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 5569 FW_PORT_ACTION_AN_RESET = 0x0045, 5570 }; 5571 5572 enum fw_port_l2cfg_ctlbf { 5573 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 5574 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 5575 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 5576 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 5577 FW_PORT_L2_CTLBF_IVLAN = 0x10, 5578 FW_PORT_L2_CTLBF_TXIPG = 0x20, 5579 FW_PORT_L2_CTLBF_MTU = 0x40 5580 }; 5581 5582 enum fw_port_dcb_cfg { 5583 FW_PORT_DCB_CFG_PG = 0x01, 5584 FW_PORT_DCB_CFG_PFC = 0x02, 5585 FW_PORT_DCB_CFG_APPL = 0x04 5586 }; 5587 5588 enum fw_port_dcb_cfg_rc { 5589 FW_PORT_DCB_CFG_SUCCESS = 0x0, 5590 FW_PORT_DCB_CFG_ERROR = 0x1 5591 }; 5592 5593 enum fw_port_dcb_type { 5594 FW_PORT_DCB_TYPE_PGID = 0x00, 5595 FW_PORT_DCB_TYPE_PGRATE = 0x01, 5596 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 5597 FW_PORT_DCB_TYPE_PFC = 0x03, 5598 FW_PORT_DCB_TYPE_APP_ID = 0x04, 5599 FW_PORT_DCB_TYPE_CONTROL = 0x05, 5600 }; 5601 5602 enum fw_port_diag_ops { 5603 FW_PORT_DIAGS_TEMP = 0x00, 5604 FW_PORT_DIAGS_TX_POWER = 0x01, 5605 FW_PORT_DIAGS_RX_POWER = 0x02, 5606 }; 5607 5608 struct fw_port_cmd { 5609 __be32 op_to_portid; 5610 __be32 action_to_len16; 5611 union fw_port { 5612 struct fw_port_l1cfg { 5613 __be32 rcap; 5614 __be32 r; 5615 } l1cfg; 5616 struct fw_port_l2cfg { 5617 __u8 ctlbf; 5618 __u8 ovlan3_to_ivlan0; 5619 __be16 ivlantype; 5620 __be16 txipg_force_pinfo; 5621 __be16 mtu; 5622 __be16 ovlan0mask; 5623 __be16 ovlan0type; 5624 __be16 ovlan1mask; 5625 __be16 ovlan1type; 5626 __be16 ovlan2mask; 5627 __be16 ovlan2type; 5628 __be16 ovlan3mask; 5629 __be16 ovlan3type; 5630 } l2cfg; 5631 struct fw_port_info { 5632 __be32 lstatus_to_modtype; 5633 __be16 pcap; 5634 __be16 acap; 5635 __be16 mtu; 5636 __u8 cbllen; 5637 __u8 auxlinfo; 5638 __be32 r8; 5639 __be64 r9; 5640 } info; 5641 struct fw_port_diags { 5642 __u8 diagop; 5643 __u8 r[3]; 5644 __be32 diagval; 5645 } diags; 5646 union fw_port_dcb { 5647 struct fw_port_dcb_pgid { 5648 __u8 type; 5649 __u8 apply_pkd; 5650 __u8 r10_lo[2]; 5651 __be32 pgid; 5652 __be64 r11; 5653 } pgid; 5654 struct fw_port_dcb_pgrate { 5655 __u8 type; 5656 __u8 apply_pkd; 5657 __u8 r10_lo[5]; 5658 __u8 num_tcs_supported; 5659 __u8 pgrate[8]; 5660 } pgrate; 5661 struct fw_port_dcb_priorate { 5662 __u8 type; 5663 __u8 apply_pkd; 5664 __u8 r10_lo[6]; 5665 __u8 strict_priorate[8]; 5666 } priorate; 5667 struct fw_port_dcb_pfc { 5668 __u8 type; 5669 __u8 pfcen; 5670 __be16 r10[3]; 5671 __be64 r11; 5672 } pfc; 5673 struct fw_port_app_priority { 5674 __u8 type; 5675 __u8 r10[2]; 5676 __u8 idx; 5677 __u8 user_prio_map; 5678 __u8 sel_field; 5679 __be16 protocolid; 5680 __be64 r12; 5681 } app_priority; 5682 struct fw_port_dcb_control { 5683 __u8 type; 5684 __u8 all_syncd_pkd; 5685 __be16 r10_lo[3]; 5686 __be64 r11; 5687 } control; 5688 } dcb; 5689 } u; 5690 }; 5691 5692 #define S_FW_PORT_CMD_READ 22 5693 #define M_FW_PORT_CMD_READ 0x1 5694 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 5695 #define G_FW_PORT_CMD_READ(x) \ 5696 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 5697 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 5698 5699 #define S_FW_PORT_CMD_PORTID 0 5700 #define M_FW_PORT_CMD_PORTID 0xf 5701 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 5702 #define G_FW_PORT_CMD_PORTID(x) \ 5703 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 5704 5705 #define S_FW_PORT_CMD_ACTION 16 5706 #define M_FW_PORT_CMD_ACTION 0xffff 5707 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 5708 #define G_FW_PORT_CMD_ACTION(x) \ 5709 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 5710 5711 #define S_FW_PORT_CMD_OVLAN3 7 5712 #define M_FW_PORT_CMD_OVLAN3 0x1 5713 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 5714 #define G_FW_PORT_CMD_OVLAN3(x) \ 5715 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 5716 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 5717 5718 #define S_FW_PORT_CMD_OVLAN2 6 5719 #define M_FW_PORT_CMD_OVLAN2 0x1 5720 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 5721 #define G_FW_PORT_CMD_OVLAN2(x) \ 5722 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 5723 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 5724 5725 #define S_FW_PORT_CMD_OVLAN1 5 5726 #define M_FW_PORT_CMD_OVLAN1 0x1 5727 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 5728 #define G_FW_PORT_CMD_OVLAN1(x) \ 5729 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 5730 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 5731 5732 #define S_FW_PORT_CMD_OVLAN0 4 5733 #define M_FW_PORT_CMD_OVLAN0 0x1 5734 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 5735 #define G_FW_PORT_CMD_OVLAN0(x) \ 5736 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 5737 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 5738 5739 #define S_FW_PORT_CMD_IVLAN0 3 5740 #define M_FW_PORT_CMD_IVLAN0 0x1 5741 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 5742 #define G_FW_PORT_CMD_IVLAN0(x) \ 5743 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 5744 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 5745 5746 #define S_FW_PORT_CMD_TXIPG 3 5747 #define M_FW_PORT_CMD_TXIPG 0x1fff 5748 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 5749 #define G_FW_PORT_CMD_TXIPG(x) \ 5750 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 5751 5752 #define S_FW_PORT_CMD_FORCE_PINFO 0 5753 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 5754 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 5755 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 5756 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 5757 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 5758 5759 #define S_FW_PORT_CMD_LSTATUS 31 5760 #define M_FW_PORT_CMD_LSTATUS 0x1 5761 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 5762 #define G_FW_PORT_CMD_LSTATUS(x) \ 5763 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 5764 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 5765 5766 #define S_FW_PORT_CMD_LSPEED 24 5767 #define M_FW_PORT_CMD_LSPEED 0x3f 5768 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 5769 #define G_FW_PORT_CMD_LSPEED(x) \ 5770 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 5771 5772 #define S_FW_PORT_CMD_TXPAUSE 23 5773 #define M_FW_PORT_CMD_TXPAUSE 0x1 5774 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 5775 #define G_FW_PORT_CMD_TXPAUSE(x) \ 5776 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 5777 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 5778 5779 #define S_FW_PORT_CMD_RXPAUSE 22 5780 #define M_FW_PORT_CMD_RXPAUSE 0x1 5781 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 5782 #define G_FW_PORT_CMD_RXPAUSE(x) \ 5783 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 5784 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 5785 5786 #define S_FW_PORT_CMD_MDIOCAP 21 5787 #define M_FW_PORT_CMD_MDIOCAP 0x1 5788 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 5789 #define G_FW_PORT_CMD_MDIOCAP(x) \ 5790 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 5791 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 5792 5793 #define S_FW_PORT_CMD_MDIOADDR 16 5794 #define M_FW_PORT_CMD_MDIOADDR 0x1f 5795 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 5796 #define G_FW_PORT_CMD_MDIOADDR(x) \ 5797 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 5798 5799 #define S_FW_PORT_CMD_LPTXPAUSE 15 5800 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 5801 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 5802 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 5803 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 5804 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 5805 5806 #define S_FW_PORT_CMD_LPRXPAUSE 14 5807 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 5808 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 5809 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 5810 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 5811 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 5812 5813 #define S_FW_PORT_CMD_PTYPE 8 5814 #define M_FW_PORT_CMD_PTYPE 0x1f 5815 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 5816 #define G_FW_PORT_CMD_PTYPE(x) \ 5817 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 5818 5819 #define S_FW_PORT_CMD_LINKDNRC 5 5820 #define M_FW_PORT_CMD_LINKDNRC 0x7 5821 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 5822 #define G_FW_PORT_CMD_LINKDNRC(x) \ 5823 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 5824 5825 #define S_FW_PORT_CMD_MODTYPE 0 5826 #define M_FW_PORT_CMD_MODTYPE 0x1f 5827 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 5828 #define G_FW_PORT_CMD_MODTYPE(x) \ 5829 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 5830 5831 #define S_FW_PORT_CMD_APPLY 7 5832 #define M_FW_PORT_CMD_APPLY 0x1 5833 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 5834 #define G_FW_PORT_CMD_APPLY(x) \ 5835 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 5836 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 5837 5838 #define S_FW_PORT_CMD_ALL_SYNCD 7 5839 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 5840 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 5841 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 5842 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 5843 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 5844 5845 /* 5846 * These are configured into the VPD and hence tools that generate 5847 * VPD may use this enumeration. 5848 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 5849 */ 5850 enum fw_port_type { 5851 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 5852 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 5853 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 5854 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ 5855 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ 5856 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 5857 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 5858 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 5859 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 5860 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 5861 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 5862 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 5863 5864 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 5865 }; 5866 5867 /* These are read from module's EEPROM and determined once the 5868 module is inserted. */ 5869 enum fw_port_module_type { 5870 FW_PORT_MOD_TYPE_NA = 0x0, 5871 FW_PORT_MOD_TYPE_LR = 0x1, 5872 FW_PORT_MOD_TYPE_SR = 0x2, 5873 FW_PORT_MOD_TYPE_ER = 0x3, 5874 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 5875 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 5876 FW_PORT_MOD_TYPE_LRM = 0x6, 5877 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 5878 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 5879 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 5880 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 5881 }; 5882 5883 /* used by FW and tools may use this to generate VPD */ 5884 enum fw_port_mod_sub_type { 5885 FW_PORT_MOD_SUB_TYPE_NA, 5886 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 5887 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 5888 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 5889 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 5890 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 5891 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 5892 5893 /* 5894 * The following will never been in the VPD. They are TWINAX cable 5895 * lengths decoded from SFP+ module i2c PROMs. These should almost 5896 * certainly go somewhere else ... 5897 */ 5898 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 5899 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 5900 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 5901 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 5902 }; 5903 5904 /* link down reason codes (3b) */ 5905 enum fw_port_link_dn_rc { 5906 FW_PORT_LINK_DN_RC_NONE, 5907 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 5908 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 5909 FW_PORT_LINK_DN_RESERVED3, 5910 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 5911 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 5912 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 5913 FW_PORT_LINK_DN_RESERVED7 5914 }; 5915 5916 /* port stats */ 5917 #define FW_NUM_PORT_STATS 50 5918 #define FW_NUM_PORT_TX_STATS 23 5919 #define FW_NUM_PORT_RX_STATS 27 5920 5921 enum fw_port_stats_tx_index { 5922 FW_STAT_TX_PORT_BYTES_IX, 5923 FW_STAT_TX_PORT_FRAMES_IX, 5924 FW_STAT_TX_PORT_BCAST_IX, 5925 FW_STAT_TX_PORT_MCAST_IX, 5926 FW_STAT_TX_PORT_UCAST_IX, 5927 FW_STAT_TX_PORT_ERROR_IX, 5928 FW_STAT_TX_PORT_64B_IX, 5929 FW_STAT_TX_PORT_65B_127B_IX, 5930 FW_STAT_TX_PORT_128B_255B_IX, 5931 FW_STAT_TX_PORT_256B_511B_IX, 5932 FW_STAT_TX_PORT_512B_1023B_IX, 5933 FW_STAT_TX_PORT_1024B_1518B_IX, 5934 FW_STAT_TX_PORT_1519B_MAX_IX, 5935 FW_STAT_TX_PORT_DROP_IX, 5936 FW_STAT_TX_PORT_PAUSE_IX, 5937 FW_STAT_TX_PORT_PPP0_IX, 5938 FW_STAT_TX_PORT_PPP1_IX, 5939 FW_STAT_TX_PORT_PPP2_IX, 5940 FW_STAT_TX_PORT_PPP3_IX, 5941 FW_STAT_TX_PORT_PPP4_IX, 5942 FW_STAT_TX_PORT_PPP5_IX, 5943 FW_STAT_TX_PORT_PPP6_IX, 5944 FW_STAT_TX_PORT_PPP7_IX 5945 }; 5946 5947 enum fw_port_stat_rx_index { 5948 FW_STAT_RX_PORT_BYTES_IX, 5949 FW_STAT_RX_PORT_FRAMES_IX, 5950 FW_STAT_RX_PORT_BCAST_IX, 5951 FW_STAT_RX_PORT_MCAST_IX, 5952 FW_STAT_RX_PORT_UCAST_IX, 5953 FW_STAT_RX_PORT_MTU_ERROR_IX, 5954 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 5955 FW_STAT_RX_PORT_CRC_ERROR_IX, 5956 FW_STAT_RX_PORT_LEN_ERROR_IX, 5957 FW_STAT_RX_PORT_SYM_ERROR_IX, 5958 FW_STAT_RX_PORT_64B_IX, 5959 FW_STAT_RX_PORT_65B_127B_IX, 5960 FW_STAT_RX_PORT_128B_255B_IX, 5961 FW_STAT_RX_PORT_256B_511B_IX, 5962 FW_STAT_RX_PORT_512B_1023B_IX, 5963 FW_STAT_RX_PORT_1024B_1518B_IX, 5964 FW_STAT_RX_PORT_1519B_MAX_IX, 5965 FW_STAT_RX_PORT_PAUSE_IX, 5966 FW_STAT_RX_PORT_PPP0_IX, 5967 FW_STAT_RX_PORT_PPP1_IX, 5968 FW_STAT_RX_PORT_PPP2_IX, 5969 FW_STAT_RX_PORT_PPP3_IX, 5970 FW_STAT_RX_PORT_PPP4_IX, 5971 FW_STAT_RX_PORT_PPP5_IX, 5972 FW_STAT_RX_PORT_PPP6_IX, 5973 FW_STAT_RX_PORT_PPP7_IX, 5974 FW_STAT_RX_PORT_LESS_64B_IX 5975 }; 5976 5977 struct fw_port_stats_cmd { 5978 __be32 op_to_portid; 5979 __be32 retval_len16; 5980 union fw_port_stats { 5981 struct fw_port_stats_ctl { 5982 __u8 nstats_bg_bm; 5983 __u8 tx_ix; 5984 __be16 r6; 5985 __be32 r7; 5986 __be64 stat0; 5987 __be64 stat1; 5988 __be64 stat2; 5989 __be64 stat3; 5990 __be64 stat4; 5991 __be64 stat5; 5992 } ctl; 5993 struct fw_port_stats_all { 5994 __be64 tx_bytes; 5995 __be64 tx_frames; 5996 __be64 tx_bcast; 5997 __be64 tx_mcast; 5998 __be64 tx_ucast; 5999 __be64 tx_error; 6000 __be64 tx_64b; 6001 __be64 tx_65b_127b; 6002 __be64 tx_128b_255b; 6003 __be64 tx_256b_511b; 6004 __be64 tx_512b_1023b; 6005 __be64 tx_1024b_1518b; 6006 __be64 tx_1519b_max; 6007 __be64 tx_drop; 6008 __be64 tx_pause; 6009 __be64 tx_ppp0; 6010 __be64 tx_ppp1; 6011 __be64 tx_ppp2; 6012 __be64 tx_ppp3; 6013 __be64 tx_ppp4; 6014 __be64 tx_ppp5; 6015 __be64 tx_ppp6; 6016 __be64 tx_ppp7; 6017 __be64 rx_bytes; 6018 __be64 rx_frames; 6019 __be64 rx_bcast; 6020 __be64 rx_mcast; 6021 __be64 rx_ucast; 6022 __be64 rx_mtu_error; 6023 __be64 rx_mtu_crc_error; 6024 __be64 rx_crc_error; 6025 __be64 rx_len_error; 6026 __be64 rx_sym_error; 6027 __be64 rx_64b; 6028 __be64 rx_65b_127b; 6029 __be64 rx_128b_255b; 6030 __be64 rx_256b_511b; 6031 __be64 rx_512b_1023b; 6032 __be64 rx_1024b_1518b; 6033 __be64 rx_1519b_max; 6034 __be64 rx_pause; 6035 __be64 rx_ppp0; 6036 __be64 rx_ppp1; 6037 __be64 rx_ppp2; 6038 __be64 rx_ppp3; 6039 __be64 rx_ppp4; 6040 __be64 rx_ppp5; 6041 __be64 rx_ppp6; 6042 __be64 rx_ppp7; 6043 __be64 rx_less_64b; 6044 __be64 rx_bg_drop; 6045 __be64 rx_bg_trunc; 6046 } all; 6047 } u; 6048 }; 6049 6050 #define S_FW_PORT_STATS_CMD_NSTATS 4 6051 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 6052 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 6053 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 6054 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 6055 6056 #define S_FW_PORT_STATS_CMD_BG_BM 0 6057 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 6058 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 6059 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 6060 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 6061 6062 #define S_FW_PORT_STATS_CMD_TX 7 6063 #define M_FW_PORT_STATS_CMD_TX 0x1 6064 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 6065 #define G_FW_PORT_STATS_CMD_TX(x) \ 6066 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 6067 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 6068 6069 #define S_FW_PORT_STATS_CMD_IX 0 6070 #define M_FW_PORT_STATS_CMD_IX 0x3f 6071 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 6072 #define G_FW_PORT_STATS_CMD_IX(x) \ 6073 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 6074 6075 /* port loopback stats */ 6076 #define FW_NUM_LB_STATS 14 6077 enum fw_port_lb_stats_index { 6078 FW_STAT_LB_PORT_BYTES_IX, 6079 FW_STAT_LB_PORT_FRAMES_IX, 6080 FW_STAT_LB_PORT_BCAST_IX, 6081 FW_STAT_LB_PORT_MCAST_IX, 6082 FW_STAT_LB_PORT_UCAST_IX, 6083 FW_STAT_LB_PORT_ERROR_IX, 6084 FW_STAT_LB_PORT_64B_IX, 6085 FW_STAT_LB_PORT_65B_127B_IX, 6086 FW_STAT_LB_PORT_128B_255B_IX, 6087 FW_STAT_LB_PORT_256B_511B_IX, 6088 FW_STAT_LB_PORT_512B_1023B_IX, 6089 FW_STAT_LB_PORT_1024B_1518B_IX, 6090 FW_STAT_LB_PORT_1519B_MAX_IX, 6091 FW_STAT_LB_PORT_DROP_FRAMES_IX 6092 }; 6093 6094 struct fw_port_lb_stats_cmd { 6095 __be32 op_to_lbport; 6096 __be32 retval_len16; 6097 union fw_port_lb_stats { 6098 struct fw_port_lb_stats_ctl { 6099 __u8 nstats_bg_bm; 6100 __u8 ix_pkd; 6101 __be16 r6; 6102 __be32 r7; 6103 __be64 stat0; 6104 __be64 stat1; 6105 __be64 stat2; 6106 __be64 stat3; 6107 __be64 stat4; 6108 __be64 stat5; 6109 } ctl; 6110 struct fw_port_lb_stats_all { 6111 __be64 tx_bytes; 6112 __be64 tx_frames; 6113 __be64 tx_bcast; 6114 __be64 tx_mcast; 6115 __be64 tx_ucast; 6116 __be64 tx_error; 6117 __be64 tx_64b; 6118 __be64 tx_65b_127b; 6119 __be64 tx_128b_255b; 6120 __be64 tx_256b_511b; 6121 __be64 tx_512b_1023b; 6122 __be64 tx_1024b_1518b; 6123 __be64 tx_1519b_max; 6124 __be64 rx_lb_drop; 6125 __be64 rx_lb_trunc; 6126 } all; 6127 } u; 6128 }; 6129 6130 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 6131 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 6132 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6133 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 6134 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6135 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 6136 6137 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 6138 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 6139 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6140 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 6141 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6142 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 6143 6144 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 6145 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 6146 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 6147 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 6148 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 6149 6150 #define S_FW_PORT_LB_STATS_CMD_IX 0 6151 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 6152 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 6153 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 6154 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 6155 6156 /* Trace related defines */ 6157 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 6158 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 6159 6160 struct fw_port_trace_cmd { 6161 __be32 op_to_portid; 6162 __be32 retval_len16; 6163 __be16 traceen_to_pciech; 6164 __be16 qnum; 6165 __be32 r5; 6166 }; 6167 6168 #define S_FW_PORT_TRACE_CMD_PORTID 0 6169 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 6170 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 6171 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 6172 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 6173 6174 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 6175 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 6176 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 6177 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 6178 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 6179 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 6180 6181 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 6182 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 6183 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 6184 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 6185 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 6186 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 6187 6188 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 6189 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 6190 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 6191 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 6192 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 6193 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 6194 6195 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 6196 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 6197 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6198 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6199 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6200 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 6201 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6202 6203 #define S_FW_PORT_TRACE_CMD_PCIECH 6 6204 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 6205 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 6206 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 6207 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 6208 6209 struct fw_port_trace_mmap_cmd { 6210 __be32 op_to_portid; 6211 __be32 retval_len16; 6212 __be32 fid_to_skipoffset; 6213 __be32 minpktsize_capturemax; 6214 __u8 map[224]; 6215 }; 6216 6217 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 6218 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 6219 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6220 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 6221 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6222 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 6223 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 6224 6225 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 6226 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 6227 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 6228 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 6229 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 6230 6231 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 6232 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 6233 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6234 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6235 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6236 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 6237 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6238 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 6239 6240 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 6241 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 6242 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6243 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6244 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6245 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 6246 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6247 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN \ 6248 V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 6249 6250 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 6251 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 6252 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6253 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6254 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6255 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 6256 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6257 6258 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 6259 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 6260 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6261 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6262 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6263 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 6264 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6265 6266 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 6267 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 6268 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6269 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6270 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6271 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 6272 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6273 6274 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 6275 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 6276 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6277 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6278 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6279 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 6280 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6281 6282 struct fw_rss_ind_tbl_cmd { 6283 __be32 op_to_viid; 6284 __be32 retval_len16; 6285 __be16 niqid; 6286 __be16 startidx; 6287 __be32 r3; 6288 __be32 iq0_to_iq2; 6289 __be32 iq3_to_iq5; 6290 __be32 iq6_to_iq8; 6291 __be32 iq9_to_iq11; 6292 __be32 iq12_to_iq14; 6293 __be32 iq15_to_iq17; 6294 __be32 iq18_to_iq20; 6295 __be32 iq21_to_iq23; 6296 __be32 iq24_to_iq26; 6297 __be32 iq27_to_iq29; 6298 __be32 iq30_iq31; 6299 __be32 r15_lo; 6300 }; 6301 6302 #define S_FW_RSS_IND_TBL_CMD_VIID 0 6303 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 6304 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 6305 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 6306 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 6307 6308 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 6309 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 6310 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 6311 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 6312 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 6313 6314 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 6315 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 6316 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 6317 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 6318 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 6319 6320 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 6321 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 6322 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 6323 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 6324 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 6325 6326 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 6327 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 6328 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 6329 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 6330 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 6331 6332 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 6333 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 6334 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 6335 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 6336 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 6337 6338 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 6339 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 6340 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 6341 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 6342 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 6343 6344 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 6345 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 6346 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 6347 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 6348 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 6349 6350 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 6351 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 6352 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 6353 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 6354 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 6355 6356 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 6357 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 6358 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 6359 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 6360 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 6361 6362 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 6363 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 6364 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 6365 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 6366 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 6367 6368 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 6369 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 6370 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 6371 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 6372 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 6373 6374 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 6375 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 6376 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 6377 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 6378 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 6379 6380 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 6381 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 6382 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 6383 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 6384 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 6385 6386 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 6387 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 6388 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 6389 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 6390 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 6391 6392 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 6393 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 6394 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 6395 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 6396 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 6397 6398 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 6399 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 6400 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 6401 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 6402 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 6403 6404 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 6405 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 6406 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 6407 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 6408 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 6409 6410 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 6411 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 6412 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 6413 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 6414 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 6415 6416 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 6417 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 6418 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 6419 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 6420 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 6421 6422 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 6423 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 6424 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 6425 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 6426 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 6427 6428 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 6429 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 6430 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 6431 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 6432 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 6433 6434 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 6435 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 6436 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 6437 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 6438 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 6439 6440 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 6441 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 6442 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 6443 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 6444 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 6445 6446 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 6447 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 6448 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 6449 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 6450 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 6451 6452 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 6453 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 6454 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 6455 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 6456 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 6457 6458 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 6459 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 6460 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 6461 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 6462 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 6463 6464 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 6465 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 6466 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 6467 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 6468 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 6469 6470 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 6471 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 6472 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 6473 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 6474 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 6475 6476 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 6477 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 6478 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 6479 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 6480 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 6481 6482 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 6483 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 6484 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 6485 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 6486 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 6487 6488 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 6489 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 6490 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 6491 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 6492 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 6493 6494 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 6495 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 6496 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 6497 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 6498 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 6499 6500 struct fw_rss_glb_config_cmd { 6501 __be32 op_to_write; 6502 __be32 retval_len16; 6503 union fw_rss_glb_config { 6504 struct fw_rss_glb_config_manual { 6505 __be32 mode_pkd; 6506 __be32 r3; 6507 __be64 r4; 6508 __be64 r5; 6509 } manual; 6510 struct fw_rss_glb_config_basicvirtual { 6511 __be32 mode_pkd; 6512 __be32 synmapen_to_hashtoeplitz; 6513 __be64 r8; 6514 __be64 r9; 6515 } basicvirtual; 6516 } u; 6517 }; 6518 6519 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 6520 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 6521 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 6522 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 6523 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 6524 6525 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 6526 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 6527 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 6528 6529 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 6530 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 6531 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6532 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6533 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6534 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 6535 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6536 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN \ 6537 V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 6538 6539 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 6540 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 6541 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6542 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6543 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6544 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 6545 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6546 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 6547 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 6548 6549 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 6550 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 6551 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6552 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6553 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6554 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 6555 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6556 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 6557 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 6558 6559 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 6560 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 6561 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6562 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6563 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6564 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 6565 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6566 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 6567 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 6568 6569 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 6570 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 6571 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6572 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6573 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6574 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 6575 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6576 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 6577 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 6578 6579 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 6580 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 6581 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6582 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6583 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6584 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 6585 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6586 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN \ 6587 V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 6588 6589 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 6590 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 6591 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6592 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6593 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6594 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 6595 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6596 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN \ 6597 V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 6598 6599 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 6600 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 6601 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6602 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6603 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6604 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 6605 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6606 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 6607 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 6608 6609 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 6610 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 6611 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6612 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6613 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6614 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 6615 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6616 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 6617 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 6618 6619 struct fw_rss_vi_config_cmd { 6620 __be32 op_to_viid; 6621 __be32 retval_len16; 6622 union fw_rss_vi_config { 6623 struct fw_rss_vi_config_manual { 6624 __be64 r3; 6625 __be64 r4; 6626 __be64 r5; 6627 } manual; 6628 struct fw_rss_vi_config_basicvirtual { 6629 __be32 r6; 6630 __be32 defaultq_to_udpen; 6631 __be64 r9; 6632 __be64 r10; 6633 } basicvirtual; 6634 } u; 6635 }; 6636 6637 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 6638 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 6639 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 6640 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 6641 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 6642 6643 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 6644 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 6645 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6646 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6647 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6648 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 6649 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6650 6651 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 6652 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 6653 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6654 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6655 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6656 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 6657 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6658 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 6659 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 6660 6661 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 6662 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 6663 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6664 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6665 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6666 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 6667 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6668 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 6669 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 6670 6671 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 6672 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 6673 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6674 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6675 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6676 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 6677 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6678 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 6679 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 6680 6681 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 6682 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 6683 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6684 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6685 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6686 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 6687 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6688 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 6689 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 6690 6691 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 6692 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 6693 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 6694 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 6695 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 6696 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 6697 6698 enum fw_sched_sc { 6699 FW_SCHED_SC_CONFIG = 0, 6700 FW_SCHED_SC_PARAMS = 1, 6701 }; 6702 6703 enum fw_sched_type { 6704 FW_SCHED_TYPE_PKTSCHED = 0, 6705 FW_SCHED_TYPE_STREAMSCHED = 1, 6706 }; 6707 6708 enum fw_sched_params_level { 6709 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 6710 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 6711 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 6712 }; 6713 6714 enum fw_sched_params_mode { 6715 FW_SCHED_PARAMS_MODE_CLASS = 0, 6716 FW_SCHED_PARAMS_MODE_FLOW = 1, 6717 }; 6718 6719 enum fw_sched_params_unit { 6720 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 6721 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 6722 }; 6723 6724 enum fw_sched_params_rate { 6725 FW_SCHED_PARAMS_RATE_REL = 0, 6726 FW_SCHED_PARAMS_RATE_ABS = 1, 6727 }; 6728 6729 struct fw_sched_cmd { 6730 __be32 op_to_write; 6731 __be32 retval_len16; 6732 union fw_sched { 6733 struct fw_sched_config { 6734 __u8 sc; 6735 __u8 type; 6736 __u8 minmaxen; 6737 __u8 r3[5]; 6738 } config; 6739 struct fw_sched_params { 6740 __u8 sc; 6741 __u8 type; 6742 __u8 level; 6743 __u8 mode; 6744 __u8 unit; 6745 __u8 rate; 6746 __u8 ch; 6747 __u8 cl; 6748 __be32 min; 6749 __be32 max; 6750 __be16 weight; 6751 __be16 pktsize; 6752 __be16 burstsize; 6753 __be16 r4; 6754 } params; 6755 } u; 6756 }; 6757 6758 /* 6759 * length of the formatting string 6760 */ 6761 #define FW_DEVLOG_FMT_LEN 192 6762 6763 /* 6764 * maximum number of the formatting string parameters 6765 */ 6766 #define FW_DEVLOG_FMT_PARAMS_NUM 8 6767 6768 /* 6769 * priority levels 6770 */ 6771 enum fw_devlog_level { 6772 FW_DEVLOG_LEVEL_EMERG = 0x0, 6773 FW_DEVLOG_LEVEL_CRIT = 0x1, 6774 FW_DEVLOG_LEVEL_ERR = 0x2, 6775 FW_DEVLOG_LEVEL_NOTICE = 0x3, 6776 FW_DEVLOG_LEVEL_INFO = 0x4, 6777 FW_DEVLOG_LEVEL_DEBUG = 0x5, 6778 FW_DEVLOG_LEVEL_MAX = 0x5, 6779 }; 6780 6781 /* 6782 * facilities that may send a log message 6783 */ 6784 enum fw_devlog_facility { 6785 FW_DEVLOG_FACILITY_CORE = 0x00, 6786 FW_DEVLOG_FACILITY_SCHED = 0x02, 6787 FW_DEVLOG_FACILITY_TIMER = 0x04, 6788 FW_DEVLOG_FACILITY_RES = 0x06, 6789 FW_DEVLOG_FACILITY_HW = 0x08, 6790 FW_DEVLOG_FACILITY_FLR = 0x10, 6791 FW_DEVLOG_FACILITY_DMAQ = 0x12, 6792 FW_DEVLOG_FACILITY_PHY = 0x14, 6793 FW_DEVLOG_FACILITY_MAC = 0x16, 6794 FW_DEVLOG_FACILITY_PORT = 0x18, 6795 FW_DEVLOG_FACILITY_VI = 0x1A, 6796 FW_DEVLOG_FACILITY_FILTER = 0x1C, 6797 FW_DEVLOG_FACILITY_ACL = 0x1E, 6798 FW_DEVLOG_FACILITY_TM = 0x20, 6799 FW_DEVLOG_FACILITY_QFC = 0x22, 6800 FW_DEVLOG_FACILITY_DCB = 0x24, 6801 FW_DEVLOG_FACILITY_ETH = 0x26, 6802 FW_DEVLOG_FACILITY_OFLD = 0x28, 6803 FW_DEVLOG_FACILITY_RI = 0x2A, 6804 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 6805 FW_DEVLOG_FACILITY_FCOE = 0x2E, 6806 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 6807 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 6808 FW_DEVLOG_FACILITY_MAX = 0x32, 6809 }; 6810 6811 /* 6812 * log message format 6813 */ 6814 struct fw_devlog_e { 6815 __be64 timestamp; 6816 __be32 seqno; 6817 __be16 reserved1; 6818 __u8 level; 6819 __u8 facility; 6820 __u8 fmt[FW_DEVLOG_FMT_LEN]; 6821 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 6822 __be32 reserved3[4]; 6823 }; 6824 6825 struct fw_devlog_cmd { 6826 __be32 op_to_write; 6827 __be32 retval_len16; 6828 __u8 level; 6829 __u8 r2[7]; 6830 __be32 memtype_devlog_memaddr16_devlog; 6831 __be32 memsize_devlog; 6832 __be32 r3[2]; 6833 }; 6834 6835 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 6836 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 6837 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 6838 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 6839 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 6840 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 6841 6842 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 6843 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 6844 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 6845 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 6846 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 6847 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 6848 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 6849 6850 enum fw_watchdog_actions { 6851 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 6852 FW_WATCHDOG_ACTION_FLR = 1, 6853 FW_WATCHDOG_ACTION_BYPASS = 2, 6854 FW_WATCHDOG_ACTION_TMPCHK = 3, 6855 6856 FW_WATCHDOG_ACTION_MAX = 4, 6857 }; 6858 6859 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 6860 6861 struct fw_watchdog_cmd { 6862 __be32 op_to_vfn; 6863 __be32 retval_len16; 6864 __be32 timeout; 6865 __be32 action; 6866 }; 6867 6868 #define S_FW_WATCHDOG_CMD_PFN 8 6869 #define M_FW_WATCHDOG_CMD_PFN 0x7 6870 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 6871 #define G_FW_WATCHDOG_CMD_PFN(x) \ 6872 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 6873 6874 #define S_FW_WATCHDOG_CMD_VFN 0 6875 #define M_FW_WATCHDOG_CMD_VFN 0xff 6876 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 6877 #define G_FW_WATCHDOG_CMD_VFN(x) \ 6878 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 6879 6880 struct fw_clip_cmd { 6881 __be32 op_to_write; 6882 __be32 alloc_to_len16; 6883 __be64 ip_hi; 6884 __be64 ip_lo; 6885 __be32 r4[2]; 6886 }; 6887 6888 #define S_FW_CLIP_CMD_ALLOC 31 6889 #define M_FW_CLIP_CMD_ALLOC 0x1 6890 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 6891 #define G_FW_CLIP_CMD_ALLOC(x) \ 6892 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 6893 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 6894 6895 #define S_FW_CLIP_CMD_FREE 30 6896 #define M_FW_CLIP_CMD_FREE 0x1 6897 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 6898 #define G_FW_CLIP_CMD_FREE(x) \ 6899 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 6900 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 6901 6902 /****************************************************************************** 6903 * F O i S C S I C O M M A N D s 6904 **************************************/ 6905 6906 #define FW_CHNET_IFACE_ADDR_MAX 3 6907 6908 enum fw_chnet_iface_cmd_subop { 6909 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 6910 6911 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 6912 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 6913 6914 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 6915 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 6916 6917 FW_CHNET_IFACE_CMD_SUBOP_MAX, 6918 }; 6919 6920 struct fw_chnet_iface_cmd { 6921 __be32 op_to_portid; 6922 __be32 retval_len16; 6923 __u8 subop; 6924 __u8 r2[3]; 6925 __be32 ifid_ifstate; 6926 __be16 mtu; 6927 __be16 vlanid; 6928 __be32 r3; 6929 __be16 r4; 6930 __u8 mac[6]; 6931 }; 6932 6933 #define S_FW_CHNET_IFACE_CMD_PORTID 0 6934 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 6935 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 6936 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 6937 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 6938 6939 #define S_FW_CHNET_IFACE_CMD_IFID 8 6940 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 6941 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 6942 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 6943 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 6944 6945 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 6946 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 6947 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 6948 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 6949 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 6950 6951 /****************************************************************************** 6952 * F O F C O E C O M M A N D s 6953 ************************************/ 6954 6955 struct fw_fcoe_res_info_cmd { 6956 __be32 op_to_read; 6957 __be32 retval_len16; 6958 __be16 e_d_tov; 6959 __be16 r_a_tov_seq; 6960 __be16 r_a_tov_els; 6961 __be16 r_r_tov; 6962 __be32 max_xchgs; 6963 __be32 max_ssns; 6964 __be32 used_xchgs; 6965 __be32 used_ssns; 6966 __be32 max_fcfs; 6967 __be32 max_vnps; 6968 __be32 used_fcfs; 6969 __be32 used_vnps; 6970 }; 6971 6972 struct fw_fcoe_link_cmd { 6973 __be32 op_to_portid; 6974 __be32 retval_len16; 6975 __be32 sub_opcode_fcfi; 6976 __u8 r3; 6977 __u8 lstatus; 6978 __be16 flags; 6979 __u8 r4; 6980 __u8 set_vlan; 6981 __be16 vlan_id; 6982 __be32 vnpi_pkd; 6983 __be16 r6; 6984 __u8 phy_mac[6]; 6985 __u8 vnport_wwnn[8]; 6986 __u8 vnport_wwpn[8]; 6987 }; 6988 6989 #define S_FW_FCOE_LINK_CMD_PORTID 0 6990 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 6991 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 6992 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 6993 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 6994 6995 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 6996 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 6997 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 6998 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 6999 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 7000 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 7001 7002 #define S_FW_FCOE_LINK_CMD_FCFI 0 7003 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 7004 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 7005 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 7006 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 7007 7008 #define S_FW_FCOE_LINK_CMD_VNPI 0 7009 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 7010 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 7011 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 7012 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 7013 7014 struct fw_fcoe_vnp_cmd { 7015 __be32 op_to_fcfi; 7016 __be32 alloc_to_len16; 7017 __be32 gen_wwn_to_vnpi; 7018 __be32 vf_id; 7019 __be16 iqid; 7020 __u8 vnport_mac[6]; 7021 __u8 vnport_wwnn[8]; 7022 __u8 vnport_wwpn[8]; 7023 __u8 cmn_srv_parms[16]; 7024 __u8 clsp_word_0_1[8]; 7025 }; 7026 7027 #define S_FW_FCOE_VNP_CMD_FCFI 0 7028 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 7029 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 7030 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 7031 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 7032 7033 #define S_FW_FCOE_VNP_CMD_ALLOC 31 7034 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 7035 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 7036 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 7037 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 7038 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 7039 7040 #define S_FW_FCOE_VNP_CMD_FREE 30 7041 #define M_FW_FCOE_VNP_CMD_FREE 0x1 7042 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 7043 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 7044 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 7045 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 7046 7047 #define S_FW_FCOE_VNP_CMD_MODIFY 29 7048 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 7049 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 7050 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 7051 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 7052 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 7053 7054 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 7055 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 7056 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 7057 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 7058 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 7059 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 7060 7061 #define S_FW_FCOE_VNP_CMD_PERSIST 21 7062 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 7063 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 7064 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 7065 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 7066 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 7067 7068 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 7069 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 7070 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 7071 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 7072 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 7073 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 7074 7075 #define S_FW_FCOE_VNP_CMD_VNPI 0 7076 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 7077 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 7078 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 7079 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 7080 7081 struct fw_fcoe_sparams_cmd { 7082 __be32 op_to_portid; 7083 __be32 retval_len16; 7084 __u8 r3[7]; 7085 __u8 cos; 7086 __u8 lport_wwnn[8]; 7087 __u8 lport_wwpn[8]; 7088 __u8 cmn_srv_parms[16]; 7089 __u8 cls_srv_parms[16]; 7090 }; 7091 7092 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 7093 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 7094 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 7095 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 7096 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 7097 7098 struct fw_fcoe_stats_cmd { 7099 __be32 op_to_flowid; 7100 __be32 free_to_len16; 7101 union fw_fcoe_stats { 7102 struct fw_fcoe_stats_ctl { 7103 __u8 nstats_port; 7104 __u8 port_valid_ix; 7105 __be16 r6; 7106 __be32 r7; 7107 __be64 stat0; 7108 __be64 stat1; 7109 __be64 stat2; 7110 __be64 stat3; 7111 __be64 stat4; 7112 __be64 stat5; 7113 } ctl; 7114 struct fw_fcoe_port_stats { 7115 __be64 tx_bcast_bytes; 7116 __be64 tx_bcast_frames; 7117 __be64 tx_mcast_bytes; 7118 __be64 tx_mcast_frames; 7119 __be64 tx_ucast_bytes; 7120 __be64 tx_ucast_frames; 7121 __be64 tx_drop_frames; 7122 __be64 tx_offload_bytes; 7123 __be64 tx_offload_frames; 7124 __be64 rx_bcast_bytes; 7125 __be64 rx_bcast_frames; 7126 __be64 rx_mcast_bytes; 7127 __be64 rx_mcast_frames; 7128 __be64 rx_ucast_bytes; 7129 __be64 rx_ucast_frames; 7130 __be64 rx_err_frames; 7131 } port_stats; 7132 struct fw_fcoe_fcf_stats { 7133 __be32 fip_tx_bytes; 7134 __be32 fip_tx_fr; 7135 __be64 fcf_ka; 7136 __be64 mcast_adv_rcvd; 7137 __be16 ucast_adv_rcvd; 7138 __be16 sol_sent; 7139 __be16 vlan_req; 7140 __be16 vlan_rpl; 7141 __be16 clr_vlink; 7142 __be16 link_down; 7143 __be16 link_up; 7144 __be16 logo; 7145 __be16 flogi_req; 7146 __be16 flogi_rpl; 7147 __be16 fdisc_req; 7148 __be16 fdisc_rpl; 7149 __be16 fka_prd_chg; 7150 __be16 fc_map_chg; 7151 __be16 vfid_chg; 7152 __u8 no_fka_req; 7153 __u8 no_vnp; 7154 } fcf_stats; 7155 struct fw_fcoe_pcb_stats { 7156 __be64 tx_bytes; 7157 __be64 tx_frames; 7158 __be64 rx_bytes; 7159 __be64 rx_frames; 7160 __be32 vnp_ka; 7161 __be32 unsol_els_rcvd; 7162 __be64 unsol_cmd_rcvd; 7163 __be16 implicit_logo; 7164 __be16 flogi_inv_sparm; 7165 __be16 fdisc_inv_sparm; 7166 __be16 flogi_rjt; 7167 __be16 fdisc_rjt; 7168 __be16 no_ssn; 7169 __be16 mac_flt_fail; 7170 __be16 inv_fr_rcvd; 7171 } pcb_stats; 7172 struct fw_fcoe_scb_stats { 7173 __be64 tx_bytes; 7174 __be64 tx_frames; 7175 __be64 rx_bytes; 7176 __be64 rx_frames; 7177 __be32 host_abrt_req; 7178 __be32 adap_auto_abrt; 7179 __be32 adap_abrt_rsp; 7180 __be32 host_ios_req; 7181 __be16 ssn_offl_ios; 7182 __be16 ssn_not_rdy_ios; 7183 __u8 rx_data_ddp_err; 7184 __u8 ddp_flt_set_err; 7185 __be16 rx_data_fr_err; 7186 __u8 bad_st_abrt_req; 7187 __u8 no_io_abrt_req; 7188 __u8 abort_tmo; 7189 __u8 abort_tmo_2; 7190 __be32 abort_req; 7191 __u8 no_ppod_res_tmo; 7192 __u8 bp_tmo; 7193 __u8 adap_auto_cls; 7194 __u8 no_io_cls_req; 7195 __be32 host_cls_req; 7196 __be64 unsol_cmd_rcvd; 7197 __be32 plogi_req_rcvd; 7198 __be32 prli_req_rcvd; 7199 __be16 logo_req_rcvd; 7200 __be16 prlo_req_rcvd; 7201 __be16 plogi_rjt_rcvd; 7202 __be16 prli_rjt_rcvd; 7203 __be32 adisc_req_rcvd; 7204 __be32 rscn_rcvd; 7205 __be32 rrq_req_rcvd; 7206 __be32 unsol_els_rcvd; 7207 __u8 adisc_rjt_rcvd; 7208 __u8 scr_rjt; 7209 __u8 ct_rjt; 7210 __u8 inval_bls_rcvd; 7211 __be32 ba_rjt_rcvd; 7212 } scb_stats; 7213 } u; 7214 }; 7215 7216 #define S_FW_FCOE_STATS_CMD_FLOWID 0 7217 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 7218 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 7219 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 7220 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 7221 7222 #define S_FW_FCOE_STATS_CMD_FREE 30 7223 #define M_FW_FCOE_STATS_CMD_FREE 0x1 7224 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 7225 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 7226 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 7227 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 7228 7229 #define S_FW_FCOE_STATS_CMD_NSTATS 4 7230 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 7231 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 7232 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 7233 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 7234 7235 #define S_FW_FCOE_STATS_CMD_PORT 0 7236 #define M_FW_FCOE_STATS_CMD_PORT 0x3 7237 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 7238 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 7239 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 7240 7241 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 7242 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 7243 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7244 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 7245 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7246 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 7247 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 7248 7249 #define S_FW_FCOE_STATS_CMD_IX 0 7250 #define M_FW_FCOE_STATS_CMD_IX 0x3f 7251 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 7252 #define G_FW_FCOE_STATS_CMD_IX(x) \ 7253 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 7254 7255 struct fw_fcoe_fcf_cmd { 7256 __be32 op_to_fcfi; 7257 __be32 retval_len16; 7258 __be16 priority_pkd; 7259 __u8 mac[6]; 7260 __u8 name_id[8]; 7261 __u8 fabric[8]; 7262 __be16 vf_id; 7263 __be16 max_fcoe_size; 7264 __u8 vlan_id; 7265 __u8 fc_map[3]; 7266 __be32 fka_adv; 7267 __be32 r6; 7268 __u8 r7_hi; 7269 __u8 fpma_to_portid; 7270 __u8 spma_mac[6]; 7271 __be64 r8; 7272 }; 7273 7274 #define S_FW_FCOE_FCF_CMD_FCFI 0 7275 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 7276 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 7277 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 7278 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 7279 7280 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 7281 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 7282 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 7283 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 7284 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 7285 7286 #define S_FW_FCOE_FCF_CMD_FPMA 6 7287 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 7288 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 7289 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 7290 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 7291 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 7292 7293 #define S_FW_FCOE_FCF_CMD_SPMA 5 7294 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 7295 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 7296 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 7297 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 7298 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 7299 7300 #define S_FW_FCOE_FCF_CMD_LOGIN 4 7301 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 7302 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 7303 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 7304 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 7305 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 7306 7307 #define S_FW_FCOE_FCF_CMD_PORTID 0 7308 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 7309 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 7310 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 7311 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 7312 7313 /****************************************************************************** 7314 * E R R O R a n d D E B U G C O M M A N D s 7315 ******************************************************/ 7316 7317 enum fw_error_type { 7318 FW_ERROR_TYPE_EXCEPTION = 0x0, 7319 FW_ERROR_TYPE_HWMODULE = 0x1, 7320 FW_ERROR_TYPE_WR = 0x2, 7321 FW_ERROR_TYPE_ACL = 0x3, 7322 }; 7323 7324 struct fw_error_cmd { 7325 __be32 op_to_type; 7326 __be32 len16_pkd; 7327 union fw_error { 7328 struct fw_error_exception { 7329 __be32 info[6]; 7330 } exception; 7331 struct fw_error_hwmodule { 7332 __be32 regaddr; 7333 __be32 regval; 7334 } hwmodule; 7335 struct fw_error_wr { 7336 __be16 cidx; 7337 __be16 pfn_vfn; 7338 __be32 eqid; 7339 __u8 wrhdr[16]; 7340 } wr; 7341 struct fw_error_acl { 7342 __be16 cidx; 7343 __be16 pfn_vfn; 7344 __be32 eqid; 7345 __be16 mv_pkd; 7346 __u8 val[6]; 7347 __be64 r4; 7348 } acl; 7349 } u; 7350 }; 7351 7352 #define S_FW_ERROR_CMD_FATAL 4 7353 #define M_FW_ERROR_CMD_FATAL 0x1 7354 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 7355 #define G_FW_ERROR_CMD_FATAL(x) \ 7356 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 7357 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 7358 7359 #define S_FW_ERROR_CMD_TYPE 0 7360 #define M_FW_ERROR_CMD_TYPE 0xf 7361 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 7362 #define G_FW_ERROR_CMD_TYPE(x) \ 7363 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 7364 7365 #define S_FW_ERROR_CMD_PFN 8 7366 #define M_FW_ERROR_CMD_PFN 0x7 7367 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7368 #define G_FW_ERROR_CMD_PFN(x) \ 7369 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7370 7371 #define S_FW_ERROR_CMD_VFN 0 7372 #define M_FW_ERROR_CMD_VFN 0xff 7373 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7374 #define G_FW_ERROR_CMD_VFN(x) \ 7375 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7376 7377 #define S_FW_ERROR_CMD_PFN 8 7378 #define M_FW_ERROR_CMD_PFN 0x7 7379 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7380 #define G_FW_ERROR_CMD_PFN(x) \ 7381 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7382 7383 #define S_FW_ERROR_CMD_VFN 0 7384 #define M_FW_ERROR_CMD_VFN 0xff 7385 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7386 #define G_FW_ERROR_CMD_VFN(x) \ 7387 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7388 7389 #define S_FW_ERROR_CMD_MV 15 7390 #define M_FW_ERROR_CMD_MV 0x1 7391 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 7392 #define G_FW_ERROR_CMD_MV(x) \ 7393 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 7394 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 7395 7396 struct fw_debug_cmd { 7397 __be32 op_type; 7398 __be32 len16_pkd; 7399 union fw_debug { 7400 struct fw_debug_assert { 7401 __be32 fcid; 7402 __be32 line; 7403 __be32 x; 7404 __be32 y; 7405 __u8 filename_0_7[8]; 7406 __u8 filename_8_15[8]; 7407 __be64 r3; 7408 } assert; 7409 struct fw_debug_prt { 7410 __be16 dprtstridx; 7411 __be16 r3[3]; 7412 __be32 dprtstrparam0; 7413 __be32 dprtstrparam1; 7414 __be32 dprtstrparam2; 7415 __be32 dprtstrparam3; 7416 } prt; 7417 } u; 7418 }; 7419 7420 #define S_FW_DEBUG_CMD_TYPE 0 7421 #define M_FW_DEBUG_CMD_TYPE 0xff 7422 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 7423 #define G_FW_DEBUG_CMD_TYPE(x) \ 7424 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 7425 7426 /****************************************************************************** 7427 * P C I E F W R E G I S T E R 7428 **************************************/ 7429 7430 enum pcie_fw_eval { 7431 PCIE_FW_EVAL_CRASH = 0, 7432 PCIE_FW_EVAL_PREP = 1, 7433 PCIE_FW_EVAL_CONF = 2, 7434 PCIE_FW_EVAL_INIT = 3, 7435 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 7436 PCIE_FW_EVAL_OVERHEAT = 5, 7437 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 7438 }; 7439 7440 /** 7441 * Register definitions for the PCIE_FW register which the firmware uses 7442 * to retain status across RESETs. This register should be considered 7443 * as a READ-ONLY register for Host Software and only to be used to 7444 * track firmware initialization/error state, etc. 7445 */ 7446 #define S_PCIE_FW_ERR 31 7447 #define M_PCIE_FW_ERR 0x1 7448 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 7449 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 7450 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 7451 7452 #define S_PCIE_FW_INIT 30 7453 #define M_PCIE_FW_INIT 0x1 7454 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 7455 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 7456 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 7457 7458 #define S_PCIE_FW_HALT 29 7459 #define M_PCIE_FW_HALT 0x1 7460 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 7461 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 7462 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 7463 7464 #define S_PCIE_FW_EVAL 24 7465 #define M_PCIE_FW_EVAL 0x7 7466 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 7467 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 7468 7469 #define S_PCIE_FW_STAGE 21 7470 #define M_PCIE_FW_STAGE 0x7 7471 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 7472 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 7473 7474 #define S_PCIE_FW_ASYNCNOT_VLD 20 7475 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 7476 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 7477 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 7478 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 7479 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 7480 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 7481 7482 #define S_PCIE_FW_ASYNCNOTINT 19 7483 #define M_PCIE_FW_ASYNCNOTINT 0x1 7484 #define V_PCIE_FW_ASYNCNOTINT(x) \ 7485 ((x) << S_PCIE_FW_ASYNCNOTINT) 7486 #define G_PCIE_FW_ASYNCNOTINT(x) \ 7487 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 7488 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 7489 7490 #define S_PCIE_FW_ASYNCNOT 16 7491 #define M_PCIE_FW_ASYNCNOT 0x7 7492 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 7493 #define G_PCIE_FW_ASYNCNOT(x) \ 7494 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 7495 7496 #define S_PCIE_FW_MASTER_VLD 15 7497 #define M_PCIE_FW_MASTER_VLD 0x1 7498 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 7499 #define G_PCIE_FW_MASTER_VLD(x) \ 7500 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 7501 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 7502 7503 #define S_PCIE_FW_MASTER 12 7504 #define M_PCIE_FW_MASTER 0x7 7505 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 7506 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 7507 7508 #define S_PCIE_FW_RESET_VLD 11 7509 #define M_PCIE_FW_RESET_VLD 0x1 7510 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 7511 #define G_PCIE_FW_RESET_VLD(x) \ 7512 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 7513 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 7514 7515 #define S_PCIE_FW_RESET 8 7516 #define M_PCIE_FW_RESET 0x7 7517 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 7518 #define G_PCIE_FW_RESET(x) \ 7519 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 7520 7521 #define S_PCIE_FW_REGISTERED 0 7522 #define M_PCIE_FW_REGISTERED 0xff 7523 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 7524 #define G_PCIE_FW_REGISTERED(x) \ 7525 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 7526 7527 7528 /****************************************************************************** 7529 * B I N A R Y H E A D E R F O R M A T 7530 **********************************************/ 7531 7532 /* 7533 * firmware binary header format 7534 */ 7535 struct fw_hdr { 7536 __u8 ver; 7537 __u8 chip; /* terminator chip family */ 7538 __be16 len512; /* bin length in units of 512-bytes */ 7539 __be32 fw_ver; /* firmware version */ 7540 __be32 tp_microcode_ver; /* tcp processor microcode version */ 7541 __u8 intfver_nic; 7542 __u8 intfver_vnic; 7543 __u8 intfver_ofld; 7544 __u8 intfver_ri; 7545 __u8 intfver_iscsipdu; 7546 __u8 intfver_iscsi; 7547 __u8 intfver_fcoepdu; 7548 __u8 intfver_fcoe; 7549 __u32 reserved2; 7550 __u32 reserved3; 7551 __u32 reserved4; 7552 __be32 flags; 7553 __be32 reserved6[23]; 7554 }; 7555 7556 enum fw_hdr_chip { 7557 FW_HDR_CHIP_T4, 7558 FW_HDR_CHIP_T5 7559 }; 7560 7561 #define S_FW_HDR_FW_VER_MAJOR 24 7562 #define M_FW_HDR_FW_VER_MAJOR 0xff 7563 #define V_FW_HDR_FW_VER_MAJOR(x) \ 7564 ((x) << S_FW_HDR_FW_VER_MAJOR) 7565 #define G_FW_HDR_FW_VER_MAJOR(x) \ 7566 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 7567 7568 #define S_FW_HDR_FW_VER_MINOR 16 7569 #define M_FW_HDR_FW_VER_MINOR 0xff 7570 #define V_FW_HDR_FW_VER_MINOR(x) \ 7571 ((x) << S_FW_HDR_FW_VER_MINOR) 7572 #define G_FW_HDR_FW_VER_MINOR(x) \ 7573 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 7574 7575 #define S_FW_HDR_FW_VER_MICRO 8 7576 #define M_FW_HDR_FW_VER_MICRO 0xff 7577 #define V_FW_HDR_FW_VER_MICRO(x) \ 7578 ((x) << S_FW_HDR_FW_VER_MICRO) 7579 #define G_FW_HDR_FW_VER_MICRO(x) \ 7580 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 7581 7582 #define S_FW_HDR_FW_VER_BUILD 0 7583 #define M_FW_HDR_FW_VER_BUILD 0xff 7584 #define V_FW_HDR_FW_VER_BUILD(x) \ 7585 ((x) << S_FW_HDR_FW_VER_BUILD) 7586 #define G_FW_HDR_FW_VER_BUILD(x) \ 7587 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 7588 7589 enum { 7590 FW_HDR_INTFVER_NIC = 0x00, 7591 FW_HDR_INTFVER_VNIC = 0x00, 7592 FW_HDR_INTFVER_OFLD = 0x00, 7593 FW_HDR_INTFVER_RI = 0x00, 7594 FW_HDR_INTFVER_ISCSIPDU = 0x00, 7595 FW_HDR_INTFVER_ISCSI = 0x00, 7596 FW_HDR_INTFVER_FCOEPDU = 0x00, 7597 FW_HDR_INTFVER_FCOE = 0x00, 7598 }; 7599 7600 enum fw_hdr_flags { 7601 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 7602 }; 7603 7604 #endif /* _T4FW_INTERFACE_H_ */ 7605