1 /*- 2 * Copyright (c) 2012-2016 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _T4FW_INTERFACE_H_ 31 #define _T4FW_INTERFACE_H_ 32 33 /****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37 enum fw_retval { 38 FW_SUCCESS = 0, /* completed successfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_ENODEV = 19, /* no such device */ 49 FW_EINVAL = 22, /* invalid argument */ 50 FW_ENOSPC = 28, /* no space left on device */ 51 FW_ENOSYS = 38, /* functionality not implemented */ 52 FW_ENODATA = 61, /* no data available */ 53 FW_EPROTO = 71, /* protocol error */ 54 FW_EADDRINUSE = 98, /* address already in use */ 55 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 56 FW_ENETDOWN = 100, /* network is down */ 57 FW_ENETUNREACH = 101, /* network is unreachable */ 58 FW_ENOBUFS = 105, /* no buffer space available */ 59 FW_ETIMEDOUT = 110, /* timeout */ 60 FW_EINPROGRESS = 115, /* fw internal */ 61 FW_SCSI_ABORT_REQUESTED = 128, /* */ 62 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 63 FW_SCSI_ABORTED = 130, /* */ 64 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 65 FW_ERR_LINK_DOWN = 132, /* */ 66 FW_RDEV_NOT_READY = 133, /* */ 67 FW_ERR_RDEV_LOST = 134, /* */ 68 FW_ERR_RDEV_LOGO = 135, /* */ 69 FW_FCOE_NO_XCHG = 136, /* */ 70 FW_SCSI_RSP_ERR = 137, /* */ 71 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 72 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 73 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 74 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 75 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 76 }; 77 78 /****************************************************************************** 79 * M E M O R Y T Y P E s 80 ******************************/ 81 82 enum fw_memtype { 83 FW_MEMTYPE_EDC0 = 0x0, 84 FW_MEMTYPE_EDC1 = 0x1, 85 FW_MEMTYPE_EXTMEM = 0x2, 86 FW_MEMTYPE_FLASH = 0x4, 87 FW_MEMTYPE_INTERNAL = 0x5, 88 FW_MEMTYPE_EXTMEM1 = 0x6, 89 }; 90 91 /****************************************************************************** 92 * W O R K R E Q U E S T s 93 ********************************/ 94 95 enum fw_wr_opcodes { 96 FW_FRAG_WR = 0x1d, 97 FW_FILTER_WR = 0x02, 98 FW_ULPTX_WR = 0x04, 99 FW_TP_WR = 0x05, 100 FW_ETH_TX_PKT_WR = 0x08, 101 FW_ETH_TX_PKT2_WR = 0x44, 102 FW_ETH_TX_PKTS_WR = 0x09, 103 FW_ETH_TX_EO_WR = 0x1c, 104 FW_EQ_FLUSH_WR = 0x1b, 105 FW_OFLD_CONNECTION_WR = 0x2f, 106 FW_FLOWC_WR = 0x0a, 107 FW_OFLD_TX_DATA_WR = 0x0b, 108 FW_CMD_WR = 0x10, 109 FW_ETH_TX_PKT_VM_WR = 0x11, 110 FW_RI_RES_WR = 0x0c, 111 FW_RI_RDMA_WRITE_WR = 0x14, 112 FW_RI_SEND_WR = 0x15, 113 FW_RI_RDMA_READ_WR = 0x16, 114 FW_RI_RECV_WR = 0x17, 115 FW_RI_BIND_MW_WR = 0x18, 116 FW_RI_FR_NSMR_WR = 0x19, 117 FW_RI_INV_LSTAG_WR = 0x1a, 118 FW_RI_SEND_IMMEDIATE_WR = 0x15, 119 FW_RI_ATOMIC_WR = 0x16, 120 FW_RI_WR = 0x0d, 121 FW_CHNET_IFCONF_WR = 0x6b, 122 FW_RDEV_WR = 0x38, 123 FW_FOISCSI_NODE_WR = 0x60, 124 FW_FOISCSI_CTRL_WR = 0x6a, 125 FW_FOISCSI_CHAP_WR = 0x6c, 126 FW_FCOE_ELS_CT_WR = 0x30, 127 FW_SCSI_WRITE_WR = 0x31, 128 FW_SCSI_READ_WR = 0x32, 129 FW_SCSI_CMD_WR = 0x33, 130 FW_SCSI_ABRT_CLS_WR = 0x34, 131 FW_SCSI_TGT_ACC_WR = 0x35, 132 FW_SCSI_TGT_XMIT_WR = 0x36, 133 FW_SCSI_TGT_RSP_WR = 0x37, 134 FW_POFCOE_TCB_WR = 0x42, 135 FW_POFCOE_ULPTX_WR = 0x43, 136 FW_ISCSI_TX_DATA_WR = 0x45, 137 FW_PTP_TX_PKT_WR = 0x46, 138 FW_TLSTX_DATA_WR = 0x68, 139 FW_TLS_KEYCTX_TX_WR = 0x69, 140 FW_CRYPTO_LOOKASIDE_WR = 0x6d, 141 FW_COiSCSI_TGT_WR = 0x70, 142 FW_COiSCSI_TGT_CONN_WR = 0x71, 143 FW_COiSCSI_TGT_XMIT_WR = 0x72, 144 FW_ISNS_WR = 0x75, 145 FW_ISNS_XMIT_WR = 0x76, 146 FW_LASTC2E_WR = 0x80 147 }; 148 149 /* 150 * Generic work request header flit0 151 */ 152 struct fw_wr_hdr { 153 __be32 hi; 154 __be32 lo; 155 }; 156 157 /* work request opcode (hi) 158 */ 159 #define S_FW_WR_OP 24 160 #define M_FW_WR_OP 0xff 161 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 162 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 163 164 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 165 */ 166 #define S_FW_WR_ATOMIC 23 167 #define M_FW_WR_ATOMIC 0x1 168 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 169 #define G_FW_WR_ATOMIC(x) \ 170 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 171 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 172 173 /* flush flag (hi) - firmware flushes flushable work request buffered 174 * in the flow context. 175 */ 176 #define S_FW_WR_FLUSH 22 177 #define M_FW_WR_FLUSH 0x1 178 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 179 #define G_FW_WR_FLUSH(x) \ 180 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 181 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 182 183 /* completion flag (hi) - firmware generates a cpl_fw6_ack 184 */ 185 #define S_FW_WR_COMPL 21 186 #define M_FW_WR_COMPL 0x1 187 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 188 #define G_FW_WR_COMPL(x) \ 189 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 190 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 191 192 193 /* work request immediate data lengh (hi) 194 */ 195 #define S_FW_WR_IMMDLEN 0 196 #define M_FW_WR_IMMDLEN 0xff 197 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 198 #define G_FW_WR_IMMDLEN(x) \ 199 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 200 201 /* egress queue status update to associated ingress queue entry (lo) 202 */ 203 #define S_FW_WR_EQUIQ 31 204 #define M_FW_WR_EQUIQ 0x1 205 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 206 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 207 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 208 209 /* egress queue status update to egress queue status entry (lo) 210 */ 211 #define S_FW_WR_EQUEQ 30 212 #define M_FW_WR_EQUEQ 0x1 213 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 214 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 215 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 216 217 /* flow context identifier (lo) 218 */ 219 #define S_FW_WR_FLOWID 8 220 #define M_FW_WR_FLOWID 0xfffff 221 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 222 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 223 224 /* length in units of 16-bytes (lo) 225 */ 226 #define S_FW_WR_LEN16 0 227 #define M_FW_WR_LEN16 0xff 228 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 229 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 230 231 struct fw_frag_wr { 232 __be32 op_to_fragoff16; 233 __be32 flowid_len16; 234 __be64 r4; 235 }; 236 237 #define S_FW_FRAG_WR_EOF 15 238 #define M_FW_FRAG_WR_EOF 0x1 239 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 240 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 241 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 242 243 #define S_FW_FRAG_WR_FRAGOFF16 8 244 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 245 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 246 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 247 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 248 249 /* valid filter configurations for compressed tuple 250 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 251 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 252 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 253 * OV - Outer VLAN/VNIC_ID, 254 */ 255 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 256 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 257 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 258 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 259 #define HW_TPL_FR_MT_E_PR_T 0x370 260 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 261 #define HW_TPL_FR_MT_E_T_P_FC 0X353 262 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 263 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 264 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 265 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 266 #define HW_TPL_FR_M_E_PR_FC 0X2E1 267 #define HW_TPL_FR_M_E_T_FC 0X2D1 268 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 269 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 270 #define HW_TPL_FR_M_T_IV_FC 0X299 271 #define HW_TPL_FR_M_T_OV_FC 0X295 272 #define HW_TPL_FR_E_PR_T_P 0X272 273 #define HW_TPL_FR_E_PR_T_FC 0X271 274 #define HW_TPL_FR_E_IV_FC 0X249 275 #define HW_TPL_FR_E_OV_FC 0X245 276 #define HW_TPL_FR_PR_T_IV_FC 0X239 277 #define HW_TPL_FR_PR_T_OV_FC 0X235 278 #define HW_TPL_FR_IV_OV_FC 0X20D 279 #define HW_TPL_MT_M_E_PR 0X1E0 280 #define HW_TPL_MT_M_E_T 0X1D0 281 #define HW_TPL_MT_E_PR_T_FC 0X171 282 #define HW_TPL_MT_E_IV 0X148 283 #define HW_TPL_MT_E_OV 0X144 284 #define HW_TPL_MT_PR_T_IV 0X138 285 #define HW_TPL_MT_PR_T_OV 0X134 286 #define HW_TPL_M_E_PR_P 0X0E2 287 #define HW_TPL_M_E_T_P 0X0D2 288 #define HW_TPL_E_PR_T_P_FC 0X073 289 #define HW_TPL_E_IV_P 0X04A 290 #define HW_TPL_E_OV_P 0X046 291 #define HW_TPL_PR_T_IV_P 0X03A 292 #define HW_TPL_PR_T_OV_P 0X036 293 294 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 295 enum fw_filter_wr_cookie { 296 FW_FILTER_WR_SUCCESS, 297 FW_FILTER_WR_FLT_ADDED, 298 FW_FILTER_WR_FLT_DELETED, 299 FW_FILTER_WR_SMT_TBL_FULL, 300 FW_FILTER_WR_EINVAL, 301 }; 302 303 struct fw_filter_wr { 304 __be32 op_pkd; 305 __be32 len16_pkd; 306 __be64 r3; 307 __be32 tid_to_iq; 308 __be32 del_filter_to_l2tix; 309 __be16 ethtype; 310 __be16 ethtypem; 311 __u8 frag_to_ovlan_vldm; 312 __u8 smac_sel; 313 __be16 rx_chan_rx_rpl_iq; 314 __be32 maci_to_matchtypem; 315 __u8 ptcl; 316 __u8 ptclm; 317 __u8 ttyp; 318 __u8 ttypm; 319 __be16 ivlan; 320 __be16 ivlanm; 321 __be16 ovlan; 322 __be16 ovlanm; 323 __u8 lip[16]; 324 __u8 lipm[16]; 325 __u8 fip[16]; 326 __u8 fipm[16]; 327 __be16 lp; 328 __be16 lpm; 329 __be16 fp; 330 __be16 fpm; 331 __be16 r7; 332 __u8 sma[6]; 333 }; 334 335 #define S_FW_FILTER_WR_TID 12 336 #define M_FW_FILTER_WR_TID 0xfffff 337 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 338 #define G_FW_FILTER_WR_TID(x) \ 339 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 340 341 #define S_FW_FILTER_WR_RQTYPE 11 342 #define M_FW_FILTER_WR_RQTYPE 0x1 343 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 344 #define G_FW_FILTER_WR_RQTYPE(x) \ 345 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 346 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 347 348 #define S_FW_FILTER_WR_NOREPLY 10 349 #define M_FW_FILTER_WR_NOREPLY 0x1 350 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 351 #define G_FW_FILTER_WR_NOREPLY(x) \ 352 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 353 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 354 355 #define S_FW_FILTER_WR_IQ 0 356 #define M_FW_FILTER_WR_IQ 0x3ff 357 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 358 #define G_FW_FILTER_WR_IQ(x) \ 359 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 360 361 #define S_FW_FILTER_WR_DEL_FILTER 31 362 #define M_FW_FILTER_WR_DEL_FILTER 0x1 363 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 364 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 365 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 366 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 367 368 #define S_FW_FILTER_WR_RPTTID 25 369 #define M_FW_FILTER_WR_RPTTID 0x1 370 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 371 #define G_FW_FILTER_WR_RPTTID(x) \ 372 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 373 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 374 375 #define S_FW_FILTER_WR_DROP 24 376 #define M_FW_FILTER_WR_DROP 0x1 377 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 378 #define G_FW_FILTER_WR_DROP(x) \ 379 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 380 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 381 382 #define S_FW_FILTER_WR_DIRSTEER 23 383 #define M_FW_FILTER_WR_DIRSTEER 0x1 384 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 385 #define G_FW_FILTER_WR_DIRSTEER(x) \ 386 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 387 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 388 389 #define S_FW_FILTER_WR_MASKHASH 22 390 #define M_FW_FILTER_WR_MASKHASH 0x1 391 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 392 #define G_FW_FILTER_WR_MASKHASH(x) \ 393 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 394 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 395 396 #define S_FW_FILTER_WR_DIRSTEERHASH 21 397 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 398 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 399 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 400 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 401 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 402 403 #define S_FW_FILTER_WR_LPBK 20 404 #define M_FW_FILTER_WR_LPBK 0x1 405 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 406 #define G_FW_FILTER_WR_LPBK(x) \ 407 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 408 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 409 410 #define S_FW_FILTER_WR_DMAC 19 411 #define M_FW_FILTER_WR_DMAC 0x1 412 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 413 #define G_FW_FILTER_WR_DMAC(x) \ 414 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 415 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 416 417 #define S_FW_FILTER_WR_SMAC 18 418 #define M_FW_FILTER_WR_SMAC 0x1 419 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 420 #define G_FW_FILTER_WR_SMAC(x) \ 421 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 422 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 423 424 #define S_FW_FILTER_WR_INSVLAN 17 425 #define M_FW_FILTER_WR_INSVLAN 0x1 426 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 427 #define G_FW_FILTER_WR_INSVLAN(x) \ 428 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 429 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 430 431 #define S_FW_FILTER_WR_RMVLAN 16 432 #define M_FW_FILTER_WR_RMVLAN 0x1 433 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 434 #define G_FW_FILTER_WR_RMVLAN(x) \ 435 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 436 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 437 438 #define S_FW_FILTER_WR_HITCNTS 15 439 #define M_FW_FILTER_WR_HITCNTS 0x1 440 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 441 #define G_FW_FILTER_WR_HITCNTS(x) \ 442 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 443 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 444 445 #define S_FW_FILTER_WR_TXCHAN 13 446 #define M_FW_FILTER_WR_TXCHAN 0x3 447 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 448 #define G_FW_FILTER_WR_TXCHAN(x) \ 449 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 450 451 #define S_FW_FILTER_WR_PRIO 12 452 #define M_FW_FILTER_WR_PRIO 0x1 453 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 454 #define G_FW_FILTER_WR_PRIO(x) \ 455 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 456 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 457 458 #define S_FW_FILTER_WR_L2TIX 0 459 #define M_FW_FILTER_WR_L2TIX 0xfff 460 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 461 #define G_FW_FILTER_WR_L2TIX(x) \ 462 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 463 464 #define S_FW_FILTER_WR_FRAG 7 465 #define M_FW_FILTER_WR_FRAG 0x1 466 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 467 #define G_FW_FILTER_WR_FRAG(x) \ 468 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 469 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 470 471 #define S_FW_FILTER_WR_FRAGM 6 472 #define M_FW_FILTER_WR_FRAGM 0x1 473 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 474 #define G_FW_FILTER_WR_FRAGM(x) \ 475 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 476 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 477 478 #define S_FW_FILTER_WR_IVLAN_VLD 5 479 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 480 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 481 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 482 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 483 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 484 485 #define S_FW_FILTER_WR_OVLAN_VLD 4 486 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 487 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 488 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 489 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 490 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 491 492 #define S_FW_FILTER_WR_IVLAN_VLDM 3 493 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 494 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 495 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 496 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 497 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 498 499 #define S_FW_FILTER_WR_OVLAN_VLDM 2 500 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 501 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 502 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 503 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 504 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 505 506 #define S_FW_FILTER_WR_RX_CHAN 15 507 #define M_FW_FILTER_WR_RX_CHAN 0x1 508 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 509 #define G_FW_FILTER_WR_RX_CHAN(x) \ 510 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 511 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 512 513 #define S_FW_FILTER_WR_RX_RPL_IQ 0 514 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 515 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 516 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 517 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 518 519 #define S_FW_FILTER_WR_MACI 23 520 #define M_FW_FILTER_WR_MACI 0x1ff 521 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 522 #define G_FW_FILTER_WR_MACI(x) \ 523 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 524 525 #define S_FW_FILTER_WR_MACIM 14 526 #define M_FW_FILTER_WR_MACIM 0x1ff 527 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 528 #define G_FW_FILTER_WR_MACIM(x) \ 529 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 530 531 #define S_FW_FILTER_WR_FCOE 13 532 #define M_FW_FILTER_WR_FCOE 0x1 533 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 534 #define G_FW_FILTER_WR_FCOE(x) \ 535 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 536 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 537 538 #define S_FW_FILTER_WR_FCOEM 12 539 #define M_FW_FILTER_WR_FCOEM 0x1 540 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 541 #define G_FW_FILTER_WR_FCOEM(x) \ 542 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 543 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 544 545 #define S_FW_FILTER_WR_PORT 9 546 #define M_FW_FILTER_WR_PORT 0x7 547 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 548 #define G_FW_FILTER_WR_PORT(x) \ 549 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 550 551 #define S_FW_FILTER_WR_PORTM 6 552 #define M_FW_FILTER_WR_PORTM 0x7 553 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 554 #define G_FW_FILTER_WR_PORTM(x) \ 555 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 556 557 #define S_FW_FILTER_WR_MATCHTYPE 3 558 #define M_FW_FILTER_WR_MATCHTYPE 0x7 559 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 560 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 561 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 562 563 #define S_FW_FILTER_WR_MATCHTYPEM 0 564 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 565 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 566 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 567 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 568 569 struct fw_ulptx_wr { 570 __be32 op_to_compl; 571 __be32 flowid_len16; 572 __u64 cookie; 573 }; 574 575 struct fw_tp_wr { 576 __be32 op_to_immdlen; 577 __be32 flowid_len16; 578 __u64 cookie; 579 }; 580 581 struct fw_eth_tx_pkt_wr { 582 __be32 op_immdlen; 583 __be32 equiq_to_len16; 584 __be64 r3; 585 }; 586 587 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 588 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 589 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 590 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 591 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 592 593 struct fw_eth_tx_pkt2_wr { 594 __be32 op_immdlen; 595 __be32 equiq_to_len16; 596 __be32 r3; 597 __be32 L4ChkDisable_to_IpHdrLen; 598 }; 599 600 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 601 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 602 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 603 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 604 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 605 606 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 607 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 608 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 609 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 610 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 611 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 612 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 613 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 614 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 615 616 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 617 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 618 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 619 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 620 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 621 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 622 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 623 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 624 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 625 626 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 627 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 628 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 629 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 630 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 631 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 632 633 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 634 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 635 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 636 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 637 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 638 639 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 640 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 641 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 642 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 643 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 644 645 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 646 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 647 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 648 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 649 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 650 651 struct fw_eth_tx_pkts_wr { 652 __be32 op_pkd; 653 __be32 equiq_to_len16; 654 __be32 r3; 655 __be16 plen; 656 __u8 npkt; 657 __u8 type; 658 }; 659 660 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 661 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 662 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 663 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 664 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 665 666 struct fw_eth_tx_pkt_ptp_wr { 667 __be32 op_immdlen; 668 __be32 equiq_to_len16; 669 __be64 r3; 670 }; 671 672 enum fw_eth_tx_eo_type { 673 FW_ETH_TX_EO_TYPE_UDPSEG, 674 FW_ETH_TX_EO_TYPE_TCPSEG, 675 FW_ETH_TX_EO_TYPE_NVGRESEG, 676 FW_ETH_TX_EO_TYPE_VXLANSEG, 677 FW_ETH_TX_EO_TYPE_GENEVESEG, 678 }; 679 680 struct fw_eth_tx_eo_wr { 681 __be32 op_immdlen; 682 __be32 equiq_to_len16; 683 __be64 r3; 684 union fw_eth_tx_eo { 685 struct fw_eth_tx_eo_udpseg { 686 __u8 type; 687 __u8 ethlen; 688 __be16 iplen; 689 __u8 udplen; 690 __u8 rtplen; 691 __be16 r4; 692 __be16 mss; 693 __be16 schedpktsize; 694 __be32 plen; 695 } udpseg; 696 struct fw_eth_tx_eo_tcpseg { 697 __u8 type; 698 __u8 ethlen; 699 __be16 iplen; 700 __u8 tcplen; 701 __u8 tsclk_tsoff; 702 __be16 r4; 703 __be16 mss; 704 __be16 r5; 705 __be32 plen; 706 } tcpseg; 707 struct fw_eth_tx_eo_nvgreseg { 708 __u8 type; 709 __u8 iphdroffout; 710 __be16 grehdroff; 711 __be16 iphdroffin; 712 __be16 tcphdroffin; 713 __be16 mss; 714 __be16 r4; 715 __be32 plen; 716 } nvgreseg; 717 struct fw_eth_tx_eo_vxlanseg { 718 __u8 type; 719 __u8 iphdroffout; 720 __be16 vxlanhdroff; 721 __be16 iphdroffin; 722 __be16 tcphdroffin; 723 __be16 mss; 724 __be16 r4; 725 __be32 plen; 726 727 } vxlanseg; 728 struct fw_eth_tx_eo_geneveseg { 729 __u8 type; 730 __u8 iphdroffout; 731 __be16 genevehdroff; 732 __be16 iphdroffin; 733 __be16 tcphdroffin; 734 __be16 mss; 735 __be16 r4; 736 __be32 plen; 737 } geneveseg; 738 } u; 739 }; 740 741 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 742 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 743 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 744 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 745 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 746 747 #define S_FW_ETH_TX_EO_WR_TSCLK 6 748 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 749 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 750 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 751 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 752 753 #define S_FW_ETH_TX_EO_WR_TSOFF 0 754 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 755 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 756 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 757 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 758 759 struct fw_eq_flush_wr { 760 __u8 opcode; 761 __u8 r1[3]; 762 __be32 equiq_to_len16; 763 __be64 r3; 764 }; 765 766 struct fw_ofld_connection_wr { 767 __be32 op_compl; 768 __be32 len16_pkd; 769 __u64 cookie; 770 __be64 r2; 771 __be64 r3; 772 struct fw_ofld_connection_le { 773 __be32 version_cpl; 774 __be32 filter; 775 __be32 r1; 776 __be16 lport; 777 __be16 pport; 778 union fw_ofld_connection_leip { 779 struct fw_ofld_connection_le_ipv4 { 780 __be32 pip; 781 __be32 lip; 782 __be64 r0; 783 __be64 r1; 784 __be64 r2; 785 } ipv4; 786 struct fw_ofld_connection_le_ipv6 { 787 __be64 pip_hi; 788 __be64 pip_lo; 789 __be64 lip_hi; 790 __be64 lip_lo; 791 } ipv6; 792 } u; 793 } le; 794 struct fw_ofld_connection_tcb { 795 __be32 t_state_to_astid; 796 __be16 cplrxdataack_cplpassacceptrpl; 797 __be16 rcv_adv; 798 __be32 rcv_nxt; 799 __be32 tx_max; 800 __be64 opt0; 801 __be32 opt2; 802 __be32 r1; 803 __be64 r2; 804 __be64 r3; 805 } tcb; 806 }; 807 808 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 809 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 810 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 811 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 812 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 813 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 814 M_FW_OFLD_CONNECTION_WR_VERSION) 815 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 816 817 #define S_FW_OFLD_CONNECTION_WR_CPL 30 818 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 819 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 820 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 821 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 822 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 823 824 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 825 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 826 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 827 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 828 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 829 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 830 M_FW_OFLD_CONNECTION_WR_T_STATE) 831 832 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 833 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 834 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 835 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 836 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 837 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 838 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 839 840 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 841 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 842 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 843 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 844 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 845 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 846 847 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 848 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 849 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 850 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 851 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 852 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 853 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 854 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 855 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 856 857 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 858 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 859 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 860 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 861 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 862 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 863 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 864 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 865 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 866 867 enum fw_flowc_mnem_tcpstate { 868 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 869 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 870 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 871 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 872 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 873 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 874 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 875 * will resend FIN - equiv ESTAB 876 */ 877 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 878 * will resend FIN but have 879 * received FIN 880 */ 881 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 882 * will resend FIN but have 883 * received FIN 884 */ 885 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 886 * waiting for FIN 887 */ 888 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 889 }; 890 891 enum fw_flowc_mnem_eostate { 892 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 893 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 894 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 895 * outstanding payload 896 */ 897 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 898 * discarding outstanding payload 899 */ 900 }; 901 902 enum fw_flowc_mnem { 903 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 904 FW_FLOWC_MNEM_CH = 1, 905 FW_FLOWC_MNEM_PORT = 2, 906 FW_FLOWC_MNEM_IQID = 3, 907 FW_FLOWC_MNEM_SNDNXT = 4, 908 FW_FLOWC_MNEM_RCVNXT = 5, 909 FW_FLOWC_MNEM_SNDBUF = 6, 910 FW_FLOWC_MNEM_MSS = 7, 911 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 912 FW_FLOWC_MNEM_TCPSTATE = 9, 913 FW_FLOWC_MNEM_EOSTATE = 10, 914 FW_FLOWC_MNEM_SCHEDCLASS = 11, 915 FW_FLOWC_MNEM_DCBPRIO = 12, 916 FW_FLOWC_MNEM_SND_SCALE = 13, 917 FW_FLOWC_MNEM_RCV_SCALE = 14, 918 FW_FLOWC_MNEM_MAX = 15, 919 }; 920 921 struct fw_flowc_mnemval { 922 __u8 mnemonic; 923 __u8 r4[3]; 924 __be32 val; 925 }; 926 927 struct fw_flowc_wr { 928 __be32 op_to_nparams; 929 __be32 flowid_len16; 930 #ifndef C99_NOT_SUPPORTED 931 struct fw_flowc_mnemval mnemval[0]; 932 #endif 933 }; 934 935 #define S_FW_FLOWC_WR_NPARAMS 0 936 #define M_FW_FLOWC_WR_NPARAMS 0xff 937 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 938 #define G_FW_FLOWC_WR_NPARAMS(x) \ 939 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 940 941 struct fw_ofld_tx_data_wr { 942 __be32 op_to_immdlen; 943 __be32 flowid_len16; 944 __be32 plen; 945 __be32 lsodisable_to_flags; 946 }; 947 948 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 949 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 950 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 951 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 952 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 953 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 954 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 955 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 956 957 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 958 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 959 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 960 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 961 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 962 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 963 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 964 965 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 966 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 967 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 968 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 969 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 970 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 971 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 972 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 973 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 974 975 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 976 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 977 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 978 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 979 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 980 981 982 /* Use fw_ofld_tx_data_wr structure */ 983 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 984 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 985 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 986 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 987 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 988 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 989 990 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 991 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 992 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 993 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 994 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 995 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 996 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 997 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 998 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 999 1000 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 1001 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1002 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1003 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1004 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1005 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1006 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1007 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1008 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1009 1010 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1011 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1012 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1013 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1014 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1015 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1016 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1017 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1018 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1019 1020 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1021 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1022 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1023 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1024 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1025 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1026 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1027 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1028 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1029 1030 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1031 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1032 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1033 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1034 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1035 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1036 1037 struct fw_cmd_wr { 1038 __be32 op_dma; 1039 __be32 len16_pkd; 1040 __be64 cookie_daddr; 1041 }; 1042 1043 #define S_FW_CMD_WR_DMA 17 1044 #define M_FW_CMD_WR_DMA 0x1 1045 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1046 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1047 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1048 1049 struct fw_eth_tx_pkt_vm_wr { 1050 __be32 op_immdlen; 1051 __be32 equiq_to_len16; 1052 __be32 r3[2]; 1053 __u8 ethmacdst[6]; 1054 __u8 ethmacsrc[6]; 1055 __be16 ethtype; 1056 __be16 vlantci; 1057 }; 1058 1059 /****************************************************************************** 1060 * R I W O R K R E Q U E S T s 1061 **************************************/ 1062 1063 enum fw_ri_wr_opcode { 1064 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1065 FW_RI_READ_REQ = 0x1, 1066 FW_RI_READ_RESP = 0x2, 1067 FW_RI_SEND = 0x3, 1068 FW_RI_SEND_WITH_INV = 0x4, 1069 FW_RI_SEND_WITH_SE = 0x5, 1070 FW_RI_SEND_WITH_SE_INV = 0x6, 1071 FW_RI_TERMINATE = 0x7, 1072 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1073 FW_RI_BIND_MW = 0x9, 1074 FW_RI_FAST_REGISTER = 0xa, 1075 FW_RI_LOCAL_INV = 0xb, 1076 FW_RI_QP_MODIFY = 0xc, 1077 FW_RI_BYPASS = 0xd, 1078 FW_RI_RECEIVE = 0xe, 1079 #if 0 1080 FW_RI_SEND_IMMEDIATE = 0x8, 1081 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1082 FW_RI_ATOMIC_REQUEST = 0xa, 1083 FW_RI_ATOMIC_RESPONSE = 0xb, 1084 1085 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1086 FW_RI_FAST_REGISTER = 0xd, 1087 FW_RI_LOCAL_INV = 0xe, 1088 #endif 1089 FW_RI_SGE_EC_CR_RETURN = 0xf 1090 }; 1091 1092 enum fw_ri_wr_flags { 1093 FW_RI_COMPLETION_FLAG = 0x01, 1094 FW_RI_NOTIFICATION_FLAG = 0x02, 1095 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1096 FW_RI_READ_FENCE_FLAG = 0x08, 1097 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1098 FW_RI_RDMA_READ_INVALIDATE = 0x20 1099 }; 1100 1101 enum fw_ri_mpa_attrs { 1102 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1103 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1104 FW_RI_MPA_CRC_ENABLE = 0x04, 1105 FW_RI_MPA_IETF_ENABLE = 0x08 1106 }; 1107 1108 enum fw_ri_qp_caps { 1109 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1110 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1111 FW_RI_QP_BIND_ENABLE = 0x04, 1112 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1113 FW_RI_QP_STAG0_ENABLE = 0x10, 1114 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1115 }; 1116 1117 enum fw_ri_addr_type { 1118 FW_RI_ZERO_BASED_TO = 0x00, 1119 FW_RI_VA_BASED_TO = 0x01 1120 }; 1121 1122 enum fw_ri_mem_perms { 1123 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1124 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1125 FW_RI_MEM_ACCESS_REM = 0x03, 1126 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1127 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1128 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1129 }; 1130 1131 enum fw_ri_stag_type { 1132 FW_RI_STAG_NSMR = 0x00, 1133 FW_RI_STAG_SMR = 0x01, 1134 FW_RI_STAG_MW = 0x02, 1135 FW_RI_STAG_MW_RELAXED = 0x03 1136 }; 1137 1138 enum fw_ri_data_op { 1139 FW_RI_DATA_IMMD = 0x81, 1140 FW_RI_DATA_DSGL = 0x82, 1141 FW_RI_DATA_ISGL = 0x83 1142 }; 1143 1144 enum fw_ri_sgl_depth { 1145 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1146 FW_RI_SGL_DEPTH_MAX_RQ = 4 1147 }; 1148 1149 enum fw_ri_cqe_err { 1150 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1151 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1152 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1153 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1154 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1155 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1156 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1157 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1158 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1159 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1160 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1161 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1162 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1163 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1164 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1165 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1166 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1167 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1168 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1169 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1170 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1171 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1172 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1173 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1174 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1175 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1176 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1177 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1178 1179 }; 1180 1181 struct fw_ri_dsge_pair { 1182 __be32 len[2]; 1183 __be64 addr[2]; 1184 }; 1185 1186 struct fw_ri_dsgl { 1187 __u8 op; 1188 __u8 r1; 1189 __be16 nsge; 1190 __be32 len0; 1191 __be64 addr0; 1192 #ifndef C99_NOT_SUPPORTED 1193 struct fw_ri_dsge_pair sge[0]; 1194 #endif 1195 }; 1196 1197 struct fw_ri_sge { 1198 __be32 stag; 1199 __be32 len; 1200 __be64 to; 1201 }; 1202 1203 struct fw_ri_isgl { 1204 __u8 op; 1205 __u8 r1; 1206 __be16 nsge; 1207 __be32 r2; 1208 #ifndef C99_NOT_SUPPORTED 1209 struct fw_ri_sge sge[0]; 1210 #endif 1211 }; 1212 1213 struct fw_ri_immd { 1214 __u8 op; 1215 __u8 r1; 1216 __be16 r2; 1217 __be32 immdlen; 1218 #ifndef C99_NOT_SUPPORTED 1219 __u8 data[0]; 1220 #endif 1221 }; 1222 1223 struct fw_ri_tpte { 1224 __be32 valid_to_pdid; 1225 __be32 locread_to_qpid; 1226 __be32 nosnoop_pbladdr; 1227 __be32 len_lo; 1228 __be32 va_hi; 1229 __be32 va_lo_fbo; 1230 __be32 dca_mwbcnt_pstag; 1231 __be32 len_hi; 1232 }; 1233 1234 #define S_FW_RI_TPTE_VALID 31 1235 #define M_FW_RI_TPTE_VALID 0x1 1236 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1237 #define G_FW_RI_TPTE_VALID(x) \ 1238 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1239 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1240 1241 #define S_FW_RI_TPTE_STAGKEY 23 1242 #define M_FW_RI_TPTE_STAGKEY 0xff 1243 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1244 #define G_FW_RI_TPTE_STAGKEY(x) \ 1245 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1246 1247 #define S_FW_RI_TPTE_STAGSTATE 22 1248 #define M_FW_RI_TPTE_STAGSTATE 0x1 1249 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1250 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1251 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1252 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1253 1254 #define S_FW_RI_TPTE_STAGTYPE 20 1255 #define M_FW_RI_TPTE_STAGTYPE 0x3 1256 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1257 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1258 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1259 1260 #define S_FW_RI_TPTE_PDID 0 1261 #define M_FW_RI_TPTE_PDID 0xfffff 1262 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1263 #define G_FW_RI_TPTE_PDID(x) \ 1264 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1265 1266 #define S_FW_RI_TPTE_PERM 28 1267 #define M_FW_RI_TPTE_PERM 0xf 1268 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1269 #define G_FW_RI_TPTE_PERM(x) \ 1270 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1271 1272 #define S_FW_RI_TPTE_REMINVDIS 27 1273 #define M_FW_RI_TPTE_REMINVDIS 0x1 1274 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1275 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1276 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1277 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1278 1279 #define S_FW_RI_TPTE_ADDRTYPE 26 1280 #define M_FW_RI_TPTE_ADDRTYPE 1 1281 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1282 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1283 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1284 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1285 1286 #define S_FW_RI_TPTE_MWBINDEN 25 1287 #define M_FW_RI_TPTE_MWBINDEN 0x1 1288 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1289 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1290 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1291 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1292 1293 #define S_FW_RI_TPTE_PS 20 1294 #define M_FW_RI_TPTE_PS 0x1f 1295 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1296 #define G_FW_RI_TPTE_PS(x) \ 1297 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1298 1299 #define S_FW_RI_TPTE_QPID 0 1300 #define M_FW_RI_TPTE_QPID 0xfffff 1301 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1302 #define G_FW_RI_TPTE_QPID(x) \ 1303 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1304 1305 #define S_FW_RI_TPTE_NOSNOOP 31 1306 #define M_FW_RI_TPTE_NOSNOOP 0x1 1307 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1308 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1309 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1310 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1311 1312 #define S_FW_RI_TPTE_PBLADDR 0 1313 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1314 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1315 #define G_FW_RI_TPTE_PBLADDR(x) \ 1316 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1317 1318 #define S_FW_RI_TPTE_DCA 24 1319 #define M_FW_RI_TPTE_DCA 0x1f 1320 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1321 #define G_FW_RI_TPTE_DCA(x) \ 1322 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1323 1324 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1325 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1326 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1327 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1328 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1329 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1330 1331 enum fw_ri_cqe_rxtx { 1332 FW_RI_CQE_RXTX_RX = 0x0, 1333 FW_RI_CQE_RXTX_TX = 0x1, 1334 }; 1335 1336 struct fw_ri_cqe { 1337 union fw_ri_rxtx { 1338 struct fw_ri_scqe { 1339 __be32 qpid_n_stat_rxtx_type; 1340 __be32 plen; 1341 __be32 reserved; 1342 __be32 wrid; 1343 } scqe; 1344 struct fw_ri_rcqe { 1345 __be32 qpid_n_stat_rxtx_type; 1346 __be32 plen; 1347 __be32 stag; 1348 __be32 msn; 1349 } rcqe; 1350 } u; 1351 }; 1352 1353 #define S_FW_RI_CQE_QPID 12 1354 #define M_FW_RI_CQE_QPID 0xfffff 1355 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1356 #define G_FW_RI_CQE_QPID(x) \ 1357 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1358 1359 #define S_FW_RI_CQE_NOTIFY 10 1360 #define M_FW_RI_CQE_NOTIFY 0x1 1361 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1362 #define G_FW_RI_CQE_NOTIFY(x) \ 1363 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1364 1365 #define S_FW_RI_CQE_STATUS 5 1366 #define M_FW_RI_CQE_STATUS 0x1f 1367 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1368 #define G_FW_RI_CQE_STATUS(x) \ 1369 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1370 1371 1372 #define S_FW_RI_CQE_RXTX 4 1373 #define M_FW_RI_CQE_RXTX 0x1 1374 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1375 #define G_FW_RI_CQE_RXTX(x) \ 1376 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1377 1378 #define S_FW_RI_CQE_TYPE 0 1379 #define M_FW_RI_CQE_TYPE 0xf 1380 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1381 #define G_FW_RI_CQE_TYPE(x) \ 1382 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1383 1384 enum fw_ri_res_type { 1385 FW_RI_RES_TYPE_SQ, 1386 FW_RI_RES_TYPE_RQ, 1387 FW_RI_RES_TYPE_CQ, 1388 FW_RI_RES_TYPE_SRQ, 1389 }; 1390 1391 enum fw_ri_res_op { 1392 FW_RI_RES_OP_WRITE, 1393 FW_RI_RES_OP_RESET, 1394 }; 1395 1396 struct fw_ri_res { 1397 union fw_ri_restype { 1398 struct fw_ri_res_sqrq { 1399 __u8 restype; 1400 __u8 op; 1401 __be16 r3; 1402 __be32 eqid; 1403 __be32 r4[2]; 1404 __be32 fetchszm_to_iqid; 1405 __be32 dcaen_to_eqsize; 1406 __be64 eqaddr; 1407 } sqrq; 1408 struct fw_ri_res_cq { 1409 __u8 restype; 1410 __u8 op; 1411 __be16 r3; 1412 __be32 iqid; 1413 __be32 r4[2]; 1414 __be32 iqandst_to_iqandstindex; 1415 __be16 iqdroprss_to_iqesize; 1416 __be16 iqsize; 1417 __be64 iqaddr; 1418 __be32 iqns_iqro; 1419 __be32 r6_lo; 1420 __be64 r7; 1421 } cq; 1422 struct fw_ri_res_srq { 1423 __u8 restype; 1424 __u8 op; 1425 __be16 r3; 1426 __be32 eqid; 1427 __be32 r4[2]; 1428 __be32 fetchszm_to_iqid; 1429 __be32 dcaen_to_eqsize; 1430 __be64 eqaddr; 1431 __be32 srqid; 1432 __be32 pdid; 1433 __be32 hwsrqsize; 1434 __be32 hwsrqaddr; 1435 } srq; 1436 } u; 1437 }; 1438 1439 struct fw_ri_res_wr { 1440 __be32 op_nres; 1441 __be32 len16_pkd; 1442 __u64 cookie; 1443 #ifndef C99_NOT_SUPPORTED 1444 struct fw_ri_res res[0]; 1445 #endif 1446 }; 1447 1448 #define S_FW_RI_RES_WR_NRES 0 1449 #define M_FW_RI_RES_WR_NRES 0xff 1450 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1451 #define G_FW_RI_RES_WR_NRES(x) \ 1452 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1453 1454 #define S_FW_RI_RES_WR_FETCHSZM 26 1455 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1456 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1457 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1458 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1459 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1460 1461 #define S_FW_RI_RES_WR_STATUSPGNS 25 1462 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1463 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1464 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1465 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1466 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1467 1468 #define S_FW_RI_RES_WR_STATUSPGRO 24 1469 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1470 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1471 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1472 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1473 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1474 1475 #define S_FW_RI_RES_WR_FETCHNS 23 1476 #define M_FW_RI_RES_WR_FETCHNS 0x1 1477 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1478 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1479 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1480 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1481 1482 #define S_FW_RI_RES_WR_FETCHRO 22 1483 #define M_FW_RI_RES_WR_FETCHRO 0x1 1484 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1485 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1486 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1487 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1488 1489 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1490 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1491 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1492 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1493 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1494 1495 #define S_FW_RI_RES_WR_CPRIO 19 1496 #define M_FW_RI_RES_WR_CPRIO 0x1 1497 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1498 #define G_FW_RI_RES_WR_CPRIO(x) \ 1499 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1500 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1501 1502 #define S_FW_RI_RES_WR_ONCHIP 18 1503 #define M_FW_RI_RES_WR_ONCHIP 0x1 1504 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1505 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1506 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1507 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1508 1509 #define S_FW_RI_RES_WR_PCIECHN 16 1510 #define M_FW_RI_RES_WR_PCIECHN 0x3 1511 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1512 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1513 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1514 1515 #define S_FW_RI_RES_WR_IQID 0 1516 #define M_FW_RI_RES_WR_IQID 0xffff 1517 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1518 #define G_FW_RI_RES_WR_IQID(x) \ 1519 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1520 1521 #define S_FW_RI_RES_WR_DCAEN 31 1522 #define M_FW_RI_RES_WR_DCAEN 0x1 1523 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1524 #define G_FW_RI_RES_WR_DCAEN(x) \ 1525 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1526 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1527 1528 #define S_FW_RI_RES_WR_DCACPU 26 1529 #define M_FW_RI_RES_WR_DCACPU 0x1f 1530 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1531 #define G_FW_RI_RES_WR_DCACPU(x) \ 1532 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1533 1534 #define S_FW_RI_RES_WR_FBMIN 23 1535 #define M_FW_RI_RES_WR_FBMIN 0x7 1536 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1537 #define G_FW_RI_RES_WR_FBMIN(x) \ 1538 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1539 1540 #define S_FW_RI_RES_WR_FBMAX 20 1541 #define M_FW_RI_RES_WR_FBMAX 0x7 1542 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1543 #define G_FW_RI_RES_WR_FBMAX(x) \ 1544 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1545 1546 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1547 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1548 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1549 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1550 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1551 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1552 1553 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1554 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1555 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1556 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1557 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1558 1559 #define S_FW_RI_RES_WR_EQSIZE 0 1560 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1561 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1562 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1563 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1564 1565 #define S_FW_RI_RES_WR_IQANDST 15 1566 #define M_FW_RI_RES_WR_IQANDST 0x1 1567 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1568 #define G_FW_RI_RES_WR_IQANDST(x) \ 1569 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1570 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1571 1572 #define S_FW_RI_RES_WR_IQANUS 14 1573 #define M_FW_RI_RES_WR_IQANUS 0x1 1574 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1575 #define G_FW_RI_RES_WR_IQANUS(x) \ 1576 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1577 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1578 1579 #define S_FW_RI_RES_WR_IQANUD 12 1580 #define M_FW_RI_RES_WR_IQANUD 0x3 1581 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1582 #define G_FW_RI_RES_WR_IQANUD(x) \ 1583 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1584 1585 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1586 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1587 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1588 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1589 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1590 1591 #define S_FW_RI_RES_WR_IQDROPRSS 15 1592 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1593 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1594 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1595 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1596 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1597 1598 #define S_FW_RI_RES_WR_IQGTSMODE 14 1599 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1600 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1601 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1602 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1603 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1604 1605 #define S_FW_RI_RES_WR_IQPCIECH 12 1606 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1607 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1608 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1609 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1610 1611 #define S_FW_RI_RES_WR_IQDCAEN 11 1612 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1613 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1614 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1615 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1616 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1617 1618 #define S_FW_RI_RES_WR_IQDCACPU 6 1619 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1620 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1621 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1622 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1623 1624 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1625 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1626 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1627 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1628 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1629 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1630 1631 #define S_FW_RI_RES_WR_IQO 3 1632 #define M_FW_RI_RES_WR_IQO 0x1 1633 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1634 #define G_FW_RI_RES_WR_IQO(x) \ 1635 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1636 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1637 1638 #define S_FW_RI_RES_WR_IQCPRIO 2 1639 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1640 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1641 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1642 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1643 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1644 1645 #define S_FW_RI_RES_WR_IQESIZE 0 1646 #define M_FW_RI_RES_WR_IQESIZE 0x3 1647 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1648 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1649 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1650 1651 #define S_FW_RI_RES_WR_IQNS 31 1652 #define M_FW_RI_RES_WR_IQNS 0x1 1653 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1654 #define G_FW_RI_RES_WR_IQNS(x) \ 1655 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1656 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1657 1658 #define S_FW_RI_RES_WR_IQRO 30 1659 #define M_FW_RI_RES_WR_IQRO 0x1 1660 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1661 #define G_FW_RI_RES_WR_IQRO(x) \ 1662 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1663 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1664 1665 struct fw_ri_rdma_write_wr { 1666 __u8 opcode; 1667 __u8 flags; 1668 __u16 wrid; 1669 __u8 r1[3]; 1670 __u8 len16; 1671 __be64 r2; 1672 __be32 plen; 1673 __be32 stag_sink; 1674 __be64 to_sink; 1675 #ifndef C99_NOT_SUPPORTED 1676 union { 1677 struct fw_ri_immd immd_src[0]; 1678 struct fw_ri_isgl isgl_src[0]; 1679 } u; 1680 #endif 1681 }; 1682 1683 struct fw_ri_send_wr { 1684 __u8 opcode; 1685 __u8 flags; 1686 __u16 wrid; 1687 __u8 r1[3]; 1688 __u8 len16; 1689 __be32 sendop_pkd; 1690 __be32 stag_inv; 1691 __be32 plen; 1692 __be32 r3; 1693 __be64 r4; 1694 #ifndef C99_NOT_SUPPORTED 1695 union { 1696 struct fw_ri_immd immd_src[0]; 1697 struct fw_ri_isgl isgl_src[0]; 1698 } u; 1699 #endif 1700 }; 1701 1702 #define S_FW_RI_SEND_WR_SENDOP 0 1703 #define M_FW_RI_SEND_WR_SENDOP 0xf 1704 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1705 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1706 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1707 1708 struct fw_ri_rdma_read_wr { 1709 __u8 opcode; 1710 __u8 flags; 1711 __u16 wrid; 1712 __u8 r1[3]; 1713 __u8 len16; 1714 __be64 r2; 1715 __be32 stag_sink; 1716 __be32 to_sink_hi; 1717 __be32 to_sink_lo; 1718 __be32 plen; 1719 __be32 stag_src; 1720 __be32 to_src_hi; 1721 __be32 to_src_lo; 1722 __be32 r5; 1723 }; 1724 1725 struct fw_ri_recv_wr { 1726 __u8 opcode; 1727 __u8 r1; 1728 __u16 wrid; 1729 __u8 r2[3]; 1730 __u8 len16; 1731 struct fw_ri_isgl isgl; 1732 }; 1733 1734 struct fw_ri_bind_mw_wr { 1735 __u8 opcode; 1736 __u8 flags; 1737 __u16 wrid; 1738 __u8 r1[3]; 1739 __u8 len16; 1740 __u8 qpbinde_to_dcacpu; 1741 __u8 pgsz_shift; 1742 __u8 addr_type; 1743 __u8 mem_perms; 1744 __be32 stag_mr; 1745 __be32 stag_mw; 1746 __be32 r3; 1747 __be64 len_mw; 1748 __be64 va_fbo; 1749 __be64 r4; 1750 }; 1751 1752 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1753 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1754 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1755 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1756 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1757 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1758 1759 #define S_FW_RI_BIND_MW_WR_NS 5 1760 #define M_FW_RI_BIND_MW_WR_NS 0x1 1761 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1762 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1763 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1764 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1765 1766 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1767 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1768 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1769 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1770 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1771 1772 struct fw_ri_fr_nsmr_wr { 1773 __u8 opcode; 1774 __u8 flags; 1775 __u16 wrid; 1776 __u8 r1[3]; 1777 __u8 len16; 1778 __u8 qpbinde_to_dcacpu; 1779 __u8 pgsz_shift; 1780 __u8 addr_type; 1781 __u8 mem_perms; 1782 __be32 stag; 1783 __be32 len_hi; 1784 __be32 len_lo; 1785 __be32 va_hi; 1786 __be32 va_lo_fbo; 1787 }; 1788 1789 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1790 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1791 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1792 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1793 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1794 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1795 1796 #define S_FW_RI_FR_NSMR_WR_NS 5 1797 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1798 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1799 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1800 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1801 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1802 1803 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1804 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1805 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1806 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1807 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1808 1809 struct fw_ri_inv_lstag_wr { 1810 __u8 opcode; 1811 __u8 flags; 1812 __u16 wrid; 1813 __u8 r1[3]; 1814 __u8 len16; 1815 __be32 r2; 1816 __be32 stag_inv; 1817 }; 1818 1819 struct fw_ri_send_immediate_wr { 1820 __u8 opcode; 1821 __u8 flags; 1822 __u16 wrid; 1823 __u8 r1[3]; 1824 __u8 len16; 1825 __be32 sendimmop_pkd; 1826 __be32 r3; 1827 __be32 plen; 1828 __be32 r4; 1829 __be64 r5; 1830 #ifndef C99_NOT_SUPPORTED 1831 struct fw_ri_immd immd_src[0]; 1832 #endif 1833 }; 1834 1835 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1836 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1837 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1838 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1839 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1840 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1841 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1842 1843 enum fw_ri_atomic_op { 1844 FW_RI_ATOMIC_OP_FETCHADD, 1845 FW_RI_ATOMIC_OP_SWAP, 1846 FW_RI_ATOMIC_OP_CMDSWAP, 1847 }; 1848 1849 struct fw_ri_atomic_wr { 1850 __u8 opcode; 1851 __u8 flags; 1852 __u16 wrid; 1853 __u8 r1[3]; 1854 __u8 len16; 1855 __be32 atomicop_pkd; 1856 __be64 r3; 1857 __be32 aopcode_pkd; 1858 __be32 reqid; 1859 __be32 stag; 1860 __be32 to_hi; 1861 __be32 to_lo; 1862 __be32 addswap_data_hi; 1863 __be32 addswap_data_lo; 1864 __be32 addswap_mask_hi; 1865 __be32 addswap_mask_lo; 1866 __be32 compare_data_hi; 1867 __be32 compare_data_lo; 1868 __be32 compare_mask_hi; 1869 __be32 compare_mask_lo; 1870 __be32 r5; 1871 }; 1872 1873 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1874 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1875 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1876 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1877 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 1878 1879 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 1880 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1881 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1882 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1883 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 1884 1885 enum fw_ri_type { 1886 FW_RI_TYPE_INIT, 1887 FW_RI_TYPE_FINI, 1888 FW_RI_TYPE_TERMINATE 1889 }; 1890 1891 enum fw_ri_init_p2ptype { 1892 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 1893 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 1894 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 1895 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 1896 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 1897 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 1898 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 1899 }; 1900 1901 enum fw_ri_init_rqeqid_srq { 1902 FW_RI_INIT_RQEQID_SRQ = 1 << 31, 1903 }; 1904 1905 struct fw_ri_wr { 1906 __be32 op_compl; 1907 __be32 flowid_len16; 1908 __u64 cookie; 1909 union fw_ri { 1910 struct fw_ri_init { 1911 __u8 type; 1912 __u8 mpareqbit_p2ptype; 1913 __u8 r4[2]; 1914 __u8 mpa_attrs; 1915 __u8 qp_caps; 1916 __be16 nrqe; 1917 __be32 pdid; 1918 __be32 qpid; 1919 __be32 sq_eqid; 1920 __be32 rq_eqid; 1921 __be32 scqid; 1922 __be32 rcqid; 1923 __be32 ord_max; 1924 __be32 ird_max; 1925 __be32 iss; 1926 __be32 irs; 1927 __be32 hwrqsize; 1928 __be32 hwrqaddr; 1929 __be64 r5; 1930 union fw_ri_init_p2p { 1931 struct fw_ri_rdma_write_wr write; 1932 struct fw_ri_rdma_read_wr read; 1933 struct fw_ri_send_wr send; 1934 } u; 1935 } init; 1936 struct fw_ri_fini { 1937 __u8 type; 1938 __u8 r3[7]; 1939 __be64 r4; 1940 } fini; 1941 struct fw_ri_terminate { 1942 __u8 type; 1943 __u8 r3[3]; 1944 __be32 immdlen; 1945 __u8 termmsg[40]; 1946 } terminate; 1947 } u; 1948 }; 1949 1950 #define S_FW_RI_WR_MPAREQBIT 7 1951 #define M_FW_RI_WR_MPAREQBIT 0x1 1952 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 1953 #define G_FW_RI_WR_MPAREQBIT(x) \ 1954 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 1955 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 1956 1957 #define S_FW_RI_WR_0BRRBIT 6 1958 #define M_FW_RI_WR_0BRRBIT 0x1 1959 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 1960 #define G_FW_RI_WR_0BRRBIT(x) \ 1961 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 1962 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 1963 1964 #define S_FW_RI_WR_P2PTYPE 0 1965 #define M_FW_RI_WR_P2PTYPE 0xf 1966 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1967 #define G_FW_RI_WR_P2PTYPE(x) \ 1968 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1969 1970 /****************************************************************************** 1971 * F O i S C S I W O R K R E Q U E S T s 1972 *********************************************/ 1973 1974 #define FW_FOISCSI_NAME_MAX_LEN 224 1975 #define FW_FOISCSI_ALIAS_MAX_LEN 224 1976 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 1977 #define FW_FOISCSI_INIT_NODE_MAX 8 1978 1979 enum fw_chnet_ifconf_wr_subop { 1980 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 1981 1982 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 1983 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 1984 1985 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 1986 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 1987 1988 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 1989 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 1990 1991 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 1992 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 1993 1994 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 1995 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 1996 1997 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 1998 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 1999 2000 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 2001 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 2002 2003 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 2004 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 2005 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 2006 2007 FW_CHNET_IFCONF_WR_SUBOP_MAX, 2008 }; 2009 2010 struct fw_chnet_ifconf_wr { 2011 __be32 op_compl; 2012 __be32 flowid_len16; 2013 __be64 cookie; 2014 __be32 if_flowid; 2015 __u8 idx; 2016 __u8 subop; 2017 __u8 retval; 2018 __u8 r2; 2019 __be64 r3; 2020 struct fw_chnet_ifconf_params { 2021 __be32 r0; 2022 __be16 vlanid; 2023 __be16 mtu; 2024 union fw_chnet_ifconf_addr_type { 2025 struct fw_chnet_ifconf_ipv4 { 2026 __be32 addr; 2027 __be32 mask; 2028 __be32 router; 2029 __be32 r0; 2030 __be64 r1; 2031 } ipv4; 2032 struct fw_chnet_ifconf_ipv6 { 2033 __u8 prefix_len; 2034 __u8 r0; 2035 __be16 r1; 2036 __be32 r2; 2037 __be64 addr_hi; 2038 __be64 addr_lo; 2039 __be64 router_hi; 2040 __be64 router_lo; 2041 } ipv6; 2042 } in_attr; 2043 } param; 2044 }; 2045 2046 enum fw_foiscsi_node_type { 2047 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 2048 FW_FOISCSI_NODE_TYPE_TARGET, 2049 }; 2050 2051 enum fw_foiscsi_session_type { 2052 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 2053 FW_FOISCSI_SESSION_TYPE_NORMAL, 2054 }; 2055 2056 enum fw_foiscsi_auth_policy { 2057 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 2058 FW_FOISCSI_AUTH_POLICY_MUTUAL, 2059 }; 2060 2061 enum fw_foiscsi_auth_method { 2062 FW_FOISCSI_AUTH_METHOD_NONE = 0, 2063 FW_FOISCSI_AUTH_METHOD_CHAP, 2064 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 2065 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 2066 }; 2067 2068 enum fw_foiscsi_digest_type { 2069 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 2070 FW_FOISCSI_DIGEST_TYPE_CRC32, 2071 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 2072 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 2073 }; 2074 2075 enum fw_foiscsi_wr_subop { 2076 FW_FOISCSI_WR_SUBOP_ADD = 1, 2077 FW_FOISCSI_WR_SUBOP_DEL = 2, 2078 FW_FOISCSI_WR_SUBOP_MOD = 4, 2079 }; 2080 2081 enum fw_foiscsi_ctrl_state { 2082 FW_FOISCSI_CTRL_STATE_FREE = 0, 2083 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 2084 FW_FOISCSI_CTRL_STATE_FAILED, 2085 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 2086 FW_FOISCSI_CTRL_STATE_REDIRECT, 2087 }; 2088 2089 struct fw_rdev_wr { 2090 __be32 op_to_immdlen; 2091 __be32 alloc_to_len16; 2092 __be64 cookie; 2093 __u8 protocol; 2094 __u8 event_cause; 2095 __u8 cur_state; 2096 __u8 prev_state; 2097 __be32 flags_to_assoc_flowid; 2098 union rdev_entry { 2099 struct fcoe_rdev_entry { 2100 __be32 flowid; 2101 __u8 protocol; 2102 __u8 event_cause; 2103 __u8 flags; 2104 __u8 rjt_reason; 2105 __u8 cur_login_st; 2106 __u8 prev_login_st; 2107 __be16 rcv_fr_sz; 2108 __u8 rd_xfer_rdy_to_rport_type; 2109 __u8 vft_to_qos; 2110 __u8 org_proc_assoc_to_acc_rsp_code; 2111 __u8 enh_disc_to_tgt; 2112 __u8 wwnn[8]; 2113 __u8 wwpn[8]; 2114 __be16 iqid; 2115 __u8 fc_oui[3]; 2116 __u8 r_id[3]; 2117 } fcoe_rdev; 2118 struct iscsi_rdev_entry { 2119 __be32 flowid; 2120 __u8 protocol; 2121 __u8 event_cause; 2122 __u8 flags; 2123 __u8 r3; 2124 __be16 iscsi_opts; 2125 __be16 tcp_opts; 2126 __be16 ip_opts; 2127 __be16 max_rcv_len; 2128 __be16 max_snd_len; 2129 __be16 first_brst_len; 2130 __be16 max_brst_len; 2131 __be16 r4; 2132 __be16 def_time2wait; 2133 __be16 def_time2ret; 2134 __be16 nop_out_intrvl; 2135 __be16 non_scsi_to; 2136 __be16 isid; 2137 __be16 tsid; 2138 __be16 port; 2139 __be16 tpgt; 2140 __u8 r5[6]; 2141 __be16 iqid; 2142 } iscsi_rdev; 2143 } u; 2144 }; 2145 2146 #define S_FW_RDEV_WR_IMMDLEN 0 2147 #define M_FW_RDEV_WR_IMMDLEN 0xff 2148 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 2149 #define G_FW_RDEV_WR_IMMDLEN(x) \ 2150 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 2151 2152 #define S_FW_RDEV_WR_ALLOC 31 2153 #define M_FW_RDEV_WR_ALLOC 0x1 2154 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 2155 #define G_FW_RDEV_WR_ALLOC(x) \ 2156 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 2157 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 2158 2159 #define S_FW_RDEV_WR_FREE 30 2160 #define M_FW_RDEV_WR_FREE 0x1 2161 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 2162 #define G_FW_RDEV_WR_FREE(x) \ 2163 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 2164 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 2165 2166 #define S_FW_RDEV_WR_MODIFY 29 2167 #define M_FW_RDEV_WR_MODIFY 0x1 2168 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 2169 #define G_FW_RDEV_WR_MODIFY(x) \ 2170 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 2171 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 2172 2173 #define S_FW_RDEV_WR_FLOWID 8 2174 #define M_FW_RDEV_WR_FLOWID 0xfffff 2175 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 2176 #define G_FW_RDEV_WR_FLOWID(x) \ 2177 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 2178 2179 #define S_FW_RDEV_WR_LEN16 0 2180 #define M_FW_RDEV_WR_LEN16 0xff 2181 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 2182 #define G_FW_RDEV_WR_LEN16(x) \ 2183 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 2184 2185 #define S_FW_RDEV_WR_FLAGS 24 2186 #define M_FW_RDEV_WR_FLAGS 0xff 2187 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 2188 #define G_FW_RDEV_WR_FLAGS(x) \ 2189 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 2190 2191 #define S_FW_RDEV_WR_GET_NEXT 20 2192 #define M_FW_RDEV_WR_GET_NEXT 0xf 2193 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 2194 #define G_FW_RDEV_WR_GET_NEXT(x) \ 2195 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 2196 2197 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 2198 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 2199 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 2200 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 2201 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 2202 2203 #define S_FW_RDEV_WR_RJT 7 2204 #define M_FW_RDEV_WR_RJT 0x1 2205 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 2206 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 2207 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 2208 2209 #define S_FW_RDEV_WR_REASON 0 2210 #define M_FW_RDEV_WR_REASON 0x7f 2211 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 2212 #define G_FW_RDEV_WR_REASON(x) \ 2213 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 2214 2215 #define S_FW_RDEV_WR_RD_XFER_RDY 7 2216 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 2217 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 2218 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 2219 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 2220 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 2221 2222 #define S_FW_RDEV_WR_WR_XFER_RDY 6 2223 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 2224 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 2225 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 2226 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 2227 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 2228 2229 #define S_FW_RDEV_WR_FC_SP 5 2230 #define M_FW_RDEV_WR_FC_SP 0x1 2231 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 2232 #define G_FW_RDEV_WR_FC_SP(x) \ 2233 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 2234 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 2235 2236 #define S_FW_RDEV_WR_RPORT_TYPE 0 2237 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 2238 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 2239 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 2240 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 2241 2242 #define S_FW_RDEV_WR_VFT 7 2243 #define M_FW_RDEV_WR_VFT 0x1 2244 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2245 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2246 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2247 2248 #define S_FW_RDEV_WR_NPIV 6 2249 #define M_FW_RDEV_WR_NPIV 0x1 2250 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2251 #define G_FW_RDEV_WR_NPIV(x) \ 2252 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2253 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2254 2255 #define S_FW_RDEV_WR_CLASS 4 2256 #define M_FW_RDEV_WR_CLASS 0x3 2257 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2258 #define G_FW_RDEV_WR_CLASS(x) \ 2259 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2260 2261 #define S_FW_RDEV_WR_SEQ_DEL 3 2262 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2263 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2264 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2265 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2266 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2267 2268 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2269 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2270 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2271 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2272 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2273 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2274 2275 #define S_FW_RDEV_WR_PREF 1 2276 #define M_FW_RDEV_WR_PREF 0x1 2277 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2278 #define G_FW_RDEV_WR_PREF(x) \ 2279 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2280 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2281 2282 #define S_FW_RDEV_WR_QOS 0 2283 #define M_FW_RDEV_WR_QOS 0x1 2284 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2285 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2286 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2287 2288 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2289 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2290 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2291 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2292 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2293 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2294 2295 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2296 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2297 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2298 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2299 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2300 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2301 2302 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2303 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2304 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2305 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2306 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2307 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2308 2309 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2310 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2311 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2312 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2313 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2314 2315 #define S_FW_RDEV_WR_ENH_DISC 7 2316 #define M_FW_RDEV_WR_ENH_DISC 0x1 2317 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2318 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2319 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2320 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2321 2322 #define S_FW_RDEV_WR_REC 6 2323 #define M_FW_RDEV_WR_REC 0x1 2324 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2325 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2326 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2327 2328 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2329 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2330 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2331 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2332 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2333 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2334 2335 #define S_FW_RDEV_WR_RETRY 4 2336 #define M_FW_RDEV_WR_RETRY 0x1 2337 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2338 #define G_FW_RDEV_WR_RETRY(x) \ 2339 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2340 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2341 2342 #define S_FW_RDEV_WR_CONF_CMPL 3 2343 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2344 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2345 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2346 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2347 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2348 2349 #define S_FW_RDEV_WR_DATA_OVLY 2 2350 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2351 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2352 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2353 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2354 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2355 2356 #define S_FW_RDEV_WR_INI 1 2357 #define M_FW_RDEV_WR_INI 0x1 2358 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2359 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2360 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2361 2362 #define S_FW_RDEV_WR_TGT 0 2363 #define M_FW_RDEV_WR_TGT 0x1 2364 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2365 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2366 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2367 2368 struct fw_foiscsi_node_wr { 2369 __be32 op_to_immdlen; 2370 __be32 flowid_len16; 2371 __u64 cookie; 2372 __u8 subop; 2373 __u8 status; 2374 __u8 alias_len; 2375 __u8 iqn_len; 2376 __be32 node_flowid; 2377 __be16 nodeid; 2378 __be16 login_retry; 2379 __be16 retry_timeout; 2380 __be16 r3; 2381 __u8 iqn[224]; 2382 __u8 alias[224]; 2383 }; 2384 2385 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2386 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2387 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2388 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2389 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2390 2391 struct fw_foiscsi_ctrl_wr { 2392 __be32 op_compl; 2393 __be32 flowid_len16; 2394 __u64 cookie; 2395 __u8 subop; 2396 __u8 status; 2397 __u8 ctrl_state; 2398 __u8 io_state; 2399 __be32 node_id; 2400 __be32 ctrl_id; 2401 __be32 io_id; 2402 struct fw_foiscsi_sess_attr { 2403 __be32 sess_type_to_erl; 2404 __be16 max_conn; 2405 __be16 max_r2t; 2406 __be16 time2wait; 2407 __be16 time2retain; 2408 __be32 max_burst; 2409 __be32 first_burst; 2410 __be32 r1; 2411 } sess_attr; 2412 struct fw_foiscsi_conn_attr { 2413 __be32 hdigest_to_ddp_pgsz; 2414 __be32 max_rcv_dsl; 2415 __be32 ping_tmo; 2416 __be16 dst_port; 2417 __be16 src_port; 2418 union fw_foiscsi_conn_attr_addr { 2419 struct fw_foiscsi_conn_attr_ipv6 { 2420 __be64 dst_addr[2]; 2421 __be64 src_addr[2]; 2422 } ipv6_addr; 2423 struct fw_foiscsi_conn_attr_ipv4 { 2424 __be32 dst_addr; 2425 __be32 src_addr; 2426 } ipv4_addr; 2427 } u; 2428 } conn_attr; 2429 __u8 tgt_name_len; 2430 __u8 r3[7]; 2431 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2432 }; 2433 2434 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2435 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2436 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2437 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2438 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2439 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2440 2441 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2442 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2443 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2444 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2445 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2446 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2447 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2448 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2449 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2450 2451 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2452 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2453 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2454 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2455 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2456 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2457 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2458 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2459 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2460 2461 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2462 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2463 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2464 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2465 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2466 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2467 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2468 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2469 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2470 2471 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2472 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2473 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2474 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2475 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2476 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2477 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2478 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2479 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2480 2481 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2482 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2483 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2484 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2485 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2486 2487 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2488 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2489 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2490 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2491 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2492 2493 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2494 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2495 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2496 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2497 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2498 2499 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2500 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2501 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2502 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2503 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2504 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2505 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2506 2507 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2508 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2509 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2510 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2511 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2512 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2513 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2514 2515 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2516 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2517 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2518 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2519 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2520 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2521 2522 #define S_FW_FOISCSI_CTRL_WR_IPV6 20 2523 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 2524 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 2525 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 2526 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 2527 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 2528 2529 struct fw_foiscsi_chap_wr { 2530 __be32 op_compl; 2531 __be32 flowid_len16; 2532 __u64 cookie; 2533 __u8 status; 2534 __u8 id_len; 2535 __u8 sec_len; 2536 __u8 node_type; 2537 __be16 node_id; 2538 __u8 r3[2]; 2539 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2540 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 2541 }; 2542 2543 /****************************************************************************** 2544 * C O i S C S I W O R K R E Q U E S T S 2545 ********************************************/ 2546 2547 enum fw_chnet_addr_type { 2548 FW_CHNET_ADDD_TYPE_NONE = 0, 2549 FW_CHNET_ADDR_TYPE_IPV4, 2550 FW_CHNET_ADDR_TYPE_IPV6, 2551 }; 2552 2553 enum fw_msg_wr_type { 2554 FW_MSG_WR_TYPE_RPL = 0, 2555 FW_MSG_WR_TYPE_ERR, 2556 FW_MSG_WR_TYPE_PLD, 2557 }; 2558 2559 struct fw_coiscsi_tgt_wr { 2560 __be32 op_compl; 2561 __be32 flowid_len16; 2562 __u64 cookie; 2563 __u8 subop; 2564 __u8 status; 2565 __be16 r4; 2566 __be32 flags; 2567 struct fw_coiscsi_tgt_conn_attr { 2568 __be32 in_tid; 2569 __be16 in_port; 2570 __u8 in_type; 2571 __u8 r6; 2572 union fw_coiscsi_tgt_conn_attr_addr { 2573 struct fw_coiscsi_tgt_conn_attr_in_addr { 2574 __be32 addr; 2575 __be32 r7; 2576 __be32 r8[2]; 2577 } in_addr; 2578 struct fw_coiscsi_tgt_conn_attr_in_addr6 { 2579 __be64 addr[2]; 2580 } in_addr6; 2581 } u; 2582 } conn_attr; 2583 }; 2584 2585 struct fw_coiscsi_tgt_conn_wr { 2586 __be32 op_compl; 2587 __be32 flowid_len16; 2588 __u64 cookie; 2589 __u8 subop; 2590 __u8 status; 2591 __be16 iq_id; 2592 __be32 in_stid; 2593 __be32 io_id; 2594 __be32 flags; 2595 struct fw_coiscsi_tgt_conn_tcp { 2596 __be16 in_sport; 2597 __be16 in_dport; 2598 __be32 r4; 2599 union fw_coiscsi_tgt_conn_tcp_addr { 2600 struct fw_coiscsi_tgt_conn_tcp_in_addr { 2601 __be32 saddr; 2602 __be32 daddr; 2603 } in_addr; 2604 struct fw_coiscsi_tgt_conn_tcp_in_addr6 { 2605 __be64 saddr[2]; 2606 __be64 daddr[2]; 2607 } in_addr6; 2608 } u; 2609 } conn_tcp; 2610 struct fw_coiscsi_tgt_conn_iscsi { 2611 __be32 hdigest_to_ddp_pgsz; 2612 __be32 tgt_id; 2613 __be16 max_r2t; 2614 __be16 r5; 2615 __be32 max_burst; 2616 __be32 max_rdsl; 2617 __be32 max_tdsl; 2618 __be32 nxt_sn; 2619 __be32 r6; 2620 } conn_iscsi; 2621 }; 2622 2623 struct fw_coiscsi_tgt_xmit_wr { 2624 __be32 op_to_immdlen; 2625 __be32 flowid_len16; 2626 __be64 cookie; 2627 __be16 iq_id; 2628 __be16 r4; 2629 __be32 datasn; 2630 __be32 t_xfer_len; 2631 __be32 flags; 2632 __be32 tag; 2633 __be32 tidx; 2634 __be32 r5[2]; 2635 }; 2636 2637 #define S_FW_COiSCSI_TGT_XMIT_WR_DDGST 23 2638 #define M_FW_COiSCSI_TGT_XMIT_WR_DDGST 0x1 2639 #define V_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2640 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2641 #define G_FW_COiSCSI_TGT_XMIT_WR_DDGST(x) \ 2642 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDGST) & M_FW_COiSCSI_TGT_XMIT_WR_DDGST) 2643 #define F_FW_COiSCSI_TGT_XMIT_WR_DDGST V_FW_COiSCSI_TGT_XMIT_WR_DDGST(1U) 2644 2645 #define S_FW_COiSCSI_TGT_XMIT_WR_HDGST 22 2646 #define M_FW_COiSCSI_TGT_XMIT_WR_HDGST 0x1 2647 #define V_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2648 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2649 #define G_FW_COiSCSI_TGT_XMIT_WR_HDGST(x) \ 2650 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_HDGST) & M_FW_COiSCSI_TGT_XMIT_WR_HDGST) 2651 #define F_FW_COiSCSI_TGT_XMIT_WR_HDGST V_FW_COiSCSI_TGT_XMIT_WR_HDGST(1U) 2652 2653 #define S_FW_COiSCSI_TGT_XMIT_WR_DDP 20 2654 #define M_FW_COiSCSI_TGT_XMIT_WR_DDP 0x1 2655 #define V_FW_COiSCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COiSCSI_TGT_XMIT_WR_DDP) 2656 #define G_FW_COiSCSI_TGT_XMIT_WR_DDP(x) \ 2657 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_DDP) & M_FW_COiSCSI_TGT_XMIT_WR_DDP) 2658 #define F_FW_COiSCSI_TGT_XMIT_WR_DDP V_FW_COiSCSI_TGT_XMIT_WR_DDP(1U) 2659 2660 #define S_FW_COiSCSI_TGT_XMIT_WR_ABORT 19 2661 #define M_FW_COiSCSI_TGT_XMIT_WR_ABORT 0x1 2662 #define V_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 2663 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_ABORT) 2664 #define G_FW_COiSCSI_TGT_XMIT_WR_ABORT(x) \ 2665 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_ABORT) & M_FW_COiSCSI_TGT_XMIT_WR_ABORT) 2666 #define F_FW_COiSCSI_TGT_XMIT_WR_ABORT V_FW_COiSCSI_TGT_XMIT_WR_ABORT(1U) 2667 2668 #define S_FW_COiSCSI_TGT_XMIT_WR_FINAL 18 2669 #define M_FW_COiSCSI_TGT_XMIT_WR_FINAL 0x1 2670 #define V_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 2671 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_FINAL) 2672 #define G_FW_COiSCSI_TGT_XMIT_WR_FINAL(x) \ 2673 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_FINAL) & M_FW_COiSCSI_TGT_XMIT_WR_FINAL) 2674 #define F_FW_COiSCSI_TGT_XMIT_WR_FINAL V_FW_COiSCSI_TGT_XMIT_WR_FINAL(1U) 2675 2676 #define S_FW_COiSCSI_TGT_XMIT_WR_PADLEN 16 2677 #define M_FW_COiSCSI_TGT_XMIT_WR_PADLEN 0x3 2678 #define V_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 2679 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 2680 #define G_FW_COiSCSI_TGT_XMIT_WR_PADLEN(x) \ 2681 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_PADLEN) & \ 2682 M_FW_COiSCSI_TGT_XMIT_WR_PADLEN) 2683 2684 #define S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0 2685 #define M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN 0xff 2686 #define V_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2687 ((x) << S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2688 #define G_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2689 (((x) >> S_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) & \ 2690 M_FW_COiSCSI_TGT_XMIT_WR_IMMDLEN) 2691 2692 struct fw_isns_wr { 2693 __be32 op_compl; 2694 __be32 flowid_len16; 2695 __u64 cookie; 2696 __u8 subop; 2697 __u8 status; 2698 __be16 iq_id; 2699 __be32 r4; 2700 struct fw_tcp_conn_attr { 2701 __be32 in_tid; 2702 __be16 in_port; 2703 __u8 in_type; 2704 __u8 r6; 2705 union fw_tcp_conn_attr_addr { 2706 struct fw_tcp_conn_attr_in_addr { 2707 __be32 addr; 2708 __be32 r7; 2709 __be32 r8[2]; 2710 } in_addr; 2711 struct fw_tcp_conn_attr_in_addr6 { 2712 __be64 addr[2]; 2713 } in_addr6; 2714 } u; 2715 } conn_attr; 2716 }; 2717 2718 struct fw_isns_xmit_wr { 2719 __be32 op_to_immdlen; 2720 __be32 flowid_len16; 2721 __be64 cookie; 2722 __be16 iq_id; 2723 __be16 r4; 2724 __be32 xfer_len; 2725 __be64 r5; 2726 }; 2727 2728 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0 2729 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 2730 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 2731 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 2732 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 2733 2734 /****************************************************************************** 2735 * F O F C O E W O R K R E Q U E S T s 2736 *******************************************/ 2737 2738 struct fw_fcoe_els_ct_wr { 2739 __be32 op_immdlen; 2740 __be32 flowid_len16; 2741 __be64 cookie; 2742 __be16 iqid; 2743 __u8 tmo_val; 2744 __u8 els_ct_type; 2745 __u8 ctl_pri; 2746 __u8 cp_en_class; 2747 __be16 xfer_cnt; 2748 __u8 fl_to_sp; 2749 __u8 l_id[3]; 2750 __u8 r5; 2751 __u8 r_id[3]; 2752 __be64 rsp_dmaaddr; 2753 __be32 rsp_dmalen; 2754 __be32 r6; 2755 }; 2756 2757 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2758 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2759 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2760 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2761 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2762 2763 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2764 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2765 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2766 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2767 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2768 2769 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2770 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2771 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2772 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2773 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2774 2775 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 2776 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2777 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2778 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2779 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2780 2781 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2782 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2783 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2784 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2785 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2786 2787 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 2788 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2789 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2790 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2791 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2792 2793 #define S_FW_FCOE_ELS_CT_WR_FL 2 2794 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 2795 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2796 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2797 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2798 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2799 2800 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 2801 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2802 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2803 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2804 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2805 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2806 2807 #define S_FW_FCOE_ELS_CT_WR_SP 0 2808 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 2809 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2810 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2811 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2812 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2813 2814 /****************************************************************************** 2815 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2816 *****************************************************************************/ 2817 2818 struct fw_scsi_write_wr { 2819 __be32 op_immdlen; 2820 __be32 flowid_len16; 2821 __be64 cookie; 2822 __be16 iqid; 2823 __u8 tmo_val; 2824 __u8 use_xfer_cnt; 2825 union fw_scsi_write_priv { 2826 struct fcoe_write_priv { 2827 __u8 ctl_pri; 2828 __u8 cp_en_class; 2829 __u8 r3_lo[2]; 2830 } fcoe; 2831 struct iscsi_write_priv { 2832 __u8 r3[4]; 2833 } iscsi; 2834 } u; 2835 __be32 xfer_cnt; 2836 __be32 ini_xfer_cnt; 2837 __be64 rsp_dmaaddr; 2838 __be32 rsp_dmalen; 2839 __be32 r4; 2840 }; 2841 2842 #define S_FW_SCSI_WRITE_WR_OPCODE 24 2843 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2844 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2845 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2846 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2847 2848 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2849 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2850 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2851 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2852 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2853 2854 #define S_FW_SCSI_WRITE_WR_FLOWID 8 2855 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2856 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2857 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2858 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2859 2860 #define S_FW_SCSI_WRITE_WR_LEN16 0 2861 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 2862 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2863 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2864 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2865 2866 #define S_FW_SCSI_WRITE_WR_CP_EN 6 2867 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2868 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2869 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2870 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2871 2872 #define S_FW_SCSI_WRITE_WR_CLASS 4 2873 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 2874 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2875 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2876 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 2877 2878 struct fw_scsi_read_wr { 2879 __be32 op_immdlen; 2880 __be32 flowid_len16; 2881 __be64 cookie; 2882 __be16 iqid; 2883 __u8 tmo_val; 2884 __u8 use_xfer_cnt; 2885 union fw_scsi_read_priv { 2886 struct fcoe_read_priv { 2887 __u8 ctl_pri; 2888 __u8 cp_en_class; 2889 __u8 r3_lo[2]; 2890 } fcoe; 2891 struct iscsi_read_priv { 2892 __u8 r3[4]; 2893 } iscsi; 2894 } u; 2895 __be32 xfer_cnt; 2896 __be32 ini_xfer_cnt; 2897 __be64 rsp_dmaaddr; 2898 __be32 rsp_dmalen; 2899 __be32 r4; 2900 }; 2901 2902 #define S_FW_SCSI_READ_WR_OPCODE 24 2903 #define M_FW_SCSI_READ_WR_OPCODE 0xff 2904 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2905 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 2906 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2907 2908 #define S_FW_SCSI_READ_WR_IMMDLEN 0 2909 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2910 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2911 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2912 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2913 2914 #define S_FW_SCSI_READ_WR_FLOWID 8 2915 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2916 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2917 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 2918 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2919 2920 #define S_FW_SCSI_READ_WR_LEN16 0 2921 #define M_FW_SCSI_READ_WR_LEN16 0xff 2922 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2923 #define G_FW_SCSI_READ_WR_LEN16(x) \ 2924 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2925 2926 #define S_FW_SCSI_READ_WR_CP_EN 6 2927 #define M_FW_SCSI_READ_WR_CP_EN 0x3 2928 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2929 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 2930 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 2931 2932 #define S_FW_SCSI_READ_WR_CLASS 4 2933 #define M_FW_SCSI_READ_WR_CLASS 0x3 2934 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 2935 #define G_FW_SCSI_READ_WR_CLASS(x) \ 2936 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 2937 2938 struct fw_scsi_cmd_wr { 2939 __be32 op_immdlen; 2940 __be32 flowid_len16; 2941 __be64 cookie; 2942 __be16 iqid; 2943 __u8 tmo_val; 2944 __u8 r3; 2945 union fw_scsi_cmd_priv { 2946 struct fcoe_cmd_priv { 2947 __u8 ctl_pri; 2948 __u8 cp_en_class; 2949 __u8 r4_lo[2]; 2950 } fcoe; 2951 struct iscsi_cmd_priv { 2952 __u8 r4[4]; 2953 } iscsi; 2954 } u; 2955 __u8 r5[8]; 2956 __be64 rsp_dmaaddr; 2957 __be32 rsp_dmalen; 2958 __be32 r6; 2959 }; 2960 2961 #define S_FW_SCSI_CMD_WR_OPCODE 24 2962 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 2963 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 2964 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 2965 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 2966 2967 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 2968 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 2969 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 2970 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 2971 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 2972 2973 #define S_FW_SCSI_CMD_WR_FLOWID 8 2974 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 2975 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 2976 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 2977 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 2978 2979 #define S_FW_SCSI_CMD_WR_LEN16 0 2980 #define M_FW_SCSI_CMD_WR_LEN16 0xff 2981 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 2982 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 2983 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 2984 2985 #define S_FW_SCSI_CMD_WR_CP_EN 6 2986 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 2987 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 2988 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 2989 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 2990 2991 #define S_FW_SCSI_CMD_WR_CLASS 4 2992 #define M_FW_SCSI_CMD_WR_CLASS 0x3 2993 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 2994 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 2995 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 2996 2997 struct fw_scsi_abrt_cls_wr { 2998 __be32 op_immdlen; 2999 __be32 flowid_len16; 3000 __be64 cookie; 3001 __be16 iqid; 3002 __u8 tmo_val; 3003 __u8 sub_opcode_to_chk_all_io; 3004 __u8 r3[4]; 3005 __be64 t_cookie; 3006 }; 3007 3008 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 3009 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 3010 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 3011 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 3012 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 3013 3014 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 3015 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 3016 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3017 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3018 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 3019 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 3020 3021 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 3022 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 3023 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 3024 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 3025 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 3026 3027 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 3028 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 3029 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 3030 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 3031 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 3032 3033 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 3034 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 3035 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3036 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3037 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 3038 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 3039 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 3040 3041 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 3042 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 3043 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 3044 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 3045 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 3046 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 3047 3048 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 3049 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 3050 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3051 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3052 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 3053 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 3054 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 3055 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 3056 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 3057 3058 struct fw_scsi_tgt_acc_wr { 3059 __be32 op_immdlen; 3060 __be32 flowid_len16; 3061 __be64 cookie; 3062 __be16 iqid; 3063 __u8 r3; 3064 __u8 use_burst_len; 3065 union fw_scsi_tgt_acc_priv { 3066 struct fcoe_tgt_acc_priv { 3067 __u8 ctl_pri; 3068 __u8 cp_en_class; 3069 __u8 r4_lo[2]; 3070 } fcoe; 3071 struct iscsi_tgt_acc_priv { 3072 __u8 r4[4]; 3073 } iscsi; 3074 } u; 3075 __be32 burst_len; 3076 __be32 rel_off; 3077 __be64 r5; 3078 __be32 r6; 3079 __be32 tot_xfer_len; 3080 }; 3081 3082 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 3083 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 3084 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 3085 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 3086 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 3087 3088 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 3089 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 3090 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3091 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 3092 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 3093 3094 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 3095 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 3096 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 3097 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 3098 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 3099 3100 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 3101 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 3102 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 3103 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 3104 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 3105 3106 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 3107 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 3108 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 3109 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 3110 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 3111 3112 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 3113 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 3114 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 3115 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 3116 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 3117 3118 struct fw_scsi_tgt_xmit_wr { 3119 __be32 op_immdlen; 3120 __be32 flowid_len16; 3121 __be64 cookie; 3122 __be16 iqid; 3123 __u8 auto_rsp; 3124 __u8 use_xfer_cnt; 3125 union fw_scsi_tgt_xmit_priv { 3126 struct fcoe_tgt_xmit_priv { 3127 __u8 ctl_pri; 3128 __u8 cp_en_class; 3129 __u8 r3_lo[2]; 3130 } fcoe; 3131 struct iscsi_tgt_xmit_priv { 3132 __u8 r3[4]; 3133 } iscsi; 3134 } u; 3135 __be32 xfer_cnt; 3136 __be32 r4; 3137 __be64 r5; 3138 __be32 r6; 3139 __be32 tot_xfer_len; 3140 }; 3141 3142 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 3143 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 3144 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 3145 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 3146 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 3147 3148 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 3149 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 3150 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3151 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3152 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 3153 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 3154 3155 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 3156 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 3157 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 3158 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 3159 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 3160 3161 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 3162 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 3163 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 3164 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 3165 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 3166 3167 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 3168 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 3169 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 3170 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 3171 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 3172 3173 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 3174 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 3175 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 3176 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 3177 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 3178 3179 struct fw_scsi_tgt_rsp_wr { 3180 __be32 op_immdlen; 3181 __be32 flowid_len16; 3182 __be64 cookie; 3183 __be16 iqid; 3184 __u8 r3[2]; 3185 union fw_scsi_tgt_rsp_priv { 3186 struct fcoe_tgt_rsp_priv { 3187 __u8 ctl_pri; 3188 __u8 cp_en_class; 3189 __u8 r4_lo[2]; 3190 } fcoe; 3191 struct iscsi_tgt_rsp_priv { 3192 __u8 r4[4]; 3193 } iscsi; 3194 } u; 3195 __u8 r5[8]; 3196 }; 3197 3198 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 3199 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 3200 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 3201 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 3202 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 3203 3204 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 3205 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 3206 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3207 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 3208 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 3209 3210 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 3211 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 3212 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 3213 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 3214 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 3215 3216 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 3217 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 3218 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 3219 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 3220 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 3221 3222 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 3223 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 3224 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 3225 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 3226 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 3227 3228 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 3229 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 3230 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 3231 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 3232 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 3233 3234 struct fw_pofcoe_tcb_wr { 3235 __be32 op_compl; 3236 __be32 equiq_to_len16; 3237 __be32 r4; 3238 __be32 xfer_len; 3239 __be32 tid_to_port; 3240 __be16 x_id; 3241 __be16 vlan_id; 3242 __be64 cookie; 3243 __be32 s_id; 3244 __be32 d_id; 3245 __be32 tag; 3246 __be16 r6; 3247 __be16 iqid; 3248 }; 3249 3250 #define S_FW_POFCOE_TCB_WR_TID 12 3251 #define M_FW_POFCOE_TCB_WR_TID 0xfffff 3252 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 3253 #define G_FW_POFCOE_TCB_WR_TID(x) \ 3254 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 3255 3256 #define S_FW_POFCOE_TCB_WR_ALLOC 4 3257 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 3258 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 3259 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 3260 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 3261 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 3262 3263 #define S_FW_POFCOE_TCB_WR_FREE 3 3264 #define M_FW_POFCOE_TCB_WR_FREE 0x1 3265 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 3266 #define G_FW_POFCOE_TCB_WR_FREE(x) \ 3267 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 3268 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 3269 3270 #define S_FW_POFCOE_TCB_WR_PORT 0 3271 #define M_FW_POFCOE_TCB_WR_PORT 0x7 3272 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 3273 #define G_FW_POFCOE_TCB_WR_PORT(x) \ 3274 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 3275 3276 struct fw_pofcoe_ulptx_wr { 3277 __be32 op_pkd; 3278 __be32 equiq_to_len16; 3279 __u64 cookie; 3280 }; 3281 3282 /******************************************************************* 3283 * T10 DIF related definition 3284 *******************************************************************/ 3285 struct fw_tx_pi_header { 3286 __be16 op_to_inline; 3287 __u8 pi_interval_tag_type; 3288 __u8 num_pi; 3289 __be32 pi_start4_pi_end4; 3290 __u8 tag_gen_enabled_pkd; 3291 __u8 num_pi_dsg; 3292 __be16 app_tag; 3293 __be32 ref_tag; 3294 }; 3295 3296 #define S_FW_TX_PI_HEADER_OP 8 3297 #define M_FW_TX_PI_HEADER_OP 0xff 3298 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 3299 #define G_FW_TX_PI_HEADER_OP(x) \ 3300 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 3301 3302 #define S_FW_TX_PI_HEADER_ULPTXMORE 7 3303 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 3304 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 3305 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 3306 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 3307 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 3308 3309 #define S_FW_TX_PI_HEADER_PI_CONTROL 4 3310 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 3311 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 3312 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 3313 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 3314 3315 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2 3316 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 3317 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 3318 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 3319 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 3320 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 3321 3322 #define S_FW_TX_PI_HEADER_VALIDATE 1 3323 #define M_FW_TX_PI_HEADER_VALIDATE 0x1 3324 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 3325 #define G_FW_TX_PI_HEADER_VALIDATE(x) \ 3326 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 3327 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 3328 3329 #define S_FW_TX_PI_HEADER_INLINE 0 3330 #define M_FW_TX_PI_HEADER_INLINE 0x1 3331 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 3332 #define G_FW_TX_PI_HEADER_INLINE(x) \ 3333 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 3334 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 3335 3336 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7 3337 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 3338 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3339 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 3340 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 3341 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 3342 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 3343 3344 #define S_FW_TX_PI_HEADER_TAG_TYPE 5 3345 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 3346 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 3347 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 3348 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 3349 3350 #define S_FW_TX_PI_HEADER_PI_START4 22 3351 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff 3352 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 3353 #define G_FW_TX_PI_HEADER_PI_START4(x) \ 3354 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 3355 3356 #define S_FW_TX_PI_HEADER_PI_END4 0 3357 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 3358 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 3359 #define G_FW_TX_PI_HEADER_PI_END4(x) \ 3360 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 3361 3362 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 3363 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 3364 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3365 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3366 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 3367 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 3368 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 3369 3370 enum fw_pi_error_type { 3371 FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 3372 }; 3373 3374 struct fw_pi_error { 3375 __be32 err_type_pkd; 3376 __be32 flowid_len16; 3377 __be16 r2; 3378 __be16 app_tag; 3379 __be32 ref_tag; 3380 __be32 pisc[4]; 3381 }; 3382 3383 #define S_FW_PI_ERROR_ERR_TYPE 24 3384 #define M_FW_PI_ERROR_ERR_TYPE 0xff 3385 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 3386 #define G_FW_PI_ERROR_ERR_TYPE(x) \ 3387 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 3388 3389 struct fw_tlstx_data_wr { 3390 __be32 op_to_immdlen; 3391 __be32 flowid_len16; 3392 __be32 plen; 3393 __be32 lsodisable_to_flags; 3394 __be32 ddraddr; 3395 __be32 ctxloc_to_exp; 3396 __be16 mfs; 3397 __u8 r6[6]; 3398 }; 3399 3400 #define S_FW_TLSTX_DATA_WR_COMPL 21 3401 #define M_FW_TLSTX_DATA_WR_COMPL 0x1 3402 #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL) 3403 #define G_FW_TLSTX_DATA_WR_COMPL(x) \ 3404 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL) 3405 #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U) 3406 3407 #define S_FW_TLSTX_DATA_WR_IMMDLEN 0 3408 #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff 3409 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN) 3410 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \ 3411 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN) 3412 3413 #define S_FW_TLSTX_DATA_WR_FLOWID 8 3414 #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff 3415 #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID) 3416 #define G_FW_TLSTX_DATA_WR_FLOWID(x) \ 3417 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID) 3418 3419 #define S_FW_TLSTX_DATA_WR_LEN16 0 3420 #define M_FW_TLSTX_DATA_WR_LEN16 0xff 3421 #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16) 3422 #define G_FW_TLSTX_DATA_WR_LEN16(x) \ 3423 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16) 3424 3425 #define S_FW_TLSTX_DATA_WR_LSODISABLE 31 3426 #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1 3427 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3428 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE) 3429 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 3430 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE) 3431 #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U) 3432 3433 #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30 3434 #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1 3435 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD) 3436 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \ 3437 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD) 3438 #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U) 3439 3440 #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29 3441 #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1 3442 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3443 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3444 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 3445 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \ 3446 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 3447 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U) 3448 3449 #define S_FW_TLSTX_DATA_WR_FLAGS 0 3450 #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff 3451 #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS) 3452 #define G_FW_TLSTX_DATA_WR_FLAGS(x) \ 3453 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS) 3454 3455 #define S_FW_TLSTX_DATA_WR_CTXLOC 30 3456 #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3 3457 #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC) 3458 #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \ 3459 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC) 3460 3461 #define S_FW_TLSTX_DATA_WR_IVDSGL 29 3462 #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1 3463 #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL) 3464 #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \ 3465 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL) 3466 #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U) 3467 3468 #define S_FW_TLSTX_DATA_WR_KEYSIZE 24 3469 #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f 3470 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE) 3471 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \ 3472 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE) 3473 3474 #define S_FW_TLSTX_DATA_WR_NUMIVS 14 3475 #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff 3476 #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS) 3477 #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \ 3478 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS) 3479 3480 #define S_FW_TLSTX_DATA_WR_EXP 0 3481 #define M_FW_TLSTX_DATA_WR_EXP 0x3fff 3482 #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP) 3483 #define G_FW_TLSTX_DATA_WR_EXP(x) \ 3484 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP) 3485 3486 struct fw_tls_keyctx_tx_wr { 3487 __be32 op_to_compl; 3488 __be32 flowid_len16; 3489 union fw_key_ctx { 3490 struct fw_tx_keyctx_hdr { 3491 __u8 ctxlen; 3492 __u8 r2; 3493 __be16 dualck_to_txvalid; 3494 __u8 txsalt[4]; 3495 __be64 r5; 3496 } txhdr; 3497 struct fw_rx_keyctx_hdr { 3498 __u8 flitcnt_hmacctrl; 3499 __u8 protover_ciphmode; 3500 __u8 authmode_to_rxvalid; 3501 __u8 ivpresent_to_rxmk_size; 3502 __u8 rxsalt[4]; 3503 __be64 ivinsert_to_authinsrt; 3504 } rxhdr; 3505 struct fw_keyctx_clear { 3506 __be32 tx_key; 3507 __be32 rx_key; 3508 } kctx_clr; 3509 } u; 3510 struct keys { 3511 __u8 edkey[32]; 3512 __u8 ipad[64]; 3513 __u8 opad[64]; 3514 } keys; 3515 __u8 reneg_to_write_rx; 3516 __u8 protocol; 3517 __u8 r7[2]; 3518 __be32 ftid; 3519 }; 3520 3521 #define S_FW_TLS_KEYCTX_TX_WR_OPCODE 24 3522 #define M_FW_TLS_KEYCTX_TX_WR_OPCODE 0xff 3523 #define V_FW_TLS_KEYCTX_TX_WR_OPCODE(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_OPCODE) 3524 #define G_FW_TLS_KEYCTX_TX_WR_OPCODE(x) \ 3525 (((x) >> S_FW_TLS_KEYCTX_TX_WR_OPCODE) & M_FW_TLS_KEYCTX_TX_WR_OPCODE) 3526 3527 #define S_FW_TLS_KEYCTX_TX_WR_ATOMIC 23 3528 #define M_FW_TLS_KEYCTX_TX_WR_ATOMIC 0x1 3529 #define V_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_ATOMIC) 3530 #define G_FW_TLS_KEYCTX_TX_WR_ATOMIC(x) \ 3531 (((x) >> S_FW_TLS_KEYCTX_TX_WR_ATOMIC) & M_FW_TLS_KEYCTX_TX_WR_ATOMIC) 3532 #define F_FW_TLS_KEYCTX_TX_WR_ATOMIC V_FW_TLS_KEYCTX_TX_WR_ATOMIC(1U) 3533 3534 #define S_FW_TLS_KEYCTX_TX_WR_FLUSH 22 3535 #define M_FW_TLS_KEYCTX_TX_WR_FLUSH 0x1 3536 #define V_FW_TLS_KEYCTX_TX_WR_FLUSH(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLUSH) 3537 #define G_FW_TLS_KEYCTX_TX_WR_FLUSH(x) \ 3538 (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLUSH) & M_FW_TLS_KEYCTX_TX_WR_FLUSH) 3539 #define F_FW_TLS_KEYCTX_TX_WR_FLUSH V_FW_TLS_KEYCTX_TX_WR_FLUSH(1U) 3540 3541 #define S_FW_TLS_KEYCTX_TX_WR_COMPL 21 3542 #define M_FW_TLS_KEYCTX_TX_WR_COMPL 0x1 3543 #define V_FW_TLS_KEYCTX_TX_WR_COMPL(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_COMPL) 3544 #define G_FW_TLS_KEYCTX_TX_WR_COMPL(x) \ 3545 (((x) >> S_FW_TLS_KEYCTX_TX_WR_COMPL) & M_FW_TLS_KEYCTX_TX_WR_COMPL) 3546 #define F_FW_TLS_KEYCTX_TX_WR_COMPL V_FW_TLS_KEYCTX_TX_WR_COMPL(1U) 3547 3548 #define S_FW_TLS_KEYCTX_TX_WR_FLOWID 8 3549 #define M_FW_TLS_KEYCTX_TX_WR_FLOWID 0xfffff 3550 #define V_FW_TLS_KEYCTX_TX_WR_FLOWID(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_FLOWID) 3551 #define G_FW_TLS_KEYCTX_TX_WR_FLOWID(x) \ 3552 (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLOWID) & M_FW_TLS_KEYCTX_TX_WR_FLOWID) 3553 3554 #define S_FW_TLS_KEYCTX_TX_WR_LEN16 0 3555 #define M_FW_TLS_KEYCTX_TX_WR_LEN16 0xff 3556 #define V_FW_TLS_KEYCTX_TX_WR_LEN16(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_LEN16) 3557 #define G_FW_TLS_KEYCTX_TX_WR_LEN16(x) \ 3558 (((x) >> S_FW_TLS_KEYCTX_TX_WR_LEN16) & M_FW_TLS_KEYCTX_TX_WR_LEN16) 3559 3560 #define S_FW_TLS_KEYCTX_TX_WR_DUALCK 12 3561 #define M_FW_TLS_KEYCTX_TX_WR_DUALCK 0x1 3562 #define V_FW_TLS_KEYCTX_TX_WR_DUALCK(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_DUALCK) 3563 #define G_FW_TLS_KEYCTX_TX_WR_DUALCK(x) \ 3564 (((x) >> S_FW_TLS_KEYCTX_TX_WR_DUALCK) & M_FW_TLS_KEYCTX_TX_WR_DUALCK) 3565 #define F_FW_TLS_KEYCTX_TX_WR_DUALCK V_FW_TLS_KEYCTX_TX_WR_DUALCK(1U) 3566 3567 #define S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 11 3568 #define M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT 0x1 3569 #define V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \ 3570 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) 3571 #define G_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(x) \ 3572 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) & \ 3573 M_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT) 3574 #define F_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT \ 3575 V_FW_TLS_KEYCTX_TX_WR_TXOPAD_PRESENT(1U) 3576 3577 #define S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 10 3578 #define M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT 0x1 3579 #define V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \ 3580 ((x) << S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) 3581 #define G_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(x) \ 3582 (((x) >> S_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) & \ 3583 M_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT) 3584 #define F_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT \ 3585 V_FW_TLS_KEYCTX_TX_WR_SALT_PRESENT(1U) 3586 3587 #define S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 6 3588 #define M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE 0xf 3589 #define V_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \ 3590 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) 3591 #define G_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE(x) \ 3592 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) & \ 3593 M_FW_TLS_KEYCTX_TX_WR_TXCK_SIZE) 3594 3595 #define S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 2 3596 #define M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE 0xf 3597 #define V_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \ 3598 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) 3599 #define G_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE(x) \ 3600 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) & \ 3601 M_FW_TLS_KEYCTX_TX_WR_TXMK_SIZE) 3602 3603 #define S_FW_TLS_KEYCTX_TX_WR_TXVALID 0 3604 #define M_FW_TLS_KEYCTX_TX_WR_TXVALID 0x1 3605 #define V_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \ 3606 ((x) << S_FW_TLS_KEYCTX_TX_WR_TXVALID) 3607 #define G_FW_TLS_KEYCTX_TX_WR_TXVALID(x) \ 3608 (((x) >> S_FW_TLS_KEYCTX_TX_WR_TXVALID) & M_FW_TLS_KEYCTX_TX_WR_TXVALID) 3609 #define F_FW_TLS_KEYCTX_TX_WR_TXVALID V_FW_TLS_KEYCTX_TX_WR_TXVALID(1U) 3610 3611 #define S_FW_TLS_KEYCTX_TX_WR_FLITCNT 3 3612 #define M_FW_TLS_KEYCTX_TX_WR_FLITCNT 0x1f 3613 #define V_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \ 3614 ((x) << S_FW_TLS_KEYCTX_TX_WR_FLITCNT) 3615 #define G_FW_TLS_KEYCTX_TX_WR_FLITCNT(x) \ 3616 (((x) >> S_FW_TLS_KEYCTX_TX_WR_FLITCNT) & M_FW_TLS_KEYCTX_TX_WR_FLITCNT) 3617 3618 #define S_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0 3619 #define M_FW_TLS_KEYCTX_TX_WR_HMACCTRL 0x7 3620 #define V_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \ 3621 ((x) << S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) 3622 #define G_FW_TLS_KEYCTX_TX_WR_HMACCTRL(x) \ 3623 (((x) >> S_FW_TLS_KEYCTX_TX_WR_HMACCTRL) & M_FW_TLS_KEYCTX_TX_WR_HMACCTRL) 3624 3625 #define S_FW_TLS_KEYCTX_TX_WR_PROTOVER 4 3626 #define M_FW_TLS_KEYCTX_TX_WR_PROTOVER 0xf 3627 #define V_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \ 3628 ((x) << S_FW_TLS_KEYCTX_TX_WR_PROTOVER) 3629 #define G_FW_TLS_KEYCTX_TX_WR_PROTOVER(x) \ 3630 (((x) >> S_FW_TLS_KEYCTX_TX_WR_PROTOVER) & M_FW_TLS_KEYCTX_TX_WR_PROTOVER) 3631 3632 #define S_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0 3633 #define M_FW_TLS_KEYCTX_TX_WR_CIPHMODE 0xf 3634 #define V_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \ 3635 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) 3636 #define G_FW_TLS_KEYCTX_TX_WR_CIPHMODE(x) \ 3637 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHMODE) & M_FW_TLS_KEYCTX_TX_WR_CIPHMODE) 3638 3639 #define S_FW_TLS_KEYCTX_TX_WR_AUTHMODE 4 3640 #define M_FW_TLS_KEYCTX_TX_WR_AUTHMODE 0xf 3641 #define V_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \ 3642 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) 3643 #define G_FW_TLS_KEYCTX_TX_WR_AUTHMODE(x) \ 3644 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHMODE) & M_FW_TLS_KEYCTX_TX_WR_AUTHMODE) 3645 3646 #define S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 3 3647 #define M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL 0x1 3648 #define V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \ 3649 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) 3650 #define G_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(x) \ 3651 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) & \ 3652 M_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL) 3653 #define F_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL \ 3654 V_FW_TLS_KEYCTX_TX_WR_CIPHAUTHSEQCTRL(1U) 3655 3656 #define S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 1 3657 #define M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL 0x3 3658 #define V_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \ 3659 ((x) << S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) 3660 #define G_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL(x) \ 3661 (((x) >> S_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) & \ 3662 M_FW_TLS_KEYCTX_TX_WR_SEQNUMCTRL) 3663 3664 #define S_FW_TLS_KEYCTX_TX_WR_RXVALID 0 3665 #define M_FW_TLS_KEYCTX_TX_WR_RXVALID 0x1 3666 #define V_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \ 3667 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXVALID) 3668 #define G_FW_TLS_KEYCTX_TX_WR_RXVALID(x) \ 3669 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXVALID) & M_FW_TLS_KEYCTX_TX_WR_RXVALID) 3670 #define F_FW_TLS_KEYCTX_TX_WR_RXVALID V_FW_TLS_KEYCTX_TX_WR_RXVALID(1U) 3671 3672 #define S_FW_TLS_KEYCTX_TX_WR_IVPRESENT 7 3673 #define M_FW_TLS_KEYCTX_TX_WR_IVPRESENT 0x1 3674 #define V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \ 3675 ((x) << S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) 3676 #define G_FW_TLS_KEYCTX_TX_WR_IVPRESENT(x) \ 3677 (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVPRESENT) & \ 3678 M_FW_TLS_KEYCTX_TX_WR_IVPRESENT) 3679 #define F_FW_TLS_KEYCTX_TX_WR_IVPRESENT V_FW_TLS_KEYCTX_TX_WR_IVPRESENT(1U) 3680 3681 #define S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 6 3682 #define M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT 0x1 3683 #define V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \ 3684 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) 3685 #define G_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(x) \ 3686 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) & \ 3687 M_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT) 3688 #define F_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT \ 3689 V_FW_TLS_KEYCTX_TX_WR_RXOPAD_PRESENT(1U) 3690 3691 #define S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 3 3692 #define M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE 0x7 3693 #define V_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \ 3694 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) 3695 #define G_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE(x) \ 3696 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) & \ 3697 M_FW_TLS_KEYCTX_TX_WR_RXCK_SIZE) 3698 3699 #define S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0 3700 #define M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE 0x7 3701 #define V_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \ 3702 ((x) << S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) 3703 #define G_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE(x) \ 3704 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) & \ 3705 M_FW_TLS_KEYCTX_TX_WR_RXMK_SIZE) 3706 3707 #define S_FW_TLS_KEYCTX_TX_WR_IVINSERT 55 3708 #define M_FW_TLS_KEYCTX_TX_WR_IVINSERT 0x1ffULL 3709 #define V_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \ 3710 ((x) << S_FW_TLS_KEYCTX_TX_WR_IVINSERT) 3711 #define G_FW_TLS_KEYCTX_TX_WR_IVINSERT(x) \ 3712 (((x) >> S_FW_TLS_KEYCTX_TX_WR_IVINSERT) & M_FW_TLS_KEYCTX_TX_WR_IVINSERT) 3713 3714 #define S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 47 3715 #define M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST 0xffULL 3716 #define V_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \ 3717 ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) 3718 #define G_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST(x) \ 3719 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) & \ 3720 M_FW_TLS_KEYCTX_TX_WR_AADSTRTOFST) 3721 3722 #define S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 39 3723 #define M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST 0xffULL 3724 #define V_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \ 3725 ((x) << S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) 3726 #define G_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST(x) \ 3727 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) & \ 3728 M_FW_TLS_KEYCTX_TX_WR_AADSTOPOFST) 3729 3730 #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 30 3731 #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST 0x1ffULL 3732 #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \ 3733 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) 3734 #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST(x) \ 3735 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) & \ 3736 M_FW_TLS_KEYCTX_TX_WR_CIPHERSRTOFST) 3737 3738 #define S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 23 3739 #define M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST 0x7f 3740 #define V_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \ 3741 ((x) << S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) 3742 #define G_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST(x) \ 3743 (((x) >> S_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) & \ 3744 M_FW_TLS_KEYCTX_TX_WR_CIPHERSTOPOFST) 3745 3746 #define S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 14 3747 #define M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST 0x1ff 3748 #define V_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \ 3749 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) 3750 #define G_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST(x) \ 3751 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) & \ 3752 M_FW_TLS_KEYCTX_TX_WR_AUTHSRTOFST) 3753 3754 #define S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 7 3755 #define M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST 0x7f 3756 #define V_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \ 3757 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) 3758 #define G_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST(x) \ 3759 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) & \ 3760 M_FW_TLS_KEYCTX_TX_WR_AUTHSTOPOFST) 3761 3762 #define S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0 3763 #define M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT 0x7f 3764 #define V_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \ 3765 ((x) << S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) 3766 #define G_FW_TLS_KEYCTX_TX_WR_AUTHINSRT(x) \ 3767 (((x) >> S_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) & \ 3768 M_FW_TLS_KEYCTX_TX_WR_AUTHINSRT) 3769 3770 #define S_FW_TLS_KEYCTX_TX_WR_RENEG 4 3771 #define M_FW_TLS_KEYCTX_TX_WR_RENEG 0x1 3772 #define V_FW_TLS_KEYCTX_TX_WR_RENEG(x) ((x) << S_FW_TLS_KEYCTX_TX_WR_RENEG) 3773 #define G_FW_TLS_KEYCTX_TX_WR_RENEG(x) \ 3774 (((x) >> S_FW_TLS_KEYCTX_TX_WR_RENEG) & M_FW_TLS_KEYCTX_TX_WR_RENEG) 3775 #define F_FW_TLS_KEYCTX_TX_WR_RENEG V_FW_TLS_KEYCTX_TX_WR_RENEG(1U) 3776 3777 #define S_FW_TLS_KEYCTX_TX_WR_DELETE_TX 3 3778 #define M_FW_TLS_KEYCTX_TX_WR_DELETE_TX 0x1 3779 #define V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \ 3780 ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) 3781 #define G_FW_TLS_KEYCTX_TX_WR_DELETE_TX(x) \ 3782 (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_TX) & \ 3783 M_FW_TLS_KEYCTX_TX_WR_DELETE_TX) 3784 #define F_FW_TLS_KEYCTX_TX_WR_DELETE_TX V_FW_TLS_KEYCTX_TX_WR_DELETE_TX(1U) 3785 3786 #define S_FW_TLS_KEYCTX_TX_WR_DELETE_RX 2 3787 #define M_FW_TLS_KEYCTX_TX_WR_DELETE_RX 0x1 3788 #define V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \ 3789 ((x) << S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) 3790 #define G_FW_TLS_KEYCTX_TX_WR_DELETE_RX(x) \ 3791 (((x) >> S_FW_TLS_KEYCTX_TX_WR_DELETE_RX) & \ 3792 M_FW_TLS_KEYCTX_TX_WR_DELETE_RX) 3793 #define F_FW_TLS_KEYCTX_TX_WR_DELETE_RX V_FW_TLS_KEYCTX_TX_WR_DELETE_RX(1U) 3794 3795 #define S_FW_TLS_KEYCTX_TX_WR_WRITE_TX 1 3796 #define M_FW_TLS_KEYCTX_TX_WR_WRITE_TX 0x1 3797 #define V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \ 3798 ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) 3799 #define G_FW_TLS_KEYCTX_TX_WR_WRITE_TX(x) \ 3800 (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_TX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_TX) 3801 #define F_FW_TLS_KEYCTX_TX_WR_WRITE_TX V_FW_TLS_KEYCTX_TX_WR_WRITE_TX(1U) 3802 3803 #define S_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0 3804 #define M_FW_TLS_KEYCTX_TX_WR_WRITE_RX 0x1 3805 #define V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \ 3806 ((x) << S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) 3807 #define G_FW_TLS_KEYCTX_TX_WR_WRITE_RX(x) \ 3808 (((x) >> S_FW_TLS_KEYCTX_TX_WR_WRITE_RX) & M_FW_TLS_KEYCTX_TX_WR_WRITE_RX) 3809 #define F_FW_TLS_KEYCTX_TX_WR_WRITE_RX V_FW_TLS_KEYCTX_TX_WR_WRITE_RX(1U) 3810 3811 struct fw_crypto_lookaside_wr { 3812 __be32 op_to_cctx_size; 3813 __be32 len16_pkd; 3814 __be32 session_id; 3815 __be32 rx_chid_to_rx_q_id; 3816 __be32 key_addr; 3817 __be32 pld_size_hash_size; 3818 __be64 cookie; 3819 }; 3820 3821 #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24 3822 #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff 3823 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3824 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3825 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 3826 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \ 3827 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 3828 3829 #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23 3830 #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1 3831 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3832 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3833 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 3834 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \ 3835 M_FW_CRYPTO_LOOKASIDE_WR_COMPL) 3836 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U) 3837 3838 #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15 3839 #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff 3840 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3841 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3842 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 3843 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \ 3844 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 3845 3846 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5 3847 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3 3848 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 3849 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 3850 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 3851 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \ 3852 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 3853 3854 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0 3855 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f 3856 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 3857 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 3858 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 3859 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \ 3860 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 3861 3862 #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0 3863 #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff 3864 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 3865 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16) 3866 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 3867 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \ 3868 M_FW_CRYPTO_LOOKASIDE_WR_LEN16) 3869 3870 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29 3871 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3 3872 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 3873 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 3874 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 3875 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \ 3876 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 3877 3878 #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27 3879 #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3 3880 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 3881 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB) 3882 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 3883 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB) 3884 3885 #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25 3886 #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3 3887 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 3888 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH) 3889 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 3890 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \ 3891 M_FW_CRYPTO_LOOKASIDE_WR_PHASH) 3892 3893 #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23 3894 #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3 3895 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 3896 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV) 3897 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 3898 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV) 3899 3900 #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10 3901 #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3 3902 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 3903 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 3904 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 3905 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \ 3906 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 3907 3908 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0 3909 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff 3910 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 3911 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 3912 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 3913 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \ 3914 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 3915 3916 #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24 3917 #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff 3918 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 3919 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 3920 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 3921 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \ 3922 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 3923 3924 #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17 3925 #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f 3926 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 3927 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 3928 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 3929 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \ 3930 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 3931 3932 /****************************************************************************** 3933 * C O M M A N D s 3934 *********************/ 3935 3936 /* 3937 * The maximum length of time, in miliseconds, that we expect any firmware 3938 * command to take to execute and return a reply to the host. The RESET 3939 * and INITIALIZE commands can take a fair amount of time to execute but 3940 * most execute in far less time than this maximum. This constant is used 3941 * by host software to determine how long to wait for a firmware command 3942 * reply before declaring the firmware as dead/unreachable ... 3943 */ 3944 #define FW_CMD_MAX_TIMEOUT 10000 3945 3946 /* 3947 * If a host driver does a HELLO and discovers that there's already a MASTER 3948 * selected, we may have to wait for that MASTER to finish issuing RESET, 3949 * configuration and INITIALIZE commands. Also, there's a possibility that 3950 * our own HELLO may get lost if it happens right as the MASTER is issuign a 3951 * RESET command, so we need to be willing to make a few retries of our HELLO. 3952 */ 3953 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 3954 #define FW_CMD_HELLO_RETRIES 3 3955 3956 enum fw_cmd_opcodes { 3957 FW_LDST_CMD = 0x01, 3958 FW_RESET_CMD = 0x03, 3959 FW_HELLO_CMD = 0x04, 3960 FW_BYE_CMD = 0x05, 3961 FW_INITIALIZE_CMD = 0x06, 3962 FW_CAPS_CONFIG_CMD = 0x07, 3963 FW_PARAMS_CMD = 0x08, 3964 FW_PFVF_CMD = 0x09, 3965 FW_IQ_CMD = 0x10, 3966 FW_EQ_MNGT_CMD = 0x11, 3967 FW_EQ_ETH_CMD = 0x12, 3968 FW_EQ_CTRL_CMD = 0x13, 3969 FW_EQ_OFLD_CMD = 0x21, 3970 FW_VI_CMD = 0x14, 3971 FW_VI_MAC_CMD = 0x15, 3972 FW_VI_RXMODE_CMD = 0x16, 3973 FW_VI_ENABLE_CMD = 0x17, 3974 FW_VI_STATS_CMD = 0x1a, 3975 FW_ACL_MAC_CMD = 0x18, 3976 FW_ACL_VLAN_CMD = 0x19, 3977 FW_PORT_CMD = 0x1b, 3978 FW_PORT_STATS_CMD = 0x1c, 3979 FW_PORT_LB_STATS_CMD = 0x1d, 3980 FW_PORT_TRACE_CMD = 0x1e, 3981 FW_PORT_TRACE_MMAP_CMD = 0x1f, 3982 FW_RSS_IND_TBL_CMD = 0x20, 3983 FW_RSS_GLB_CONFIG_CMD = 0x22, 3984 FW_RSS_VI_CONFIG_CMD = 0x23, 3985 FW_SCHED_CMD = 0x24, 3986 FW_DEVLOG_CMD = 0x25, 3987 FW_WATCHDOG_CMD = 0x27, 3988 FW_CLIP_CMD = 0x28, 3989 FW_CHNET_IFACE_CMD = 0x26, 3990 FW_FCOE_RES_INFO_CMD = 0x31, 3991 FW_FCOE_LINK_CMD = 0x32, 3992 FW_FCOE_VNP_CMD = 0x33, 3993 FW_FCOE_SPARAMS_CMD = 0x35, 3994 FW_FCOE_STATS_CMD = 0x37, 3995 FW_FCOE_FCF_CMD = 0x38, 3996 FW_DCB_IEEE_CMD = 0x3a, 3997 FW_PTP_CMD = 0x3e, 3998 FW_LASTC2E_CMD = 0x40, 3999 FW_ERROR_CMD = 0x80, 4000 FW_DEBUG_CMD = 0x81, 4001 }; 4002 4003 enum fw_cmd_cap { 4004 FW_CMD_CAP_PF = 0x01, 4005 FW_CMD_CAP_DMAQ = 0x02, 4006 FW_CMD_CAP_PORT = 0x04, 4007 FW_CMD_CAP_PORTPROMISC = 0x08, 4008 FW_CMD_CAP_PORTSTATS = 0x10, 4009 FW_CMD_CAP_VF = 0x80, 4010 }; 4011 4012 /* 4013 * Generic command header flit0 4014 */ 4015 struct fw_cmd_hdr { 4016 __be32 hi; 4017 __be32 lo; 4018 }; 4019 4020 #define S_FW_CMD_OP 24 4021 #define M_FW_CMD_OP 0xff 4022 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 4023 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 4024 4025 #define S_FW_CMD_REQUEST 23 4026 #define M_FW_CMD_REQUEST 0x1 4027 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 4028 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 4029 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 4030 4031 #define S_FW_CMD_READ 22 4032 #define M_FW_CMD_READ 0x1 4033 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 4034 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 4035 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 4036 4037 #define S_FW_CMD_WRITE 21 4038 #define M_FW_CMD_WRITE 0x1 4039 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 4040 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 4041 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 4042 4043 #define S_FW_CMD_EXEC 20 4044 #define M_FW_CMD_EXEC 0x1 4045 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 4046 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 4047 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 4048 4049 #define S_FW_CMD_RAMASK 20 4050 #define M_FW_CMD_RAMASK 0xf 4051 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 4052 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 4053 4054 #define S_FW_CMD_RETVAL 8 4055 #define M_FW_CMD_RETVAL 0xff 4056 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 4057 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 4058 4059 #define S_FW_CMD_LEN16 0 4060 #define M_FW_CMD_LEN16 0xff 4061 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 4062 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 4063 4064 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 4065 4066 /* 4067 * address spaces 4068 */ 4069 enum fw_ldst_addrspc { 4070 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 4071 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 4072 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 4073 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 4074 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 4075 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 4076 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 4077 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 4078 FW_LDST_ADDRSPC_MDIO = 0x0018, 4079 FW_LDST_ADDRSPC_MPS = 0x0020, 4080 FW_LDST_ADDRSPC_FUNC = 0x0028, 4081 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 4082 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 4083 FW_LDST_ADDRSPC_LE = 0x0030, 4084 FW_LDST_ADDRSPC_I2C = 0x0038, 4085 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 4086 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 4087 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 4088 FW_LDST_ADDRSPC_CIM_Q = 0x0048, 4089 }; 4090 4091 /* 4092 * MDIO VSC8634 register access control field 4093 */ 4094 enum fw_ldst_mdio_vsc8634_aid { 4095 FW_LDST_MDIO_VS_STANDARD, 4096 FW_LDST_MDIO_VS_EXTENDED, 4097 FW_LDST_MDIO_VS_GPIO 4098 }; 4099 4100 enum fw_ldst_mps_fid { 4101 FW_LDST_MPS_ATRB, 4102 FW_LDST_MPS_RPLC 4103 }; 4104 4105 enum fw_ldst_func_access_ctl { 4106 FW_LDST_FUNC_ACC_CTL_VIID, 4107 FW_LDST_FUNC_ACC_CTL_FID 4108 }; 4109 4110 enum fw_ldst_func_mod_index { 4111 FW_LDST_FUNC_MPS 4112 }; 4113 4114 struct fw_ldst_cmd { 4115 __be32 op_to_addrspace; 4116 __be32 cycles_to_len16; 4117 union fw_ldst { 4118 struct fw_ldst_addrval { 4119 __be32 addr; 4120 __be32 val; 4121 } addrval; 4122 struct fw_ldst_idctxt { 4123 __be32 physid; 4124 __be32 msg_ctxtflush; 4125 __be32 ctxt_data7; 4126 __be32 ctxt_data6; 4127 __be32 ctxt_data5; 4128 __be32 ctxt_data4; 4129 __be32 ctxt_data3; 4130 __be32 ctxt_data2; 4131 __be32 ctxt_data1; 4132 __be32 ctxt_data0; 4133 } idctxt; 4134 struct fw_ldst_mdio { 4135 __be16 paddr_mmd; 4136 __be16 raddr; 4137 __be16 vctl; 4138 __be16 rval; 4139 } mdio; 4140 struct fw_ldst_cim_rq { 4141 __u8 req_first64[8]; 4142 __u8 req_second64[8]; 4143 __u8 resp_first64[8]; 4144 __u8 resp_second64[8]; 4145 __be32 r3[2]; 4146 } cim_rq; 4147 union fw_ldst_mps { 4148 struct fw_ldst_mps_rplc { 4149 __be16 fid_idx; 4150 __be16 rplcpf_pkd; 4151 __be32 rplc255_224; 4152 __be32 rplc223_192; 4153 __be32 rplc191_160; 4154 __be32 rplc159_128; 4155 __be32 rplc127_96; 4156 __be32 rplc95_64; 4157 __be32 rplc63_32; 4158 __be32 rplc31_0; 4159 } rplc; 4160 struct fw_ldst_mps_atrb { 4161 __be16 fid_mpsid; 4162 __be16 r2[3]; 4163 __be32 r3[2]; 4164 __be32 r4; 4165 __be32 atrb; 4166 __be16 vlan[16]; 4167 } atrb; 4168 } mps; 4169 struct fw_ldst_func { 4170 __u8 access_ctl; 4171 __u8 mod_index; 4172 __be16 ctl_id; 4173 __be32 offset; 4174 __be64 data0; 4175 __be64 data1; 4176 } func; 4177 struct fw_ldst_pcie { 4178 __u8 ctrl_to_fn; 4179 __u8 bnum; 4180 __u8 r; 4181 __u8 ext_r; 4182 __u8 select_naccess; 4183 __u8 pcie_fn; 4184 __be16 nset_pkd; 4185 __be32 data[12]; 4186 } pcie; 4187 struct fw_ldst_i2c_deprecated { 4188 __u8 pid_pkd; 4189 __u8 base; 4190 __u8 boffset; 4191 __u8 data; 4192 __be32 r9; 4193 } i2c_deprecated; 4194 struct fw_ldst_i2c { 4195 __u8 pid; 4196 __u8 did; 4197 __u8 boffset; 4198 __u8 blen; 4199 __be32 r9; 4200 __u8 data[48]; 4201 } i2c; 4202 struct fw_ldst_le { 4203 __be32 index; 4204 __be32 r9; 4205 __u8 val[33]; 4206 __u8 r11[7]; 4207 } le; 4208 } u; 4209 }; 4210 4211 #define S_FW_LDST_CMD_ADDRSPACE 0 4212 #define M_FW_LDST_CMD_ADDRSPACE 0xff 4213 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 4214 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 4215 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 4216 4217 #define S_FW_LDST_CMD_CYCLES 16 4218 #define M_FW_LDST_CMD_CYCLES 0xffff 4219 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 4220 #define G_FW_LDST_CMD_CYCLES(x) \ 4221 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 4222 4223 #define S_FW_LDST_CMD_MSG 31 4224 #define M_FW_LDST_CMD_MSG 0x1 4225 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 4226 #define G_FW_LDST_CMD_MSG(x) \ 4227 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 4228 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 4229 4230 #define S_FW_LDST_CMD_CTXTFLUSH 30 4231 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 4232 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 4233 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 4234 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 4235 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 4236 4237 #define S_FW_LDST_CMD_PADDR 8 4238 #define M_FW_LDST_CMD_PADDR 0x1f 4239 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 4240 #define G_FW_LDST_CMD_PADDR(x) \ 4241 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 4242 4243 #define S_FW_LDST_CMD_MMD 0 4244 #define M_FW_LDST_CMD_MMD 0x1f 4245 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 4246 #define G_FW_LDST_CMD_MMD(x) \ 4247 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 4248 4249 #define S_FW_LDST_CMD_FID 15 4250 #define M_FW_LDST_CMD_FID 0x1 4251 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 4252 #define G_FW_LDST_CMD_FID(x) \ 4253 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 4254 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 4255 4256 #define S_FW_LDST_CMD_IDX 0 4257 #define M_FW_LDST_CMD_IDX 0x7fff 4258 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 4259 #define G_FW_LDST_CMD_IDX(x) \ 4260 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 4261 4262 #define S_FW_LDST_CMD_RPLCPF 0 4263 #define M_FW_LDST_CMD_RPLCPF 0xff 4264 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 4265 #define G_FW_LDST_CMD_RPLCPF(x) \ 4266 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 4267 4268 #define S_FW_LDST_CMD_MPSID 0 4269 #define M_FW_LDST_CMD_MPSID 0x7fff 4270 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 4271 #define G_FW_LDST_CMD_MPSID(x) \ 4272 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 4273 4274 #define S_FW_LDST_CMD_CTRL 7 4275 #define M_FW_LDST_CMD_CTRL 0x1 4276 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 4277 #define G_FW_LDST_CMD_CTRL(x) \ 4278 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 4279 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 4280 4281 #define S_FW_LDST_CMD_LC 4 4282 #define M_FW_LDST_CMD_LC 0x1 4283 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 4284 #define G_FW_LDST_CMD_LC(x) \ 4285 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 4286 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 4287 4288 #define S_FW_LDST_CMD_AI 3 4289 #define M_FW_LDST_CMD_AI 0x1 4290 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 4291 #define G_FW_LDST_CMD_AI(x) \ 4292 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 4293 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 4294 4295 #define S_FW_LDST_CMD_FN 0 4296 #define M_FW_LDST_CMD_FN 0x7 4297 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 4298 #define G_FW_LDST_CMD_FN(x) \ 4299 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 4300 4301 #define S_FW_LDST_CMD_SELECT 4 4302 #define M_FW_LDST_CMD_SELECT 0xf 4303 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 4304 #define G_FW_LDST_CMD_SELECT(x) \ 4305 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 4306 4307 #define S_FW_LDST_CMD_NACCESS 0 4308 #define M_FW_LDST_CMD_NACCESS 0xf 4309 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 4310 #define G_FW_LDST_CMD_NACCESS(x) \ 4311 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 4312 4313 #define S_FW_LDST_CMD_NSET 14 4314 #define M_FW_LDST_CMD_NSET 0x3 4315 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 4316 #define G_FW_LDST_CMD_NSET(x) \ 4317 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 4318 4319 #define S_FW_LDST_CMD_PID 6 4320 #define M_FW_LDST_CMD_PID 0x3 4321 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 4322 #define G_FW_LDST_CMD_PID(x) \ 4323 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 4324 4325 struct fw_reset_cmd { 4326 __be32 op_to_write; 4327 __be32 retval_len16; 4328 __be32 val; 4329 __be32 halt_pkd; 4330 }; 4331 4332 #define S_FW_RESET_CMD_HALT 31 4333 #define M_FW_RESET_CMD_HALT 0x1 4334 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 4335 #define G_FW_RESET_CMD_HALT(x) \ 4336 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 4337 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 4338 4339 enum { 4340 FW_HELLO_CMD_STAGE_OS = 0, 4341 FW_HELLO_CMD_STAGE_PREOS0 = 1, 4342 FW_HELLO_CMD_STAGE_PREOS1 = 2, 4343 FW_HELLO_CMD_STAGE_POSTOS = 3, 4344 }; 4345 4346 struct fw_hello_cmd { 4347 __be32 op_to_write; 4348 __be32 retval_len16; 4349 __be32 err_to_clearinit; 4350 __be32 fwrev; 4351 }; 4352 4353 #define S_FW_HELLO_CMD_ERR 31 4354 #define M_FW_HELLO_CMD_ERR 0x1 4355 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 4356 #define G_FW_HELLO_CMD_ERR(x) \ 4357 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 4358 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 4359 4360 #define S_FW_HELLO_CMD_INIT 30 4361 #define M_FW_HELLO_CMD_INIT 0x1 4362 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 4363 #define G_FW_HELLO_CMD_INIT(x) \ 4364 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 4365 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 4366 4367 #define S_FW_HELLO_CMD_MASTERDIS 29 4368 #define M_FW_HELLO_CMD_MASTERDIS 0x1 4369 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 4370 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 4371 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 4372 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 4373 4374 #define S_FW_HELLO_CMD_MASTERFORCE 28 4375 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 4376 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 4377 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 4378 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 4379 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 4380 4381 #define S_FW_HELLO_CMD_MBMASTER 24 4382 #define M_FW_HELLO_CMD_MBMASTER 0xf 4383 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 4384 #define G_FW_HELLO_CMD_MBMASTER(x) \ 4385 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 4386 4387 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 4388 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 4389 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 4390 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 4391 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 4392 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 4393 4394 #define S_FW_HELLO_CMD_MBASYNCNOT 20 4395 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 4396 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 4397 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 4398 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 4399 4400 #define S_FW_HELLO_CMD_STAGE 17 4401 #define M_FW_HELLO_CMD_STAGE 0x7 4402 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 4403 #define G_FW_HELLO_CMD_STAGE(x) \ 4404 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 4405 4406 #define S_FW_HELLO_CMD_CLEARINIT 16 4407 #define M_FW_HELLO_CMD_CLEARINIT 0x1 4408 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 4409 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 4410 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 4411 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 4412 4413 struct fw_bye_cmd { 4414 __be32 op_to_write; 4415 __be32 retval_len16; 4416 __be64 r3; 4417 }; 4418 4419 struct fw_initialize_cmd { 4420 __be32 op_to_write; 4421 __be32 retval_len16; 4422 __be64 r3; 4423 }; 4424 4425 enum fw_caps_config_hm { 4426 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 4427 FW_CAPS_CONFIG_HM_PL = 0x00000002, 4428 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 4429 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 4430 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 4431 FW_CAPS_CONFIG_HM_TP = 0x00000020, 4432 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 4433 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 4434 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 4435 FW_CAPS_CONFIG_HM_MC = 0x00000200, 4436 FW_CAPS_CONFIG_HM_LE = 0x00000400, 4437 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 4438 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 4439 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 4440 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 4441 FW_CAPS_CONFIG_HM_MI = 0x00008000, 4442 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 4443 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 4444 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 4445 FW_CAPS_CONFIG_HM_MA = 0x00080000, 4446 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 4447 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 4448 FW_CAPS_CONFIG_HM_UART = 0x00400000, 4449 FW_CAPS_CONFIG_HM_SF = 0x00800000, 4450 }; 4451 4452 /* 4453 * The VF Register Map. 4454 * 4455 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 4456 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 4457 * the Slice to Module Map Table (see below) in the Physical Function Register 4458 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 4459 * and Offset registers in the PF Register Map. The MBDATA base address is 4460 * quite constrained as it determines the Mailbox Data addresses for both PFs 4461 * and VFs, and therefore must fit in both the VF and PF Register Maps without 4462 * overlapping other registers. 4463 */ 4464 #define FW_T4VF_SGE_BASE_ADDR 0x0000 4465 #define FW_T4VF_MPS_BASE_ADDR 0x0100 4466 #define FW_T4VF_PL_BASE_ADDR 0x0200 4467 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 4468 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 4469 #define FW_T4VF_CIM_BASE_ADDR 0x0300 4470 4471 #define FW_T4VF_REGMAP_START 0x0000 4472 #define FW_T4VF_REGMAP_SIZE 0x0400 4473 4474 enum fw_caps_config_nbm { 4475 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 4476 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 4477 }; 4478 4479 enum fw_caps_config_link { 4480 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 4481 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 4482 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 4483 }; 4484 4485 enum fw_caps_config_switch { 4486 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 4487 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 4488 }; 4489 4490 enum fw_caps_config_nic { 4491 FW_CAPS_CONFIG_NIC = 0x00000001, 4492 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 4493 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 4494 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 4495 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 4496 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 4497 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 4498 }; 4499 4500 enum fw_caps_config_toe { 4501 FW_CAPS_CONFIG_TOE = 0x00000001, 4502 }; 4503 4504 enum fw_caps_config_rdma { 4505 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 4506 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 4507 }; 4508 4509 enum fw_caps_config_iscsi { 4510 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 4511 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 4512 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 4513 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 4514 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 4515 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 4516 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 4517 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 4518 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 4519 }; 4520 4521 enum fw_caps_config_crypto { 4522 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 4523 FW_CAPS_CONFIG_TLSKEYS = 0x00000002, 4524 }; 4525 4526 enum fw_caps_config_fcoe { 4527 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 4528 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 4529 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 4530 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 4531 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 4532 }; 4533 4534 enum fw_memtype_cf { 4535 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 4536 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 4537 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 4538 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 4539 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 4540 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 4541 }; 4542 4543 struct fw_caps_config_cmd { 4544 __be32 op_to_write; 4545 __be32 cfvalid_to_len16; 4546 __be32 r2; 4547 __be32 hwmbitmap; 4548 __be16 nbmcaps; 4549 __be16 linkcaps; 4550 __be16 switchcaps; 4551 __be16 r3; 4552 __be16 niccaps; 4553 __be16 toecaps; 4554 __be16 rdmacaps; 4555 __be16 cryptocaps; 4556 __be16 iscsicaps; 4557 __be16 fcoecaps; 4558 __be32 cfcsum; 4559 __be32 finiver; 4560 __be32 finicsum; 4561 }; 4562 4563 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 4564 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 4565 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 4566 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 4567 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 4568 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 4569 4570 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 4571 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 4572 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4573 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4574 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 4575 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 4576 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 4577 4578 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 4579 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 4580 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4581 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4582 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 4583 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 4584 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 4585 4586 /* 4587 * params command mnemonics 4588 */ 4589 enum fw_params_mnem { 4590 FW_PARAMS_MNEM_DEV = 1, /* device params */ 4591 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 4592 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 4593 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 4594 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 4595 FW_PARAMS_MNEM_LAST 4596 }; 4597 4598 /* 4599 * device parameters 4600 */ 4601 enum fw_params_param_dev { 4602 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 4603 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 4604 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 4605 * allocated by the device's 4606 * Lookup Engine 4607 */ 4608 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 4609 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 4610 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 4611 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 4612 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 4613 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 4614 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 4615 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 4616 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 4617 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 4618 FW_PARAMS_PARAM_DEV_CF = 0x0D, 4619 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 4620 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 4621 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 4622 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 4623 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 4624 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 4625 */ 4626 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 4627 */ 4628 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 4629 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 4630 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 4631 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 4632 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 4633 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 4634 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 4635 }; 4636 4637 /* 4638 * dev bypass parameters; actions and modes 4639 */ 4640 enum fw_params_param_dev_bypass { 4641 4642 /* actions 4643 */ 4644 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 4645 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 4646 4647 /* modes 4648 */ 4649 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 4650 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 4651 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 4652 }; 4653 4654 enum fw_params_param_dev_phyfw { 4655 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 4656 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 4657 }; 4658 4659 enum fw_params_param_dev_diag { 4660 FW_PARAM_DEV_DIAG_TMP = 0x00, 4661 FW_PARAM_DEV_DIAG_VDD = 0x01, 4662 }; 4663 4664 enum fw_params_param_dev_fwcache { 4665 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 4666 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 4667 }; 4668 4669 /* 4670 * physical and virtual function parameters 4671 */ 4672 enum fw_params_param_pfvf { 4673 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 4674 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 4675 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 4676 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 4677 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 4678 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 4679 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 4680 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 4681 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 4682 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 4683 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 4684 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 4685 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 4686 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 4687 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 4688 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 4689 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 4690 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 4691 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 4692 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 4693 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 4694 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 4695 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 4696 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 4697 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 4698 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 4699 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 4700 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 4701 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 4702 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 4703 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 4704 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 4705 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 4706 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 4707 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 4708 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 4709 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 4710 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 4711 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 4712 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 4713 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 4714 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 4715 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 4716 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 4717 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 4718 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 4719 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 4720 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 4721 }; 4722 4723 /* 4724 * dma queue parameters 4725 */ 4726 enum fw_params_param_dmaq { 4727 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 4728 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 4729 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 4730 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 4731 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 4732 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 4733 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 4734 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 4735 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 4736 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 4737 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 4738 }; 4739 4740 /* 4741 * chnet parameters 4742 */ 4743 enum fw_params_param_chnet { 4744 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 4745 }; 4746 4747 enum fw_params_param_chnet_flags { 4748 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 4749 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 4750 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 4751 }; 4752 4753 #define S_FW_PARAMS_MNEM 24 4754 #define M_FW_PARAMS_MNEM 0xff 4755 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 4756 #define G_FW_PARAMS_MNEM(x) \ 4757 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 4758 4759 #define S_FW_PARAMS_PARAM_X 16 4760 #define M_FW_PARAMS_PARAM_X 0xff 4761 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 4762 #define G_FW_PARAMS_PARAM_X(x) \ 4763 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 4764 4765 #define S_FW_PARAMS_PARAM_Y 8 4766 #define M_FW_PARAMS_PARAM_Y 0xff 4767 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 4768 #define G_FW_PARAMS_PARAM_Y(x) \ 4769 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 4770 4771 #define S_FW_PARAMS_PARAM_Z 0 4772 #define M_FW_PARAMS_PARAM_Z 0xff 4773 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 4774 #define G_FW_PARAMS_PARAM_Z(x) \ 4775 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 4776 4777 #define S_FW_PARAMS_PARAM_XYZ 0 4778 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 4779 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 4780 #define G_FW_PARAMS_PARAM_XYZ(x) \ 4781 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 4782 4783 #define S_FW_PARAMS_PARAM_YZ 0 4784 #define M_FW_PARAMS_PARAM_YZ 0xffff 4785 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 4786 #define G_FW_PARAMS_PARAM_YZ(x) \ 4787 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 4788 4789 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 4790 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 4791 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4792 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4793 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 4794 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 4795 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 4796 4797 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 4798 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 4799 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4800 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4801 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 4802 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 4803 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 4804 4805 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 4806 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 4807 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4808 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4809 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 4810 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 4811 4812 struct fw_params_cmd { 4813 __be32 op_to_vfn; 4814 __be32 retval_len16; 4815 struct fw_params_param { 4816 __be32 mnem; 4817 __be32 val; 4818 } param[7]; 4819 }; 4820 4821 #define S_FW_PARAMS_CMD_PFN 8 4822 #define M_FW_PARAMS_CMD_PFN 0x7 4823 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 4824 #define G_FW_PARAMS_CMD_PFN(x) \ 4825 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 4826 4827 #define S_FW_PARAMS_CMD_VFN 0 4828 #define M_FW_PARAMS_CMD_VFN 0xff 4829 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 4830 #define G_FW_PARAMS_CMD_VFN(x) \ 4831 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 4832 4833 struct fw_pfvf_cmd { 4834 __be32 op_to_vfn; 4835 __be32 retval_len16; 4836 __be32 niqflint_niq; 4837 __be32 type_to_neq; 4838 __be32 tc_to_nexactf; 4839 __be32 r_caps_to_nethctrl; 4840 __be16 nricq; 4841 __be16 nriqp; 4842 __be32 r4; 4843 }; 4844 4845 #define S_FW_PFVF_CMD_PFN 8 4846 #define M_FW_PFVF_CMD_PFN 0x7 4847 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 4848 #define G_FW_PFVF_CMD_PFN(x) \ 4849 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 4850 4851 #define S_FW_PFVF_CMD_VFN 0 4852 #define M_FW_PFVF_CMD_VFN 0xff 4853 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 4854 #define G_FW_PFVF_CMD_VFN(x) \ 4855 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 4856 4857 #define S_FW_PFVF_CMD_NIQFLINT 20 4858 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 4859 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 4860 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 4861 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 4862 4863 #define S_FW_PFVF_CMD_NIQ 0 4864 #define M_FW_PFVF_CMD_NIQ 0xfffff 4865 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 4866 #define G_FW_PFVF_CMD_NIQ(x) \ 4867 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 4868 4869 #define S_FW_PFVF_CMD_TYPE 31 4870 #define M_FW_PFVF_CMD_TYPE 0x1 4871 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 4872 #define G_FW_PFVF_CMD_TYPE(x) \ 4873 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 4874 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 4875 4876 #define S_FW_PFVF_CMD_CMASK 24 4877 #define M_FW_PFVF_CMD_CMASK 0xf 4878 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 4879 #define G_FW_PFVF_CMD_CMASK(x) \ 4880 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 4881 4882 #define S_FW_PFVF_CMD_PMASK 20 4883 #define M_FW_PFVF_CMD_PMASK 0xf 4884 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 4885 #define G_FW_PFVF_CMD_PMASK(x) \ 4886 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 4887 4888 #define S_FW_PFVF_CMD_NEQ 0 4889 #define M_FW_PFVF_CMD_NEQ 0xfffff 4890 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 4891 #define G_FW_PFVF_CMD_NEQ(x) \ 4892 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 4893 4894 #define S_FW_PFVF_CMD_TC 24 4895 #define M_FW_PFVF_CMD_TC 0xff 4896 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 4897 #define G_FW_PFVF_CMD_TC(x) \ 4898 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 4899 4900 #define S_FW_PFVF_CMD_NVI 16 4901 #define M_FW_PFVF_CMD_NVI 0xff 4902 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 4903 #define G_FW_PFVF_CMD_NVI(x) \ 4904 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 4905 4906 #define S_FW_PFVF_CMD_NEXACTF 0 4907 #define M_FW_PFVF_CMD_NEXACTF 0xffff 4908 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 4909 #define G_FW_PFVF_CMD_NEXACTF(x) \ 4910 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 4911 4912 #define S_FW_PFVF_CMD_R_CAPS 24 4913 #define M_FW_PFVF_CMD_R_CAPS 0xff 4914 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 4915 #define G_FW_PFVF_CMD_R_CAPS(x) \ 4916 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 4917 4918 #define S_FW_PFVF_CMD_WX_CAPS 16 4919 #define M_FW_PFVF_CMD_WX_CAPS 0xff 4920 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 4921 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 4922 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 4923 4924 #define S_FW_PFVF_CMD_NETHCTRL 0 4925 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 4926 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 4927 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 4928 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 4929 4930 /* 4931 * ingress queue type; the first 1K ingress queues can have associated 0, 4932 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 4933 * capabilities 4934 */ 4935 enum fw_iq_type { 4936 FW_IQ_TYPE_FL_INT_CAP, 4937 FW_IQ_TYPE_NO_FL_INT_CAP 4938 }; 4939 4940 struct fw_iq_cmd { 4941 __be32 op_to_vfn; 4942 __be32 alloc_to_len16; 4943 __be16 physiqid; 4944 __be16 iqid; 4945 __be16 fl0id; 4946 __be16 fl1id; 4947 __be32 type_to_iqandstindex; 4948 __be16 iqdroprss_to_iqesize; 4949 __be16 iqsize; 4950 __be64 iqaddr; 4951 __be32 iqns_to_fl0congen; 4952 __be16 fl0dcaen_to_fl0cidxfthresh; 4953 __be16 fl0size; 4954 __be64 fl0addr; 4955 __be32 fl1cngchmap_to_fl1congen; 4956 __be16 fl1dcaen_to_fl1cidxfthresh; 4957 __be16 fl1size; 4958 __be64 fl1addr; 4959 }; 4960 4961 #define S_FW_IQ_CMD_PFN 8 4962 #define M_FW_IQ_CMD_PFN 0x7 4963 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 4964 #define G_FW_IQ_CMD_PFN(x) \ 4965 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 4966 4967 #define S_FW_IQ_CMD_VFN 0 4968 #define M_FW_IQ_CMD_VFN 0xff 4969 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 4970 #define G_FW_IQ_CMD_VFN(x) \ 4971 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 4972 4973 #define S_FW_IQ_CMD_ALLOC 31 4974 #define M_FW_IQ_CMD_ALLOC 0x1 4975 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 4976 #define G_FW_IQ_CMD_ALLOC(x) \ 4977 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 4978 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 4979 4980 #define S_FW_IQ_CMD_FREE 30 4981 #define M_FW_IQ_CMD_FREE 0x1 4982 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 4983 #define G_FW_IQ_CMD_FREE(x) \ 4984 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 4985 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 4986 4987 #define S_FW_IQ_CMD_MODIFY 29 4988 #define M_FW_IQ_CMD_MODIFY 0x1 4989 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 4990 #define G_FW_IQ_CMD_MODIFY(x) \ 4991 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 4992 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 4993 4994 #define S_FW_IQ_CMD_IQSTART 28 4995 #define M_FW_IQ_CMD_IQSTART 0x1 4996 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 4997 #define G_FW_IQ_CMD_IQSTART(x) \ 4998 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 4999 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 5000 5001 #define S_FW_IQ_CMD_IQSTOP 27 5002 #define M_FW_IQ_CMD_IQSTOP 0x1 5003 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 5004 #define G_FW_IQ_CMD_IQSTOP(x) \ 5005 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 5006 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 5007 5008 #define S_FW_IQ_CMD_TYPE 29 5009 #define M_FW_IQ_CMD_TYPE 0x7 5010 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 5011 #define G_FW_IQ_CMD_TYPE(x) \ 5012 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 5013 5014 #define S_FW_IQ_CMD_IQASYNCH 28 5015 #define M_FW_IQ_CMD_IQASYNCH 0x1 5016 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 5017 #define G_FW_IQ_CMD_IQASYNCH(x) \ 5018 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 5019 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 5020 5021 #define S_FW_IQ_CMD_VIID 16 5022 #define M_FW_IQ_CMD_VIID 0xfff 5023 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 5024 #define G_FW_IQ_CMD_VIID(x) \ 5025 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 5026 5027 #define S_FW_IQ_CMD_IQANDST 15 5028 #define M_FW_IQ_CMD_IQANDST 0x1 5029 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 5030 #define G_FW_IQ_CMD_IQANDST(x) \ 5031 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 5032 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 5033 5034 #define S_FW_IQ_CMD_IQANUS 14 5035 #define M_FW_IQ_CMD_IQANUS 0x1 5036 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 5037 #define G_FW_IQ_CMD_IQANUS(x) \ 5038 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 5039 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 5040 5041 #define S_FW_IQ_CMD_IQANUD 12 5042 #define M_FW_IQ_CMD_IQANUD 0x3 5043 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 5044 #define G_FW_IQ_CMD_IQANUD(x) \ 5045 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 5046 5047 #define S_FW_IQ_CMD_IQANDSTINDEX 0 5048 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 5049 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 5050 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 5051 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 5052 5053 #define S_FW_IQ_CMD_IQDROPRSS 15 5054 #define M_FW_IQ_CMD_IQDROPRSS 0x1 5055 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 5056 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 5057 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 5058 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 5059 5060 #define S_FW_IQ_CMD_IQGTSMODE 14 5061 #define M_FW_IQ_CMD_IQGTSMODE 0x1 5062 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 5063 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 5064 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 5065 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 5066 5067 #define S_FW_IQ_CMD_IQPCIECH 12 5068 #define M_FW_IQ_CMD_IQPCIECH 0x3 5069 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 5070 #define G_FW_IQ_CMD_IQPCIECH(x) \ 5071 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 5072 5073 #define S_FW_IQ_CMD_IQDCAEN 11 5074 #define M_FW_IQ_CMD_IQDCAEN 0x1 5075 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 5076 #define G_FW_IQ_CMD_IQDCAEN(x) \ 5077 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 5078 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 5079 5080 #define S_FW_IQ_CMD_IQDCACPU 6 5081 #define M_FW_IQ_CMD_IQDCACPU 0x1f 5082 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 5083 #define G_FW_IQ_CMD_IQDCACPU(x) \ 5084 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 5085 5086 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 5087 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 5088 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 5089 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 5090 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 5091 5092 #define S_FW_IQ_CMD_IQO 3 5093 #define M_FW_IQ_CMD_IQO 0x1 5094 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 5095 #define G_FW_IQ_CMD_IQO(x) \ 5096 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 5097 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 5098 5099 #define S_FW_IQ_CMD_IQCPRIO 2 5100 #define M_FW_IQ_CMD_IQCPRIO 0x1 5101 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 5102 #define G_FW_IQ_CMD_IQCPRIO(x) \ 5103 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 5104 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 5105 5106 #define S_FW_IQ_CMD_IQESIZE 0 5107 #define M_FW_IQ_CMD_IQESIZE 0x3 5108 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 5109 #define G_FW_IQ_CMD_IQESIZE(x) \ 5110 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 5111 5112 #define S_FW_IQ_CMD_IQNS 31 5113 #define M_FW_IQ_CMD_IQNS 0x1 5114 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 5115 #define G_FW_IQ_CMD_IQNS(x) \ 5116 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 5117 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 5118 5119 #define S_FW_IQ_CMD_IQRO 30 5120 #define M_FW_IQ_CMD_IQRO 0x1 5121 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 5122 #define G_FW_IQ_CMD_IQRO(x) \ 5123 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 5124 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 5125 5126 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 5127 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 5128 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 5129 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 5130 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 5131 5132 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 5133 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 5134 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 5135 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 5136 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 5137 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 5138 5139 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 5140 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 5141 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 5142 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 5143 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 5144 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 5145 5146 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 5147 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 5148 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 5149 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 5150 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 5151 5152 #define S_FW_IQ_CMD_FL0CONGDROP 16 5153 #define M_FW_IQ_CMD_FL0CONGDROP 0x1 5154 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 5155 #define G_FW_IQ_CMD_FL0CONGDROP(x) \ 5156 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 5157 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 5158 5159 #define S_FW_IQ_CMD_FL0CACHELOCK 15 5160 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 5161 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 5162 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 5163 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 5164 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 5165 5166 #define S_FW_IQ_CMD_FL0DBP 14 5167 #define M_FW_IQ_CMD_FL0DBP 0x1 5168 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 5169 #define G_FW_IQ_CMD_FL0DBP(x) \ 5170 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 5171 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 5172 5173 #define S_FW_IQ_CMD_FL0DATANS 13 5174 #define M_FW_IQ_CMD_FL0DATANS 0x1 5175 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 5176 #define G_FW_IQ_CMD_FL0DATANS(x) \ 5177 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 5178 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 5179 5180 #define S_FW_IQ_CMD_FL0DATARO 12 5181 #define M_FW_IQ_CMD_FL0DATARO 0x1 5182 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 5183 #define G_FW_IQ_CMD_FL0DATARO(x) \ 5184 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 5185 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 5186 5187 #define S_FW_IQ_CMD_FL0CONGCIF 11 5188 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 5189 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 5190 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 5191 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 5192 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 5193 5194 #define S_FW_IQ_CMD_FL0ONCHIP 10 5195 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 5196 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 5197 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 5198 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 5199 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 5200 5201 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 5202 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 5203 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 5204 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 5205 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 5206 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 5207 5208 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 5209 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 5210 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 5211 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 5212 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 5213 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 5214 5215 #define S_FW_IQ_CMD_FL0FETCHNS 7 5216 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 5217 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 5218 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 5219 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 5220 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 5221 5222 #define S_FW_IQ_CMD_FL0FETCHRO 6 5223 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 5224 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 5225 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 5226 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 5227 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 5228 5229 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 5230 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 5231 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 5232 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 5233 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 5234 5235 #define S_FW_IQ_CMD_FL0CPRIO 3 5236 #define M_FW_IQ_CMD_FL0CPRIO 0x1 5237 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 5238 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 5239 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 5240 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 5241 5242 #define S_FW_IQ_CMD_FL0PADEN 2 5243 #define M_FW_IQ_CMD_FL0PADEN 0x1 5244 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 5245 #define G_FW_IQ_CMD_FL0PADEN(x) \ 5246 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 5247 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 5248 5249 #define S_FW_IQ_CMD_FL0PACKEN 1 5250 #define M_FW_IQ_CMD_FL0PACKEN 0x1 5251 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 5252 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 5253 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 5254 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 5255 5256 #define S_FW_IQ_CMD_FL0CONGEN 0 5257 #define M_FW_IQ_CMD_FL0CONGEN 0x1 5258 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 5259 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 5260 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 5261 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 5262 5263 #define S_FW_IQ_CMD_FL0DCAEN 15 5264 #define M_FW_IQ_CMD_FL0DCAEN 0x1 5265 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 5266 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 5267 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 5268 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 5269 5270 #define S_FW_IQ_CMD_FL0DCACPU 10 5271 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 5272 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 5273 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 5274 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 5275 5276 #define S_FW_IQ_CMD_FL0FBMIN 7 5277 #define M_FW_IQ_CMD_FL0FBMIN 0x7 5278 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 5279 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 5280 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 5281 5282 #define S_FW_IQ_CMD_FL0FBMAX 4 5283 #define M_FW_IQ_CMD_FL0FBMAX 0x7 5284 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 5285 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 5286 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 5287 5288 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 5289 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 5290 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 5291 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 5292 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 5293 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 5294 5295 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 5296 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 5297 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 5298 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 5299 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 5300 5301 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 5302 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 5303 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 5304 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 5305 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 5306 5307 #define S_FW_IQ_CMD_FL1CONGDROP 16 5308 #define M_FW_IQ_CMD_FL1CONGDROP 0x1 5309 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 5310 #define G_FW_IQ_CMD_FL1CONGDROP(x) \ 5311 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 5312 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 5313 5314 #define S_FW_IQ_CMD_FL1CACHELOCK 15 5315 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 5316 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 5317 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 5318 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 5319 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 5320 5321 #define S_FW_IQ_CMD_FL1DBP 14 5322 #define M_FW_IQ_CMD_FL1DBP 0x1 5323 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 5324 #define G_FW_IQ_CMD_FL1DBP(x) \ 5325 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 5326 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 5327 5328 #define S_FW_IQ_CMD_FL1DATANS 13 5329 #define M_FW_IQ_CMD_FL1DATANS 0x1 5330 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 5331 #define G_FW_IQ_CMD_FL1DATANS(x) \ 5332 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 5333 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 5334 5335 #define S_FW_IQ_CMD_FL1DATARO 12 5336 #define M_FW_IQ_CMD_FL1DATARO 0x1 5337 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 5338 #define G_FW_IQ_CMD_FL1DATARO(x) \ 5339 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 5340 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 5341 5342 #define S_FW_IQ_CMD_FL1CONGCIF 11 5343 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 5344 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 5345 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 5346 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 5347 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 5348 5349 #define S_FW_IQ_CMD_FL1ONCHIP 10 5350 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 5351 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 5352 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 5353 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 5354 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 5355 5356 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 5357 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 5358 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 5359 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 5360 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 5361 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 5362 5363 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 5364 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 5365 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 5366 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 5367 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 5368 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 5369 5370 #define S_FW_IQ_CMD_FL1FETCHNS 7 5371 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 5372 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 5373 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 5374 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 5375 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 5376 5377 #define S_FW_IQ_CMD_FL1FETCHRO 6 5378 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 5379 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 5380 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 5381 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 5382 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 5383 5384 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 5385 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 5386 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 5387 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 5388 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 5389 5390 #define S_FW_IQ_CMD_FL1CPRIO 3 5391 #define M_FW_IQ_CMD_FL1CPRIO 0x1 5392 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 5393 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 5394 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 5395 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 5396 5397 #define S_FW_IQ_CMD_FL1PADEN 2 5398 #define M_FW_IQ_CMD_FL1PADEN 0x1 5399 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 5400 #define G_FW_IQ_CMD_FL1PADEN(x) \ 5401 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 5402 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 5403 5404 #define S_FW_IQ_CMD_FL1PACKEN 1 5405 #define M_FW_IQ_CMD_FL1PACKEN 0x1 5406 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 5407 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 5408 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 5409 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 5410 5411 #define S_FW_IQ_CMD_FL1CONGEN 0 5412 #define M_FW_IQ_CMD_FL1CONGEN 0x1 5413 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 5414 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 5415 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 5416 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 5417 5418 #define S_FW_IQ_CMD_FL1DCAEN 15 5419 #define M_FW_IQ_CMD_FL1DCAEN 0x1 5420 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 5421 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 5422 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 5423 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 5424 5425 #define S_FW_IQ_CMD_FL1DCACPU 10 5426 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 5427 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 5428 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 5429 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 5430 5431 #define S_FW_IQ_CMD_FL1FBMIN 7 5432 #define M_FW_IQ_CMD_FL1FBMIN 0x7 5433 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 5434 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 5435 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 5436 5437 #define S_FW_IQ_CMD_FL1FBMAX 4 5438 #define M_FW_IQ_CMD_FL1FBMAX 0x7 5439 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 5440 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 5441 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 5442 5443 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 5444 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 5445 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 5446 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 5447 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 5448 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 5449 5450 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 5451 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 5452 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 5453 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 5454 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 5455 5456 struct fw_eq_mngt_cmd { 5457 __be32 op_to_vfn; 5458 __be32 alloc_to_len16; 5459 __be32 cmpliqid_eqid; 5460 __be32 physeqid_pkd; 5461 __be32 fetchszm_to_iqid; 5462 __be32 dcaen_to_eqsize; 5463 __be64 eqaddr; 5464 }; 5465 5466 #define S_FW_EQ_MNGT_CMD_PFN 8 5467 #define M_FW_EQ_MNGT_CMD_PFN 0x7 5468 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 5469 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 5470 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 5471 5472 #define S_FW_EQ_MNGT_CMD_VFN 0 5473 #define M_FW_EQ_MNGT_CMD_VFN 0xff 5474 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 5475 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 5476 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 5477 5478 #define S_FW_EQ_MNGT_CMD_ALLOC 31 5479 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 5480 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 5481 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 5482 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 5483 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 5484 5485 #define S_FW_EQ_MNGT_CMD_FREE 30 5486 #define M_FW_EQ_MNGT_CMD_FREE 0x1 5487 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 5488 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 5489 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 5490 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 5491 5492 #define S_FW_EQ_MNGT_CMD_MODIFY 29 5493 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 5494 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 5495 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 5496 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 5497 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 5498 5499 #define S_FW_EQ_MNGT_CMD_EQSTART 28 5500 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 5501 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 5502 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 5503 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 5504 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 5505 5506 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 5507 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 5508 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 5509 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 5510 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 5511 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 5512 5513 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 5514 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 5515 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 5516 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 5517 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 5518 5519 #define S_FW_EQ_MNGT_CMD_EQID 0 5520 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 5521 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 5522 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 5523 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 5524 5525 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 5526 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 5527 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 5528 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 5529 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 5530 5531 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 5532 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 5533 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 5534 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 5535 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 5536 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 5537 5538 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 5539 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 5540 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 5541 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 5542 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 5543 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 5544 5545 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 5546 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 5547 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 5548 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 5549 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 5550 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 5551 5552 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 5553 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 5554 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 5555 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 5556 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 5557 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 5558 5559 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 5560 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 5561 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 5562 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 5563 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 5564 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 5565 5566 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 5567 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 5568 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 5569 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 5570 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 5571 5572 #define S_FW_EQ_MNGT_CMD_CPRIO 19 5573 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 5574 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 5575 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 5576 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 5577 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 5578 5579 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 5580 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 5581 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 5582 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 5583 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 5584 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 5585 5586 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 5587 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 5588 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 5589 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 5590 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 5591 5592 #define S_FW_EQ_MNGT_CMD_IQID 0 5593 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 5594 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 5595 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 5596 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 5597 5598 #define S_FW_EQ_MNGT_CMD_DCAEN 31 5599 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 5600 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 5601 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 5602 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 5603 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 5604 5605 #define S_FW_EQ_MNGT_CMD_DCACPU 26 5606 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 5607 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 5608 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 5609 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 5610 5611 #define S_FW_EQ_MNGT_CMD_FBMIN 23 5612 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 5613 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 5614 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 5615 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 5616 5617 #define S_FW_EQ_MNGT_CMD_FBMAX 20 5618 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 5619 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 5620 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 5621 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 5622 5623 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 5624 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 5625 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5626 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5627 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 5628 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 5629 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 5630 5631 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 5632 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 5633 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5634 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 5635 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 5636 5637 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 5638 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 5639 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 5640 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 5641 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 5642 5643 struct fw_eq_eth_cmd { 5644 __be32 op_to_vfn; 5645 __be32 alloc_to_len16; 5646 __be32 eqid_pkd; 5647 __be32 physeqid_pkd; 5648 __be32 fetchszm_to_iqid; 5649 __be32 dcaen_to_eqsize; 5650 __be64 eqaddr; 5651 __be32 autoequiqe_to_viid; 5652 __be32 r8_lo; 5653 __be64 r9; 5654 }; 5655 5656 #define S_FW_EQ_ETH_CMD_PFN 8 5657 #define M_FW_EQ_ETH_CMD_PFN 0x7 5658 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 5659 #define G_FW_EQ_ETH_CMD_PFN(x) \ 5660 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 5661 5662 #define S_FW_EQ_ETH_CMD_VFN 0 5663 #define M_FW_EQ_ETH_CMD_VFN 0xff 5664 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 5665 #define G_FW_EQ_ETH_CMD_VFN(x) \ 5666 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 5667 5668 #define S_FW_EQ_ETH_CMD_ALLOC 31 5669 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 5670 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 5671 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 5672 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 5673 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 5674 5675 #define S_FW_EQ_ETH_CMD_FREE 30 5676 #define M_FW_EQ_ETH_CMD_FREE 0x1 5677 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 5678 #define G_FW_EQ_ETH_CMD_FREE(x) \ 5679 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 5680 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 5681 5682 #define S_FW_EQ_ETH_CMD_MODIFY 29 5683 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 5684 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 5685 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 5686 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 5687 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 5688 5689 #define S_FW_EQ_ETH_CMD_EQSTART 28 5690 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 5691 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 5692 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 5693 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 5694 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 5695 5696 #define S_FW_EQ_ETH_CMD_EQSTOP 27 5697 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 5698 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 5699 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 5700 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 5701 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 5702 5703 #define S_FW_EQ_ETH_CMD_EQID 0 5704 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 5705 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 5706 #define G_FW_EQ_ETH_CMD_EQID(x) \ 5707 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 5708 5709 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 5710 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 5711 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 5712 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 5713 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 5714 5715 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 5716 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 5717 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 5718 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 5719 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 5720 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 5721 5722 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 5723 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 5724 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 5725 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 5726 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 5727 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 5728 5729 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 5730 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 5731 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 5732 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 5733 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 5734 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 5735 5736 #define S_FW_EQ_ETH_CMD_FETCHNS 23 5737 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 5738 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 5739 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 5740 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 5741 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 5742 5743 #define S_FW_EQ_ETH_CMD_FETCHRO 22 5744 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 5745 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 5746 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 5747 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 5748 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 5749 5750 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 5751 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 5752 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 5753 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 5754 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 5755 5756 #define S_FW_EQ_ETH_CMD_CPRIO 19 5757 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 5758 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 5759 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 5760 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 5761 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 5762 5763 #define S_FW_EQ_ETH_CMD_ONCHIP 18 5764 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 5765 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 5766 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 5767 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 5768 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 5769 5770 #define S_FW_EQ_ETH_CMD_PCIECHN 16 5771 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 5772 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 5773 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 5774 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 5775 5776 #define S_FW_EQ_ETH_CMD_IQID 0 5777 #define M_FW_EQ_ETH_CMD_IQID 0xffff 5778 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 5779 #define G_FW_EQ_ETH_CMD_IQID(x) \ 5780 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 5781 5782 #define S_FW_EQ_ETH_CMD_DCAEN 31 5783 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 5784 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 5785 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 5786 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 5787 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 5788 5789 #define S_FW_EQ_ETH_CMD_DCACPU 26 5790 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 5791 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 5792 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 5793 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 5794 5795 #define S_FW_EQ_ETH_CMD_FBMIN 23 5796 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 5797 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 5798 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 5799 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 5800 5801 #define S_FW_EQ_ETH_CMD_FBMAX 20 5802 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 5803 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 5804 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 5805 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 5806 5807 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 5808 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 5809 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5810 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 5811 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 5812 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 5813 5814 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 5815 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 5816 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 5817 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 5818 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 5819 5820 #define S_FW_EQ_ETH_CMD_EQSIZE 0 5821 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 5822 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 5823 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 5824 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 5825 5826 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 5827 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 5828 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 5829 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 5830 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 5831 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 5832 5833 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 5834 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 5835 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 5836 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 5837 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 5838 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 5839 5840 #define S_FW_EQ_ETH_CMD_VIID 16 5841 #define M_FW_EQ_ETH_CMD_VIID 0xfff 5842 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 5843 #define G_FW_EQ_ETH_CMD_VIID(x) \ 5844 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 5845 5846 struct fw_eq_ctrl_cmd { 5847 __be32 op_to_vfn; 5848 __be32 alloc_to_len16; 5849 __be32 cmpliqid_eqid; 5850 __be32 physeqid_pkd; 5851 __be32 fetchszm_to_iqid; 5852 __be32 dcaen_to_eqsize; 5853 __be64 eqaddr; 5854 }; 5855 5856 #define S_FW_EQ_CTRL_CMD_PFN 8 5857 #define M_FW_EQ_CTRL_CMD_PFN 0x7 5858 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 5859 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 5860 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 5861 5862 #define S_FW_EQ_CTRL_CMD_VFN 0 5863 #define M_FW_EQ_CTRL_CMD_VFN 0xff 5864 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 5865 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 5866 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 5867 5868 #define S_FW_EQ_CTRL_CMD_ALLOC 31 5869 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 5870 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 5871 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 5872 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 5873 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 5874 5875 #define S_FW_EQ_CTRL_CMD_FREE 30 5876 #define M_FW_EQ_CTRL_CMD_FREE 0x1 5877 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 5878 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 5879 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 5880 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 5881 5882 #define S_FW_EQ_CTRL_CMD_MODIFY 29 5883 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 5884 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 5885 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 5886 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 5887 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 5888 5889 #define S_FW_EQ_CTRL_CMD_EQSTART 28 5890 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 5891 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 5892 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 5893 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 5894 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 5895 5896 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 5897 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 5898 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 5899 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 5900 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 5901 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 5902 5903 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 5904 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 5905 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 5906 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 5907 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 5908 5909 #define S_FW_EQ_CTRL_CMD_EQID 0 5910 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 5911 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 5912 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 5913 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 5914 5915 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 5916 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 5917 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 5918 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 5919 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 5920 5921 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 5922 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 5923 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 5924 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 5925 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 5926 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 5927 5928 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 5929 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 5930 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 5931 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 5932 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 5933 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 5934 5935 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 5936 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 5937 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 5938 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 5939 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 5940 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 5941 5942 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 5943 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 5944 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 5945 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 5946 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 5947 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 5948 5949 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 5950 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 5951 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 5952 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 5953 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 5954 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 5955 5956 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 5957 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 5958 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 5959 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 5960 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 5961 5962 #define S_FW_EQ_CTRL_CMD_CPRIO 19 5963 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 5964 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 5965 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 5966 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 5967 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 5968 5969 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 5970 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 5971 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 5972 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 5973 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 5974 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 5975 5976 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 5977 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 5978 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 5979 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 5980 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 5981 5982 #define S_FW_EQ_CTRL_CMD_IQID 0 5983 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 5984 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 5985 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 5986 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 5987 5988 #define S_FW_EQ_CTRL_CMD_DCAEN 31 5989 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 5990 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 5991 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 5992 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 5993 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 5994 5995 #define S_FW_EQ_CTRL_CMD_DCACPU 26 5996 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 5997 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 5998 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 5999 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 6000 6001 #define S_FW_EQ_CTRL_CMD_FBMIN 23 6002 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 6003 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 6004 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 6005 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 6006 6007 #define S_FW_EQ_CTRL_CMD_FBMAX 20 6008 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 6009 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 6010 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 6011 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 6012 6013 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 6014 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 6015 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6016 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6017 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 6018 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 6019 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 6020 6021 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 6022 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 6023 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6024 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 6025 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 6026 6027 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 6028 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 6029 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 6030 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 6031 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 6032 6033 struct fw_eq_ofld_cmd { 6034 __be32 op_to_vfn; 6035 __be32 alloc_to_len16; 6036 __be32 eqid_pkd; 6037 __be32 physeqid_pkd; 6038 __be32 fetchszm_to_iqid; 6039 __be32 dcaen_to_eqsize; 6040 __be64 eqaddr; 6041 }; 6042 6043 #define S_FW_EQ_OFLD_CMD_PFN 8 6044 #define M_FW_EQ_OFLD_CMD_PFN 0x7 6045 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 6046 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 6047 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 6048 6049 #define S_FW_EQ_OFLD_CMD_VFN 0 6050 #define M_FW_EQ_OFLD_CMD_VFN 0xff 6051 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 6052 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 6053 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 6054 6055 #define S_FW_EQ_OFLD_CMD_ALLOC 31 6056 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 6057 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 6058 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 6059 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 6060 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 6061 6062 #define S_FW_EQ_OFLD_CMD_FREE 30 6063 #define M_FW_EQ_OFLD_CMD_FREE 0x1 6064 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 6065 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 6066 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 6067 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 6068 6069 #define S_FW_EQ_OFLD_CMD_MODIFY 29 6070 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 6071 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 6072 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 6073 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 6074 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 6075 6076 #define S_FW_EQ_OFLD_CMD_EQSTART 28 6077 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 6078 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 6079 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 6080 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 6081 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 6082 6083 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 6084 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 6085 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 6086 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 6087 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 6088 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 6089 6090 #define S_FW_EQ_OFLD_CMD_EQID 0 6091 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 6092 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 6093 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 6094 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 6095 6096 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 6097 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 6098 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 6099 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 6100 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 6101 6102 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 6103 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 6104 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 6105 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 6106 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 6107 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 6108 6109 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 6110 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 6111 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 6112 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 6113 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 6114 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 6115 6116 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 6117 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 6118 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 6119 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 6120 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 6121 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 6122 6123 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 6124 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 6125 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 6126 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 6127 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 6128 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 6129 6130 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 6131 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 6132 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 6133 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 6134 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 6135 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 6136 6137 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 6138 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 6139 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 6140 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 6141 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 6142 6143 #define S_FW_EQ_OFLD_CMD_CPRIO 19 6144 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 6145 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 6146 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 6147 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 6148 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 6149 6150 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 6151 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 6152 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 6153 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 6154 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 6155 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 6156 6157 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 6158 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 6159 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 6160 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 6161 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 6162 6163 #define S_FW_EQ_OFLD_CMD_IQID 0 6164 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 6165 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 6166 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 6167 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 6168 6169 #define S_FW_EQ_OFLD_CMD_DCAEN 31 6170 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 6171 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 6172 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 6173 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 6174 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 6175 6176 #define S_FW_EQ_OFLD_CMD_DCACPU 26 6177 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 6178 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 6179 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 6180 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 6181 6182 #define S_FW_EQ_OFLD_CMD_FBMIN 23 6183 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 6184 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 6185 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 6186 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 6187 6188 #define S_FW_EQ_OFLD_CMD_FBMAX 20 6189 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 6190 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 6191 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 6192 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 6193 6194 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 6195 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 6196 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6197 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6198 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 6199 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 6200 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 6201 6202 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 6203 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 6204 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6205 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 6206 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 6207 6208 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 6209 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 6210 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 6211 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 6212 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 6213 6214 /* Macros for VIID parsing: 6215 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 6216 #define S_FW_VIID_PFN 8 6217 #define M_FW_VIID_PFN 0x7 6218 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 6219 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 6220 6221 #define S_FW_VIID_VIVLD 7 6222 #define M_FW_VIID_VIVLD 0x1 6223 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 6224 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 6225 6226 #define S_FW_VIID_VIN 0 6227 #define M_FW_VIID_VIN 0x7F 6228 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 6229 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 6230 6231 enum fw_vi_func { 6232 FW_VI_FUNC_ETH, 6233 FW_VI_FUNC_OFLD, 6234 FW_VI_FUNC_IWARP, 6235 FW_VI_FUNC_OPENISCSI, 6236 FW_VI_FUNC_OPENFCOE, 6237 FW_VI_FUNC_FOISCSI, 6238 FW_VI_FUNC_FOFCOE, 6239 FW_VI_FUNC_FW, 6240 }; 6241 6242 struct fw_vi_cmd { 6243 __be32 op_to_vfn; 6244 __be32 alloc_to_len16; 6245 __be16 type_to_viid; 6246 __u8 mac[6]; 6247 __u8 portid_pkd; 6248 __u8 nmac; 6249 __u8 nmac0[6]; 6250 __be16 norss_rsssize; 6251 __u8 nmac1[6]; 6252 __be16 idsiiq_pkd; 6253 __u8 nmac2[6]; 6254 __be16 idseiq_pkd; 6255 __u8 nmac3[6]; 6256 __be64 r9; 6257 __be64 r10; 6258 }; 6259 6260 #define S_FW_VI_CMD_PFN 8 6261 #define M_FW_VI_CMD_PFN 0x7 6262 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 6263 #define G_FW_VI_CMD_PFN(x) \ 6264 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 6265 6266 #define S_FW_VI_CMD_VFN 0 6267 #define M_FW_VI_CMD_VFN 0xff 6268 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 6269 #define G_FW_VI_CMD_VFN(x) \ 6270 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 6271 6272 #define S_FW_VI_CMD_ALLOC 31 6273 #define M_FW_VI_CMD_ALLOC 0x1 6274 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 6275 #define G_FW_VI_CMD_ALLOC(x) \ 6276 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 6277 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 6278 6279 #define S_FW_VI_CMD_FREE 30 6280 #define M_FW_VI_CMD_FREE 0x1 6281 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 6282 #define G_FW_VI_CMD_FREE(x) \ 6283 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 6284 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 6285 6286 #define S_FW_VI_CMD_TYPE 15 6287 #define M_FW_VI_CMD_TYPE 0x1 6288 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 6289 #define G_FW_VI_CMD_TYPE(x) \ 6290 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 6291 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 6292 6293 #define S_FW_VI_CMD_FUNC 12 6294 #define M_FW_VI_CMD_FUNC 0x7 6295 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 6296 #define G_FW_VI_CMD_FUNC(x) \ 6297 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 6298 6299 #define S_FW_VI_CMD_VIID 0 6300 #define M_FW_VI_CMD_VIID 0xfff 6301 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 6302 #define G_FW_VI_CMD_VIID(x) \ 6303 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 6304 6305 #define S_FW_VI_CMD_PORTID 4 6306 #define M_FW_VI_CMD_PORTID 0xf 6307 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 6308 #define G_FW_VI_CMD_PORTID(x) \ 6309 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 6310 6311 #define S_FW_VI_CMD_NORSS 11 6312 #define M_FW_VI_CMD_NORSS 0x1 6313 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 6314 #define G_FW_VI_CMD_NORSS(x) \ 6315 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 6316 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 6317 6318 #define S_FW_VI_CMD_RSSSIZE 0 6319 #define M_FW_VI_CMD_RSSSIZE 0x7ff 6320 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 6321 #define G_FW_VI_CMD_RSSSIZE(x) \ 6322 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 6323 6324 #define S_FW_VI_CMD_IDSIIQ 0 6325 #define M_FW_VI_CMD_IDSIIQ 0x3ff 6326 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 6327 #define G_FW_VI_CMD_IDSIIQ(x) \ 6328 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 6329 6330 #define S_FW_VI_CMD_IDSEIQ 0 6331 #define M_FW_VI_CMD_IDSEIQ 0x3ff 6332 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 6333 #define G_FW_VI_CMD_IDSEIQ(x) \ 6334 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 6335 6336 /* Special VI_MAC command index ids */ 6337 #define FW_VI_MAC_ADD_MAC 0x3FF 6338 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 6339 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 6340 6341 enum fw_vi_mac_smac { 6342 FW_VI_MAC_MPS_TCAM_ENTRY, 6343 FW_VI_MAC_MPS_TCAM_ONLY, 6344 FW_VI_MAC_SMT_ONLY, 6345 FW_VI_MAC_SMT_AND_MPSTCAM 6346 }; 6347 6348 enum fw_vi_mac_result { 6349 FW_VI_MAC_R_SUCCESS, 6350 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 6351 FW_VI_MAC_R_SMAC_FAIL, 6352 FW_VI_MAC_R_F_ACL_CHECK 6353 }; 6354 6355 enum fw_vi_mac_entry_types { 6356 FW_VI_MAC_TYPE_EXACTMAC, 6357 FW_VI_MAC_TYPE_HASHVEC, 6358 FW_VI_MAC_TYPE_RAW, 6359 }; 6360 6361 struct fw_vi_mac_cmd { 6362 __be32 op_to_viid; 6363 __be32 freemacs_to_len16; 6364 union fw_vi_mac { 6365 struct fw_vi_mac_exact { 6366 __be16 valid_to_idx; 6367 __u8 macaddr[6]; 6368 } exact[7]; 6369 struct fw_vi_mac_hash { 6370 __be64 hashvec; 6371 } hash; 6372 struct fw_vi_mac_raw { 6373 __be32 raw_idx_pkd; 6374 __be32 data0_pkd; 6375 __be32 data1[2]; 6376 __be64 data0m_pkd; 6377 __be32 data1m[2]; 6378 } raw; 6379 } u; 6380 }; 6381 6382 #define S_FW_VI_MAC_CMD_VIID 0 6383 #define M_FW_VI_MAC_CMD_VIID 0xfff 6384 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 6385 #define G_FW_VI_MAC_CMD_VIID(x) \ 6386 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 6387 6388 #define S_FW_VI_MAC_CMD_FREEMACS 31 6389 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 6390 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 6391 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 6392 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 6393 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 6394 6395 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 6396 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 6397 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 6398 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 6399 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 6400 6401 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 6402 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 6403 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 6404 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 6405 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 6406 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 6407 6408 #define S_FW_VI_MAC_CMD_VALID 15 6409 #define M_FW_VI_MAC_CMD_VALID 0x1 6410 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 6411 #define G_FW_VI_MAC_CMD_VALID(x) \ 6412 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 6413 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 6414 6415 #define S_FW_VI_MAC_CMD_PRIO 12 6416 #define M_FW_VI_MAC_CMD_PRIO 0x7 6417 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 6418 #define G_FW_VI_MAC_CMD_PRIO(x) \ 6419 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 6420 6421 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 6422 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 6423 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 6424 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 6425 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 6426 6427 #define S_FW_VI_MAC_CMD_IDX 0 6428 #define M_FW_VI_MAC_CMD_IDX 0x3ff 6429 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 6430 #define G_FW_VI_MAC_CMD_IDX(x) \ 6431 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 6432 6433 #define S_FW_VI_MAC_CMD_RAW_IDX 16 6434 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 6435 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 6436 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 6437 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 6438 6439 #define S_FW_VI_MAC_CMD_DATA0 0 6440 #define M_FW_VI_MAC_CMD_DATA0 0xffff 6441 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 6442 #define G_FW_VI_MAC_CMD_DATA0(x) \ 6443 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 6444 6445 /* T4 max MTU supported */ 6446 #define T4_MAX_MTU_SUPPORTED 9600 6447 #define FW_RXMODE_MTU_NO_CHG 65535 6448 6449 struct fw_vi_rxmode_cmd { 6450 __be32 op_to_viid; 6451 __be32 retval_len16; 6452 __be32 mtu_to_vlanexen; 6453 __be32 r4_lo; 6454 }; 6455 6456 #define S_FW_VI_RXMODE_CMD_VIID 0 6457 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 6458 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 6459 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 6460 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 6461 6462 #define S_FW_VI_RXMODE_CMD_MTU 16 6463 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 6464 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 6465 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 6466 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 6467 6468 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 6469 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 6470 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 6471 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 6472 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 6473 6474 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 6475 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 6476 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6477 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 6478 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 6479 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 6480 6481 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 6482 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 6483 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6484 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 6485 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 6486 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 6487 6488 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 6489 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 6490 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 6491 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 6492 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 6493 6494 struct fw_vi_enable_cmd { 6495 __be32 op_to_viid; 6496 __be32 ien_to_len16; 6497 __be16 blinkdur; 6498 __be16 r3; 6499 __be32 r4; 6500 }; 6501 6502 #define S_FW_VI_ENABLE_CMD_VIID 0 6503 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 6504 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 6505 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 6506 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 6507 6508 #define S_FW_VI_ENABLE_CMD_IEN 31 6509 #define M_FW_VI_ENABLE_CMD_IEN 0x1 6510 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 6511 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 6512 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 6513 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 6514 6515 #define S_FW_VI_ENABLE_CMD_EEN 30 6516 #define M_FW_VI_ENABLE_CMD_EEN 0x1 6517 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 6518 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 6519 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 6520 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 6521 6522 #define S_FW_VI_ENABLE_CMD_LED 29 6523 #define M_FW_VI_ENABLE_CMD_LED 0x1 6524 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 6525 #define G_FW_VI_ENABLE_CMD_LED(x) \ 6526 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 6527 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 6528 6529 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 6530 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 6531 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 6532 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 6533 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 6534 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 6535 6536 /* VI VF stats offset definitions */ 6537 #define VI_VF_NUM_STATS 16 6538 enum fw_vi_stats_vf_index { 6539 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 6540 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 6541 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 6542 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 6543 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 6544 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 6545 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 6546 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 6547 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 6548 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 6549 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 6550 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 6551 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 6552 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 6553 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 6554 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 6555 }; 6556 6557 /* VI PF stats offset definitions */ 6558 #define VI_PF_NUM_STATS 17 6559 enum fw_vi_stats_pf_index { 6560 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 6561 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 6562 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 6563 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 6564 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 6565 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 6566 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 6567 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 6568 FW_VI_PF_STAT_RX_BYTES_IX, 6569 FW_VI_PF_STAT_RX_FRAMES_IX, 6570 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 6571 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 6572 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 6573 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 6574 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 6575 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 6576 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 6577 }; 6578 6579 struct fw_vi_stats_cmd { 6580 __be32 op_to_viid; 6581 __be32 retval_len16; 6582 union fw_vi_stats { 6583 struct fw_vi_stats_ctl { 6584 __be16 nstats_ix; 6585 __be16 r6; 6586 __be32 r7; 6587 __be64 stat0; 6588 __be64 stat1; 6589 __be64 stat2; 6590 __be64 stat3; 6591 __be64 stat4; 6592 __be64 stat5; 6593 } ctl; 6594 struct fw_vi_stats_pf { 6595 __be64 tx_bcast_bytes; 6596 __be64 tx_bcast_frames; 6597 __be64 tx_mcast_bytes; 6598 __be64 tx_mcast_frames; 6599 __be64 tx_ucast_bytes; 6600 __be64 tx_ucast_frames; 6601 __be64 tx_offload_bytes; 6602 __be64 tx_offload_frames; 6603 __be64 rx_pf_bytes; 6604 __be64 rx_pf_frames; 6605 __be64 rx_bcast_bytes; 6606 __be64 rx_bcast_frames; 6607 __be64 rx_mcast_bytes; 6608 __be64 rx_mcast_frames; 6609 __be64 rx_ucast_bytes; 6610 __be64 rx_ucast_frames; 6611 __be64 rx_err_frames; 6612 } pf; 6613 struct fw_vi_stats_vf { 6614 __be64 tx_bcast_bytes; 6615 __be64 tx_bcast_frames; 6616 __be64 tx_mcast_bytes; 6617 __be64 tx_mcast_frames; 6618 __be64 tx_ucast_bytes; 6619 __be64 tx_ucast_frames; 6620 __be64 tx_drop_frames; 6621 __be64 tx_offload_bytes; 6622 __be64 tx_offload_frames; 6623 __be64 rx_bcast_bytes; 6624 __be64 rx_bcast_frames; 6625 __be64 rx_mcast_bytes; 6626 __be64 rx_mcast_frames; 6627 __be64 rx_ucast_bytes; 6628 __be64 rx_ucast_frames; 6629 __be64 rx_err_frames; 6630 } vf; 6631 } u; 6632 }; 6633 6634 #define S_FW_VI_STATS_CMD_VIID 0 6635 #define M_FW_VI_STATS_CMD_VIID 0xfff 6636 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 6637 #define G_FW_VI_STATS_CMD_VIID(x) \ 6638 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 6639 6640 #define S_FW_VI_STATS_CMD_NSTATS 12 6641 #define M_FW_VI_STATS_CMD_NSTATS 0x7 6642 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 6643 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 6644 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 6645 6646 #define S_FW_VI_STATS_CMD_IX 0 6647 #define M_FW_VI_STATS_CMD_IX 0x1f 6648 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 6649 #define G_FW_VI_STATS_CMD_IX(x) \ 6650 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 6651 6652 struct fw_acl_mac_cmd { 6653 __be32 op_to_vfn; 6654 __be32 en_to_len16; 6655 __u8 nmac; 6656 __u8 r3[7]; 6657 __be16 r4; 6658 __u8 macaddr0[6]; 6659 __be16 r5; 6660 __u8 macaddr1[6]; 6661 __be16 r6; 6662 __u8 macaddr2[6]; 6663 __be16 r7; 6664 __u8 macaddr3[6]; 6665 }; 6666 6667 #define S_FW_ACL_MAC_CMD_PFN 8 6668 #define M_FW_ACL_MAC_CMD_PFN 0x7 6669 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 6670 #define G_FW_ACL_MAC_CMD_PFN(x) \ 6671 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 6672 6673 #define S_FW_ACL_MAC_CMD_VFN 0 6674 #define M_FW_ACL_MAC_CMD_VFN 0xff 6675 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 6676 #define G_FW_ACL_MAC_CMD_VFN(x) \ 6677 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 6678 6679 #define S_FW_ACL_MAC_CMD_EN 31 6680 #define M_FW_ACL_MAC_CMD_EN 0x1 6681 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 6682 #define G_FW_ACL_MAC_CMD_EN(x) \ 6683 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 6684 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 6685 6686 struct fw_acl_vlan_cmd { 6687 __be32 op_to_vfn; 6688 __be32 en_to_len16; 6689 __u8 nvlan; 6690 __u8 dropnovlan_fm; 6691 __u8 r3_lo[6]; 6692 __be16 vlanid[16]; 6693 }; 6694 6695 #define S_FW_ACL_VLAN_CMD_PFN 8 6696 #define M_FW_ACL_VLAN_CMD_PFN 0x7 6697 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 6698 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 6699 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 6700 6701 #define S_FW_ACL_VLAN_CMD_VFN 0 6702 #define M_FW_ACL_VLAN_CMD_VFN 0xff 6703 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 6704 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 6705 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 6706 6707 #define S_FW_ACL_VLAN_CMD_EN 31 6708 #define M_FW_ACL_VLAN_CMD_EN 0x1 6709 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 6710 #define G_FW_ACL_VLAN_CMD_EN(x) \ 6711 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 6712 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 6713 6714 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 6715 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 6716 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 6717 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 6718 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 6719 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 6720 6721 #define S_FW_ACL_VLAN_CMD_FM 6 6722 #define M_FW_ACL_VLAN_CMD_FM 0x1 6723 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 6724 #define G_FW_ACL_VLAN_CMD_FM(x) \ 6725 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 6726 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 6727 6728 /* port capabilities bitmap */ 6729 enum fw_port_cap { 6730 FW_PORT_CAP_SPEED_100M = 0x0001, 6731 FW_PORT_CAP_SPEED_1G = 0x0002, 6732 FW_PORT_CAP_SPEED_25G = 0x0004, 6733 FW_PORT_CAP_SPEED_10G = 0x0008, 6734 FW_PORT_CAP_SPEED_40G = 0x0010, 6735 FW_PORT_CAP_SPEED_100G = 0x0020, 6736 FW_PORT_CAP_FC_RX = 0x0040, 6737 FW_PORT_CAP_FC_TX = 0x0080, 6738 FW_PORT_CAP_ANEG = 0x0100, 6739 FW_PORT_CAP_MDIX = 0x0200, 6740 FW_PORT_CAP_MDIAUTO = 0x0400, 6741 FW_PORT_CAP_FEC = 0x0800, 6742 FW_PORT_CAP_TECHKR = 0x1000, 6743 FW_PORT_CAP_TECHKX4 = 0x2000, 6744 FW_PORT_CAP_802_3_PAUSE = 0x4000, 6745 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 6746 }; 6747 6748 #define S_FW_PORT_AUXLINFO_MDI 3 6749 #define M_FW_PORT_AUXLINFO_MDI 0x3 6750 #define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI) 6751 #define G_FW_PORT_AUXLINFO_MDI(x) \ 6752 (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI) 6753 6754 #define S_FW_PORT_AUXLINFO_KX4 2 6755 #define M_FW_PORT_AUXLINFO_KX4 0x1 6756 #define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4) 6757 #define G_FW_PORT_AUXLINFO_KX4(x) \ 6758 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 6759 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 6760 6761 #define S_FW_PORT_AUXLINFO_KR 1 6762 #define M_FW_PORT_AUXLINFO_KR 0x1 6763 #define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR) 6764 #define G_FW_PORT_AUXLINFO_KR(x) \ 6765 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 6766 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 6767 6768 #define S_FW_PORT_AUXLINFO_FEC 0 6769 #define M_FW_PORT_AUXLINFO_FEC 0x1 6770 #define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) 6771 #define G_FW_PORT_AUXLINFO_FEC(x) \ 6772 (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) 6773 #define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) 6774 6775 #define S_FW_PORT_RCAP_AUX 11 6776 #define M_FW_PORT_RCAP_AUX 0x7 6777 #define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX) 6778 #define G_FW_PORT_RCAP_AUX(x) \ 6779 (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX) 6780 6781 #define S_FW_PORT_CAP_SPEED 0 6782 #define M_FW_PORT_CAP_SPEED 0x3f 6783 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 6784 #define G_FW_PORT_CAP_SPEED(x) \ 6785 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 6786 6787 #define S_FW_PORT_CAP_FC 6 6788 #define M_FW_PORT_CAP_FC 0x3 6789 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 6790 #define G_FW_PORT_CAP_FC(x) \ 6791 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 6792 6793 #define S_FW_PORT_CAP_ANEG 8 6794 #define M_FW_PORT_CAP_ANEG 0x1 6795 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 6796 #define G_FW_PORT_CAP_ANEG(x) \ 6797 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 6798 6799 #define S_FW_PORT_CAP_802_3 14 6800 #define M_FW_PORT_CAP_802_3 0x3 6801 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 6802 #define G_FW_PORT_CAP_802_3(x) \ 6803 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 6804 6805 enum fw_port_mdi { 6806 FW_PORT_CAP_MDI_UNCHANGED, 6807 FW_PORT_CAP_MDI_AUTO, 6808 FW_PORT_CAP_MDI_F_STRAIGHT, 6809 FW_PORT_CAP_MDI_F_CROSSOVER 6810 }; 6811 6812 #define S_FW_PORT_CAP_MDI 9 6813 #define M_FW_PORT_CAP_MDI 3 6814 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 6815 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 6816 6817 enum fw_port_action { 6818 FW_PORT_ACTION_L1_CFG = 0x0001, 6819 FW_PORT_ACTION_L2_CFG = 0x0002, 6820 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 6821 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 6822 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 6823 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 6824 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 6825 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 6826 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 6827 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 6828 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 6829 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 6830 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 6831 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 6832 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 6833 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 6834 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 6835 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 6836 FW_PORT_ACTION_PHY_RESET = 0x0040, 6837 FW_PORT_ACTION_PMA_RESET = 0x0041, 6838 FW_PORT_ACTION_PCS_RESET = 0x0042, 6839 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 6840 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 6841 FW_PORT_ACTION_AN_RESET = 0x0045, 6842 6843 }; 6844 6845 enum fw_port_l2cfg_ctlbf { 6846 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 6847 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 6848 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 6849 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 6850 FW_PORT_L2_CTLBF_IVLAN = 0x10, 6851 FW_PORT_L2_CTLBF_TXIPG = 0x20, 6852 FW_PORT_L2_CTLBF_MTU = 0x40 6853 }; 6854 6855 enum fw_dcb_app_tlv_sf { 6856 FW_DCB_APP_SF_ETHERTYPE, 6857 FW_DCB_APP_SF_SOCKET_TCP, 6858 FW_DCB_APP_SF_SOCKET_UDP, 6859 FW_DCB_APP_SF_SOCKET_ALL, 6860 }; 6861 6862 enum fw_port_dcb_versions { 6863 FW_PORT_DCB_VER_UNKNOWN, 6864 FW_PORT_DCB_VER_CEE1D0, 6865 FW_PORT_DCB_VER_CEE1D01, 6866 FW_PORT_DCB_VER_IEEE, 6867 FW_PORT_DCB_VER_AUTO=7 6868 }; 6869 6870 enum fw_port_dcb_cfg { 6871 FW_PORT_DCB_CFG_PG = 0x01, 6872 FW_PORT_DCB_CFG_PFC = 0x02, 6873 FW_PORT_DCB_CFG_APPL = 0x04 6874 }; 6875 6876 enum fw_port_dcb_cfg_rc { 6877 FW_PORT_DCB_CFG_SUCCESS = 0x0, 6878 FW_PORT_DCB_CFG_ERROR = 0x1 6879 }; 6880 6881 enum fw_port_dcb_type { 6882 FW_PORT_DCB_TYPE_PGID = 0x00, 6883 FW_PORT_DCB_TYPE_PGRATE = 0x01, 6884 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 6885 FW_PORT_DCB_TYPE_PFC = 0x03, 6886 FW_PORT_DCB_TYPE_APP_ID = 0x04, 6887 FW_PORT_DCB_TYPE_CONTROL = 0x05, 6888 }; 6889 6890 enum fw_port_dcb_feature_state { 6891 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 6892 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 6893 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 6894 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 6895 }; 6896 6897 enum fw_port_diag_ops { 6898 FW_PORT_DIAGS_TEMP = 0x00, 6899 FW_PORT_DIAGS_TX_POWER = 0x01, 6900 FW_PORT_DIAGS_RX_POWER = 0x02, 6901 FW_PORT_DIAGS_TX_DIS = 0x03, 6902 }; 6903 6904 struct fw_port_cmd { 6905 __be32 op_to_portid; 6906 __be32 action_to_len16; 6907 union fw_port { 6908 struct fw_port_l1cfg { 6909 __be32 rcap; 6910 __be32 r; 6911 } l1cfg; 6912 struct fw_port_l2cfg { 6913 __u8 ctlbf; 6914 __u8 ovlan3_to_ivlan0; 6915 __be16 ivlantype; 6916 __be16 txipg_force_pinfo; 6917 __be16 mtu; 6918 __be16 ovlan0mask; 6919 __be16 ovlan0type; 6920 __be16 ovlan1mask; 6921 __be16 ovlan1type; 6922 __be16 ovlan2mask; 6923 __be16 ovlan2type; 6924 __be16 ovlan3mask; 6925 __be16 ovlan3type; 6926 } l2cfg; 6927 struct fw_port_info { 6928 __be32 lstatus_to_modtype; 6929 __be16 pcap; 6930 __be16 acap; 6931 __be16 mtu; 6932 __u8 cbllen; 6933 __u8 auxlinfo; 6934 __u8 dcbxdis_pkd; 6935 __u8 r8_lo; 6936 __be16 lpacap; 6937 __be64 r9; 6938 } info; 6939 struct fw_port_diags { 6940 __u8 diagop; 6941 __u8 r[3]; 6942 __be32 diagval; 6943 } diags; 6944 union fw_port_dcb { 6945 struct fw_port_dcb_pgid { 6946 __u8 type; 6947 __u8 apply_pkd; 6948 __u8 r10_lo[2]; 6949 __be32 pgid; 6950 __be64 r11; 6951 } pgid; 6952 struct fw_port_dcb_pgrate { 6953 __u8 type; 6954 __u8 apply_pkd; 6955 __u8 r10_lo[5]; 6956 __u8 num_tcs_supported; 6957 __u8 pgrate[8]; 6958 __u8 tsa[8]; 6959 } pgrate; 6960 struct fw_port_dcb_priorate { 6961 __u8 type; 6962 __u8 apply_pkd; 6963 __u8 r10_lo[6]; 6964 __u8 strict_priorate[8]; 6965 } priorate; 6966 struct fw_port_dcb_pfc { 6967 __u8 type; 6968 __u8 pfcen; 6969 __u8 r10[5]; 6970 __u8 max_pfc_tcs; 6971 __be64 r11; 6972 } pfc; 6973 struct fw_port_app_priority { 6974 __u8 type; 6975 __u8 r10[2]; 6976 __u8 idx; 6977 __u8 user_prio_map; 6978 __u8 sel_field; 6979 __be16 protocolid; 6980 __be64 r12; 6981 } app_priority; 6982 struct fw_port_dcb_control { 6983 __u8 type; 6984 __u8 all_syncd_pkd; 6985 __be16 dcb_version_to_app_state; 6986 __be32 r11; 6987 __be64 r12; 6988 } control; 6989 } dcb; 6990 } u; 6991 }; 6992 6993 #define S_FW_PORT_CMD_READ 22 6994 #define M_FW_PORT_CMD_READ 0x1 6995 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 6996 #define G_FW_PORT_CMD_READ(x) \ 6997 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 6998 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 6999 7000 #define S_FW_PORT_CMD_PORTID 0 7001 #define M_FW_PORT_CMD_PORTID 0xf 7002 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 7003 #define G_FW_PORT_CMD_PORTID(x) \ 7004 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 7005 7006 #define S_FW_PORT_CMD_ACTION 16 7007 #define M_FW_PORT_CMD_ACTION 0xffff 7008 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 7009 #define G_FW_PORT_CMD_ACTION(x) \ 7010 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 7011 7012 #define S_FW_PORT_CMD_OVLAN3 7 7013 #define M_FW_PORT_CMD_OVLAN3 0x1 7014 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 7015 #define G_FW_PORT_CMD_OVLAN3(x) \ 7016 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 7017 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 7018 7019 #define S_FW_PORT_CMD_OVLAN2 6 7020 #define M_FW_PORT_CMD_OVLAN2 0x1 7021 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 7022 #define G_FW_PORT_CMD_OVLAN2(x) \ 7023 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 7024 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 7025 7026 #define S_FW_PORT_CMD_OVLAN1 5 7027 #define M_FW_PORT_CMD_OVLAN1 0x1 7028 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 7029 #define G_FW_PORT_CMD_OVLAN1(x) \ 7030 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 7031 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 7032 7033 #define S_FW_PORT_CMD_OVLAN0 4 7034 #define M_FW_PORT_CMD_OVLAN0 0x1 7035 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 7036 #define G_FW_PORT_CMD_OVLAN0(x) \ 7037 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 7038 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 7039 7040 #define S_FW_PORT_CMD_IVLAN0 3 7041 #define M_FW_PORT_CMD_IVLAN0 0x1 7042 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 7043 #define G_FW_PORT_CMD_IVLAN0(x) \ 7044 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 7045 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 7046 7047 #define S_FW_PORT_CMD_TXIPG 3 7048 #define M_FW_PORT_CMD_TXIPG 0x1fff 7049 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 7050 #define G_FW_PORT_CMD_TXIPG(x) \ 7051 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 7052 7053 #define S_FW_PORT_CMD_FORCE_PINFO 0 7054 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 7055 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 7056 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 7057 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 7058 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 7059 7060 #define S_FW_PORT_CMD_LSTATUS 31 7061 #define M_FW_PORT_CMD_LSTATUS 0x1 7062 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 7063 #define G_FW_PORT_CMD_LSTATUS(x) \ 7064 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 7065 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 7066 7067 #define S_FW_PORT_CMD_LSPEED 24 7068 #define M_FW_PORT_CMD_LSPEED 0x3f 7069 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 7070 #define G_FW_PORT_CMD_LSPEED(x) \ 7071 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 7072 7073 #define S_FW_PORT_CMD_TXPAUSE 23 7074 #define M_FW_PORT_CMD_TXPAUSE 0x1 7075 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 7076 #define G_FW_PORT_CMD_TXPAUSE(x) \ 7077 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 7078 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 7079 7080 #define S_FW_PORT_CMD_RXPAUSE 22 7081 #define M_FW_PORT_CMD_RXPAUSE 0x1 7082 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 7083 #define G_FW_PORT_CMD_RXPAUSE(x) \ 7084 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 7085 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 7086 7087 #define S_FW_PORT_CMD_MDIOCAP 21 7088 #define M_FW_PORT_CMD_MDIOCAP 0x1 7089 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 7090 #define G_FW_PORT_CMD_MDIOCAP(x) \ 7091 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 7092 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 7093 7094 #define S_FW_PORT_CMD_MDIOADDR 16 7095 #define M_FW_PORT_CMD_MDIOADDR 0x1f 7096 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 7097 #define G_FW_PORT_CMD_MDIOADDR(x) \ 7098 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 7099 7100 #define S_FW_PORT_CMD_LPTXPAUSE 15 7101 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 7102 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 7103 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 7104 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 7105 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 7106 7107 #define S_FW_PORT_CMD_LPRXPAUSE 14 7108 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 7109 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 7110 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 7111 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 7112 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 7113 7114 #define S_FW_PORT_CMD_PTYPE 8 7115 #define M_FW_PORT_CMD_PTYPE 0x1f 7116 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 7117 #define G_FW_PORT_CMD_PTYPE(x) \ 7118 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 7119 7120 #define S_FW_PORT_CMD_LINKDNRC 5 7121 #define M_FW_PORT_CMD_LINKDNRC 0x7 7122 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 7123 #define G_FW_PORT_CMD_LINKDNRC(x) \ 7124 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 7125 7126 #define S_FW_PORT_CMD_MODTYPE 0 7127 #define M_FW_PORT_CMD_MODTYPE 0x1f 7128 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 7129 #define G_FW_PORT_CMD_MODTYPE(x) \ 7130 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 7131 7132 #define S_FW_PORT_CMD_DCBXDIS 7 7133 #define M_FW_PORT_CMD_DCBXDIS 0x1 7134 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 7135 #define G_FW_PORT_CMD_DCBXDIS(x) \ 7136 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 7137 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 7138 7139 #define S_FW_PORT_CMD_APPLY 7 7140 #define M_FW_PORT_CMD_APPLY 0x1 7141 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 7142 #define G_FW_PORT_CMD_APPLY(x) \ 7143 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 7144 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 7145 7146 #define S_FW_PORT_CMD_ALL_SYNCD 7 7147 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 7148 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 7149 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 7150 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 7151 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 7152 7153 #define S_FW_PORT_CMD_DCB_VERSION 12 7154 #define M_FW_PORT_CMD_DCB_VERSION 0x7 7155 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 7156 #define G_FW_PORT_CMD_DCB_VERSION(x) \ 7157 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 7158 7159 #define S_FW_PORT_CMD_PFC_STATE 8 7160 #define M_FW_PORT_CMD_PFC_STATE 0xf 7161 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 7162 #define G_FW_PORT_CMD_PFC_STATE(x) \ 7163 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 7164 7165 #define S_FW_PORT_CMD_ETS_STATE 4 7166 #define M_FW_PORT_CMD_ETS_STATE 0xf 7167 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 7168 #define G_FW_PORT_CMD_ETS_STATE(x) \ 7169 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 7170 7171 #define S_FW_PORT_CMD_APP_STATE 0 7172 #define M_FW_PORT_CMD_APP_STATE 0xf 7173 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 7174 #define G_FW_PORT_CMD_APP_STATE(x) \ 7175 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 7176 7177 /* 7178 * These are configured into the VPD and hence tools that generate 7179 * VPD may use this enumeration. 7180 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 7181 * 7182 * REMEMBER: 7183 * Update the Common Code t4_hw.c:t4_get_port_type_description() 7184 * with any new Firmware Port Technology Types! 7185 */ 7186 enum fw_port_type { 7187 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 7188 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 7189 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 7190 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 7191 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 7192 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 7193 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 7194 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 7195 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 7196 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 7197 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 7198 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 7199 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 7200 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 7201 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 7202 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP ANGE */ 7203 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G */ 7204 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G */ 7205 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G */ 7206 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G */ 7207 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G */ 7208 7209 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 7210 }; 7211 7212 /* These are read from module's EEPROM and determined once the 7213 module is inserted. */ 7214 enum fw_port_module_type { 7215 FW_PORT_MOD_TYPE_NA = 0x0, 7216 FW_PORT_MOD_TYPE_LR = 0x1, 7217 FW_PORT_MOD_TYPE_SR = 0x2, 7218 FW_PORT_MOD_TYPE_ER = 0x3, 7219 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 7220 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 7221 FW_PORT_MOD_TYPE_LRM = 0x6, 7222 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 7223 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 7224 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 7225 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 7226 }; 7227 7228 /* used by FW and tools may use this to generate VPD */ 7229 enum fw_port_mod_sub_type { 7230 FW_PORT_MOD_SUB_TYPE_NA, 7231 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 7232 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 7233 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 7234 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 7235 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 7236 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 7237 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 7238 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 7239 7240 /* 7241 * The following will never been in the VPD. They are TWINAX cable 7242 * lengths decoded from SFP+ module i2c PROMs. These should almost 7243 * certainly go somewhere else ... 7244 */ 7245 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 7246 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 7247 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 7248 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 7249 }; 7250 7251 /* link down reason codes (3b) */ 7252 enum fw_port_link_dn_rc { 7253 FW_PORT_LINK_DN_RC_NONE, 7254 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 7255 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 7256 FW_PORT_LINK_DN_RESERVED3, 7257 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 7258 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 7259 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 7260 FW_PORT_LINK_DN_RESERVED7 7261 }; 7262 enum fw_port_stats_tx_index { 7263 FW_STAT_TX_PORT_BYTES_IX = 0, 7264 FW_STAT_TX_PORT_FRAMES_IX, 7265 FW_STAT_TX_PORT_BCAST_IX, 7266 FW_STAT_TX_PORT_MCAST_IX, 7267 FW_STAT_TX_PORT_UCAST_IX, 7268 FW_STAT_TX_PORT_ERROR_IX, 7269 FW_STAT_TX_PORT_64B_IX, 7270 FW_STAT_TX_PORT_65B_127B_IX, 7271 FW_STAT_TX_PORT_128B_255B_IX, 7272 FW_STAT_TX_PORT_256B_511B_IX, 7273 FW_STAT_TX_PORT_512B_1023B_IX, 7274 FW_STAT_TX_PORT_1024B_1518B_IX, 7275 FW_STAT_TX_PORT_1519B_MAX_IX, 7276 FW_STAT_TX_PORT_DROP_IX, 7277 FW_STAT_TX_PORT_PAUSE_IX, 7278 FW_STAT_TX_PORT_PPP0_IX, 7279 FW_STAT_TX_PORT_PPP1_IX, 7280 FW_STAT_TX_PORT_PPP2_IX, 7281 FW_STAT_TX_PORT_PPP3_IX, 7282 FW_STAT_TX_PORT_PPP4_IX, 7283 FW_STAT_TX_PORT_PPP5_IX, 7284 FW_STAT_TX_PORT_PPP6_IX, 7285 FW_STAT_TX_PORT_PPP7_IX, 7286 FW_NUM_PORT_TX_STATS 7287 }; 7288 7289 enum fw_port_stat_rx_index { 7290 FW_STAT_RX_PORT_BYTES_IX = 0, 7291 FW_STAT_RX_PORT_FRAMES_IX, 7292 FW_STAT_RX_PORT_BCAST_IX, 7293 FW_STAT_RX_PORT_MCAST_IX, 7294 FW_STAT_RX_PORT_UCAST_IX, 7295 FW_STAT_RX_PORT_MTU_ERROR_IX, 7296 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 7297 FW_STAT_RX_PORT_CRC_ERROR_IX, 7298 FW_STAT_RX_PORT_LEN_ERROR_IX, 7299 FW_STAT_RX_PORT_SYM_ERROR_IX, 7300 FW_STAT_RX_PORT_64B_IX, 7301 FW_STAT_RX_PORT_65B_127B_IX, 7302 FW_STAT_RX_PORT_128B_255B_IX, 7303 FW_STAT_RX_PORT_256B_511B_IX, 7304 FW_STAT_RX_PORT_512B_1023B_IX, 7305 FW_STAT_RX_PORT_1024B_1518B_IX, 7306 FW_STAT_RX_PORT_1519B_MAX_IX, 7307 FW_STAT_RX_PORT_PAUSE_IX, 7308 FW_STAT_RX_PORT_PPP0_IX, 7309 FW_STAT_RX_PORT_PPP1_IX, 7310 FW_STAT_RX_PORT_PPP2_IX, 7311 FW_STAT_RX_PORT_PPP3_IX, 7312 FW_STAT_RX_PORT_PPP4_IX, 7313 FW_STAT_RX_PORT_PPP5_IX, 7314 FW_STAT_RX_PORT_PPP6_IX, 7315 FW_STAT_RX_PORT_PPP7_IX, 7316 FW_STAT_RX_PORT_LESS_64B_IX, 7317 FW_STAT_RX_PORT_MAC_ERROR_IX, 7318 FW_NUM_PORT_RX_STATS 7319 }; 7320 /* port stats */ 7321 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 7322 FW_NUM_PORT_RX_STATS) 7323 7324 7325 struct fw_port_stats_cmd { 7326 __be32 op_to_portid; 7327 __be32 retval_len16; 7328 union fw_port_stats { 7329 struct fw_port_stats_ctl { 7330 __u8 nstats_bg_bm; 7331 __u8 tx_ix; 7332 __be16 r6; 7333 __be32 r7; 7334 __be64 stat0; 7335 __be64 stat1; 7336 __be64 stat2; 7337 __be64 stat3; 7338 __be64 stat4; 7339 __be64 stat5; 7340 } ctl; 7341 struct fw_port_stats_all { 7342 __be64 tx_bytes; 7343 __be64 tx_frames; 7344 __be64 tx_bcast; 7345 __be64 tx_mcast; 7346 __be64 tx_ucast; 7347 __be64 tx_error; 7348 __be64 tx_64b; 7349 __be64 tx_65b_127b; 7350 __be64 tx_128b_255b; 7351 __be64 tx_256b_511b; 7352 __be64 tx_512b_1023b; 7353 __be64 tx_1024b_1518b; 7354 __be64 tx_1519b_max; 7355 __be64 tx_drop; 7356 __be64 tx_pause; 7357 __be64 tx_ppp0; 7358 __be64 tx_ppp1; 7359 __be64 tx_ppp2; 7360 __be64 tx_ppp3; 7361 __be64 tx_ppp4; 7362 __be64 tx_ppp5; 7363 __be64 tx_ppp6; 7364 __be64 tx_ppp7; 7365 __be64 rx_bytes; 7366 __be64 rx_frames; 7367 __be64 rx_bcast; 7368 __be64 rx_mcast; 7369 __be64 rx_ucast; 7370 __be64 rx_mtu_error; 7371 __be64 rx_mtu_crc_error; 7372 __be64 rx_crc_error; 7373 __be64 rx_len_error; 7374 __be64 rx_sym_error; 7375 __be64 rx_64b; 7376 __be64 rx_65b_127b; 7377 __be64 rx_128b_255b; 7378 __be64 rx_256b_511b; 7379 __be64 rx_512b_1023b; 7380 __be64 rx_1024b_1518b; 7381 __be64 rx_1519b_max; 7382 __be64 rx_pause; 7383 __be64 rx_ppp0; 7384 __be64 rx_ppp1; 7385 __be64 rx_ppp2; 7386 __be64 rx_ppp3; 7387 __be64 rx_ppp4; 7388 __be64 rx_ppp5; 7389 __be64 rx_ppp6; 7390 __be64 rx_ppp7; 7391 __be64 rx_less_64b; 7392 __be64 rx_bg_drop; 7393 __be64 rx_bg_trunc; 7394 } all; 7395 } u; 7396 }; 7397 7398 #define S_FW_PORT_STATS_CMD_NSTATS 4 7399 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 7400 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 7401 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 7402 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 7403 7404 #define S_FW_PORT_STATS_CMD_BG_BM 0 7405 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 7406 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 7407 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 7408 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 7409 7410 #define S_FW_PORT_STATS_CMD_TX 7 7411 #define M_FW_PORT_STATS_CMD_TX 0x1 7412 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 7413 #define G_FW_PORT_STATS_CMD_TX(x) \ 7414 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 7415 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 7416 7417 #define S_FW_PORT_STATS_CMD_IX 0 7418 #define M_FW_PORT_STATS_CMD_IX 0x3f 7419 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 7420 #define G_FW_PORT_STATS_CMD_IX(x) \ 7421 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 7422 7423 /* port loopback stats */ 7424 #define FW_NUM_LB_STATS 14 7425 enum fw_port_lb_stats_index { 7426 FW_STAT_LB_PORT_BYTES_IX, 7427 FW_STAT_LB_PORT_FRAMES_IX, 7428 FW_STAT_LB_PORT_BCAST_IX, 7429 FW_STAT_LB_PORT_MCAST_IX, 7430 FW_STAT_LB_PORT_UCAST_IX, 7431 FW_STAT_LB_PORT_ERROR_IX, 7432 FW_STAT_LB_PORT_64B_IX, 7433 FW_STAT_LB_PORT_65B_127B_IX, 7434 FW_STAT_LB_PORT_128B_255B_IX, 7435 FW_STAT_LB_PORT_256B_511B_IX, 7436 FW_STAT_LB_PORT_512B_1023B_IX, 7437 FW_STAT_LB_PORT_1024B_1518B_IX, 7438 FW_STAT_LB_PORT_1519B_MAX_IX, 7439 FW_STAT_LB_PORT_DROP_FRAMES_IX 7440 }; 7441 7442 struct fw_port_lb_stats_cmd { 7443 __be32 op_to_lbport; 7444 __be32 retval_len16; 7445 union fw_port_lb_stats { 7446 struct fw_port_lb_stats_ctl { 7447 __u8 nstats_bg_bm; 7448 __u8 ix_pkd; 7449 __be16 r6; 7450 __be32 r7; 7451 __be64 stat0; 7452 __be64 stat1; 7453 __be64 stat2; 7454 __be64 stat3; 7455 __be64 stat4; 7456 __be64 stat5; 7457 } ctl; 7458 struct fw_port_lb_stats_all { 7459 __be64 tx_bytes; 7460 __be64 tx_frames; 7461 __be64 tx_bcast; 7462 __be64 tx_mcast; 7463 __be64 tx_ucast; 7464 __be64 tx_error; 7465 __be64 tx_64b; 7466 __be64 tx_65b_127b; 7467 __be64 tx_128b_255b; 7468 __be64 tx_256b_511b; 7469 __be64 tx_512b_1023b; 7470 __be64 tx_1024b_1518b; 7471 __be64 tx_1519b_max; 7472 __be64 rx_lb_drop; 7473 __be64 rx_lb_trunc; 7474 } all; 7475 } u; 7476 }; 7477 7478 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 7479 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 7480 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7481 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 7482 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 7483 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 7484 7485 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 7486 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 7487 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7488 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 7489 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 7490 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 7491 7492 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 7493 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 7494 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 7495 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 7496 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 7497 7498 #define S_FW_PORT_LB_STATS_CMD_IX 0 7499 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 7500 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 7501 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 7502 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 7503 7504 /* Trace related defines */ 7505 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 7506 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 7507 7508 struct fw_port_trace_cmd { 7509 __be32 op_to_portid; 7510 __be32 retval_len16; 7511 __be16 traceen_to_pciech; 7512 __be16 qnum; 7513 __be32 r5; 7514 }; 7515 7516 #define S_FW_PORT_TRACE_CMD_PORTID 0 7517 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 7518 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 7519 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 7520 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 7521 7522 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 7523 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 7524 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 7525 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 7526 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 7527 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 7528 7529 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 7530 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 7531 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 7532 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 7533 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 7534 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 7535 7536 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 7537 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 7538 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 7539 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 7540 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 7541 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 7542 7543 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 7544 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 7545 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7546 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7547 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 7548 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 7549 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 7550 7551 #define S_FW_PORT_TRACE_CMD_PCIECH 6 7552 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 7553 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 7554 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 7555 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 7556 7557 struct fw_port_trace_mmap_cmd { 7558 __be32 op_to_portid; 7559 __be32 retval_len16; 7560 __be32 fid_to_skipoffset; 7561 __be32 minpktsize_capturemax; 7562 __u8 map[224]; 7563 }; 7564 7565 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 7566 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 7567 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7568 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 7569 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 7570 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 7571 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 7572 7573 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 7574 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 7575 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 7576 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 7577 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 7578 7579 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 7580 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 7581 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7582 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7583 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 7584 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 7585 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 7586 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 7587 7588 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 7589 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 7590 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7591 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7592 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 7593 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 7594 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 7595 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 7596 7597 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 7598 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 7599 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 7600 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 7601 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 7602 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 7603 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 7604 7605 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 7606 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 7607 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 7608 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 7609 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 7610 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 7611 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 7612 7613 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 7614 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 7615 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 7616 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 7617 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 7618 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 7619 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 7620 7621 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 7622 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 7623 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 7624 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 7625 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 7626 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 7627 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 7628 7629 enum fw_ptp_subop { 7630 7631 /* none */ 7632 FW_PTP_SC_INIT_TIMER = 0x00, 7633 FW_PTP_SC_TX_TYPE = 0x01, 7634 7635 /* init */ 7636 FW_PTP_SC_RXTIME_STAMP = 0x08, 7637 FW_PTP_SC_RDRX_TYPE = 0x09, 7638 7639 /* ts */ 7640 FW_PTP_SC_ADJ_FREQ = 0x10, 7641 FW_PTP_SC_ADJ_TIME = 0x11, 7642 FW_PTP_SC_ADJ_FTIME = 0x12, 7643 FW_PTP_SC_WALL_CLOCK = 0x13, 7644 FW_PTP_SC_GET_TIME = 0x14, 7645 FW_PTP_SC_SET_TIME = 0x15, 7646 }; 7647 7648 struct fw_ptp_cmd { 7649 __be32 op_to_portid; 7650 __be32 retval_len16; 7651 union fw_ptp { 7652 struct fw_ptp_sc { 7653 __u8 sc; 7654 __u8 r3[7]; 7655 } scmd; 7656 struct fw_ptp_init { 7657 __u8 sc; 7658 __u8 txchan; 7659 __be16 absid; 7660 __be16 mode; 7661 __be16 r3; 7662 } init; 7663 struct fw_ptp_ts { 7664 __u8 sc; 7665 __u8 sign; 7666 __be16 r3; 7667 __be32 ppb; 7668 __be64 tm; 7669 } ts; 7670 } u; 7671 __be64 r3; 7672 }; 7673 7674 #define S_FW_PTP_CMD_PORTID 0 7675 #define M_FW_PTP_CMD_PORTID 0xf 7676 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 7677 #define G_FW_PTP_CMD_PORTID(x) \ 7678 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 7679 7680 struct fw_rss_ind_tbl_cmd { 7681 __be32 op_to_viid; 7682 __be32 retval_len16; 7683 __be16 niqid; 7684 __be16 startidx; 7685 __be32 r3; 7686 __be32 iq0_to_iq2; 7687 __be32 iq3_to_iq5; 7688 __be32 iq6_to_iq8; 7689 __be32 iq9_to_iq11; 7690 __be32 iq12_to_iq14; 7691 __be32 iq15_to_iq17; 7692 __be32 iq18_to_iq20; 7693 __be32 iq21_to_iq23; 7694 __be32 iq24_to_iq26; 7695 __be32 iq27_to_iq29; 7696 __be32 iq30_iq31; 7697 __be32 r15_lo; 7698 }; 7699 7700 #define S_FW_RSS_IND_TBL_CMD_VIID 0 7701 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 7702 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 7703 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 7704 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 7705 7706 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 7707 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 7708 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 7709 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 7710 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 7711 7712 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 7713 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 7714 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 7715 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 7716 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 7717 7718 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 7719 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 7720 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 7721 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 7722 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 7723 7724 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 7725 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 7726 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 7727 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 7728 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 7729 7730 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 7731 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 7732 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 7733 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 7734 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 7735 7736 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 7737 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 7738 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 7739 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 7740 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 7741 7742 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 7743 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 7744 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 7745 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 7746 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 7747 7748 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 7749 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 7750 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 7751 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 7752 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 7753 7754 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 7755 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 7756 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 7757 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 7758 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 7759 7760 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 7761 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 7762 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 7763 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 7764 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 7765 7766 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 7767 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 7768 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 7769 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 7770 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 7771 7772 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 7773 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 7774 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 7775 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 7776 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 7777 7778 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 7779 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 7780 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 7781 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 7782 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 7783 7784 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 7785 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 7786 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 7787 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 7788 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 7789 7790 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 7791 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 7792 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 7793 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 7794 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 7795 7796 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 7797 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 7798 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 7799 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 7800 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 7801 7802 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 7803 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 7804 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 7805 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 7806 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 7807 7808 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 7809 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 7810 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 7811 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 7812 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 7813 7814 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 7815 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 7816 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 7817 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 7818 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 7819 7820 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 7821 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 7822 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 7823 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 7824 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 7825 7826 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 7827 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 7828 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 7829 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 7830 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 7831 7832 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 7833 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 7834 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 7835 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 7836 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 7837 7838 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 7839 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 7840 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 7841 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 7842 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 7843 7844 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 7845 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 7846 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 7847 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 7848 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 7849 7850 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 7851 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 7852 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 7853 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 7854 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 7855 7856 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 7857 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 7858 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 7859 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 7860 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 7861 7862 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 7863 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 7864 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 7865 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 7866 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 7867 7868 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 7869 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 7870 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 7871 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 7872 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 7873 7874 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 7875 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 7876 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 7877 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 7878 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 7879 7880 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 7881 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 7882 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 7883 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 7884 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 7885 7886 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 7887 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 7888 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 7889 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 7890 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 7891 7892 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 7893 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 7894 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 7895 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 7896 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 7897 7898 struct fw_rss_glb_config_cmd { 7899 __be32 op_to_write; 7900 __be32 retval_len16; 7901 union fw_rss_glb_config { 7902 struct fw_rss_glb_config_manual { 7903 __be32 mode_pkd; 7904 __be32 r3; 7905 __be64 r4; 7906 __be64 r5; 7907 } manual; 7908 struct fw_rss_glb_config_basicvirtual { 7909 __be32 mode_pkd; 7910 __be32 synmapen_to_hashtoeplitz; 7911 __be64 r8; 7912 __be64 r9; 7913 } basicvirtual; 7914 } u; 7915 }; 7916 7917 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 7918 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 7919 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 7920 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 7921 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 7922 7923 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 7924 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 7925 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 7926 7927 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 7928 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 7929 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 7930 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 7931 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 7932 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 7933 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 7934 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 7935 7936 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 7937 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 7938 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 7939 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 7940 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 7941 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 7942 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 7943 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 7944 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 7945 7946 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 7947 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 7948 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 7949 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 7950 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 7951 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 7952 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 7953 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 7954 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 7955 7956 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 7957 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 7958 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 7959 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 7960 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 7961 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 7962 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 7963 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 7964 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 7965 7966 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 7967 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 7968 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 7969 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 7970 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 7971 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 7972 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 7973 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 7974 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 7975 7976 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 7977 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 7978 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 7979 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 7980 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 7981 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 7982 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 7983 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 7984 7985 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 7986 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 7987 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 7988 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 7989 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 7990 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 7991 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 7992 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 7993 7994 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 7995 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 7996 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 7997 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 7998 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 7999 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 8000 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 8001 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 8002 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 8003 8004 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 8005 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 8006 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8007 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8008 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 8009 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 8010 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 8011 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 8012 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 8013 8014 struct fw_rss_vi_config_cmd { 8015 __be32 op_to_viid; 8016 __be32 retval_len16; 8017 union fw_rss_vi_config { 8018 struct fw_rss_vi_config_manual { 8019 __be64 r3; 8020 __be64 r4; 8021 __be64 r5; 8022 } manual; 8023 struct fw_rss_vi_config_basicvirtual { 8024 __be32 r6; 8025 __be32 defaultq_to_udpen; 8026 __be64 r9; 8027 __be64 r10; 8028 } basicvirtual; 8029 } u; 8030 }; 8031 8032 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 8033 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 8034 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 8035 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 8036 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 8037 8038 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 8039 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 8040 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8041 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8042 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 8043 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 8044 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 8045 8046 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 8047 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 8048 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8049 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8050 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 8051 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 8052 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 8053 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 8054 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 8055 8056 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 8057 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 8058 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8059 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8060 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 8061 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 8062 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 8063 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 8064 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 8065 8066 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 8067 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 8068 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8069 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8070 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 8071 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 8072 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 8073 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 8074 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 8075 8076 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 8077 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 8078 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8079 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8080 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 8081 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 8082 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 8083 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 8084 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 8085 8086 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 8087 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 8088 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 8089 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 8090 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 8091 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 8092 8093 enum fw_sched_sc { 8094 FW_SCHED_SC_CONFIG = 0, 8095 FW_SCHED_SC_PARAMS = 1, 8096 }; 8097 8098 enum fw_sched_type { 8099 FW_SCHED_TYPE_PKTSCHED = 0, 8100 FW_SCHED_TYPE_STREAMSCHED = 1, 8101 }; 8102 8103 enum fw_sched_params_level { 8104 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 8105 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 8106 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 8107 }; 8108 8109 enum fw_sched_params_mode { 8110 FW_SCHED_PARAMS_MODE_CLASS = 0, 8111 FW_SCHED_PARAMS_MODE_FLOW = 1, 8112 }; 8113 8114 enum fw_sched_params_unit { 8115 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 8116 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 8117 }; 8118 8119 enum fw_sched_params_rate { 8120 FW_SCHED_PARAMS_RATE_REL = 0, 8121 FW_SCHED_PARAMS_RATE_ABS = 1, 8122 }; 8123 8124 struct fw_sched_cmd { 8125 __be32 op_to_write; 8126 __be32 retval_len16; 8127 union fw_sched { 8128 struct fw_sched_config { 8129 __u8 sc; 8130 __u8 type; 8131 __u8 minmaxen; 8132 __u8 r3[5]; 8133 __u8 nclasses[4]; 8134 __be32 r4; 8135 } config; 8136 struct fw_sched_params { 8137 __u8 sc; 8138 __u8 type; 8139 __u8 level; 8140 __u8 mode; 8141 __u8 unit; 8142 __u8 rate; 8143 __u8 ch; 8144 __u8 cl; 8145 __be32 min; 8146 __be32 max; 8147 __be16 weight; 8148 __be16 pktsize; 8149 __be16 burstsize; 8150 __be16 r4; 8151 } params; 8152 } u; 8153 }; 8154 8155 /* 8156 * length of the formatting string 8157 */ 8158 #define FW_DEVLOG_FMT_LEN 192 8159 8160 /* 8161 * maximum number of the formatting string parameters 8162 */ 8163 #define FW_DEVLOG_FMT_PARAMS_NUM 8 8164 8165 /* 8166 * priority levels 8167 */ 8168 enum fw_devlog_level { 8169 FW_DEVLOG_LEVEL_EMERG = 0x0, 8170 FW_DEVLOG_LEVEL_CRIT = 0x1, 8171 FW_DEVLOG_LEVEL_ERR = 0x2, 8172 FW_DEVLOG_LEVEL_NOTICE = 0x3, 8173 FW_DEVLOG_LEVEL_INFO = 0x4, 8174 FW_DEVLOG_LEVEL_DEBUG = 0x5, 8175 FW_DEVLOG_LEVEL_MAX = 0x5, 8176 }; 8177 8178 /* 8179 * facilities that may send a log message 8180 */ 8181 enum fw_devlog_facility { 8182 FW_DEVLOG_FACILITY_CORE = 0x00, 8183 FW_DEVLOG_FACILITY_CF = 0x01, 8184 FW_DEVLOG_FACILITY_SCHED = 0x02, 8185 FW_DEVLOG_FACILITY_TIMER = 0x04, 8186 FW_DEVLOG_FACILITY_RES = 0x06, 8187 FW_DEVLOG_FACILITY_HW = 0x08, 8188 FW_DEVLOG_FACILITY_FLR = 0x10, 8189 FW_DEVLOG_FACILITY_DMAQ = 0x12, 8190 FW_DEVLOG_FACILITY_PHY = 0x14, 8191 FW_DEVLOG_FACILITY_MAC = 0x16, 8192 FW_DEVLOG_FACILITY_PORT = 0x18, 8193 FW_DEVLOG_FACILITY_VI = 0x1A, 8194 FW_DEVLOG_FACILITY_FILTER = 0x1C, 8195 FW_DEVLOG_FACILITY_ACL = 0x1E, 8196 FW_DEVLOG_FACILITY_TM = 0x20, 8197 FW_DEVLOG_FACILITY_QFC = 0x22, 8198 FW_DEVLOG_FACILITY_DCB = 0x24, 8199 FW_DEVLOG_FACILITY_ETH = 0x26, 8200 FW_DEVLOG_FACILITY_OFLD = 0x28, 8201 FW_DEVLOG_FACILITY_RI = 0x2A, 8202 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 8203 FW_DEVLOG_FACILITY_FCOE = 0x2E, 8204 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 8205 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 8206 FW_DEVLOG_FACILITY_CHNET = 0x34, 8207 FW_DEVLOG_FACILITY_COiSCSI = 0x36, 8208 FW_DEVLOG_FACILITY_MAX = 0x38, 8209 }; 8210 8211 /* 8212 * log message format 8213 */ 8214 struct fw_devlog_e { 8215 __be64 timestamp; 8216 __be32 seqno; 8217 __be16 reserved1; 8218 __u8 level; 8219 __u8 facility; 8220 __u8 fmt[FW_DEVLOG_FMT_LEN]; 8221 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 8222 __be32 reserved3[4]; 8223 }; 8224 8225 struct fw_devlog_cmd { 8226 __be32 op_to_write; 8227 __be32 retval_len16; 8228 __u8 level; 8229 __u8 r2[7]; 8230 __be32 memtype_devlog_memaddr16_devlog; 8231 __be32 memsize_devlog; 8232 __be32 r3[2]; 8233 }; 8234 8235 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 8236 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 8237 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8238 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8239 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 8240 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 8241 8242 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 8243 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 8244 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8245 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8246 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 8247 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 8248 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 8249 8250 enum fw_watchdog_actions { 8251 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 8252 FW_WATCHDOG_ACTION_FLR = 1, 8253 FW_WATCHDOG_ACTION_BYPASS = 2, 8254 FW_WATCHDOG_ACTION_TMPCHK = 3, 8255 FW_WATCHDOG_ACTION_PAUSEOFF = 4, 8256 8257 FW_WATCHDOG_ACTION_MAX = 5, 8258 }; 8259 8260 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 8261 8262 struct fw_watchdog_cmd { 8263 __be32 op_to_vfn; 8264 __be32 retval_len16; 8265 __be32 timeout; 8266 __be32 action; 8267 }; 8268 8269 #define S_FW_WATCHDOG_CMD_PFN 8 8270 #define M_FW_WATCHDOG_CMD_PFN 0x7 8271 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 8272 #define G_FW_WATCHDOG_CMD_PFN(x) \ 8273 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 8274 8275 #define S_FW_WATCHDOG_CMD_VFN 0 8276 #define M_FW_WATCHDOG_CMD_VFN 0xff 8277 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 8278 #define G_FW_WATCHDOG_CMD_VFN(x) \ 8279 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 8280 8281 struct fw_clip_cmd { 8282 __be32 op_to_write; 8283 __be32 alloc_to_len16; 8284 __be64 ip_hi; 8285 __be64 ip_lo; 8286 __be32 r4[2]; 8287 }; 8288 8289 #define S_FW_CLIP_CMD_ALLOC 31 8290 #define M_FW_CLIP_CMD_ALLOC 0x1 8291 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 8292 #define G_FW_CLIP_CMD_ALLOC(x) \ 8293 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 8294 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 8295 8296 #define S_FW_CLIP_CMD_FREE 30 8297 #define M_FW_CLIP_CMD_FREE 0x1 8298 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 8299 #define G_FW_CLIP_CMD_FREE(x) \ 8300 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 8301 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 8302 8303 /****************************************************************************** 8304 * F O i S C S I C O M M A N D s 8305 **************************************/ 8306 8307 #define FW_CHNET_IFACE_ADDR_MAX 3 8308 8309 enum fw_chnet_iface_cmd_subop { 8310 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 8311 8312 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 8313 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 8314 8315 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 8316 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 8317 8318 FW_CHNET_IFACE_CMD_SUBOP_MAX, 8319 }; 8320 8321 struct fw_chnet_iface_cmd { 8322 __be32 op_to_portid; 8323 __be32 retval_len16; 8324 __u8 subop; 8325 __u8 r2[3]; 8326 __be32 ifid_ifstate; 8327 __be16 mtu; 8328 __be16 vlanid; 8329 __be32 r3; 8330 __be16 r4; 8331 __u8 mac[6]; 8332 }; 8333 8334 #define S_FW_CHNET_IFACE_CMD_PORTID 0 8335 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 8336 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 8337 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 8338 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 8339 8340 #define S_FW_CHNET_IFACE_CMD_IFID 8 8341 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 8342 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 8343 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 8344 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 8345 8346 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 8347 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 8348 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 8349 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 8350 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 8351 8352 struct fw_fcoe_res_info_cmd { 8353 __be32 op_to_read; 8354 __be32 retval_len16; 8355 __be16 e_d_tov; 8356 __be16 r_a_tov_seq; 8357 __be16 r_a_tov_els; 8358 __be16 r_r_tov; 8359 __be32 max_xchgs; 8360 __be32 max_ssns; 8361 __be32 used_xchgs; 8362 __be32 used_ssns; 8363 __be32 max_fcfs; 8364 __be32 max_vnps; 8365 __be32 used_fcfs; 8366 __be32 used_vnps; 8367 }; 8368 8369 struct fw_fcoe_link_cmd { 8370 __be32 op_to_portid; 8371 __be32 retval_len16; 8372 __be32 sub_opcode_fcfi; 8373 __u8 r3; 8374 __u8 lstatus; 8375 __be16 flags; 8376 __u8 r4; 8377 __u8 set_vlan; 8378 __be16 vlan_id; 8379 __be32 vnpi_pkd; 8380 __be16 r6; 8381 __u8 phy_mac[6]; 8382 __u8 vnport_wwnn[8]; 8383 __u8 vnport_wwpn[8]; 8384 }; 8385 8386 #define S_FW_FCOE_LINK_CMD_PORTID 0 8387 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 8388 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 8389 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 8390 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 8391 8392 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 8393 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 8394 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8395 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 8396 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 8397 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 8398 8399 #define S_FW_FCOE_LINK_CMD_FCFI 0 8400 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 8401 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 8402 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 8403 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 8404 8405 #define S_FW_FCOE_LINK_CMD_VNPI 0 8406 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 8407 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 8408 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 8409 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 8410 8411 struct fw_fcoe_vnp_cmd { 8412 __be32 op_to_fcfi; 8413 __be32 alloc_to_len16; 8414 __be32 gen_wwn_to_vnpi; 8415 __be32 vf_id; 8416 __be16 iqid; 8417 __u8 vnport_mac[6]; 8418 __u8 vnport_wwnn[8]; 8419 __u8 vnport_wwpn[8]; 8420 __u8 cmn_srv_parms[16]; 8421 __u8 clsp_word_0_1[8]; 8422 }; 8423 8424 #define S_FW_FCOE_VNP_CMD_FCFI 0 8425 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 8426 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 8427 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 8428 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 8429 8430 #define S_FW_FCOE_VNP_CMD_ALLOC 31 8431 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 8432 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 8433 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 8434 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 8435 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 8436 8437 #define S_FW_FCOE_VNP_CMD_FREE 30 8438 #define M_FW_FCOE_VNP_CMD_FREE 0x1 8439 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 8440 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 8441 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 8442 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 8443 8444 #define S_FW_FCOE_VNP_CMD_MODIFY 29 8445 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 8446 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 8447 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 8448 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 8449 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 8450 8451 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 8452 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 8453 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 8454 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 8455 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 8456 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 8457 8458 #define S_FW_FCOE_VNP_CMD_PERSIST 21 8459 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 8460 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 8461 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 8462 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 8463 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 8464 8465 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 8466 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 8467 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 8468 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 8469 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 8470 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 8471 8472 #define S_FW_FCOE_VNP_CMD_VNPI 0 8473 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 8474 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 8475 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 8476 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 8477 8478 struct fw_fcoe_sparams_cmd { 8479 __be32 op_to_portid; 8480 __be32 retval_len16; 8481 __u8 r3[7]; 8482 __u8 cos; 8483 __u8 lport_wwnn[8]; 8484 __u8 lport_wwpn[8]; 8485 __u8 cmn_srv_parms[16]; 8486 __u8 cls_srv_parms[16]; 8487 }; 8488 8489 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 8490 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 8491 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 8492 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 8493 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 8494 8495 struct fw_fcoe_stats_cmd { 8496 __be32 op_to_flowid; 8497 __be32 free_to_len16; 8498 union fw_fcoe_stats { 8499 struct fw_fcoe_stats_ctl { 8500 __u8 nstats_port; 8501 __u8 port_valid_ix; 8502 __be16 r6; 8503 __be32 r7; 8504 __be64 stat0; 8505 __be64 stat1; 8506 __be64 stat2; 8507 __be64 stat3; 8508 __be64 stat4; 8509 __be64 stat5; 8510 } ctl; 8511 struct fw_fcoe_port_stats { 8512 __be64 tx_bcast_bytes; 8513 __be64 tx_bcast_frames; 8514 __be64 tx_mcast_bytes; 8515 __be64 tx_mcast_frames; 8516 __be64 tx_ucast_bytes; 8517 __be64 tx_ucast_frames; 8518 __be64 tx_drop_frames; 8519 __be64 tx_offload_bytes; 8520 __be64 tx_offload_frames; 8521 __be64 rx_bcast_bytes; 8522 __be64 rx_bcast_frames; 8523 __be64 rx_mcast_bytes; 8524 __be64 rx_mcast_frames; 8525 __be64 rx_ucast_bytes; 8526 __be64 rx_ucast_frames; 8527 __be64 rx_err_frames; 8528 } port_stats; 8529 struct fw_fcoe_fcf_stats { 8530 __be32 fip_tx_bytes; 8531 __be32 fip_tx_fr; 8532 __be64 fcf_ka; 8533 __be64 mcast_adv_rcvd; 8534 __be16 ucast_adv_rcvd; 8535 __be16 sol_sent; 8536 __be16 vlan_req; 8537 __be16 vlan_rpl; 8538 __be16 clr_vlink; 8539 __be16 link_down; 8540 __be16 link_up; 8541 __be16 logo; 8542 __be16 flogi_req; 8543 __be16 flogi_rpl; 8544 __be16 fdisc_req; 8545 __be16 fdisc_rpl; 8546 __be16 fka_prd_chg; 8547 __be16 fc_map_chg; 8548 __be16 vfid_chg; 8549 __u8 no_fka_req; 8550 __u8 no_vnp; 8551 } fcf_stats; 8552 struct fw_fcoe_pcb_stats { 8553 __be64 tx_bytes; 8554 __be64 tx_frames; 8555 __be64 rx_bytes; 8556 __be64 rx_frames; 8557 __be32 vnp_ka; 8558 __be32 unsol_els_rcvd; 8559 __be64 unsol_cmd_rcvd; 8560 __be16 implicit_logo; 8561 __be16 flogi_inv_sparm; 8562 __be16 fdisc_inv_sparm; 8563 __be16 flogi_rjt; 8564 __be16 fdisc_rjt; 8565 __be16 no_ssn; 8566 __be16 mac_flt_fail; 8567 __be16 inv_fr_rcvd; 8568 } pcb_stats; 8569 struct fw_fcoe_scb_stats { 8570 __be64 tx_bytes; 8571 __be64 tx_frames; 8572 __be64 rx_bytes; 8573 __be64 rx_frames; 8574 __be32 host_abrt_req; 8575 __be32 adap_auto_abrt; 8576 __be32 adap_abrt_rsp; 8577 __be32 host_ios_req; 8578 __be16 ssn_offl_ios; 8579 __be16 ssn_not_rdy_ios; 8580 __u8 rx_data_ddp_err; 8581 __u8 ddp_flt_set_err; 8582 __be16 rx_data_fr_err; 8583 __u8 bad_st_abrt_req; 8584 __u8 no_io_abrt_req; 8585 __u8 abort_tmo; 8586 __u8 abort_tmo_2; 8587 __be32 abort_req; 8588 __u8 no_ppod_res_tmo; 8589 __u8 bp_tmo; 8590 __u8 adap_auto_cls; 8591 __u8 no_io_cls_req; 8592 __be32 host_cls_req; 8593 __be64 unsol_cmd_rcvd; 8594 __be32 plogi_req_rcvd; 8595 __be32 prli_req_rcvd; 8596 __be16 logo_req_rcvd; 8597 __be16 prlo_req_rcvd; 8598 __be16 plogi_rjt_rcvd; 8599 __be16 prli_rjt_rcvd; 8600 __be32 adisc_req_rcvd; 8601 __be32 rscn_rcvd; 8602 __be32 rrq_req_rcvd; 8603 __be32 unsol_els_rcvd; 8604 __u8 adisc_rjt_rcvd; 8605 __u8 scr_rjt; 8606 __u8 ct_rjt; 8607 __u8 inval_bls_rcvd; 8608 __be32 ba_rjt_rcvd; 8609 } scb_stats; 8610 } u; 8611 }; 8612 8613 #define S_FW_FCOE_STATS_CMD_FLOWID 0 8614 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 8615 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 8616 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 8617 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 8618 8619 #define S_FW_FCOE_STATS_CMD_FREE 30 8620 #define M_FW_FCOE_STATS_CMD_FREE 0x1 8621 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 8622 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 8623 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 8624 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 8625 8626 #define S_FW_FCOE_STATS_CMD_NSTATS 4 8627 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 8628 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 8629 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 8630 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 8631 8632 #define S_FW_FCOE_STATS_CMD_PORT 0 8633 #define M_FW_FCOE_STATS_CMD_PORT 0x3 8634 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 8635 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 8636 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 8637 8638 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 8639 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 8640 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 8641 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 8642 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 8643 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 8644 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 8645 8646 #define S_FW_FCOE_STATS_CMD_IX 0 8647 #define M_FW_FCOE_STATS_CMD_IX 0x3f 8648 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 8649 #define G_FW_FCOE_STATS_CMD_IX(x) \ 8650 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 8651 8652 struct fw_fcoe_fcf_cmd { 8653 __be32 op_to_fcfi; 8654 __be32 retval_len16; 8655 __be16 priority_pkd; 8656 __u8 mac[6]; 8657 __u8 name_id[8]; 8658 __u8 fabric[8]; 8659 __be16 vf_id; 8660 __be16 max_fcoe_size; 8661 __u8 vlan_id; 8662 __u8 fc_map[3]; 8663 __be32 fka_adv; 8664 __be32 r6; 8665 __u8 r7_hi; 8666 __u8 fpma_to_portid; 8667 __u8 spma_mac[6]; 8668 __be64 r8; 8669 }; 8670 8671 #define S_FW_FCOE_FCF_CMD_FCFI 0 8672 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 8673 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 8674 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 8675 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 8676 8677 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 8678 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 8679 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 8680 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 8681 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 8682 8683 #define S_FW_FCOE_FCF_CMD_FPMA 6 8684 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 8685 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 8686 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 8687 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 8688 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 8689 8690 #define S_FW_FCOE_FCF_CMD_SPMA 5 8691 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 8692 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 8693 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 8694 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 8695 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 8696 8697 #define S_FW_FCOE_FCF_CMD_LOGIN 4 8698 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 8699 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 8700 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 8701 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 8702 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 8703 8704 #define S_FW_FCOE_FCF_CMD_PORTID 0 8705 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 8706 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 8707 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 8708 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 8709 8710 /****************************************************************************** 8711 * E R R O R a n d D E B U G C O M M A N D s 8712 ******************************************************/ 8713 8714 enum fw_error_type { 8715 FW_ERROR_TYPE_EXCEPTION = 0x0, 8716 FW_ERROR_TYPE_HWMODULE = 0x1, 8717 FW_ERROR_TYPE_WR = 0x2, 8718 FW_ERROR_TYPE_ACL = 0x3, 8719 }; 8720 8721 enum fw_dcb_ieee_locations { 8722 FW_IEEE_LOC_LOCAL, 8723 FW_IEEE_LOC_PEER, 8724 FW_IEEE_LOC_OPERATIONAL, 8725 }; 8726 8727 struct fw_dcb_ieee_cmd { 8728 __be32 op_to_location; 8729 __be32 changed_to_len16; 8730 union fw_dcbx_stats { 8731 struct fw_dcbx_pfc_stats_ieee { 8732 __be32 pfc_mbc_pkd; 8733 __be32 pfc_willing_to_pfc_en; 8734 } dcbx_pfc_stats; 8735 struct fw_dcbx_ets_stats_ieee { 8736 __be32 cbs_to_ets_max_tc; 8737 __be32 pg_table; 8738 __u8 pg_percent[8]; 8739 __u8 tsa[8]; 8740 } dcbx_ets_stats; 8741 struct fw_dcbx_app_stats_ieee { 8742 __be32 num_apps_pkd; 8743 __be32 r6; 8744 __be32 app[4]; 8745 } dcbx_app_stats; 8746 struct fw_dcbx_control { 8747 __be32 multi_peer_invalidated; 8748 __be32 r5_lo; 8749 } dcbx_control; 8750 } u; 8751 }; 8752 8753 #define S_FW_DCB_IEEE_CMD_PORT 8 8754 #define M_FW_DCB_IEEE_CMD_PORT 0x7 8755 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 8756 #define G_FW_DCB_IEEE_CMD_PORT(x) \ 8757 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 8758 8759 #define S_FW_DCB_IEEE_CMD_FEATURE 2 8760 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7 8761 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 8762 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 8763 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 8764 8765 #define S_FW_DCB_IEEE_CMD_LOCATION 0 8766 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3 8767 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 8768 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 8769 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 8770 8771 #define S_FW_DCB_IEEE_CMD_CHANGED 20 8772 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1 8773 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 8774 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 8775 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 8776 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 8777 8778 #define S_FW_DCB_IEEE_CMD_RECEIVED 19 8779 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 8780 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 8781 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 8782 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 8783 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 8784 8785 #define S_FW_DCB_IEEE_CMD_APPLY 18 8786 #define M_FW_DCB_IEEE_CMD_APPLY 0x1 8787 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 8788 #define G_FW_DCB_IEEE_CMD_APPLY(x) \ 8789 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 8790 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 8791 8792 #define S_FW_DCB_IEEE_CMD_DISABLED 17 8793 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1 8794 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 8795 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 8796 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 8797 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 8798 8799 #define S_FW_DCB_IEEE_CMD_MORE 16 8800 #define M_FW_DCB_IEEE_CMD_MORE 0x1 8801 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 8802 #define G_FW_DCB_IEEE_CMD_MORE(x) \ 8803 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 8804 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 8805 8806 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0 8807 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 8808 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 8809 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 8810 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 8811 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 8812 8813 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 8814 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 8815 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 8816 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 8817 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 8818 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 8819 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 8820 8821 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 8822 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 8823 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 8824 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 8825 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 8826 8827 #define S_FW_DCB_IEEE_CMD_PFC_EN 0 8828 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 8829 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 8830 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 8831 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 8832 8833 #define S_FW_DCB_IEEE_CMD_CBS 16 8834 #define M_FW_DCB_IEEE_CMD_CBS 0x1 8835 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 8836 #define G_FW_DCB_IEEE_CMD_CBS(x) \ 8837 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 8838 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 8839 8840 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 8841 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 8842 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 8843 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 8844 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 8845 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 8846 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 8847 8848 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 8849 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 8850 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 8851 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 8852 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 8853 8854 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0 8855 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 8856 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 8857 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 8858 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 8859 8860 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 8861 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 8862 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 8863 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 8864 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 8865 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 8866 8867 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30 8868 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 8869 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 8870 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 8871 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 8872 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 8873 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 8874 8875 /* Hand-written */ 8876 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 8877 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 8878 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 8879 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 8880 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 8881 8882 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3 8883 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 8884 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 8885 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 8886 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 8887 8888 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 8889 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 8890 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 8891 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 8892 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 8893 8894 8895 struct fw_error_cmd { 8896 __be32 op_to_type; 8897 __be32 len16_pkd; 8898 union fw_error { 8899 struct fw_error_exception { 8900 __be32 info[6]; 8901 } exception; 8902 struct fw_error_hwmodule { 8903 __be32 regaddr; 8904 __be32 regval; 8905 } hwmodule; 8906 struct fw_error_wr { 8907 __be16 cidx; 8908 __be16 pfn_vfn; 8909 __be32 eqid; 8910 __u8 wrhdr[16]; 8911 } wr; 8912 struct fw_error_acl { 8913 __be16 cidx; 8914 __be16 pfn_vfn; 8915 __be32 eqid; 8916 __be16 mv_pkd; 8917 __u8 val[6]; 8918 __be64 r4; 8919 } acl; 8920 } u; 8921 }; 8922 8923 #define S_FW_ERROR_CMD_FATAL 4 8924 #define M_FW_ERROR_CMD_FATAL 0x1 8925 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 8926 #define G_FW_ERROR_CMD_FATAL(x) \ 8927 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 8928 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 8929 8930 #define S_FW_ERROR_CMD_TYPE 0 8931 #define M_FW_ERROR_CMD_TYPE 0xf 8932 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 8933 #define G_FW_ERROR_CMD_TYPE(x) \ 8934 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 8935 8936 #define S_FW_ERROR_CMD_PFN 8 8937 #define M_FW_ERROR_CMD_PFN 0x7 8938 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 8939 #define G_FW_ERROR_CMD_PFN(x) \ 8940 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 8941 8942 #define S_FW_ERROR_CMD_VFN 0 8943 #define M_FW_ERROR_CMD_VFN 0xff 8944 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 8945 #define G_FW_ERROR_CMD_VFN(x) \ 8946 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 8947 8948 #define S_FW_ERROR_CMD_PFN 8 8949 #define M_FW_ERROR_CMD_PFN 0x7 8950 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 8951 #define G_FW_ERROR_CMD_PFN(x) \ 8952 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 8953 8954 #define S_FW_ERROR_CMD_VFN 0 8955 #define M_FW_ERROR_CMD_VFN 0xff 8956 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 8957 #define G_FW_ERROR_CMD_VFN(x) \ 8958 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 8959 8960 #define S_FW_ERROR_CMD_MV 15 8961 #define M_FW_ERROR_CMD_MV 0x1 8962 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 8963 #define G_FW_ERROR_CMD_MV(x) \ 8964 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 8965 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 8966 8967 struct fw_debug_cmd { 8968 __be32 op_type; 8969 __be32 len16_pkd; 8970 union fw_debug { 8971 struct fw_debug_assert { 8972 __be32 fcid; 8973 __be32 line; 8974 __be32 x; 8975 __be32 y; 8976 __u8 filename_0_7[8]; 8977 __u8 filename_8_15[8]; 8978 __be64 r3; 8979 } assert; 8980 struct fw_debug_prt { 8981 __be16 dprtstridx; 8982 __be16 r3[3]; 8983 __be32 dprtstrparam0; 8984 __be32 dprtstrparam1; 8985 __be32 dprtstrparam2; 8986 __be32 dprtstrparam3; 8987 } prt; 8988 } u; 8989 }; 8990 8991 #define S_FW_DEBUG_CMD_TYPE 0 8992 #define M_FW_DEBUG_CMD_TYPE 0xff 8993 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 8994 #define G_FW_DEBUG_CMD_TYPE(x) \ 8995 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 8996 8997 /****************************************************************************** 8998 * P C I E F W R E G I S T E R 8999 **************************************/ 9000 9001 enum pcie_fw_eval { 9002 PCIE_FW_EVAL_CRASH = 0, 9003 PCIE_FW_EVAL_PREP = 1, 9004 PCIE_FW_EVAL_CONF = 2, 9005 PCIE_FW_EVAL_INIT = 3, 9006 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 9007 PCIE_FW_EVAL_OVERHEAT = 5, 9008 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 9009 }; 9010 9011 /** 9012 * Register definitions for the PCIE_FW register which the firmware uses 9013 * to retain status across RESETs. This register should be considered 9014 * as a READ-ONLY register for Host Software and only to be used to 9015 * track firmware initialization/error state, etc. 9016 */ 9017 #define S_PCIE_FW_ERR 31 9018 #define M_PCIE_FW_ERR 0x1 9019 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 9020 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 9021 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 9022 9023 #define S_PCIE_FW_INIT 30 9024 #define M_PCIE_FW_INIT 0x1 9025 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 9026 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 9027 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 9028 9029 #define S_PCIE_FW_HALT 29 9030 #define M_PCIE_FW_HALT 0x1 9031 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 9032 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 9033 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 9034 9035 #define S_PCIE_FW_EVAL 24 9036 #define M_PCIE_FW_EVAL 0x7 9037 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 9038 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 9039 9040 #define S_PCIE_FW_STAGE 21 9041 #define M_PCIE_FW_STAGE 0x7 9042 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 9043 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 9044 9045 #define S_PCIE_FW_ASYNCNOT_VLD 20 9046 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 9047 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 9048 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 9049 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 9050 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 9051 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 9052 9053 #define S_PCIE_FW_ASYNCNOTINT 19 9054 #define M_PCIE_FW_ASYNCNOTINT 0x1 9055 #define V_PCIE_FW_ASYNCNOTINT(x) \ 9056 ((x) << S_PCIE_FW_ASYNCNOTINT) 9057 #define G_PCIE_FW_ASYNCNOTINT(x) \ 9058 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 9059 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 9060 9061 #define S_PCIE_FW_ASYNCNOT 16 9062 #define M_PCIE_FW_ASYNCNOT 0x7 9063 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 9064 #define G_PCIE_FW_ASYNCNOT(x) \ 9065 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 9066 9067 #define S_PCIE_FW_MASTER_VLD 15 9068 #define M_PCIE_FW_MASTER_VLD 0x1 9069 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 9070 #define G_PCIE_FW_MASTER_VLD(x) \ 9071 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 9072 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 9073 9074 #define S_PCIE_FW_MASTER 12 9075 #define M_PCIE_FW_MASTER 0x7 9076 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 9077 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 9078 9079 #define S_PCIE_FW_RESET_VLD 11 9080 #define M_PCIE_FW_RESET_VLD 0x1 9081 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 9082 #define G_PCIE_FW_RESET_VLD(x) \ 9083 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 9084 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 9085 9086 #define S_PCIE_FW_RESET 8 9087 #define M_PCIE_FW_RESET 0x7 9088 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 9089 #define G_PCIE_FW_RESET(x) \ 9090 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 9091 9092 #define S_PCIE_FW_REGISTERED 0 9093 #define M_PCIE_FW_REGISTERED 0xff 9094 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 9095 #define G_PCIE_FW_REGISTERED(x) \ 9096 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 9097 9098 9099 /****************************************************************************** 9100 * P C I E F W P F 0 R E G I S T E R 9101 **********************************************/ 9102 9103 /* 9104 * this register is available as 32-bit of persistent storage (across 9105 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 9106 * will not write it) 9107 */ 9108 9109 9110 /****************************************************************************** 9111 * P C I E F W P F 7 R E G I S T E R 9112 **********************************************/ 9113 9114 /* 9115 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 9116 * access the "devlog" which needing to contact firmware. The encoding is 9117 * mostly the same as that returned by the DEVLOG command except for the size 9118 * which is encoded as the number of entries in multiples-1 of 128 here rather 9119 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 9120 * and 15 means 2048. This of course in turn constrains the allowed values 9121 * for the devlog size ... 9122 */ 9123 #define PCIE_FW_PF_DEVLOG 7 9124 9125 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 9126 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0xf 9127 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9128 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 9129 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 9130 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 9131 M_PCIE_FW_PF_DEVLOG_NENTRIES128) 9132 9133 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4 9134 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 9135 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 9136 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 9137 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 9138 9139 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 9140 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0xf 9141 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 9142 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 9143 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 9144 9145 9146 /****************************************************************************** 9147 * B I N A R Y H E A D E R F O R M A T 9148 **********************************************/ 9149 9150 /* 9151 * firmware binary header format 9152 */ 9153 struct fw_hdr { 9154 __u8 ver; 9155 __u8 chip; /* terminator chip family */ 9156 __be16 len512; /* bin length in units of 512-bytes */ 9157 __be32 fw_ver; /* firmware version */ 9158 __be32 tp_microcode_ver; /* tcp processor microcode version */ 9159 __u8 intfver_nic; 9160 __u8 intfver_vnic; 9161 __u8 intfver_ofld; 9162 __u8 intfver_ri; 9163 __u8 intfver_iscsipdu; 9164 __u8 intfver_iscsi; 9165 __u8 intfver_fcoepdu; 9166 __u8 intfver_fcoe; 9167 __u32 reserved2; 9168 __u32 reserved3; 9169 __be32 magic; /* runtime or bootstrap fw */ 9170 __be32 flags; 9171 __be32 reserved6[23]; 9172 }; 9173 9174 enum fw_hdr_chip { 9175 FW_HDR_CHIP_T4, 9176 FW_HDR_CHIP_T5, 9177 FW_HDR_CHIP_T6 9178 }; 9179 9180 #define S_FW_HDR_FW_VER_MAJOR 24 9181 #define M_FW_HDR_FW_VER_MAJOR 0xff 9182 #define V_FW_HDR_FW_VER_MAJOR(x) \ 9183 ((x) << S_FW_HDR_FW_VER_MAJOR) 9184 #define G_FW_HDR_FW_VER_MAJOR(x) \ 9185 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 9186 9187 #define S_FW_HDR_FW_VER_MINOR 16 9188 #define M_FW_HDR_FW_VER_MINOR 0xff 9189 #define V_FW_HDR_FW_VER_MINOR(x) \ 9190 ((x) << S_FW_HDR_FW_VER_MINOR) 9191 #define G_FW_HDR_FW_VER_MINOR(x) \ 9192 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 9193 9194 #define S_FW_HDR_FW_VER_MICRO 8 9195 #define M_FW_HDR_FW_VER_MICRO 0xff 9196 #define V_FW_HDR_FW_VER_MICRO(x) \ 9197 ((x) << S_FW_HDR_FW_VER_MICRO) 9198 #define G_FW_HDR_FW_VER_MICRO(x) \ 9199 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 9200 9201 #define S_FW_HDR_FW_VER_BUILD 0 9202 #define M_FW_HDR_FW_VER_BUILD 0xff 9203 #define V_FW_HDR_FW_VER_BUILD(x) \ 9204 ((x) << S_FW_HDR_FW_VER_BUILD) 9205 #define G_FW_HDR_FW_VER_BUILD(x) \ 9206 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 9207 9208 enum { 9209 T4FW_VERSION_MAJOR = 0x01, 9210 T4FW_VERSION_MINOR = 0x05, 9211 T4FW_VERSION_MICRO = 0x25, 9212 T4FW_VERSION_BUILD = 0x00, 9213 9214 T5FW_VERSION_MAJOR = 0x01, 9215 T5FW_VERSION_MINOR = 0x05, 9216 T5FW_VERSION_MICRO = 0x25, 9217 T5FW_VERSION_BUILD = 0x00, 9218 9219 T6FW_VERSION_MAJOR = 0x00, 9220 T6FW_VERSION_MINOR = 0x00, 9221 T6FW_VERSION_MICRO = 0x00, 9222 T6FW_VERSION_BUILD = 0x00, 9223 }; 9224 9225 enum { 9226 /* T4 9227 */ 9228 T4FW_HDR_INTFVER_NIC = 0x00, 9229 T4FW_HDR_INTFVER_VNIC = 0x00, 9230 T4FW_HDR_INTFVER_OFLD = 0x00, 9231 T4FW_HDR_INTFVER_RI = 0x00, 9232 T4FW_HDR_INTFVER_ISCSIPDU= 0x00, 9233 T4FW_HDR_INTFVER_ISCSI = 0x00, 9234 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 9235 T4FW_HDR_INTFVER_FCOE = 0x00, 9236 9237 /* T5 9238 */ 9239 T5FW_HDR_INTFVER_NIC = 0x00, 9240 T5FW_HDR_INTFVER_VNIC = 0x00, 9241 T5FW_HDR_INTFVER_OFLD = 0x00, 9242 T5FW_HDR_INTFVER_RI = 0x00, 9243 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 9244 T5FW_HDR_INTFVER_ISCSI = 0x00, 9245 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 9246 T5FW_HDR_INTFVER_FCOE = 0x00, 9247 9248 /* T6 9249 */ 9250 T6FW_HDR_INTFVER_NIC = 0x00, 9251 T6FW_HDR_INTFVER_VNIC = 0x00, 9252 T6FW_HDR_INTFVER_OFLD = 0x00, 9253 T6FW_HDR_INTFVER_RI = 0x00, 9254 T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 9255 T6FW_HDR_INTFVER_ISCSI = 0x00, 9256 T6FW_HDR_INTFVER_FCOEPDU= 0x00, 9257 T6FW_HDR_INTFVER_FCOE = 0x00, 9258 }; 9259 9260 enum { 9261 FW_HDR_MAGIC_RUNTIME = 0x00000000, 9262 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 9263 }; 9264 9265 enum fw_hdr_flags { 9266 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 9267 }; 9268 9269 /* 9270 * External PHY firmware binary header format 9271 */ 9272 struct fw_ephy_hdr { 9273 __u8 ver; 9274 __u8 reserved; 9275 __be16 len512; /* bin length in units of 512-bytes */ 9276 __be32 magic; 9277 9278 __be16 vendor_id; 9279 __be16 device_id; 9280 __be32 version; 9281 9282 __be32 reserved1[4]; 9283 }; 9284 9285 enum { 9286 FW_EPHY_HDR_MAGIC = 0x65706879, 9287 }; 9288 9289 #endif /* _T4FW_INTERFACE_H_ */ 9290