1 /*- 2 * Copyright (c) 2012 Chelsio Communications, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 * 28 */ 29 30 #ifndef _T4FW_INTERFACE_H_ 31 #define _T4FW_INTERFACE_H_ 32 33 /****************************************************************************** 34 * R E T U R N V A L U E S 35 ********************************/ 36 37 enum fw_retval { 38 FW_SUCCESS = 0, /* completed sucessfully */ 39 FW_EPERM = 1, /* operation not permitted */ 40 FW_ENOENT = 2, /* no such file or directory */ 41 FW_EIO = 5, /* input/output error; hw bad */ 42 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 43 FW_EAGAIN = 11, /* try again */ 44 FW_ENOMEM = 12, /* out of memory */ 45 FW_EFAULT = 14, /* bad address; fw bad */ 46 FW_EBUSY = 16, /* resource busy */ 47 FW_EEXIST = 17, /* file exists */ 48 FW_EINVAL = 22, /* invalid argument */ 49 FW_ENOSPC = 28, /* no space left on device */ 50 FW_ENOSYS = 38, /* functionality not implemented */ 51 FW_EPROTO = 71, /* protocol error */ 52 FW_EADDRINUSE = 98, /* address already in use */ 53 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 54 FW_ENETDOWN = 100, /* network is down */ 55 FW_ENETUNREACH = 101, /* network is unreachable */ 56 FW_ENOBUFS = 105, /* no buffer space available */ 57 FW_ETIMEDOUT = 110, /* timeout */ 58 FW_EINPROGRESS = 115, /* fw internal */ 59 FW_SCSI_ABORT_REQUESTED = 128, /* */ 60 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 61 FW_SCSI_ABORTED = 130, /* */ 62 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 63 FW_ERR_LINK_DOWN = 132, /* */ 64 FW_RDEV_NOT_READY = 133, /* */ 65 FW_ERR_RDEV_LOST = 134, /* */ 66 FW_ERR_RDEV_LOGO = 135, /* */ 67 FW_FCOE_NO_XCHG = 136, /* */ 68 FW_SCSI_RSP_ERR = 137, /* */ 69 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 70 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 71 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 72 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 73 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 74 }; 75 76 /****************************************************************************** 77 * W O R K R E Q U E S T s 78 ********************************/ 79 80 enum fw_wr_opcodes { 81 FW_FILTER_WR = 0x02, 82 FW_ULPTX_WR = 0x04, 83 FW_TP_WR = 0x05, 84 FW_ETH_TX_PKT_WR = 0x08, 85 FW_ETH_TX_PKTS_WR = 0x09, 86 FW_ETH_TX_UO_WR = 0x1c, 87 FW_EQ_FLUSH_WR = 0x1b, 88 FW_OFLD_CONNECTION_WR = 0x2f, 89 FW_FLOWC_WR = 0x0a, 90 FW_OFLD_TX_DATA_WR = 0x0b, 91 FW_CMD_WR = 0x10, 92 FW_ETH_TX_PKT_VM_WR = 0x11, 93 FW_RI_RES_WR = 0x0c, 94 FW_RI_RDMA_WRITE_WR = 0x14, 95 FW_RI_SEND_WR = 0x15, 96 FW_RI_RDMA_READ_WR = 0x16, 97 FW_RI_RECV_WR = 0x17, 98 FW_RI_BIND_MW_WR = 0x18, 99 FW_RI_FR_NSMR_WR = 0x19, 100 FW_RI_INV_LSTAG_WR = 0x1a, 101 FW_RI_SEND_IMMEDIATE_WR = 0x15, 102 FW_RI_ATOMIC_WR = 0x16, 103 FW_RI_WR = 0x0d, 104 FW_CHNET_IFCONF_WR = 0x6b, 105 FW_RDEV_WR = 0x38, 106 FW_FOISCSI_NODE_WR = 0x60, 107 FW_FOISCSI_CTRL_WR = 0x6a, 108 FW_FOISCSI_CHAP_WR = 0x6c, 109 FW_FCOE_ELS_CT_WR = 0x30, 110 FW_SCSI_WRITE_WR = 0x31, 111 FW_SCSI_READ_WR = 0x32, 112 FW_SCSI_CMD_WR = 0x33, 113 FW_SCSI_ABRT_CLS_WR = 0x34, 114 FW_SCSI_TGT_ACC_WR = 0x35, 115 FW_SCSI_TGT_XMIT_WR = 0x36, 116 FW_SCSI_TGT_RSP_WR = 0x37, 117 FW_LASTC2E_WR = 0x70 118 }; 119 120 /* 121 * Generic work request header flit0 122 */ 123 struct fw_wr_hdr { 124 __be32 hi; 125 __be32 lo; 126 }; 127 128 /* work request opcode (hi) 129 */ 130 #define S_FW_WR_OP 24 131 #define M_FW_WR_OP 0xff 132 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 133 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 134 135 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 136 */ 137 #define S_FW_WR_ATOMIC 23 138 #define M_FW_WR_ATOMIC 0x1 139 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 140 #define G_FW_WR_ATOMIC(x) \ 141 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 142 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 143 144 /* flush flag (hi) - firmware flushes flushable work request buffered 145 * in the flow context. 146 */ 147 #define S_FW_WR_FLUSH 22 148 #define M_FW_WR_FLUSH 0x1 149 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 150 #define G_FW_WR_FLUSH(x) \ 151 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 152 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 153 154 /* completion flag (hi) - firmware generates a cpl_fw6_ack 155 */ 156 #define S_FW_WR_COMPL 21 157 #define M_FW_WR_COMPL 0x1 158 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 159 #define G_FW_WR_COMPL(x) \ 160 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 161 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 162 163 164 /* work request immediate data lengh (hi) 165 */ 166 #define S_FW_WR_IMMDLEN 0 167 #define M_FW_WR_IMMDLEN 0xff 168 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 169 #define G_FW_WR_IMMDLEN(x) \ 170 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 171 172 /* egress queue status update to associated ingress queue entry (lo) 173 */ 174 #define S_FW_WR_EQUIQ 31 175 #define M_FW_WR_EQUIQ 0x1 176 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 177 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 178 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 179 180 /* egress queue status update to egress queue status entry (lo) 181 */ 182 #define S_FW_WR_EQUEQ 30 183 #define M_FW_WR_EQUEQ 0x1 184 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 185 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 186 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 187 188 /* flow context identifier (lo) 189 */ 190 #define S_FW_WR_FLOWID 8 191 #define M_FW_WR_FLOWID 0xfffff 192 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 193 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 194 195 /* length in units of 16-bytes (lo) 196 */ 197 #define S_FW_WR_LEN16 0 198 #define M_FW_WR_LEN16 0xff 199 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 200 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 201 202 /* valid filter configurations for compressed tuple 203 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 204 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 205 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 206 * OV - Outer VLAN/VNIC_ID, 207 */ 208 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 209 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 210 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 211 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 212 #define HW_TPL_FR_MT_E_PR_T 0x370 213 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 214 #define HW_TPL_FR_MT_E_T_P_FC 0X353 215 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 216 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 217 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 218 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 219 #define HW_TPL_FR_M_E_PR_FC 0X2E1 220 #define HW_TPL_FR_M_E_T_FC 0X2D1 221 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 222 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 223 #define HW_TPL_FR_M_T_IV_FC 0X299 224 #define HW_TPL_FR_M_T_OV_FC 0X295 225 #define HW_TPL_FR_E_PR_T_P 0X272 226 #define HW_TPL_FR_E_PR_T_FC 0X271 227 #define HW_TPL_FR_E_IV_FC 0X249 228 #define HW_TPL_FR_E_OV_FC 0X245 229 #define HW_TPL_FR_PR_T_IV_FC 0X239 230 #define HW_TPL_FR_PR_T_OV_FC 0X235 231 #define HW_TPL_FR_IV_OV_FC 0X20D 232 #define HW_TPL_MT_M_E_PR 0X1E0 233 #define HW_TPL_MT_M_E_T 0X1D0 234 #define HW_TPL_MT_E_PR_T_FC 0X171 235 #define HW_TPL_MT_E_IV 0X148 236 #define HW_TPL_MT_E_OV 0X144 237 #define HW_TPL_MT_PR_T_IV 0X138 238 #define HW_TPL_MT_PR_T_OV 0X134 239 #define HW_TPL_M_E_PR_P 0X0E2 240 #define HW_TPL_M_E_T_P 0X0D2 241 #define HW_TPL_E_PR_T_P_FC 0X073 242 #define HW_TPL_E_IV_P 0X04A 243 #define HW_TPL_E_OV_P 0X046 244 #define HW_TPL_PR_T_IV_P 0X03A 245 #define HW_TPL_PR_T_OV_P 0X036 246 247 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 248 enum fw_filter_wr_cookie { 249 FW_FILTER_WR_SUCCESS, 250 FW_FILTER_WR_FLT_ADDED, 251 FW_FILTER_WR_FLT_DELETED, 252 FW_FILTER_WR_SMT_TBL_FULL, 253 FW_FILTER_WR_EINVAL, 254 }; 255 256 struct fw_filter_wr { 257 __be32 op_pkd; 258 __be32 len16_pkd; 259 __be64 r3; 260 __be32 tid_to_iq; 261 __be32 del_filter_to_l2tix; 262 __be16 ethtype; 263 __be16 ethtypem; 264 __u8 frag_to_ovlan_vldm; 265 __u8 smac_sel; 266 __be16 rx_chan_rx_rpl_iq; 267 __be32 maci_to_matchtypem; 268 __u8 ptcl; 269 __u8 ptclm; 270 __u8 ttyp; 271 __u8 ttypm; 272 __be16 ivlan; 273 __be16 ivlanm; 274 __be16 ovlan; 275 __be16 ovlanm; 276 __u8 lip[16]; 277 __u8 lipm[16]; 278 __u8 fip[16]; 279 __u8 fipm[16]; 280 __be16 lp; 281 __be16 lpm; 282 __be16 fp; 283 __be16 fpm; 284 __be16 r7; 285 __u8 sma[6]; 286 }; 287 288 #define S_FW_FILTER_WR_TID 12 289 #define M_FW_FILTER_WR_TID 0xfffff 290 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 291 #define G_FW_FILTER_WR_TID(x) \ 292 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 293 294 #define S_FW_FILTER_WR_RQTYPE 11 295 #define M_FW_FILTER_WR_RQTYPE 0x1 296 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 297 #define G_FW_FILTER_WR_RQTYPE(x) \ 298 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 299 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 300 301 #define S_FW_FILTER_WR_NOREPLY 10 302 #define M_FW_FILTER_WR_NOREPLY 0x1 303 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 304 #define G_FW_FILTER_WR_NOREPLY(x) \ 305 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 306 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 307 308 #define S_FW_FILTER_WR_IQ 0 309 #define M_FW_FILTER_WR_IQ 0x3ff 310 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 311 #define G_FW_FILTER_WR_IQ(x) \ 312 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 313 314 #define S_FW_FILTER_WR_DEL_FILTER 31 315 #define M_FW_FILTER_WR_DEL_FILTER 0x1 316 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 317 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 318 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 319 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 320 321 #define S_FW_FILTER_WR_RPTTID 25 322 #define M_FW_FILTER_WR_RPTTID 0x1 323 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 324 #define G_FW_FILTER_WR_RPTTID(x) \ 325 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 326 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 327 328 #define S_FW_FILTER_WR_DROP 24 329 #define M_FW_FILTER_WR_DROP 0x1 330 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 331 #define G_FW_FILTER_WR_DROP(x) \ 332 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 333 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 334 335 #define S_FW_FILTER_WR_DIRSTEER 23 336 #define M_FW_FILTER_WR_DIRSTEER 0x1 337 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 338 #define G_FW_FILTER_WR_DIRSTEER(x) \ 339 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 340 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 341 342 #define S_FW_FILTER_WR_MASKHASH 22 343 #define M_FW_FILTER_WR_MASKHASH 0x1 344 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 345 #define G_FW_FILTER_WR_MASKHASH(x) \ 346 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 347 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 348 349 #define S_FW_FILTER_WR_DIRSTEERHASH 21 350 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 351 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 352 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 353 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 354 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 355 356 #define S_FW_FILTER_WR_LPBK 20 357 #define M_FW_FILTER_WR_LPBK 0x1 358 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 359 #define G_FW_FILTER_WR_LPBK(x) \ 360 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 361 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 362 363 #define S_FW_FILTER_WR_DMAC 19 364 #define M_FW_FILTER_WR_DMAC 0x1 365 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 366 #define G_FW_FILTER_WR_DMAC(x) \ 367 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 368 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 369 370 #define S_FW_FILTER_WR_SMAC 18 371 #define M_FW_FILTER_WR_SMAC 0x1 372 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 373 #define G_FW_FILTER_WR_SMAC(x) \ 374 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 375 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 376 377 #define S_FW_FILTER_WR_INSVLAN 17 378 #define M_FW_FILTER_WR_INSVLAN 0x1 379 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 380 #define G_FW_FILTER_WR_INSVLAN(x) \ 381 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 382 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 383 384 #define S_FW_FILTER_WR_RMVLAN 16 385 #define M_FW_FILTER_WR_RMVLAN 0x1 386 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 387 #define G_FW_FILTER_WR_RMVLAN(x) \ 388 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 389 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 390 391 #define S_FW_FILTER_WR_HITCNTS 15 392 #define M_FW_FILTER_WR_HITCNTS 0x1 393 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 394 #define G_FW_FILTER_WR_HITCNTS(x) \ 395 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 396 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 397 398 #define S_FW_FILTER_WR_TXCHAN 13 399 #define M_FW_FILTER_WR_TXCHAN 0x3 400 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 401 #define G_FW_FILTER_WR_TXCHAN(x) \ 402 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 403 404 #define S_FW_FILTER_WR_PRIO 12 405 #define M_FW_FILTER_WR_PRIO 0x1 406 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 407 #define G_FW_FILTER_WR_PRIO(x) \ 408 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 409 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 410 411 #define S_FW_FILTER_WR_L2TIX 0 412 #define M_FW_FILTER_WR_L2TIX 0xfff 413 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 414 #define G_FW_FILTER_WR_L2TIX(x) \ 415 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 416 417 #define S_FW_FILTER_WR_FRAG 7 418 #define M_FW_FILTER_WR_FRAG 0x1 419 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 420 #define G_FW_FILTER_WR_FRAG(x) \ 421 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 422 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 423 424 #define S_FW_FILTER_WR_FRAGM 6 425 #define M_FW_FILTER_WR_FRAGM 0x1 426 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 427 #define G_FW_FILTER_WR_FRAGM(x) \ 428 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 429 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 430 431 #define S_FW_FILTER_WR_IVLAN_VLD 5 432 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 433 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 434 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 435 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 436 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 437 438 #define S_FW_FILTER_WR_OVLAN_VLD 4 439 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 440 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 441 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 442 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 443 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 444 445 #define S_FW_FILTER_WR_IVLAN_VLDM 3 446 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 447 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 448 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 449 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 450 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 451 452 #define S_FW_FILTER_WR_OVLAN_VLDM 2 453 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 454 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 455 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 456 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 457 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 458 459 #define S_FW_FILTER_WR_RX_CHAN 15 460 #define M_FW_FILTER_WR_RX_CHAN 0x1 461 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 462 #define G_FW_FILTER_WR_RX_CHAN(x) \ 463 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 464 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 465 466 #define S_FW_FILTER_WR_RX_RPL_IQ 0 467 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 468 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 469 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 470 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 471 472 #define S_FW_FILTER_WR_MACI 23 473 #define M_FW_FILTER_WR_MACI 0x1ff 474 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 475 #define G_FW_FILTER_WR_MACI(x) \ 476 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 477 478 #define S_FW_FILTER_WR_MACIM 14 479 #define M_FW_FILTER_WR_MACIM 0x1ff 480 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 481 #define G_FW_FILTER_WR_MACIM(x) \ 482 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 483 484 #define S_FW_FILTER_WR_FCOE 13 485 #define M_FW_FILTER_WR_FCOE 0x1 486 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 487 #define G_FW_FILTER_WR_FCOE(x) \ 488 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 489 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 490 491 #define S_FW_FILTER_WR_FCOEM 12 492 #define M_FW_FILTER_WR_FCOEM 0x1 493 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 494 #define G_FW_FILTER_WR_FCOEM(x) \ 495 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 496 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 497 498 #define S_FW_FILTER_WR_PORT 9 499 #define M_FW_FILTER_WR_PORT 0x7 500 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 501 #define G_FW_FILTER_WR_PORT(x) \ 502 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 503 504 #define S_FW_FILTER_WR_PORTM 6 505 #define M_FW_FILTER_WR_PORTM 0x7 506 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 507 #define G_FW_FILTER_WR_PORTM(x) \ 508 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 509 510 #define S_FW_FILTER_WR_MATCHTYPE 3 511 #define M_FW_FILTER_WR_MATCHTYPE 0x7 512 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 513 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 514 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 515 516 #define S_FW_FILTER_WR_MATCHTYPEM 0 517 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 518 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 519 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 520 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 521 522 struct fw_ulptx_wr { 523 __be32 op_to_compl; 524 __be32 flowid_len16; 525 __u64 cookie; 526 }; 527 528 struct fw_tp_wr { 529 __be32 op_to_immdlen; 530 __be32 flowid_len16; 531 __u64 cookie; 532 }; 533 534 struct fw_eth_tx_pkt_wr { 535 __be32 op_immdlen; 536 __be32 equiq_to_len16; 537 __be64 r3; 538 }; 539 540 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 541 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 542 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 543 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 544 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 545 546 struct fw_eth_tx_pkts_wr { 547 __be32 op_pkd; 548 __be32 equiq_to_len16; 549 __be32 r3; 550 __be16 plen; 551 __u8 npkt; 552 __u8 type; 553 }; 554 555 struct fw_eth_tx_uo_wr { 556 __be32 op_immdlen; 557 __be32 equiq_to_len16; 558 __be64 r3; 559 __be16 ethlen; 560 __be16 iplen; 561 __be16 udplen; 562 __be16 mss; 563 __be32 length; 564 __be32 r4; 565 }; 566 567 struct fw_eq_flush_wr { 568 __u8 opcode; 569 __u8 r1[3]; 570 __be32 equiq_to_len16; 571 __be64 r3; 572 }; 573 574 struct fw_ofld_connection_wr { 575 __be32 op_compl; 576 __be32 len16_pkd; 577 __u64 cookie; 578 __be64 r2; 579 __be64 r3; 580 struct fw_ofld_connection_le { 581 __be32 version_cpl; 582 __be32 filter; 583 __be32 r1; 584 __be16 lport; 585 __be16 pport; 586 union fw_ofld_connection_leip { 587 struct fw_ofld_connection_le_ipv4 { 588 __be32 pip; 589 __be32 lip; 590 __be64 r0; 591 __be64 r1; 592 __be64 r2; 593 } ipv4; 594 struct fw_ofld_connection_le_ipv6 { 595 __be64 pip_hi; 596 __be64 pip_lo; 597 __be64 lip_hi; 598 __be64 lip_lo; 599 } ipv6; 600 } u; 601 } le; 602 struct fw_ofld_connection_tcb { 603 __be32 t_state_to_astid; 604 __be16 cplrxdataack_cplpassacceptrpl; 605 __be16 rcv_adv; 606 __be32 rcv_nxt; 607 __be32 tx_max; 608 __be64 opt0; 609 __be32 opt2; 610 __be32 r1; 611 __be64 r2; 612 __be64 r3; 613 } tcb; 614 }; 615 616 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 617 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 618 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 619 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 620 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 621 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 622 M_FW_OFLD_CONNECTION_WR_VERSION) 623 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 624 625 #define S_FW_OFLD_CONNECTION_WR_CPL 30 626 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 627 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 628 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 629 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 630 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 631 632 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 633 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 634 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 635 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 636 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 637 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 638 M_FW_OFLD_CONNECTION_WR_T_STATE) 639 640 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 641 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 642 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 643 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 644 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 645 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 646 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 647 648 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 649 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 650 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 651 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 652 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 653 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 654 655 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 656 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 657 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 658 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 659 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 660 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 661 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 662 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 663 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 664 665 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 666 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 667 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 668 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 669 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 670 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 671 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 672 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 673 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 674 675 enum fw_flowc_mnem_tcpstate { 676 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 677 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 678 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 679 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 680 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 681 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 682 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 683 * will resend FIN - equiv ESTAB 684 */ 685 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 686 * will resend FIN but have 687 * received FIN 688 */ 689 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 690 * will resend FIN but have 691 * received FIN 692 */ 693 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 694 * waiting for FIN 695 */ 696 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 697 }; 698 699 enum fw_flowc_mnem_uostate { 700 FW_FLOWC_MNEM_UOSTATE_CLOSED = 0, /* illegal */ 701 FW_FLOWC_MNEM_UOSTATE_ESTABLISHED = 1, /* default */ 702 FW_FLOWC_MNEM_UOSTATE_CLOSING = 2, /* graceful close, after sending 703 * outstanding payload 704 */ 705 FW_FLOWC_MNEM_UOSTATE_ABORTING = 3, /* immediate close, after 706 * discarding outstanding payload 707 */ 708 }; 709 710 enum fw_flowc_mnem { 711 FW_FLOWC_MNEM_PFNVFN, /* PFN [15:8] VFN [7:0] */ 712 FW_FLOWC_MNEM_CH, 713 FW_FLOWC_MNEM_PORT, 714 FW_FLOWC_MNEM_IQID, 715 FW_FLOWC_MNEM_SNDNXT, 716 FW_FLOWC_MNEM_RCVNXT, 717 FW_FLOWC_MNEM_SNDBUF, 718 FW_FLOWC_MNEM_MSS, 719 FW_FLOWC_MNEM_TXDATAPLEN_MAX, 720 FW_FLOWC_MNEM_TCPSTATE, 721 FW_FLOWC_MNEM_UOSTATE, 722 FW_FLOWC_MNEM_SCHEDCLASS, 723 FW_FLOWC_MNEM_DCBPRIO, 724 }; 725 726 struct fw_flowc_mnemval { 727 __u8 mnemonic; 728 __u8 r4[3]; 729 __be32 val; 730 }; 731 732 struct fw_flowc_wr { 733 __be32 op_to_nparams; 734 __be32 flowid_len16; 735 #ifndef C99_NOT_SUPPORTED 736 struct fw_flowc_mnemval mnemval[0]; 737 #endif 738 }; 739 740 #define S_FW_FLOWC_WR_NPARAMS 0 741 #define M_FW_FLOWC_WR_NPARAMS 0xff 742 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 743 #define G_FW_FLOWC_WR_NPARAMS(x) \ 744 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 745 746 struct fw_ofld_tx_data_wr { 747 __be32 op_to_immdlen; 748 __be32 flowid_len16; 749 __be32 plen; 750 __be32 tunnel_to_proxy; 751 }; 752 753 #define S_FW_OFLD_TX_DATA_WR_TUNNEL 19 754 #define M_FW_OFLD_TX_DATA_WR_TUNNEL 0x1 755 #define V_FW_OFLD_TX_DATA_WR_TUNNEL(x) ((x) << S_FW_OFLD_TX_DATA_WR_TUNNEL) 756 #define G_FW_OFLD_TX_DATA_WR_TUNNEL(x) \ 757 (((x) >> S_FW_OFLD_TX_DATA_WR_TUNNEL) & M_FW_OFLD_TX_DATA_WR_TUNNEL) 758 #define F_FW_OFLD_TX_DATA_WR_TUNNEL V_FW_OFLD_TX_DATA_WR_TUNNEL(1U) 759 760 #define S_FW_OFLD_TX_DATA_WR_SAVE 18 761 #define M_FW_OFLD_TX_DATA_WR_SAVE 0x1 762 #define V_FW_OFLD_TX_DATA_WR_SAVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SAVE) 763 #define G_FW_OFLD_TX_DATA_WR_SAVE(x) \ 764 (((x) >> S_FW_OFLD_TX_DATA_WR_SAVE) & M_FW_OFLD_TX_DATA_WR_SAVE) 765 #define F_FW_OFLD_TX_DATA_WR_SAVE V_FW_OFLD_TX_DATA_WR_SAVE(1U) 766 767 #define S_FW_OFLD_TX_DATA_WR_FLUSH 17 768 #define M_FW_OFLD_TX_DATA_WR_FLUSH 0x1 769 #define V_FW_OFLD_TX_DATA_WR_FLUSH(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLUSH) 770 #define G_FW_OFLD_TX_DATA_WR_FLUSH(x) \ 771 (((x) >> S_FW_OFLD_TX_DATA_WR_FLUSH) & M_FW_OFLD_TX_DATA_WR_FLUSH) 772 #define F_FW_OFLD_TX_DATA_WR_FLUSH V_FW_OFLD_TX_DATA_WR_FLUSH(1U) 773 774 #define S_FW_OFLD_TX_DATA_WR_URGENT 16 775 #define M_FW_OFLD_TX_DATA_WR_URGENT 0x1 776 #define V_FW_OFLD_TX_DATA_WR_URGENT(x) ((x) << S_FW_OFLD_TX_DATA_WR_URGENT) 777 #define G_FW_OFLD_TX_DATA_WR_URGENT(x) \ 778 (((x) >> S_FW_OFLD_TX_DATA_WR_URGENT) & M_FW_OFLD_TX_DATA_WR_URGENT) 779 #define F_FW_OFLD_TX_DATA_WR_URGENT V_FW_OFLD_TX_DATA_WR_URGENT(1U) 780 781 #define S_FW_OFLD_TX_DATA_WR_MORE 15 782 #define M_FW_OFLD_TX_DATA_WR_MORE 0x1 783 #define V_FW_OFLD_TX_DATA_WR_MORE(x) ((x) << S_FW_OFLD_TX_DATA_WR_MORE) 784 #define G_FW_OFLD_TX_DATA_WR_MORE(x) \ 785 (((x) >> S_FW_OFLD_TX_DATA_WR_MORE) & M_FW_OFLD_TX_DATA_WR_MORE) 786 #define F_FW_OFLD_TX_DATA_WR_MORE V_FW_OFLD_TX_DATA_WR_MORE(1U) 787 788 #define S_FW_OFLD_TX_DATA_WR_SHOVE 14 789 #define M_FW_OFLD_TX_DATA_WR_SHOVE 0x1 790 #define V_FW_OFLD_TX_DATA_WR_SHOVE(x) ((x) << S_FW_OFLD_TX_DATA_WR_SHOVE) 791 #define G_FW_OFLD_TX_DATA_WR_SHOVE(x) \ 792 (((x) >> S_FW_OFLD_TX_DATA_WR_SHOVE) & M_FW_OFLD_TX_DATA_WR_SHOVE) 793 #define F_FW_OFLD_TX_DATA_WR_SHOVE V_FW_OFLD_TX_DATA_WR_SHOVE(1U) 794 795 #define S_FW_OFLD_TX_DATA_WR_ULPMODE 10 796 #define M_FW_OFLD_TX_DATA_WR_ULPMODE 0xf 797 #define V_FW_OFLD_TX_DATA_WR_ULPMODE(x) ((x) << S_FW_OFLD_TX_DATA_WR_ULPMODE) 798 #define G_FW_OFLD_TX_DATA_WR_ULPMODE(x) \ 799 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPMODE) & M_FW_OFLD_TX_DATA_WR_ULPMODE) 800 801 #define S_FW_OFLD_TX_DATA_WR_ULPSUBMODE 6 802 #define M_FW_OFLD_TX_DATA_WR_ULPSUBMODE 0xf 803 #define V_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 804 ((x) << S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 805 #define G_FW_OFLD_TX_DATA_WR_ULPSUBMODE(x) \ 806 (((x) >> S_FW_OFLD_TX_DATA_WR_ULPSUBMODE) & \ 807 M_FW_OFLD_TX_DATA_WR_ULPSUBMODE) 808 809 #define S_FW_OFLD_TX_DATA_WR_PROXY 5 810 #define M_FW_OFLD_TX_DATA_WR_PROXY 0x1 811 #define V_FW_OFLD_TX_DATA_WR_PROXY(x) ((x) << S_FW_OFLD_TX_DATA_WR_PROXY) 812 #define G_FW_OFLD_TX_DATA_WR_PROXY(x) \ 813 (((x) >> S_FW_OFLD_TX_DATA_WR_PROXY) & M_FW_OFLD_TX_DATA_WR_PROXY) 814 #define F_FW_OFLD_TX_DATA_WR_PROXY V_FW_OFLD_TX_DATA_WR_PROXY(1U) 815 816 struct fw_cmd_wr { 817 __be32 op_dma; 818 __be32 len16_pkd; 819 __be64 cookie_daddr; 820 }; 821 822 #define S_FW_CMD_WR_DMA 17 823 #define M_FW_CMD_WR_DMA 0x1 824 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 825 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 826 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 827 828 struct fw_eth_tx_pkt_vm_wr { 829 __be32 op_immdlen; 830 __be32 equiq_to_len16; 831 __be32 r3[2]; 832 __u8 ethmacdst[6]; 833 __u8 ethmacsrc[6]; 834 __be16 ethtype; 835 __be16 vlantci; 836 }; 837 838 /****************************************************************************** 839 * R I W O R K R E Q U E S T s 840 **************************************/ 841 842 enum fw_ri_wr_opcode { 843 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 844 FW_RI_READ_REQ = 0x1, 845 FW_RI_READ_RESP = 0x2, 846 FW_RI_SEND = 0x3, 847 FW_RI_SEND_WITH_INV = 0x4, 848 FW_RI_SEND_WITH_SE = 0x5, 849 FW_RI_SEND_WITH_SE_INV = 0x6, 850 FW_RI_TERMINATE = 0x7, 851 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 852 FW_RI_BIND_MW = 0x9, 853 FW_RI_FAST_REGISTER = 0xa, 854 FW_RI_LOCAL_INV = 0xb, 855 FW_RI_QP_MODIFY = 0xc, 856 FW_RI_BYPASS = 0xd, 857 FW_RI_RECEIVE = 0xe, 858 #if 0 859 FW_RI_SEND_IMMEDIATE = 0x8, 860 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 861 FW_RI_ATOMIC_REQUEST = 0xa, 862 FW_RI_ATOMIC_RESPONSE = 0xb, 863 864 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 865 FW_RI_FAST_REGISTER = 0xd, 866 FW_RI_LOCAL_INV = 0xe, 867 #endif 868 FW_RI_SGE_EC_CR_RETURN = 0xf 869 }; 870 871 enum fw_ri_wr_flags { 872 FW_RI_COMPLETION_FLAG = 0x01, 873 FW_RI_NOTIFICATION_FLAG = 0x02, 874 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 875 FW_RI_READ_FENCE_FLAG = 0x08, 876 FW_RI_LOCAL_FENCE_FLAG = 0x10, 877 FW_RI_RDMA_READ_INVALIDATE = 0x20 878 }; 879 880 enum fw_ri_mpa_attrs { 881 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 882 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 883 FW_RI_MPA_CRC_ENABLE = 0x04, 884 FW_RI_MPA_IETF_ENABLE = 0x08 885 }; 886 887 enum fw_ri_qp_caps { 888 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 889 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 890 FW_RI_QP_BIND_ENABLE = 0x04, 891 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 892 FW_RI_QP_STAG0_ENABLE = 0x10, 893 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 894 }; 895 896 enum fw_ri_addr_type { 897 FW_RI_ZERO_BASED_TO = 0x00, 898 FW_RI_VA_BASED_TO = 0x01 899 }; 900 901 enum fw_ri_mem_perms { 902 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 903 FW_RI_MEM_ACCESS_REM_READ = 0x02, 904 FW_RI_MEM_ACCESS_REM = 0x03, 905 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 906 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 907 FW_RI_MEM_ACCESS_LOCAL = 0x0C 908 }; 909 910 enum fw_ri_stag_type { 911 FW_RI_STAG_NSMR = 0x00, 912 FW_RI_STAG_SMR = 0x01, 913 FW_RI_STAG_MW = 0x02, 914 FW_RI_STAG_MW_RELAXED = 0x03 915 }; 916 917 enum fw_ri_data_op { 918 FW_RI_DATA_IMMD = 0x81, 919 FW_RI_DATA_DSGL = 0x82, 920 FW_RI_DATA_ISGL = 0x83 921 }; 922 923 enum fw_ri_sgl_depth { 924 FW_RI_SGL_DEPTH_MAX_SQ = 16, 925 FW_RI_SGL_DEPTH_MAX_RQ = 4 926 }; 927 928 enum fw_ri_cqe_err { 929 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 930 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 931 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 932 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 933 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 934 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 935 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 936 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 937 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 938 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 939 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 940 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 941 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 942 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 943 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 944 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 945 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 946 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 947 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 948 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 949 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 950 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 951 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 952 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 953 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 954 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 955 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 956 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 957 958 }; 959 960 struct fw_ri_dsge_pair { 961 __be32 len[2]; 962 __be64 addr[2]; 963 }; 964 965 struct fw_ri_dsgl { 966 __u8 op; 967 __u8 r1; 968 __be16 nsge; 969 __be32 len0; 970 __be64 addr0; 971 #ifndef C99_NOT_SUPPORTED 972 struct fw_ri_dsge_pair sge[0]; 973 #endif 974 }; 975 976 struct fw_ri_sge { 977 __be32 stag; 978 __be32 len; 979 __be64 to; 980 }; 981 982 struct fw_ri_isgl { 983 __u8 op; 984 __u8 r1; 985 __be16 nsge; 986 __be32 r2; 987 #ifndef C99_NOT_SUPPORTED 988 struct fw_ri_sge sge[0]; 989 #endif 990 }; 991 992 struct fw_ri_immd { 993 __u8 op; 994 __u8 r1; 995 __be16 r2; 996 __be32 immdlen; 997 #ifndef C99_NOT_SUPPORTED 998 __u8 data[0]; 999 #endif 1000 }; 1001 1002 struct fw_ri_tpte { 1003 __be32 valid_to_pdid; 1004 __be32 locread_to_qpid; 1005 __be32 nosnoop_pbladdr; 1006 __be32 len_lo; 1007 __be32 va_hi; 1008 __be32 va_lo_fbo; 1009 __be32 dca_mwbcnt_pstag; 1010 __be32 len_hi; 1011 }; 1012 1013 #define S_FW_RI_TPTE_VALID 31 1014 #define M_FW_RI_TPTE_VALID 0x1 1015 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1016 #define G_FW_RI_TPTE_VALID(x) \ 1017 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1018 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1019 1020 #define S_FW_RI_TPTE_STAGKEY 23 1021 #define M_FW_RI_TPTE_STAGKEY 0xff 1022 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1023 #define G_FW_RI_TPTE_STAGKEY(x) \ 1024 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1025 1026 #define S_FW_RI_TPTE_STAGSTATE 22 1027 #define M_FW_RI_TPTE_STAGSTATE 0x1 1028 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1029 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1030 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1031 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1032 1033 #define S_FW_RI_TPTE_STAGTYPE 20 1034 #define M_FW_RI_TPTE_STAGTYPE 0x3 1035 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1036 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1037 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1038 1039 #define S_FW_RI_TPTE_PDID 0 1040 #define M_FW_RI_TPTE_PDID 0xfffff 1041 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1042 #define G_FW_RI_TPTE_PDID(x) \ 1043 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1044 1045 #define S_FW_RI_TPTE_PERM 28 1046 #define M_FW_RI_TPTE_PERM 0xf 1047 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1048 #define G_FW_RI_TPTE_PERM(x) \ 1049 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1050 1051 #define S_FW_RI_TPTE_REMINVDIS 27 1052 #define M_FW_RI_TPTE_REMINVDIS 0x1 1053 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1054 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1055 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1056 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1057 1058 #define S_FW_RI_TPTE_ADDRTYPE 26 1059 #define M_FW_RI_TPTE_ADDRTYPE 1 1060 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1061 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1062 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1063 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1064 1065 #define S_FW_RI_TPTE_MWBINDEN 25 1066 #define M_FW_RI_TPTE_MWBINDEN 0x1 1067 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1068 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1069 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1070 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1071 1072 #define S_FW_RI_TPTE_PS 20 1073 #define M_FW_RI_TPTE_PS 0x1f 1074 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1075 #define G_FW_RI_TPTE_PS(x) \ 1076 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1077 1078 #define S_FW_RI_TPTE_QPID 0 1079 #define M_FW_RI_TPTE_QPID 0xfffff 1080 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1081 #define G_FW_RI_TPTE_QPID(x) \ 1082 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1083 1084 #define S_FW_RI_TPTE_NOSNOOP 31 1085 #define M_FW_RI_TPTE_NOSNOOP 0x1 1086 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1087 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1088 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1089 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1090 1091 #define S_FW_RI_TPTE_PBLADDR 0 1092 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1093 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1094 #define G_FW_RI_TPTE_PBLADDR(x) \ 1095 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1096 1097 #define S_FW_RI_TPTE_DCA 24 1098 #define M_FW_RI_TPTE_DCA 0x1f 1099 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1100 #define G_FW_RI_TPTE_DCA(x) \ 1101 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1102 1103 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1104 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1105 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1106 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1107 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1108 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1109 1110 enum fw_ri_cqe_rxtx { 1111 FW_RI_CQE_RXTX_RX = 0x0, 1112 FW_RI_CQE_RXTX_TX = 0x1, 1113 }; 1114 1115 struct fw_ri_cqe { 1116 union fw_ri_rxtx { 1117 struct fw_ri_scqe { 1118 __be32 qpid_n_stat_rxtx_type; 1119 __be32 plen; 1120 __be32 reserved; 1121 __be32 wrid; 1122 } scqe; 1123 struct fw_ri_rcqe { 1124 __be32 qpid_n_stat_rxtx_type; 1125 __be32 plen; 1126 __be32 stag; 1127 __be32 msn; 1128 } rcqe; 1129 } u; 1130 }; 1131 1132 #define S_FW_RI_CQE_QPID 12 1133 #define M_FW_RI_CQE_QPID 0xfffff 1134 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1135 #define G_FW_RI_CQE_QPID(x) \ 1136 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1137 1138 #define S_FW_RI_CQE_NOTIFY 10 1139 #define M_FW_RI_CQE_NOTIFY 0x1 1140 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1141 #define G_FW_RI_CQE_NOTIFY(x) \ 1142 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1143 1144 #define S_FW_RI_CQE_STATUS 5 1145 #define M_FW_RI_CQE_STATUS 0x1f 1146 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1147 #define G_FW_RI_CQE_STATUS(x) \ 1148 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1149 1150 1151 #define S_FW_RI_CQE_RXTX 4 1152 #define M_FW_RI_CQE_RXTX 0x1 1153 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1154 #define G_FW_RI_CQE_RXTX(x) \ 1155 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1156 1157 #define S_FW_RI_CQE_TYPE 0 1158 #define M_FW_RI_CQE_TYPE 0xf 1159 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1160 #define G_FW_RI_CQE_TYPE(x) \ 1161 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1162 1163 enum fw_ri_res_type { 1164 FW_RI_RES_TYPE_SQ, 1165 FW_RI_RES_TYPE_RQ, 1166 FW_RI_RES_TYPE_CQ, 1167 }; 1168 1169 enum fw_ri_res_op { 1170 FW_RI_RES_OP_WRITE, 1171 FW_RI_RES_OP_RESET, 1172 }; 1173 1174 struct fw_ri_res { 1175 union fw_ri_restype { 1176 struct fw_ri_res_sqrq { 1177 __u8 restype; 1178 __u8 op; 1179 __be16 r3; 1180 __be32 eqid; 1181 __be32 r4[2]; 1182 __be32 fetchszm_to_iqid; 1183 __be32 dcaen_to_eqsize; 1184 __be64 eqaddr; 1185 } sqrq; 1186 struct fw_ri_res_cq { 1187 __u8 restype; 1188 __u8 op; 1189 __be16 r3; 1190 __be32 iqid; 1191 __be32 r4[2]; 1192 __be32 iqandst_to_iqandstindex; 1193 __be16 iqdroprss_to_iqesize; 1194 __be16 iqsize; 1195 __be64 iqaddr; 1196 __be32 iqns_iqro; 1197 __be32 r6_lo; 1198 __be64 r7; 1199 } cq; 1200 } u; 1201 }; 1202 1203 struct fw_ri_res_wr { 1204 __be32 op_nres; 1205 __be32 len16_pkd; 1206 __u64 cookie; 1207 #ifndef C99_NOT_SUPPORTED 1208 struct fw_ri_res res[0]; 1209 #endif 1210 }; 1211 1212 #define S_FW_RI_RES_WR_NRES 0 1213 #define M_FW_RI_RES_WR_NRES 0xff 1214 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1215 #define G_FW_RI_RES_WR_NRES(x) \ 1216 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1217 1218 #define S_FW_RI_RES_WR_FETCHSZM 26 1219 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1220 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1221 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1222 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1223 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1224 1225 #define S_FW_RI_RES_WR_STATUSPGNS 25 1226 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1227 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1228 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1229 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1230 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1231 1232 #define S_FW_RI_RES_WR_STATUSPGRO 24 1233 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1234 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1235 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1236 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1237 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1238 1239 #define S_FW_RI_RES_WR_FETCHNS 23 1240 #define M_FW_RI_RES_WR_FETCHNS 0x1 1241 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 1242 #define G_FW_RI_RES_WR_FETCHNS(x) \ 1243 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 1244 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 1245 1246 #define S_FW_RI_RES_WR_FETCHRO 22 1247 #define M_FW_RI_RES_WR_FETCHRO 0x1 1248 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 1249 #define G_FW_RI_RES_WR_FETCHRO(x) \ 1250 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 1251 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 1252 1253 #define S_FW_RI_RES_WR_HOSTFCMODE 20 1254 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 1255 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 1256 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 1257 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 1258 1259 #define S_FW_RI_RES_WR_CPRIO 19 1260 #define M_FW_RI_RES_WR_CPRIO 0x1 1261 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 1262 #define G_FW_RI_RES_WR_CPRIO(x) \ 1263 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 1264 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 1265 1266 #define S_FW_RI_RES_WR_ONCHIP 18 1267 #define M_FW_RI_RES_WR_ONCHIP 0x1 1268 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 1269 #define G_FW_RI_RES_WR_ONCHIP(x) \ 1270 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 1271 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 1272 1273 #define S_FW_RI_RES_WR_PCIECHN 16 1274 #define M_FW_RI_RES_WR_PCIECHN 0x3 1275 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 1276 #define G_FW_RI_RES_WR_PCIECHN(x) \ 1277 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 1278 1279 #define S_FW_RI_RES_WR_IQID 0 1280 #define M_FW_RI_RES_WR_IQID 0xffff 1281 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 1282 #define G_FW_RI_RES_WR_IQID(x) \ 1283 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 1284 1285 #define S_FW_RI_RES_WR_DCAEN 31 1286 #define M_FW_RI_RES_WR_DCAEN 0x1 1287 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 1288 #define G_FW_RI_RES_WR_DCAEN(x) \ 1289 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 1290 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 1291 1292 #define S_FW_RI_RES_WR_DCACPU 26 1293 #define M_FW_RI_RES_WR_DCACPU 0x1f 1294 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 1295 #define G_FW_RI_RES_WR_DCACPU(x) \ 1296 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 1297 1298 #define S_FW_RI_RES_WR_FBMIN 23 1299 #define M_FW_RI_RES_WR_FBMIN 0x7 1300 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 1301 #define G_FW_RI_RES_WR_FBMIN(x) \ 1302 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 1303 1304 #define S_FW_RI_RES_WR_FBMAX 20 1305 #define M_FW_RI_RES_WR_FBMAX 0x7 1306 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 1307 #define G_FW_RI_RES_WR_FBMAX(x) \ 1308 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 1309 1310 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 1311 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 1312 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 1313 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 1314 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 1315 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 1316 1317 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 1318 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 1319 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 1320 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 1321 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 1322 1323 #define S_FW_RI_RES_WR_EQSIZE 0 1324 #define M_FW_RI_RES_WR_EQSIZE 0xffff 1325 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 1326 #define G_FW_RI_RES_WR_EQSIZE(x) \ 1327 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 1328 1329 #define S_FW_RI_RES_WR_IQANDST 15 1330 #define M_FW_RI_RES_WR_IQANDST 0x1 1331 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 1332 #define G_FW_RI_RES_WR_IQANDST(x) \ 1333 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 1334 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 1335 1336 #define S_FW_RI_RES_WR_IQANUS 14 1337 #define M_FW_RI_RES_WR_IQANUS 0x1 1338 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 1339 #define G_FW_RI_RES_WR_IQANUS(x) \ 1340 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 1341 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 1342 1343 #define S_FW_RI_RES_WR_IQANUD 12 1344 #define M_FW_RI_RES_WR_IQANUD 0x3 1345 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 1346 #define G_FW_RI_RES_WR_IQANUD(x) \ 1347 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 1348 1349 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 1350 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 1351 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 1352 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 1353 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 1354 1355 #define S_FW_RI_RES_WR_IQDROPRSS 15 1356 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 1357 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 1358 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 1359 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 1360 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 1361 1362 #define S_FW_RI_RES_WR_IQGTSMODE 14 1363 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 1364 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 1365 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 1366 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 1367 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 1368 1369 #define S_FW_RI_RES_WR_IQPCIECH 12 1370 #define M_FW_RI_RES_WR_IQPCIECH 0x3 1371 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 1372 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 1373 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 1374 1375 #define S_FW_RI_RES_WR_IQDCAEN 11 1376 #define M_FW_RI_RES_WR_IQDCAEN 0x1 1377 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 1378 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 1379 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 1380 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 1381 1382 #define S_FW_RI_RES_WR_IQDCACPU 6 1383 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 1384 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 1385 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 1386 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 1387 1388 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 1389 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 1390 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1391 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 1392 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 1393 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 1394 1395 #define S_FW_RI_RES_WR_IQO 3 1396 #define M_FW_RI_RES_WR_IQO 0x1 1397 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 1398 #define G_FW_RI_RES_WR_IQO(x) \ 1399 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 1400 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 1401 1402 #define S_FW_RI_RES_WR_IQCPRIO 2 1403 #define M_FW_RI_RES_WR_IQCPRIO 0x1 1404 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 1405 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 1406 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 1407 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 1408 1409 #define S_FW_RI_RES_WR_IQESIZE 0 1410 #define M_FW_RI_RES_WR_IQESIZE 0x3 1411 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 1412 #define G_FW_RI_RES_WR_IQESIZE(x) \ 1413 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 1414 1415 #define S_FW_RI_RES_WR_IQNS 31 1416 #define M_FW_RI_RES_WR_IQNS 0x1 1417 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 1418 #define G_FW_RI_RES_WR_IQNS(x) \ 1419 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 1420 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 1421 1422 #define S_FW_RI_RES_WR_IQRO 30 1423 #define M_FW_RI_RES_WR_IQRO 0x1 1424 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 1425 #define G_FW_RI_RES_WR_IQRO(x) \ 1426 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 1427 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 1428 1429 struct fw_ri_rdma_write_wr { 1430 __u8 opcode; 1431 __u8 flags; 1432 __u16 wrid; 1433 __u8 r1[3]; 1434 __u8 len16; 1435 __be64 r2; 1436 __be32 plen; 1437 __be32 stag_sink; 1438 __be64 to_sink; 1439 #ifndef C99_NOT_SUPPORTED 1440 union { 1441 struct fw_ri_immd immd_src[0]; 1442 struct fw_ri_isgl isgl_src[0]; 1443 } u; 1444 #endif 1445 }; 1446 1447 struct fw_ri_send_wr { 1448 __u8 opcode; 1449 __u8 flags; 1450 __u16 wrid; 1451 __u8 r1[3]; 1452 __u8 len16; 1453 __be32 sendop_pkd; 1454 __be32 stag_inv; 1455 __be32 plen; 1456 __be32 r3; 1457 __be64 r4; 1458 #ifndef C99_NOT_SUPPORTED 1459 union { 1460 struct fw_ri_immd immd_src[0]; 1461 struct fw_ri_isgl isgl_src[0]; 1462 } u; 1463 #endif 1464 }; 1465 1466 #define S_FW_RI_SEND_WR_SENDOP 0 1467 #define M_FW_RI_SEND_WR_SENDOP 0xf 1468 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 1469 #define G_FW_RI_SEND_WR_SENDOP(x) \ 1470 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 1471 1472 struct fw_ri_rdma_read_wr { 1473 __u8 opcode; 1474 __u8 flags; 1475 __u16 wrid; 1476 __u8 r1[3]; 1477 __u8 len16; 1478 __be64 r2; 1479 __be32 stag_sink; 1480 __be32 to_sink_hi; 1481 __be32 to_sink_lo; 1482 __be32 plen; 1483 __be32 stag_src; 1484 __be32 to_src_hi; 1485 __be32 to_src_lo; 1486 __be32 r5; 1487 }; 1488 1489 struct fw_ri_recv_wr { 1490 __u8 opcode; 1491 __u8 r1; 1492 __u16 wrid; 1493 __u8 r2[3]; 1494 __u8 len16; 1495 struct fw_ri_isgl isgl; 1496 }; 1497 1498 struct fw_ri_bind_mw_wr { 1499 __u8 opcode; 1500 __u8 flags; 1501 __u16 wrid; 1502 __u8 r1[3]; 1503 __u8 len16; 1504 __u8 qpbinde_to_dcacpu; 1505 __u8 pgsz_shift; 1506 __u8 addr_type; 1507 __u8 mem_perms; 1508 __be32 stag_mr; 1509 __be32 stag_mw; 1510 __be32 r3; 1511 __be64 len_mw; 1512 __be64 va_fbo; 1513 __be64 r4; 1514 }; 1515 1516 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 1517 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 1518 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 1519 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 1520 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 1521 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 1522 1523 #define S_FW_RI_BIND_MW_WR_NS 5 1524 #define M_FW_RI_BIND_MW_WR_NS 0x1 1525 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 1526 #define G_FW_RI_BIND_MW_WR_NS(x) \ 1527 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 1528 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 1529 1530 #define S_FW_RI_BIND_MW_WR_DCACPU 0 1531 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 1532 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 1533 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 1534 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 1535 1536 struct fw_ri_fr_nsmr_wr { 1537 __u8 opcode; 1538 __u8 flags; 1539 __u16 wrid; 1540 __u8 r1[3]; 1541 __u8 len16; 1542 __u8 qpbinde_to_dcacpu; 1543 __u8 pgsz_shift; 1544 __u8 addr_type; 1545 __u8 mem_perms; 1546 __be32 stag; 1547 __be32 len_hi; 1548 __be32 len_lo; 1549 __be32 va_hi; 1550 __be32 va_lo_fbo; 1551 }; 1552 1553 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 1554 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 1555 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 1556 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 1557 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 1558 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 1559 1560 #define S_FW_RI_FR_NSMR_WR_NS 5 1561 #define M_FW_RI_FR_NSMR_WR_NS 0x1 1562 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 1563 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 1564 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 1565 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 1566 1567 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 1568 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 1569 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 1570 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 1571 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 1572 1573 struct fw_ri_inv_lstag_wr { 1574 __u8 opcode; 1575 __u8 flags; 1576 __u16 wrid; 1577 __u8 r1[3]; 1578 __u8 len16; 1579 __be32 r2; 1580 __be32 stag_inv; 1581 }; 1582 1583 struct fw_ri_send_immediate_wr { 1584 __u8 opcode; 1585 __u8 flags; 1586 __u16 wrid; 1587 __u8 r1[3]; 1588 __u8 len16; 1589 __be32 sendimmop_pkd; 1590 __be32 r3; 1591 __be32 plen; 1592 __be32 r4; 1593 __be64 r5; 1594 #ifndef C99_NOT_SUPPORTED 1595 struct fw_ri_immd immd_src[0]; 1596 #endif 1597 }; 1598 1599 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 1600 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 1601 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1602 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1603 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 1604 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 1605 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 1606 1607 enum fw_ri_atomic_op { 1608 FW_RI_ATOMIC_OP_FETCHADD, 1609 FW_RI_ATOMIC_OP_SWAP, 1610 FW_RI_ATOMIC_OP_CMDSWAP, 1611 }; 1612 1613 struct fw_ri_atomic_wr { 1614 __u8 opcode; 1615 __u8 flags; 1616 __u16 wrid; 1617 __u8 r1[3]; 1618 __u8 len16; 1619 __be32 atomicop_pkd; 1620 __be64 r3; 1621 __be32 aopcode_pkd; 1622 __be32 reqid; 1623 __be32 stag; 1624 __be32 to_hi; 1625 __be32 to_lo; 1626 __be32 addswap_data_hi; 1627 __be32 addswap_data_lo; 1628 __be32 addswap_mask_hi; 1629 __be32 addswap_mask_lo; 1630 __be32 compare_data_hi; 1631 __be32 compare_data_lo; 1632 __be32 compare_mask_hi; 1633 __be32 compare_mask_lo; 1634 __be32 r5; 1635 }; 1636 1637 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 1638 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 1639 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 1640 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 1641 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 1642 1643 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 1644 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 1645 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 1646 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 1647 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 1648 1649 enum fw_ri_type { 1650 FW_RI_TYPE_INIT, 1651 FW_RI_TYPE_FINI, 1652 FW_RI_TYPE_TERMINATE 1653 }; 1654 1655 enum fw_ri_init_p2ptype { 1656 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 1657 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 1658 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 1659 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 1660 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 1661 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 1662 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 1663 }; 1664 1665 struct fw_ri_wr { 1666 __be32 op_compl; 1667 __be32 flowid_len16; 1668 __u64 cookie; 1669 union fw_ri { 1670 struct fw_ri_init { 1671 __u8 type; 1672 __u8 mpareqbit_p2ptype; 1673 __u8 r4[2]; 1674 __u8 mpa_attrs; 1675 __u8 qp_caps; 1676 __be16 nrqe; 1677 __be32 pdid; 1678 __be32 qpid; 1679 __be32 sq_eqid; 1680 __be32 rq_eqid; 1681 __be32 scqid; 1682 __be32 rcqid; 1683 __be32 ord_max; 1684 __be32 ird_max; 1685 __be32 iss; 1686 __be32 irs; 1687 __be32 hwrqsize; 1688 __be32 hwrqaddr; 1689 __be64 r5; 1690 union fw_ri_init_p2p { 1691 struct fw_ri_rdma_write_wr write; 1692 struct fw_ri_rdma_read_wr read; 1693 struct fw_ri_send_wr send; 1694 } u; 1695 } init; 1696 struct fw_ri_fini { 1697 __u8 type; 1698 __u8 r3[7]; 1699 __be64 r4; 1700 } fini; 1701 struct fw_ri_terminate { 1702 __u8 type; 1703 __u8 r3[3]; 1704 __be32 immdlen; 1705 __u8 termmsg[40]; 1706 } terminate; 1707 } u; 1708 }; 1709 1710 #define S_FW_RI_WR_MPAREQBIT 7 1711 #define M_FW_RI_WR_MPAREQBIT 0x1 1712 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 1713 #define G_FW_RI_WR_MPAREQBIT(x) \ 1714 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 1715 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 1716 1717 #define S_FW_RI_WR_0BRRBIT 6 1718 #define M_FW_RI_WR_0BRRBIT 0x1 1719 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 1720 #define G_FW_RI_WR_0BRRBIT(x) \ 1721 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 1722 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 1723 1724 #define S_FW_RI_WR_P2PTYPE 0 1725 #define M_FW_RI_WR_P2PTYPE 0xf 1726 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 1727 #define G_FW_RI_WR_P2PTYPE(x) \ 1728 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 1729 1730 /****************************************************************************** 1731 * F O i S C S I W O R K R E Q U E S T s 1732 *********************************************/ 1733 1734 #define FW_FOISCSI_NAME_MAX_LEN 224 1735 #define FW_FOISCSI_ALIAS_MAX_LEN 224 1736 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 1737 #define FW_FOISCSI_INIT_NODE_MAX 8 1738 1739 enum fw_chnet_ifconf_wr_subop { 1740 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 1741 1742 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 1743 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 1744 1745 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 1746 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 1747 1748 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 1749 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 1750 1751 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 1752 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 1753 1754 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 1755 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 1756 1757 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 1758 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 1759 1760 FW_CHNET_IFCONF_WR_SUBOP_MAX, 1761 }; 1762 1763 struct fw_chnet_ifconf_wr { 1764 __be32 op_compl; 1765 __be32 flowid_len16; 1766 __be64 cookie; 1767 __be32 if_flowid; 1768 __u8 idx; 1769 __u8 subop; 1770 __u8 retval; 1771 __u8 r2; 1772 __be64 r3; 1773 struct fw_chnet_ifconf_params { 1774 __be32 r0; 1775 __be16 vlanid; 1776 __be16 mtu; 1777 union fw_chnet_ifconf_addr_type { 1778 struct fw_chnet_ifconf_ipv4 { 1779 __be32 addr; 1780 __be32 mask; 1781 __be32 router; 1782 __be32 r0; 1783 __be64 r1; 1784 } ipv4; 1785 struct fw_chnet_ifconf_ipv6 { 1786 __be64 linklocal_lo; 1787 __be64 linklocal_hi; 1788 __be64 router_hi; 1789 __be64 router_lo; 1790 __be64 aconf_hi; 1791 __be64 aconf_lo; 1792 __be64 linklocal_aconf_hi; 1793 __be64 linklocal_aconf_lo; 1794 __be64 router_aconf_hi; 1795 __be64 router_aconf_lo; 1796 __be64 r0; 1797 } ipv6; 1798 } in_attr; 1799 } param; 1800 }; 1801 1802 enum fw_foiscsi_node_type { 1803 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 1804 FW_FOISCSI_NODE_TYPE_TARGET, 1805 }; 1806 1807 enum fw_foiscsi_session_type { 1808 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 1809 FW_FOISCSI_SESSION_TYPE_NORMAL, 1810 }; 1811 1812 enum fw_foiscsi_auth_policy { 1813 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 1814 FW_FOISCSI_AUTH_POLICY_MUTUAL, 1815 }; 1816 1817 enum fw_foiscsi_auth_method { 1818 FW_FOISCSI_AUTH_METHOD_NONE = 0, 1819 FW_FOISCSI_AUTH_METHOD_CHAP, 1820 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 1821 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 1822 }; 1823 1824 enum fw_foiscsi_digest_type { 1825 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 1826 FW_FOISCSI_DIGEST_TYPE_CRC32, 1827 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 1828 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 1829 }; 1830 1831 enum fw_foiscsi_wr_subop { 1832 FW_FOISCSI_WR_SUBOP_ADD = 1, 1833 FW_FOISCSI_WR_SUBOP_DEL = 2, 1834 FW_FOISCSI_WR_SUBOP_MOD = 4, 1835 }; 1836 1837 enum fw_foiscsi_ctrl_state { 1838 FW_FOISCSI_CTRL_STATE_FREE = 0, 1839 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 1840 FW_FOISCSI_CTRL_STATE_FAILED, 1841 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 1842 FW_FOISCSI_CTRL_STATE_REDIRECT, 1843 }; 1844 1845 struct fw_rdev_wr { 1846 __be32 op_to_immdlen; 1847 __be32 alloc_to_len16; 1848 __be64 cookie; 1849 __u8 protocol; 1850 __u8 event_cause; 1851 __u8 cur_state; 1852 __u8 prev_state; 1853 __be32 flags_to_assoc_flowid; 1854 union rdev_entry { 1855 struct fcoe_rdev_entry { 1856 __be32 flowid; 1857 __u8 protocol; 1858 __u8 event_cause; 1859 __u8 flags; 1860 __u8 rjt_reason; 1861 __u8 cur_login_st; 1862 __u8 prev_login_st; 1863 __be16 rcv_fr_sz; 1864 __u8 rd_xfer_rdy_to_rport_type; 1865 __u8 vft_to_qos; 1866 __u8 org_proc_assoc_to_acc_rsp_code; 1867 __u8 enh_disc_to_tgt; 1868 __u8 wwnn[8]; 1869 __u8 wwpn[8]; 1870 __be16 iqid; 1871 __u8 fc_oui[3]; 1872 __u8 r_id[3]; 1873 } fcoe_rdev; 1874 struct iscsi_rdev_entry { 1875 __be32 flowid; 1876 __u8 protocol; 1877 __u8 event_cause; 1878 __u8 flags; 1879 __u8 r3; 1880 __be16 iscsi_opts; 1881 __be16 tcp_opts; 1882 __be16 ip_opts; 1883 __be16 max_rcv_len; 1884 __be16 max_snd_len; 1885 __be16 first_brst_len; 1886 __be16 max_brst_len; 1887 __be16 r4; 1888 __be16 def_time2wait; 1889 __be16 def_time2ret; 1890 __be16 nop_out_intrvl; 1891 __be16 non_scsi_to; 1892 __be16 isid; 1893 __be16 tsid; 1894 __be16 port; 1895 __be16 tpgt; 1896 __u8 r5[6]; 1897 __be16 iqid; 1898 } iscsi_rdev; 1899 } u; 1900 }; 1901 1902 #define S_FW_RDEV_WR_IMMDLEN 0 1903 #define M_FW_RDEV_WR_IMMDLEN 0xff 1904 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 1905 #define G_FW_RDEV_WR_IMMDLEN(x) \ 1906 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 1907 1908 #define S_FW_RDEV_WR_ALLOC 31 1909 #define M_FW_RDEV_WR_ALLOC 0x1 1910 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 1911 #define G_FW_RDEV_WR_ALLOC(x) \ 1912 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 1913 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 1914 1915 #define S_FW_RDEV_WR_FREE 30 1916 #define M_FW_RDEV_WR_FREE 0x1 1917 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 1918 #define G_FW_RDEV_WR_FREE(x) \ 1919 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 1920 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 1921 1922 #define S_FW_RDEV_WR_MODIFY 29 1923 #define M_FW_RDEV_WR_MODIFY 0x1 1924 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 1925 #define G_FW_RDEV_WR_MODIFY(x) \ 1926 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 1927 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 1928 1929 #define S_FW_RDEV_WR_FLOWID 8 1930 #define M_FW_RDEV_WR_FLOWID 0xfffff 1931 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 1932 #define G_FW_RDEV_WR_FLOWID(x) \ 1933 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 1934 1935 #define S_FW_RDEV_WR_LEN16 0 1936 #define M_FW_RDEV_WR_LEN16 0xff 1937 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 1938 #define G_FW_RDEV_WR_LEN16(x) \ 1939 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 1940 1941 #define S_FW_RDEV_WR_FLAGS 24 1942 #define M_FW_RDEV_WR_FLAGS 0xff 1943 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 1944 #define G_FW_RDEV_WR_FLAGS(x) \ 1945 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 1946 1947 #define S_FW_RDEV_WR_GET_NEXT 20 1948 #define M_FW_RDEV_WR_GET_NEXT 0xf 1949 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 1950 #define G_FW_RDEV_WR_GET_NEXT(x) \ 1951 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 1952 1953 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 1954 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 1955 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 1956 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 1957 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 1958 1959 #define S_FW_RDEV_WR_RJT 7 1960 #define M_FW_RDEV_WR_RJT 0x1 1961 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 1962 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 1963 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 1964 1965 #define S_FW_RDEV_WR_REASON 0 1966 #define M_FW_RDEV_WR_REASON 0x7f 1967 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 1968 #define G_FW_RDEV_WR_REASON(x) \ 1969 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 1970 1971 #define S_FW_RDEV_WR_RD_XFER_RDY 7 1972 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 1973 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 1974 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 1975 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 1976 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 1977 1978 #define S_FW_RDEV_WR_WR_XFER_RDY 6 1979 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 1980 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 1981 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 1982 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 1983 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 1984 1985 #define S_FW_RDEV_WR_FC_SP 5 1986 #define M_FW_RDEV_WR_FC_SP 0x1 1987 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 1988 #define G_FW_RDEV_WR_FC_SP(x) \ 1989 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 1990 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 1991 1992 #define S_FW_RDEV_WR_RPORT_TYPE 0 1993 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 1994 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 1995 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 1996 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 1997 1998 #define S_FW_RDEV_WR_VFT 7 1999 #define M_FW_RDEV_WR_VFT 0x1 2000 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 2001 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 2002 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 2003 2004 #define S_FW_RDEV_WR_NPIV 6 2005 #define M_FW_RDEV_WR_NPIV 0x1 2006 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 2007 #define G_FW_RDEV_WR_NPIV(x) \ 2008 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 2009 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 2010 2011 #define S_FW_RDEV_WR_CLASS 4 2012 #define M_FW_RDEV_WR_CLASS 0x3 2013 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 2014 #define G_FW_RDEV_WR_CLASS(x) \ 2015 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 2016 2017 #define S_FW_RDEV_WR_SEQ_DEL 3 2018 #define M_FW_RDEV_WR_SEQ_DEL 0x1 2019 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 2020 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 2021 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 2022 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 2023 2024 #define S_FW_RDEV_WR_PRIO_PREEMP 2 2025 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 2026 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 2027 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 2028 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 2029 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 2030 2031 #define S_FW_RDEV_WR_PREF 1 2032 #define M_FW_RDEV_WR_PREF 0x1 2033 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 2034 #define G_FW_RDEV_WR_PREF(x) \ 2035 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 2036 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 2037 2038 #define S_FW_RDEV_WR_QOS 0 2039 #define M_FW_RDEV_WR_QOS 0x1 2040 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 2041 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 2042 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 2043 2044 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 2045 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 2046 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 2047 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 2048 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 2049 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 2050 2051 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 2052 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 2053 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 2054 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 2055 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 2056 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 2057 2058 #define S_FW_RDEV_WR_IMAGE_PAIR 5 2059 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 2060 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 2061 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 2062 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 2063 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 2064 2065 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 2066 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 2067 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 2068 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 2069 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 2070 2071 #define S_FW_RDEV_WR_ENH_DISC 7 2072 #define M_FW_RDEV_WR_ENH_DISC 0x1 2073 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 2074 #define G_FW_RDEV_WR_ENH_DISC(x) \ 2075 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 2076 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 2077 2078 #define S_FW_RDEV_WR_REC 6 2079 #define M_FW_RDEV_WR_REC 0x1 2080 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 2081 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 2082 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 2083 2084 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 2085 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 2086 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 2087 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 2088 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 2089 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 2090 2091 #define S_FW_RDEV_WR_RETRY 4 2092 #define M_FW_RDEV_WR_RETRY 0x1 2093 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 2094 #define G_FW_RDEV_WR_RETRY(x) \ 2095 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 2096 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 2097 2098 #define S_FW_RDEV_WR_CONF_CMPL 3 2099 #define M_FW_RDEV_WR_CONF_CMPL 0x1 2100 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 2101 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 2102 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 2103 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 2104 2105 #define S_FW_RDEV_WR_DATA_OVLY 2 2106 #define M_FW_RDEV_WR_DATA_OVLY 0x1 2107 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 2108 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 2109 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 2110 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 2111 2112 #define S_FW_RDEV_WR_INI 1 2113 #define M_FW_RDEV_WR_INI 0x1 2114 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 2115 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 2116 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 2117 2118 #define S_FW_RDEV_WR_TGT 0 2119 #define M_FW_RDEV_WR_TGT 0x1 2120 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 2121 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 2122 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 2123 2124 struct fw_foiscsi_node_wr { 2125 __be32 op_to_immdlen; 2126 __be32 flowid_len16; 2127 __u64 cookie; 2128 __u8 subop; 2129 __u8 status; 2130 __u8 alias_len; 2131 __u8 iqn_len; 2132 __be32 node_flowid; 2133 __be16 nodeid; 2134 __be16 login_retry; 2135 __be16 retry_timeout; 2136 __be16 r3; 2137 __u8 iqn[224]; 2138 __u8 alias[224]; 2139 }; 2140 2141 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 2142 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 2143 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 2144 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 2145 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 2146 2147 struct fw_foiscsi_ctrl_wr { 2148 __be32 op_compl; 2149 __be32 flowid_len16; 2150 __u64 cookie; 2151 __u8 subop; 2152 __u8 status; 2153 __u8 ctrl_state; 2154 __u8 io_state; 2155 __be32 node_id; 2156 __be32 ctrl_id; 2157 __be32 io_id; 2158 struct fw_foiscsi_sess_attr { 2159 __be32 sess_type_to_erl; 2160 __be16 max_conn; 2161 __be16 max_r2t; 2162 __be16 time2wait; 2163 __be16 time2retain; 2164 __be32 max_burst; 2165 __be32 first_burst; 2166 __be32 r1; 2167 } sess_attr; 2168 struct fw_foiscsi_conn_attr { 2169 __be32 hdigest_to_ddp_pgsz; 2170 __be32 max_rcv_dsl; 2171 __be32 ping_tmo; 2172 __be16 dst_port; 2173 __be16 src_port; 2174 union fw_foiscsi_conn_attr_addr { 2175 struct fw_foiscsi_conn_attr_ipv6 { 2176 __be64 dst_addr[2]; 2177 __be64 src_addr[2]; 2178 } ipv6_addr; 2179 struct fw_foiscsi_conn_attr_ipv4 { 2180 __be32 dst_addr; 2181 __be32 src_addr; 2182 } ipv4_addr; 2183 } u; 2184 } conn_attr; 2185 __u8 tgt_name_len; 2186 __u8 r3[7]; 2187 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 2188 }; 2189 2190 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 2191 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 2192 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2193 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2194 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 2195 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 2196 2197 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 2198 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 2199 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2200 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2201 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 2202 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 2203 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 2204 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 2205 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 2206 2207 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 2208 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 2209 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2210 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2211 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 2212 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 2213 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 2214 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 2215 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 2216 2217 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 2218 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 2219 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2220 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2221 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 2222 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 2223 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 2224 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 2225 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 2226 2227 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 2228 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 2229 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2230 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2231 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 2232 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 2233 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 2234 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 2235 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 2236 2237 #define S_FW_FOISCSI_CTRL_WR_ERL 24 2238 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 2239 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 2240 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 2241 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 2242 2243 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 2244 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 2245 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 2246 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 2247 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 2248 2249 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 2250 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 2251 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 2252 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 2253 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 2254 2255 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 2256 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 2257 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2258 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2259 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 2260 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 2261 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 2262 2263 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 2264 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 2265 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2266 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2267 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 2268 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 2269 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 2270 2271 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 2272 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 2273 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2274 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2275 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 2276 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 2277 2278 struct fw_foiscsi_chap_wr { 2279 __be32 op_compl; 2280 __be32 flowid_len16; 2281 __u64 cookie; 2282 __u8 status; 2283 __u8 id_len; 2284 __u8 sec_len; 2285 __u8 node_type; 2286 __be16 node_id; 2287 __u8 r3[2]; 2288 __u8 chap_id[FW_FOISCSI_NAME_MAX_LEN]; 2289 __u8 chap_sec[FW_FOISCSI_CHAP_SEC_MAX_LEN]; 2290 }; 2291 2292 /****************************************************************************** 2293 * F O F C O E W O R K R E Q U E S T s 2294 *******************************************/ 2295 2296 struct fw_fcoe_els_ct_wr { 2297 __be32 op_immdlen; 2298 __be32 flowid_len16; 2299 __be64 cookie; 2300 __be16 iqid; 2301 __u8 tmo_val; 2302 __u8 els_ct_type; 2303 __u8 ctl_pri; 2304 __u8 cp_en_class; 2305 __be16 xfer_cnt; 2306 __u8 fl_to_sp; 2307 __u8 l_id[3]; 2308 __u8 r5; 2309 __u8 r_id[3]; 2310 __be64 rsp_dmaaddr; 2311 __be32 rsp_dmalen; 2312 __be32 r6; 2313 }; 2314 2315 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 2316 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 2317 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 2318 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 2319 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 2320 2321 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 2322 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 2323 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 2324 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 2325 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 2326 2327 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 2328 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 2329 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 2330 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 2331 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 2332 2333 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 2334 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 2335 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 2336 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 2337 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 2338 2339 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 2340 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 2341 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 2342 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 2343 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 2344 2345 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 2346 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 2347 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 2348 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 2349 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 2350 2351 #define S_FW_FCOE_ELS_CT_WR_FL 2 2352 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 2353 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 2354 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 2355 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 2356 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 2357 2358 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 2359 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 2360 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 2361 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 2362 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 2363 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 2364 2365 #define S_FW_FCOE_ELS_CT_WR_SP 0 2366 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 2367 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 2368 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 2369 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 2370 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 2371 2372 /****************************************************************************** 2373 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 2374 *****************************************************************************/ 2375 2376 struct fw_scsi_write_wr { 2377 __be32 op_immdlen; 2378 __be32 flowid_len16; 2379 __be64 cookie; 2380 __be16 iqid; 2381 __u8 tmo_val; 2382 __u8 use_xfer_cnt; 2383 union fw_scsi_write_priv { 2384 struct fcoe_write_priv { 2385 __u8 ctl_pri; 2386 __u8 cp_en_class; 2387 __u8 r3_lo[2]; 2388 } fcoe; 2389 struct iscsi_write_priv { 2390 __u8 r3[4]; 2391 } iscsi; 2392 } u; 2393 __be32 xfer_cnt; 2394 __be32 ini_xfer_cnt; 2395 __be64 rsp_dmaaddr; 2396 __be32 rsp_dmalen; 2397 __be32 r4; 2398 }; 2399 2400 #define S_FW_SCSI_WRITE_WR_OPCODE 24 2401 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 2402 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 2403 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 2404 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 2405 2406 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 2407 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 2408 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 2409 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 2410 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 2411 2412 #define S_FW_SCSI_WRITE_WR_FLOWID 8 2413 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 2414 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 2415 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 2416 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 2417 2418 #define S_FW_SCSI_WRITE_WR_LEN16 0 2419 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 2420 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 2421 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 2422 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 2423 2424 #define S_FW_SCSI_WRITE_WR_CP_EN 6 2425 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 2426 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 2427 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 2428 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 2429 2430 #define S_FW_SCSI_WRITE_WR_CLASS 4 2431 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 2432 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 2433 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 2434 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 2435 2436 struct fw_scsi_read_wr { 2437 __be32 op_immdlen; 2438 __be32 flowid_len16; 2439 __be64 cookie; 2440 __be16 iqid; 2441 __u8 tmo_val; 2442 __u8 use_xfer_cnt; 2443 union fw_scsi_read_priv { 2444 struct fcoe_read_priv { 2445 __u8 ctl_pri; 2446 __u8 cp_en_class; 2447 __u8 r3_lo[2]; 2448 } fcoe; 2449 struct iscsi_read_priv { 2450 __u8 r3[4]; 2451 } iscsi; 2452 } u; 2453 __be32 xfer_cnt; 2454 __be32 ini_xfer_cnt; 2455 __be64 rsp_dmaaddr; 2456 __be32 rsp_dmalen; 2457 __be32 r4; 2458 }; 2459 2460 #define S_FW_SCSI_READ_WR_OPCODE 24 2461 #define M_FW_SCSI_READ_WR_OPCODE 0xff 2462 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 2463 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 2464 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 2465 2466 #define S_FW_SCSI_READ_WR_IMMDLEN 0 2467 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 2468 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 2469 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 2470 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 2471 2472 #define S_FW_SCSI_READ_WR_FLOWID 8 2473 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 2474 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 2475 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 2476 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 2477 2478 #define S_FW_SCSI_READ_WR_LEN16 0 2479 #define M_FW_SCSI_READ_WR_LEN16 0xff 2480 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 2481 #define G_FW_SCSI_READ_WR_LEN16(x) \ 2482 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 2483 2484 #define S_FW_SCSI_READ_WR_CP_EN 6 2485 #define M_FW_SCSI_READ_WR_CP_EN 0x3 2486 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 2487 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 2488 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 2489 2490 #define S_FW_SCSI_READ_WR_CLASS 4 2491 #define M_FW_SCSI_READ_WR_CLASS 0x3 2492 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 2493 #define G_FW_SCSI_READ_WR_CLASS(x) \ 2494 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 2495 2496 struct fw_scsi_cmd_wr { 2497 __be32 op_immdlen; 2498 __be32 flowid_len16; 2499 __be64 cookie; 2500 __be16 iqid; 2501 __u8 tmo_val; 2502 __u8 r3; 2503 union fw_scsi_cmd_priv { 2504 struct fcoe_cmd_priv { 2505 __u8 ctl_pri; 2506 __u8 cp_en_class; 2507 __u8 r4_lo[2]; 2508 } fcoe; 2509 struct iscsi_cmd_priv { 2510 __u8 r4[4]; 2511 } iscsi; 2512 } u; 2513 __u8 r5[8]; 2514 __be64 rsp_dmaaddr; 2515 __be32 rsp_dmalen; 2516 __be32 r6; 2517 }; 2518 2519 #define S_FW_SCSI_CMD_WR_OPCODE 24 2520 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 2521 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 2522 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 2523 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 2524 2525 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 2526 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 2527 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 2528 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 2529 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 2530 2531 #define S_FW_SCSI_CMD_WR_FLOWID 8 2532 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 2533 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 2534 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 2535 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 2536 2537 #define S_FW_SCSI_CMD_WR_LEN16 0 2538 #define M_FW_SCSI_CMD_WR_LEN16 0xff 2539 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 2540 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 2541 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 2542 2543 #define S_FW_SCSI_CMD_WR_CP_EN 6 2544 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 2545 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 2546 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 2547 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 2548 2549 #define S_FW_SCSI_CMD_WR_CLASS 4 2550 #define M_FW_SCSI_CMD_WR_CLASS 0x3 2551 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 2552 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 2553 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 2554 2555 struct fw_scsi_abrt_cls_wr { 2556 __be32 op_immdlen; 2557 __be32 flowid_len16; 2558 __be64 cookie; 2559 __be16 iqid; 2560 __u8 tmo_val; 2561 __u8 sub_opcode_to_chk_all_io; 2562 __u8 r3[4]; 2563 __be64 t_cookie; 2564 }; 2565 2566 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 2567 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 2568 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 2569 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 2570 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 2571 2572 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 2573 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 2574 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2575 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2576 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 2577 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 2578 2579 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 2580 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 2581 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 2582 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 2583 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 2584 2585 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 2586 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 2587 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 2588 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 2589 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 2590 2591 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 2592 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 2593 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2594 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2595 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 2596 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 2597 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 2598 2599 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 2600 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 2601 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 2602 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 2603 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 2604 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 2605 2606 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 2607 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 2608 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2609 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2610 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 2611 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 2612 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 2613 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 2614 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 2615 2616 struct fw_scsi_tgt_acc_wr { 2617 __be32 op_immdlen; 2618 __be32 flowid_len16; 2619 __be64 cookie; 2620 __be16 iqid; 2621 __u8 r3; 2622 __u8 use_burst_len; 2623 union fw_scsi_tgt_acc_priv { 2624 struct fcoe_tgt_acc_priv { 2625 __u8 ctl_pri; 2626 __u8 cp_en_class; 2627 __u8 r4_lo[2]; 2628 } fcoe; 2629 struct iscsi_tgt_acc_priv { 2630 __u8 r4[4]; 2631 } iscsi; 2632 } u; 2633 __be32 burst_len; 2634 __be32 rel_off; 2635 __be64 r5; 2636 __be32 r6; 2637 __be32 tot_xfer_len; 2638 }; 2639 2640 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 2641 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 2642 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 2643 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 2644 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 2645 2646 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 2647 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 2648 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2649 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 2650 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 2651 2652 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 2653 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 2654 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 2655 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 2656 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 2657 2658 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 2659 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 2660 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 2661 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 2662 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 2663 2664 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 2665 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 2666 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 2667 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 2668 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 2669 2670 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 2671 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 2672 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 2673 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 2674 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 2675 2676 struct fw_scsi_tgt_xmit_wr { 2677 __be32 op_immdlen; 2678 __be32 flowid_len16; 2679 __be64 cookie; 2680 __be16 iqid; 2681 __u8 auto_rsp; 2682 __u8 use_xfer_cnt; 2683 union fw_scsi_tgt_xmit_priv { 2684 struct fcoe_tgt_xmit_priv { 2685 __u8 ctl_pri; 2686 __u8 cp_en_class; 2687 __u8 r3_lo[2]; 2688 } fcoe; 2689 struct iscsi_tgt_xmit_priv { 2690 __u8 r3[4]; 2691 } iscsi; 2692 } u; 2693 __be32 xfer_cnt; 2694 __be32 r4; 2695 __be64 r5; 2696 __be32 r6; 2697 __be32 tot_xfer_len; 2698 }; 2699 2700 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 2701 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 2702 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 2703 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 2704 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 2705 2706 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 2707 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 2708 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2709 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2710 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 2711 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 2712 2713 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 2714 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 2715 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 2716 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 2717 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 2718 2719 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 2720 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 2721 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 2722 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 2723 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 2724 2725 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 2726 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 2727 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 2728 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 2729 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 2730 2731 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 2732 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 2733 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 2734 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 2735 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 2736 2737 struct fw_scsi_tgt_rsp_wr { 2738 __be32 op_immdlen; 2739 __be32 flowid_len16; 2740 __be64 cookie; 2741 __be16 iqid; 2742 __u8 r3[2]; 2743 union fw_scsi_tgt_rsp_priv { 2744 struct fcoe_tgt_rsp_priv { 2745 __u8 ctl_pri; 2746 __u8 cp_en_class; 2747 __u8 r4_lo[2]; 2748 } fcoe; 2749 struct iscsi_tgt_rsp_priv { 2750 __u8 r4[4]; 2751 } iscsi; 2752 } u; 2753 __u8 r5[8]; 2754 }; 2755 2756 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 2757 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 2758 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 2759 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 2760 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 2761 2762 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 2763 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 2764 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2765 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 2766 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 2767 2768 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 2769 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 2770 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 2771 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 2772 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 2773 2774 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 2775 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 2776 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 2777 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 2778 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 2779 2780 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 2781 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 2782 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 2783 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 2784 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 2785 2786 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 2787 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 2788 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 2789 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 2790 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 2791 2792 /****************************************************************************** 2793 * C O M M A N D s 2794 *********************/ 2795 2796 /* 2797 * The maximum length of time, in miliseconds, that we expect any firmware 2798 * command to take to execute and return a reply to the host. The RESET 2799 * and INITIALIZE commands can take a fair amount of time to execute but 2800 * most execute in far less time than this maximum. This constant is used 2801 * by host software to determine how long to wait for a firmware command 2802 * reply before declaring the firmware as dead/unreachable ... 2803 */ 2804 #define FW_CMD_MAX_TIMEOUT 10000 2805 2806 /* 2807 * If a host driver does a HELLO and discovers that there's already a MASTER 2808 * selected, we may have to wait for that MASTER to finish issuing RESET, 2809 * configuration and INITIALIZE commands. Also, there's a possibility that 2810 * our own HELLO may get lost if it happens right as the MASTER is issuign a 2811 * RESET command, so we need to be willing to make a few retries of our HELLO. 2812 */ 2813 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 2814 #define FW_CMD_HELLO_RETRIES 3 2815 2816 enum fw_cmd_opcodes { 2817 FW_LDST_CMD = 0x01, 2818 FW_RESET_CMD = 0x03, 2819 FW_HELLO_CMD = 0x04, 2820 FW_BYE_CMD = 0x05, 2821 FW_INITIALIZE_CMD = 0x06, 2822 FW_CAPS_CONFIG_CMD = 0x07, 2823 FW_PARAMS_CMD = 0x08, 2824 FW_PFVF_CMD = 0x09, 2825 FW_IQ_CMD = 0x10, 2826 FW_EQ_MNGT_CMD = 0x11, 2827 FW_EQ_ETH_CMD = 0x12, 2828 FW_EQ_CTRL_CMD = 0x13, 2829 FW_EQ_OFLD_CMD = 0x21, 2830 FW_VI_CMD = 0x14, 2831 FW_VI_MAC_CMD = 0x15, 2832 FW_VI_RXMODE_CMD = 0x16, 2833 FW_VI_ENABLE_CMD = 0x17, 2834 FW_VI_STATS_CMD = 0x1a, 2835 FW_ACL_MAC_CMD = 0x18, 2836 FW_ACL_VLAN_CMD = 0x19, 2837 FW_PORT_CMD = 0x1b, 2838 FW_PORT_STATS_CMD = 0x1c, 2839 FW_PORT_LB_STATS_CMD = 0x1d, 2840 FW_PORT_TRACE_CMD = 0x1e, 2841 FW_PORT_TRACE_MMAP_CMD = 0x1f, 2842 FW_RSS_IND_TBL_CMD = 0x20, 2843 FW_RSS_GLB_CONFIG_CMD = 0x22, 2844 FW_RSS_VI_CONFIG_CMD = 0x23, 2845 FW_SCHED_CMD = 0x24, 2846 FW_DEVLOG_CMD = 0x25, 2847 FW_WATCHDOG_CMD = 0x27, 2848 FW_CLIP_CMD = 0x28, 2849 FW_CHNET_IFACE_CMD = 0x26, 2850 FW_FCOE_RES_INFO_CMD = 0x31, 2851 FW_FCOE_LINK_CMD = 0x32, 2852 FW_FCOE_VNP_CMD = 0x33, 2853 FW_FCOE_SPARAMS_CMD = 0x35, 2854 FW_FCOE_STATS_CMD = 0x37, 2855 FW_FCOE_FCF_CMD = 0x38, 2856 FW_LASTC2E_CMD = 0x40, 2857 FW_ERROR_CMD = 0x80, 2858 FW_DEBUG_CMD = 0x81, 2859 }; 2860 2861 enum fw_cmd_cap { 2862 FW_CMD_CAP_PF = 0x01, 2863 FW_CMD_CAP_DMAQ = 0x02, 2864 FW_CMD_CAP_PORT = 0x04, 2865 FW_CMD_CAP_PORTPROMISC = 0x08, 2866 FW_CMD_CAP_PORTSTATS = 0x10, 2867 FW_CMD_CAP_VF = 0x80, 2868 }; 2869 2870 /* 2871 * Generic command header flit0 2872 */ 2873 struct fw_cmd_hdr { 2874 __be32 hi; 2875 __be32 lo; 2876 }; 2877 2878 #define S_FW_CMD_OP 24 2879 #define M_FW_CMD_OP 0xff 2880 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 2881 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 2882 2883 #define S_FW_CMD_REQUEST 23 2884 #define M_FW_CMD_REQUEST 0x1 2885 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 2886 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 2887 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 2888 2889 #define S_FW_CMD_READ 22 2890 #define M_FW_CMD_READ 0x1 2891 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 2892 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 2893 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 2894 2895 #define S_FW_CMD_WRITE 21 2896 #define M_FW_CMD_WRITE 0x1 2897 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 2898 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 2899 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 2900 2901 #define S_FW_CMD_EXEC 20 2902 #define M_FW_CMD_EXEC 0x1 2903 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 2904 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 2905 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 2906 2907 #define S_FW_CMD_RAMASK 20 2908 #define M_FW_CMD_RAMASK 0xf 2909 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 2910 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 2911 2912 #define S_FW_CMD_RETVAL 8 2913 #define M_FW_CMD_RETVAL 0xff 2914 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 2915 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 2916 2917 #define S_FW_CMD_LEN16 0 2918 #define M_FW_CMD_LEN16 0xff 2919 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 2920 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 2921 2922 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 2923 2924 /* 2925 * address spaces 2926 */ 2927 enum fw_ldst_addrspc { 2928 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 2929 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 2930 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 2931 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 2932 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 2933 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 2934 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 2935 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 2936 FW_LDST_ADDRSPC_MDIO = 0x0018, 2937 FW_LDST_ADDRSPC_MPS = 0x0020, 2938 FW_LDST_ADDRSPC_FUNC = 0x0028, 2939 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 2940 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, 2941 FW_LDST_ADDRSPC_LE = 0x0030, 2942 }; 2943 2944 /* 2945 * MDIO VSC8634 register access control field 2946 */ 2947 enum fw_ldst_mdio_vsc8634_aid { 2948 FW_LDST_MDIO_VS_STANDARD, 2949 FW_LDST_MDIO_VS_EXTENDED, 2950 FW_LDST_MDIO_VS_GPIO 2951 }; 2952 2953 enum fw_ldst_mps_fid { 2954 FW_LDST_MPS_ATRB, 2955 FW_LDST_MPS_RPLC 2956 }; 2957 2958 enum fw_ldst_func_access_ctl { 2959 FW_LDST_FUNC_ACC_CTL_VIID, 2960 FW_LDST_FUNC_ACC_CTL_FID 2961 }; 2962 2963 enum fw_ldst_func_mod_index { 2964 FW_LDST_FUNC_MPS 2965 }; 2966 2967 struct fw_ldst_cmd { 2968 __be32 op_to_addrspace; 2969 __be32 cycles_to_len16; 2970 union fw_ldst { 2971 struct fw_ldst_addrval { 2972 __be32 addr; 2973 __be32 val; 2974 } addrval; 2975 struct fw_ldst_idctxt { 2976 __be32 physid; 2977 __be32 msg_ctxtflush; 2978 __be32 ctxt_data7; 2979 __be32 ctxt_data6; 2980 __be32 ctxt_data5; 2981 __be32 ctxt_data4; 2982 __be32 ctxt_data3; 2983 __be32 ctxt_data2; 2984 __be32 ctxt_data1; 2985 __be32 ctxt_data0; 2986 } idctxt; 2987 struct fw_ldst_mdio { 2988 __be16 paddr_mmd; 2989 __be16 raddr; 2990 __be16 vctl; 2991 __be16 rval; 2992 } mdio; 2993 struct fw_ldst_mps { 2994 __be16 fid_ctl; 2995 __be16 rplcpf_pkd; 2996 __be32 rplc127_96; 2997 __be32 rplc95_64; 2998 __be32 rplc63_32; 2999 __be32 rplc31_0; 3000 __be32 atrb; 3001 __be16 vlan[16]; 3002 } mps; 3003 struct fw_ldst_func { 3004 __u8 access_ctl; 3005 __u8 mod_index; 3006 __be16 ctl_id; 3007 __be32 offset; 3008 __be64 data0; 3009 __be64 data1; 3010 } func; 3011 struct fw_ldst_pcie { 3012 __u8 ctrl_to_fn; 3013 __u8 bnum; 3014 __u8 r; 3015 __u8 ext_r; 3016 __u8 select_naccess; 3017 __u8 pcie_fn; 3018 __be16 nset_pkd; 3019 __be32 data[12]; 3020 } pcie; 3021 struct fw_ldst_i2c { 3022 __u8 pid_pkd; 3023 __u8 base; 3024 __u8 boffset; 3025 __u8 data; 3026 __be32 r9; 3027 } i2c; 3028 struct fw_ldst_le { 3029 __be16 region; 3030 __be16 nval; 3031 __u32 val[12]; 3032 } le; 3033 } u; 3034 }; 3035 3036 #define S_FW_LDST_CMD_ADDRSPACE 0 3037 #define M_FW_LDST_CMD_ADDRSPACE 0xff 3038 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 3039 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 3040 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 3041 3042 #define S_FW_LDST_CMD_CYCLES 16 3043 #define M_FW_LDST_CMD_CYCLES 0xffff 3044 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 3045 #define G_FW_LDST_CMD_CYCLES(x) \ 3046 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 3047 3048 #define S_FW_LDST_CMD_MSG 31 3049 #define M_FW_LDST_CMD_MSG 0x1 3050 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 3051 #define G_FW_LDST_CMD_MSG(x) \ 3052 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 3053 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 3054 3055 #define S_FW_LDST_CMD_CTXTFLUSH 30 3056 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 3057 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 3058 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 3059 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 3060 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 3061 3062 #define S_FW_LDST_CMD_PADDR 8 3063 #define M_FW_LDST_CMD_PADDR 0x1f 3064 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 3065 #define G_FW_LDST_CMD_PADDR(x) \ 3066 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 3067 3068 #define S_FW_LDST_CMD_MMD 0 3069 #define M_FW_LDST_CMD_MMD 0x1f 3070 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 3071 #define G_FW_LDST_CMD_MMD(x) \ 3072 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 3073 3074 #define S_FW_LDST_CMD_FID 15 3075 #define M_FW_LDST_CMD_FID 0x1 3076 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 3077 #define G_FW_LDST_CMD_FID(x) \ 3078 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 3079 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 3080 3081 #define S_FW_LDST_CMD_CTL 0 3082 #define M_FW_LDST_CMD_CTL 0x7fff 3083 #define V_FW_LDST_CMD_CTL(x) ((x) << S_FW_LDST_CMD_CTL) 3084 #define G_FW_LDST_CMD_CTL(x) \ 3085 (((x) >> S_FW_LDST_CMD_CTL) & M_FW_LDST_CMD_CTL) 3086 3087 #define S_FW_LDST_CMD_RPLCPF 0 3088 #define M_FW_LDST_CMD_RPLCPF 0xff 3089 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 3090 #define G_FW_LDST_CMD_RPLCPF(x) \ 3091 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 3092 3093 #define S_FW_LDST_CMD_CTRL 7 3094 #define M_FW_LDST_CMD_CTRL 0x1 3095 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 3096 #define G_FW_LDST_CMD_CTRL(x) \ 3097 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 3098 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 3099 3100 #define S_FW_LDST_CMD_LC 4 3101 #define M_FW_LDST_CMD_LC 0x1 3102 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 3103 #define G_FW_LDST_CMD_LC(x) (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 3104 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 3105 3106 #define S_FW_LDST_CMD_AI 3 3107 #define M_FW_LDST_CMD_AI 0x1 3108 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 3109 #define G_FW_LDST_CMD_AI(x) (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 3110 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 3111 3112 #define S_FW_LDST_CMD_FN 0 3113 #define M_FW_LDST_CMD_FN 0x7 3114 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 3115 #define G_FW_LDST_CMD_FN(x) (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 3116 3117 #define S_FW_LDST_CMD_SELECT 4 3118 #define M_FW_LDST_CMD_SELECT 0xf 3119 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 3120 #define G_FW_LDST_CMD_SELECT(x) \ 3121 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 3122 3123 #define S_FW_LDST_CMD_NACCESS 0 3124 #define M_FW_LDST_CMD_NACCESS 0xf 3125 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 3126 #define G_FW_LDST_CMD_NACCESS(x) \ 3127 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 3128 3129 #define S_FW_LDST_CMD_NSET 14 3130 #define M_FW_LDST_CMD_NSET 0x3 3131 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 3132 #define G_FW_LDST_CMD_NSET(x) \ 3133 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 3134 3135 #define S_FW_LDST_CMD_PID 6 3136 #define M_FW_LDST_CMD_PID 0x3 3137 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 3138 #define G_FW_LDST_CMD_PID(x) \ 3139 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 3140 3141 struct fw_reset_cmd { 3142 __be32 op_to_write; 3143 __be32 retval_len16; 3144 __be32 val; 3145 __be32 halt_pkd; 3146 }; 3147 3148 #define S_FW_RESET_CMD_HALT 31 3149 #define M_FW_RESET_CMD_HALT 0x1 3150 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 3151 #define G_FW_RESET_CMD_HALT(x) \ 3152 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 3153 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 3154 3155 enum { 3156 FW_HELLO_CMD_STAGE_OS = 0, 3157 FW_HELLO_CMD_STAGE_PREOS0 = 1, 3158 FW_HELLO_CMD_STAGE_PREOS1 = 2, 3159 FW_HELLO_CMD_STAGE_POSTOS = 3, 3160 }; 3161 3162 struct fw_hello_cmd { 3163 __be32 op_to_write; 3164 __be32 retval_len16; 3165 __be32 err_to_clearinit; 3166 __be32 fwrev; 3167 }; 3168 3169 #define S_FW_HELLO_CMD_ERR 31 3170 #define M_FW_HELLO_CMD_ERR 0x1 3171 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 3172 #define G_FW_HELLO_CMD_ERR(x) \ 3173 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 3174 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 3175 3176 #define S_FW_HELLO_CMD_INIT 30 3177 #define M_FW_HELLO_CMD_INIT 0x1 3178 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 3179 #define G_FW_HELLO_CMD_INIT(x) \ 3180 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 3181 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 3182 3183 #define S_FW_HELLO_CMD_MASTERDIS 29 3184 #define M_FW_HELLO_CMD_MASTERDIS 0x1 3185 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 3186 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 3187 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 3188 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 3189 3190 #define S_FW_HELLO_CMD_MASTERFORCE 28 3191 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 3192 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 3193 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 3194 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 3195 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 3196 3197 #define S_FW_HELLO_CMD_MBMASTER 24 3198 #define M_FW_HELLO_CMD_MBMASTER 0xf 3199 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 3200 #define G_FW_HELLO_CMD_MBMASTER(x) \ 3201 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 3202 3203 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 3204 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 3205 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 3206 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 3207 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 3208 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 3209 3210 #define S_FW_HELLO_CMD_MBASYNCNOT 20 3211 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 3212 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 3213 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 3214 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 3215 3216 #define S_FW_HELLO_CMD_STAGE 17 3217 #define M_FW_HELLO_CMD_STAGE 0x7 3218 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 3219 #define G_FW_HELLO_CMD_STAGE(x) \ 3220 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 3221 3222 #define S_FW_HELLO_CMD_CLEARINIT 16 3223 #define M_FW_HELLO_CMD_CLEARINIT 0x1 3224 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 3225 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 3226 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 3227 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 3228 3229 struct fw_bye_cmd { 3230 __be32 op_to_write; 3231 __be32 retval_len16; 3232 __be64 r3; 3233 }; 3234 3235 struct fw_initialize_cmd { 3236 __be32 op_to_write; 3237 __be32 retval_len16; 3238 __be64 r3; 3239 }; 3240 3241 enum fw_caps_config_hm { 3242 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 3243 FW_CAPS_CONFIG_HM_PL = 0x00000002, 3244 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 3245 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 3246 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 3247 FW_CAPS_CONFIG_HM_TP = 0x00000020, 3248 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 3249 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 3250 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 3251 FW_CAPS_CONFIG_HM_MC = 0x00000200, 3252 FW_CAPS_CONFIG_HM_LE = 0x00000400, 3253 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 3254 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 3255 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 3256 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 3257 FW_CAPS_CONFIG_HM_MI = 0x00008000, 3258 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 3259 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 3260 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 3261 FW_CAPS_CONFIG_HM_MA = 0x00080000, 3262 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 3263 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 3264 FW_CAPS_CONFIG_HM_UART = 0x00400000, 3265 FW_CAPS_CONFIG_HM_SF = 0x00800000, 3266 }; 3267 3268 /* 3269 * The VF Register Map. 3270 * 3271 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 3272 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 3273 * the Slice to Module Map Table (see below) in the Physical Function Register 3274 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 3275 * and Offset registers in the PF Register Map. The MBDATA base address is 3276 * quite constrained as it determines the Mailbox Data addresses for both PFs 3277 * and VFs, and therefore must fit in both the VF and PF Register Maps without 3278 * overlapping other registers. 3279 */ 3280 #define FW_T4VF_SGE_BASE_ADDR 0x0000 3281 #define FW_T4VF_MPS_BASE_ADDR 0x0100 3282 #define FW_T4VF_PL_BASE_ADDR 0x0200 3283 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 3284 #define FW_T4VF_CIM_BASE_ADDR 0x0300 3285 3286 #define FW_T4VF_REGMAP_START 0x0000 3287 #define FW_T4VF_REGMAP_SIZE 0x0400 3288 3289 enum fw_caps_config_nbm { 3290 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 3291 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 3292 }; 3293 3294 enum fw_caps_config_link { 3295 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 3296 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 3297 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 3298 }; 3299 3300 enum fw_caps_config_switch { 3301 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 3302 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 3303 }; 3304 3305 enum fw_caps_config_nic { 3306 FW_CAPS_CONFIG_NIC = 0x00000001, 3307 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 3308 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 3309 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 3310 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 3311 }; 3312 3313 enum fw_caps_config_toe { 3314 FW_CAPS_CONFIG_TOE = 0x00000001, 3315 }; 3316 3317 enum fw_caps_config_rdma { 3318 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 3319 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 3320 }; 3321 3322 enum fw_caps_config_iscsi { 3323 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 3324 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 3325 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 3326 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 3327 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 3328 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 3329 }; 3330 3331 enum fw_caps_config_fcoe { 3332 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 3333 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 3334 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 3335 }; 3336 3337 enum fw_memtype_cf { 3338 FW_MEMTYPE_CF_EDC0 = 0x0, 3339 FW_MEMTYPE_CF_EDC1 = 0x1, 3340 FW_MEMTYPE_CF_EXTMEM = 0x2, 3341 FW_MEMTYPE_CF_FLASH = 0x4, 3342 FW_MEMTYPE_CF_INTERNAL = 0x5, 3343 }; 3344 3345 struct fw_caps_config_cmd { 3346 __be32 op_to_write; 3347 __be32 cfvalid_to_len16; 3348 __be32 r2; 3349 __be32 hwmbitmap; 3350 __be16 nbmcaps; 3351 __be16 linkcaps; 3352 __be16 switchcaps; 3353 __be16 r3; 3354 __be16 niccaps; 3355 __be16 toecaps; 3356 __be16 rdmacaps; 3357 __be16 r4; 3358 __be16 iscsicaps; 3359 __be16 fcoecaps; 3360 __be32 cfcsum; 3361 __be32 finiver; 3362 __be32 finicsum; 3363 }; 3364 3365 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 3366 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 3367 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 3368 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 3369 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 3370 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 3371 3372 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 3373 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 3374 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3375 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3376 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 3377 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 3378 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 3379 3380 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 3381 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 3382 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3383 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3384 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 3385 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 3386 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 3387 3388 /* 3389 * params command mnemonics 3390 */ 3391 enum fw_params_mnem { 3392 FW_PARAMS_MNEM_DEV = 1, /* device params */ 3393 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 3394 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 3395 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 3396 FW_PARAMS_MNEM_LAST 3397 }; 3398 3399 /* 3400 * device parameters 3401 */ 3402 enum fw_params_param_dev { 3403 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 3404 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 3405 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 3406 * allocated by the device's 3407 * Lookup Engine 3408 */ 3409 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 3410 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 3411 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 3412 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 3413 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 3414 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 3415 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 3416 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 3417 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 3418 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 3419 FW_PARAMS_PARAM_DEV_CF = 0x0D, 3420 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 3421 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 3422 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 3423 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 3424 }; 3425 3426 /* 3427 * physical and virtual function parameters 3428 */ 3429 enum fw_params_param_pfvf { 3430 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 3431 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 3432 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 3433 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 3434 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 3435 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 3436 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 3437 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 3438 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 3439 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 3440 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 3441 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 3442 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 3443 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 3444 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 3445 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 3446 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 3447 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 3448 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 3449 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 3450 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 3451 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 3452 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 3453 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 3454 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 3455 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 3456 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 3457 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 3458 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 3459 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 3460 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 3461 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 3462 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 3463 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 3464 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 3465 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 3466 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 3467 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 3468 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30 3469 }; 3470 3471 /* 3472 * dma queue parameters 3473 */ 3474 enum fw_params_param_dmaq { 3475 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 3476 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 3477 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 3478 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 3479 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 3480 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13 3481 }; 3482 3483 /* 3484 * dev bypass parameters; actions and modes 3485 */ 3486 enum fw_params_param_dev_bypass { 3487 3488 /* actions 3489 */ 3490 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 3491 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 3492 3493 /* modes 3494 */ 3495 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 3496 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 3497 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 3498 }; 3499 3500 enum fw_params_phyfw_actions { 3501 FW_PARAMS_PARAM_PHYFW_DOWNLOAD = 0x00, 3502 FW_PARAMS_PARAM_PHYFW_VERSION = 0x01, 3503 }; 3504 3505 enum fw_params_param_dev_diag { 3506 FW_PARAM_DEV_DIAG_TMP = 0x00, 3507 }; 3508 3509 #define S_FW_PARAMS_MNEM 24 3510 #define M_FW_PARAMS_MNEM 0xff 3511 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 3512 #define G_FW_PARAMS_MNEM(x) \ 3513 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 3514 3515 #define S_FW_PARAMS_PARAM_X 16 3516 #define M_FW_PARAMS_PARAM_X 0xff 3517 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 3518 #define G_FW_PARAMS_PARAM_X(x) \ 3519 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 3520 3521 #define S_FW_PARAMS_PARAM_Y 8 3522 #define M_FW_PARAMS_PARAM_Y 0xff 3523 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 3524 #define G_FW_PARAMS_PARAM_Y(x) \ 3525 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 3526 3527 #define S_FW_PARAMS_PARAM_Z 0 3528 #define M_FW_PARAMS_PARAM_Z 0xff 3529 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 3530 #define G_FW_PARAMS_PARAM_Z(x) \ 3531 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 3532 3533 #define S_FW_PARAMS_PARAM_XYZ 0 3534 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 3535 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 3536 #define G_FW_PARAMS_PARAM_XYZ(x) \ 3537 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 3538 3539 #define S_FW_PARAMS_PARAM_YZ 0 3540 #define M_FW_PARAMS_PARAM_YZ 0xffff 3541 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 3542 #define G_FW_PARAMS_PARAM_YZ(x) \ 3543 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 3544 3545 struct fw_params_cmd { 3546 __be32 op_to_vfn; 3547 __be32 retval_len16; 3548 struct fw_params_param { 3549 __be32 mnem; 3550 __be32 val; 3551 } param[7]; 3552 }; 3553 3554 #define S_FW_PARAMS_CMD_PFN 8 3555 #define M_FW_PARAMS_CMD_PFN 0x7 3556 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 3557 #define G_FW_PARAMS_CMD_PFN(x) \ 3558 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 3559 3560 #define S_FW_PARAMS_CMD_VFN 0 3561 #define M_FW_PARAMS_CMD_VFN 0xff 3562 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 3563 #define G_FW_PARAMS_CMD_VFN(x) \ 3564 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 3565 3566 struct fw_pfvf_cmd { 3567 __be32 op_to_vfn; 3568 __be32 retval_len16; 3569 __be32 niqflint_niq; 3570 __be32 type_to_neq; 3571 __be32 tc_to_nexactf; 3572 __be32 r_caps_to_nethctrl; 3573 __be16 nricq; 3574 __be16 nriqp; 3575 __be32 r4; 3576 }; 3577 3578 #define S_FW_PFVF_CMD_PFN 8 3579 #define M_FW_PFVF_CMD_PFN 0x7 3580 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 3581 #define G_FW_PFVF_CMD_PFN(x) \ 3582 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 3583 3584 #define S_FW_PFVF_CMD_VFN 0 3585 #define M_FW_PFVF_CMD_VFN 0xff 3586 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 3587 #define G_FW_PFVF_CMD_VFN(x) \ 3588 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 3589 3590 #define S_FW_PFVF_CMD_NIQFLINT 20 3591 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 3592 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 3593 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 3594 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 3595 3596 #define S_FW_PFVF_CMD_NIQ 0 3597 #define M_FW_PFVF_CMD_NIQ 0xfffff 3598 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 3599 #define G_FW_PFVF_CMD_NIQ(x) \ 3600 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 3601 3602 #define S_FW_PFVF_CMD_TYPE 31 3603 #define M_FW_PFVF_CMD_TYPE 0x1 3604 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 3605 #define G_FW_PFVF_CMD_TYPE(x) \ 3606 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 3607 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 3608 3609 #define S_FW_PFVF_CMD_CMASK 24 3610 #define M_FW_PFVF_CMD_CMASK 0xf 3611 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 3612 #define G_FW_PFVF_CMD_CMASK(x) \ 3613 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 3614 3615 #define S_FW_PFVF_CMD_PMASK 20 3616 #define M_FW_PFVF_CMD_PMASK 0xf 3617 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 3618 #define G_FW_PFVF_CMD_PMASK(x) \ 3619 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 3620 3621 #define S_FW_PFVF_CMD_NEQ 0 3622 #define M_FW_PFVF_CMD_NEQ 0xfffff 3623 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 3624 #define G_FW_PFVF_CMD_NEQ(x) \ 3625 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 3626 3627 #define S_FW_PFVF_CMD_TC 24 3628 #define M_FW_PFVF_CMD_TC 0xff 3629 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 3630 #define G_FW_PFVF_CMD_TC(x) (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 3631 3632 #define S_FW_PFVF_CMD_NVI 16 3633 #define M_FW_PFVF_CMD_NVI 0xff 3634 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 3635 #define G_FW_PFVF_CMD_NVI(x) \ 3636 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 3637 3638 #define S_FW_PFVF_CMD_NEXACTF 0 3639 #define M_FW_PFVF_CMD_NEXACTF 0xffff 3640 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 3641 #define G_FW_PFVF_CMD_NEXACTF(x) \ 3642 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 3643 3644 #define S_FW_PFVF_CMD_R_CAPS 24 3645 #define M_FW_PFVF_CMD_R_CAPS 0xff 3646 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 3647 #define G_FW_PFVF_CMD_R_CAPS(x) \ 3648 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 3649 3650 #define S_FW_PFVF_CMD_WX_CAPS 16 3651 #define M_FW_PFVF_CMD_WX_CAPS 0xff 3652 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 3653 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 3654 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 3655 3656 #define S_FW_PFVF_CMD_NETHCTRL 0 3657 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 3658 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 3659 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 3660 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 3661 3662 /* 3663 * ingress queue type; the first 1K ingress queues can have associated 0, 3664 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 3665 * capabilities 3666 */ 3667 enum fw_iq_type { 3668 FW_IQ_TYPE_FL_INT_CAP, 3669 FW_IQ_TYPE_NO_FL_INT_CAP 3670 }; 3671 3672 struct fw_iq_cmd { 3673 __be32 op_to_vfn; 3674 __be32 alloc_to_len16; 3675 __be16 physiqid; 3676 __be16 iqid; 3677 __be16 fl0id; 3678 __be16 fl1id; 3679 __be32 type_to_iqandstindex; 3680 __be16 iqdroprss_to_iqesize; 3681 __be16 iqsize; 3682 __be64 iqaddr; 3683 __be32 iqns_to_fl0congen; 3684 __be16 fl0dcaen_to_fl0cidxfthresh; 3685 __be16 fl0size; 3686 __be64 fl0addr; 3687 __be32 fl1cngchmap_to_fl1congen; 3688 __be16 fl1dcaen_to_fl1cidxfthresh; 3689 __be16 fl1size; 3690 __be64 fl1addr; 3691 }; 3692 3693 #define S_FW_IQ_CMD_PFN 8 3694 #define M_FW_IQ_CMD_PFN 0x7 3695 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 3696 #define G_FW_IQ_CMD_PFN(x) (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 3697 3698 #define S_FW_IQ_CMD_VFN 0 3699 #define M_FW_IQ_CMD_VFN 0xff 3700 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 3701 #define G_FW_IQ_CMD_VFN(x) (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 3702 3703 #define S_FW_IQ_CMD_ALLOC 31 3704 #define M_FW_IQ_CMD_ALLOC 0x1 3705 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 3706 #define G_FW_IQ_CMD_ALLOC(x) \ 3707 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 3708 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 3709 3710 #define S_FW_IQ_CMD_FREE 30 3711 #define M_FW_IQ_CMD_FREE 0x1 3712 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 3713 #define G_FW_IQ_CMD_FREE(x) (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 3714 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 3715 3716 #define S_FW_IQ_CMD_MODIFY 29 3717 #define M_FW_IQ_CMD_MODIFY 0x1 3718 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 3719 #define G_FW_IQ_CMD_MODIFY(x) \ 3720 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 3721 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 3722 3723 #define S_FW_IQ_CMD_IQSTART 28 3724 #define M_FW_IQ_CMD_IQSTART 0x1 3725 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 3726 #define G_FW_IQ_CMD_IQSTART(x) \ 3727 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 3728 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 3729 3730 #define S_FW_IQ_CMD_IQSTOP 27 3731 #define M_FW_IQ_CMD_IQSTOP 0x1 3732 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 3733 #define G_FW_IQ_CMD_IQSTOP(x) \ 3734 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 3735 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 3736 3737 #define S_FW_IQ_CMD_TYPE 29 3738 #define M_FW_IQ_CMD_TYPE 0x7 3739 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 3740 #define G_FW_IQ_CMD_TYPE(x) (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 3741 3742 #define S_FW_IQ_CMD_IQASYNCH 28 3743 #define M_FW_IQ_CMD_IQASYNCH 0x1 3744 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 3745 #define G_FW_IQ_CMD_IQASYNCH(x) \ 3746 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 3747 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 3748 3749 #define S_FW_IQ_CMD_VIID 16 3750 #define M_FW_IQ_CMD_VIID 0xfff 3751 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 3752 #define G_FW_IQ_CMD_VIID(x) (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 3753 3754 #define S_FW_IQ_CMD_IQANDST 15 3755 #define M_FW_IQ_CMD_IQANDST 0x1 3756 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 3757 #define G_FW_IQ_CMD_IQANDST(x) \ 3758 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 3759 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 3760 3761 #define S_FW_IQ_CMD_IQANUS 14 3762 #define M_FW_IQ_CMD_IQANUS 0x1 3763 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 3764 #define G_FW_IQ_CMD_IQANUS(x) \ 3765 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 3766 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 3767 3768 #define S_FW_IQ_CMD_IQANUD 12 3769 #define M_FW_IQ_CMD_IQANUD 0x3 3770 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 3771 #define G_FW_IQ_CMD_IQANUD(x) \ 3772 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 3773 3774 #define S_FW_IQ_CMD_IQANDSTINDEX 0 3775 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 3776 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 3777 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 3778 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 3779 3780 #define S_FW_IQ_CMD_IQDROPRSS 15 3781 #define M_FW_IQ_CMD_IQDROPRSS 0x1 3782 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 3783 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 3784 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 3785 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 3786 3787 #define S_FW_IQ_CMD_IQGTSMODE 14 3788 #define M_FW_IQ_CMD_IQGTSMODE 0x1 3789 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 3790 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 3791 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 3792 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 3793 3794 #define S_FW_IQ_CMD_IQPCIECH 12 3795 #define M_FW_IQ_CMD_IQPCIECH 0x3 3796 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 3797 #define G_FW_IQ_CMD_IQPCIECH(x) \ 3798 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 3799 3800 #define S_FW_IQ_CMD_IQDCAEN 11 3801 #define M_FW_IQ_CMD_IQDCAEN 0x1 3802 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 3803 #define G_FW_IQ_CMD_IQDCAEN(x) \ 3804 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 3805 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 3806 3807 #define S_FW_IQ_CMD_IQDCACPU 6 3808 #define M_FW_IQ_CMD_IQDCACPU 0x1f 3809 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 3810 #define G_FW_IQ_CMD_IQDCACPU(x) \ 3811 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 3812 3813 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 3814 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 3815 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 3816 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 3817 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 3818 3819 #define S_FW_IQ_CMD_IQO 3 3820 #define M_FW_IQ_CMD_IQO 0x1 3821 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 3822 #define G_FW_IQ_CMD_IQO(x) (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 3823 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 3824 3825 #define S_FW_IQ_CMD_IQCPRIO 2 3826 #define M_FW_IQ_CMD_IQCPRIO 0x1 3827 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 3828 #define G_FW_IQ_CMD_IQCPRIO(x) \ 3829 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 3830 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 3831 3832 #define S_FW_IQ_CMD_IQESIZE 0 3833 #define M_FW_IQ_CMD_IQESIZE 0x3 3834 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 3835 #define G_FW_IQ_CMD_IQESIZE(x) \ 3836 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 3837 3838 #define S_FW_IQ_CMD_IQNS 31 3839 #define M_FW_IQ_CMD_IQNS 0x1 3840 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 3841 #define G_FW_IQ_CMD_IQNS(x) (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 3842 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 3843 3844 #define S_FW_IQ_CMD_IQRO 30 3845 #define M_FW_IQ_CMD_IQRO 0x1 3846 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 3847 #define G_FW_IQ_CMD_IQRO(x) (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 3848 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 3849 3850 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 3851 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 3852 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 3853 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 3854 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 3855 3856 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 3857 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 3858 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 3859 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 3860 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 3861 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 3862 3863 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 3864 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 3865 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 3866 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 3867 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 3868 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 3869 3870 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 3871 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 3872 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 3873 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 3874 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 3875 3876 #define S_FW_IQ_CMD_FL0CACHELOCK 15 3877 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 3878 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 3879 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 3880 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 3881 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 3882 3883 #define S_FW_IQ_CMD_FL0DBP 14 3884 #define M_FW_IQ_CMD_FL0DBP 0x1 3885 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 3886 #define G_FW_IQ_CMD_FL0DBP(x) \ 3887 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 3888 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 3889 3890 #define S_FW_IQ_CMD_FL0DATANS 13 3891 #define M_FW_IQ_CMD_FL0DATANS 0x1 3892 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 3893 #define G_FW_IQ_CMD_FL0DATANS(x) \ 3894 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 3895 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 3896 3897 #define S_FW_IQ_CMD_FL0DATARO 12 3898 #define M_FW_IQ_CMD_FL0DATARO 0x1 3899 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 3900 #define G_FW_IQ_CMD_FL0DATARO(x) \ 3901 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 3902 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 3903 3904 #define S_FW_IQ_CMD_FL0CONGCIF 11 3905 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 3906 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 3907 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 3908 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 3909 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 3910 3911 #define S_FW_IQ_CMD_FL0ONCHIP 10 3912 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 3913 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 3914 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 3915 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 3916 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 3917 3918 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 3919 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 3920 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 3921 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 3922 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 3923 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 3924 3925 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 3926 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 3927 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 3928 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 3929 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 3930 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 3931 3932 #define S_FW_IQ_CMD_FL0FETCHNS 7 3933 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 3934 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 3935 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 3936 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 3937 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 3938 3939 #define S_FW_IQ_CMD_FL0FETCHRO 6 3940 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 3941 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 3942 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 3943 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 3944 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 3945 3946 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 3947 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 3948 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 3949 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 3950 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 3951 3952 #define S_FW_IQ_CMD_FL0CPRIO 3 3953 #define M_FW_IQ_CMD_FL0CPRIO 0x1 3954 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 3955 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 3956 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 3957 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 3958 3959 #define S_FW_IQ_CMD_FL0PADEN 2 3960 #define M_FW_IQ_CMD_FL0PADEN 0x1 3961 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 3962 #define G_FW_IQ_CMD_FL0PADEN(x) \ 3963 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 3964 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 3965 3966 #define S_FW_IQ_CMD_FL0PACKEN 1 3967 #define M_FW_IQ_CMD_FL0PACKEN 0x1 3968 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 3969 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 3970 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 3971 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 3972 3973 #define S_FW_IQ_CMD_FL0CONGEN 0 3974 #define M_FW_IQ_CMD_FL0CONGEN 0x1 3975 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 3976 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 3977 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 3978 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 3979 3980 #define S_FW_IQ_CMD_FL0DCAEN 15 3981 #define M_FW_IQ_CMD_FL0DCAEN 0x1 3982 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 3983 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 3984 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 3985 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 3986 3987 #define S_FW_IQ_CMD_FL0DCACPU 10 3988 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 3989 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 3990 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 3991 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 3992 3993 #define S_FW_IQ_CMD_FL0FBMIN 7 3994 #define M_FW_IQ_CMD_FL0FBMIN 0x7 3995 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 3996 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 3997 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 3998 3999 #define S_FW_IQ_CMD_FL0FBMAX 4 4000 #define M_FW_IQ_CMD_FL0FBMAX 0x7 4001 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 4002 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 4003 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 4004 4005 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 4006 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 4007 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 4008 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 4009 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 4010 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 4011 4012 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 4013 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 4014 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 4015 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 4016 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 4017 4018 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 4019 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 4020 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 4021 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 4022 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 4023 4024 #define S_FW_IQ_CMD_FL1CACHELOCK 15 4025 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 4026 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 4027 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 4028 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 4029 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 4030 4031 #define S_FW_IQ_CMD_FL1DBP 14 4032 #define M_FW_IQ_CMD_FL1DBP 0x1 4033 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 4034 #define G_FW_IQ_CMD_FL1DBP(x) \ 4035 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 4036 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 4037 4038 #define S_FW_IQ_CMD_FL1DATANS 13 4039 #define M_FW_IQ_CMD_FL1DATANS 0x1 4040 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 4041 #define G_FW_IQ_CMD_FL1DATANS(x) \ 4042 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 4043 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 4044 4045 #define S_FW_IQ_CMD_FL1DATARO 12 4046 #define M_FW_IQ_CMD_FL1DATARO 0x1 4047 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 4048 #define G_FW_IQ_CMD_FL1DATARO(x) \ 4049 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 4050 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 4051 4052 #define S_FW_IQ_CMD_FL1CONGCIF 11 4053 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 4054 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 4055 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 4056 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 4057 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 4058 4059 #define S_FW_IQ_CMD_FL1ONCHIP 10 4060 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 4061 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 4062 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 4063 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 4064 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 4065 4066 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 4067 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 4068 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 4069 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 4070 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 4071 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 4072 4073 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 4074 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 4075 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 4076 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 4077 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 4078 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 4079 4080 #define S_FW_IQ_CMD_FL1FETCHNS 7 4081 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 4082 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 4083 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 4084 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 4085 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 4086 4087 #define S_FW_IQ_CMD_FL1FETCHRO 6 4088 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 4089 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 4090 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 4091 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 4092 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 4093 4094 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 4095 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 4096 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 4097 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 4098 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 4099 4100 #define S_FW_IQ_CMD_FL1CPRIO 3 4101 #define M_FW_IQ_CMD_FL1CPRIO 0x1 4102 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 4103 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 4104 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 4105 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 4106 4107 #define S_FW_IQ_CMD_FL1PADEN 2 4108 #define M_FW_IQ_CMD_FL1PADEN 0x1 4109 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 4110 #define G_FW_IQ_CMD_FL1PADEN(x) \ 4111 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 4112 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 4113 4114 #define S_FW_IQ_CMD_FL1PACKEN 1 4115 #define M_FW_IQ_CMD_FL1PACKEN 0x1 4116 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 4117 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 4118 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 4119 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 4120 4121 #define S_FW_IQ_CMD_FL1CONGEN 0 4122 #define M_FW_IQ_CMD_FL1CONGEN 0x1 4123 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 4124 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 4125 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 4126 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 4127 4128 #define S_FW_IQ_CMD_FL1DCAEN 15 4129 #define M_FW_IQ_CMD_FL1DCAEN 0x1 4130 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 4131 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 4132 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 4133 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 4134 4135 #define S_FW_IQ_CMD_FL1DCACPU 10 4136 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 4137 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 4138 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 4139 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 4140 4141 #define S_FW_IQ_CMD_FL1FBMIN 7 4142 #define M_FW_IQ_CMD_FL1FBMIN 0x7 4143 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 4144 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 4145 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 4146 4147 #define S_FW_IQ_CMD_FL1FBMAX 4 4148 #define M_FW_IQ_CMD_FL1FBMAX 0x7 4149 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 4150 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 4151 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 4152 4153 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 4154 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 4155 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 4156 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 4157 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 4158 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 4159 4160 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 4161 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 4162 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 4163 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 4164 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 4165 4166 struct fw_eq_mngt_cmd { 4167 __be32 op_to_vfn; 4168 __be32 alloc_to_len16; 4169 __be32 cmpliqid_eqid; 4170 __be32 physeqid_pkd; 4171 __be32 fetchszm_to_iqid; 4172 __be32 dcaen_to_eqsize; 4173 __be64 eqaddr; 4174 }; 4175 4176 #define S_FW_EQ_MNGT_CMD_PFN 8 4177 #define M_FW_EQ_MNGT_CMD_PFN 0x7 4178 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 4179 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 4180 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 4181 4182 #define S_FW_EQ_MNGT_CMD_VFN 0 4183 #define M_FW_EQ_MNGT_CMD_VFN 0xff 4184 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 4185 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 4186 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 4187 4188 #define S_FW_EQ_MNGT_CMD_ALLOC 31 4189 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 4190 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 4191 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 4192 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 4193 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 4194 4195 #define S_FW_EQ_MNGT_CMD_FREE 30 4196 #define M_FW_EQ_MNGT_CMD_FREE 0x1 4197 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 4198 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 4199 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 4200 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 4201 4202 #define S_FW_EQ_MNGT_CMD_MODIFY 29 4203 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 4204 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 4205 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 4206 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 4207 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 4208 4209 #define S_FW_EQ_MNGT_CMD_EQSTART 28 4210 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 4211 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 4212 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 4213 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 4214 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 4215 4216 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 4217 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 4218 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 4219 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 4220 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 4221 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 4222 4223 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 4224 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 4225 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 4226 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 4227 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 4228 4229 #define S_FW_EQ_MNGT_CMD_EQID 0 4230 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 4231 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 4232 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 4233 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 4234 4235 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 4236 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 4237 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 4238 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 4239 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 4240 4241 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 4242 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 4243 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 4244 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 4245 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 4246 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 4247 4248 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 4249 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 4250 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 4251 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 4252 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 4253 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 4254 4255 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 4256 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 4257 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 4258 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 4259 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 4260 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 4261 4262 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 4263 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 4264 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 4265 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 4266 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 4267 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 4268 4269 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 4270 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 4271 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 4272 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 4273 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 4274 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 4275 4276 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 4277 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 4278 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 4279 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 4280 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 4281 4282 #define S_FW_EQ_MNGT_CMD_CPRIO 19 4283 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 4284 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 4285 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 4286 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 4287 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 4288 4289 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 4290 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 4291 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 4292 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 4293 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 4294 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 4295 4296 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 4297 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 4298 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 4299 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 4300 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 4301 4302 #define S_FW_EQ_MNGT_CMD_IQID 0 4303 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 4304 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 4305 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 4306 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 4307 4308 #define S_FW_EQ_MNGT_CMD_DCAEN 31 4309 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 4310 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 4311 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 4312 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 4313 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 4314 4315 #define S_FW_EQ_MNGT_CMD_DCACPU 26 4316 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 4317 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 4318 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 4319 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 4320 4321 #define S_FW_EQ_MNGT_CMD_FBMIN 23 4322 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 4323 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 4324 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 4325 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 4326 4327 #define S_FW_EQ_MNGT_CMD_FBMAX 20 4328 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 4329 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 4330 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 4331 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 4332 4333 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 4334 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 4335 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4336 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4337 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 4338 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 4339 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 4340 4341 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 4342 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 4343 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4344 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 4345 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 4346 4347 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 4348 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 4349 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 4350 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 4351 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 4352 4353 struct fw_eq_eth_cmd { 4354 __be32 op_to_vfn; 4355 __be32 alloc_to_len16; 4356 __be32 eqid_pkd; 4357 __be32 physeqid_pkd; 4358 __be32 fetchszm_to_iqid; 4359 __be32 dcaen_to_eqsize; 4360 __be64 eqaddr; 4361 __be32 viid_pkd; 4362 __be32 r8_lo; 4363 __be64 r9; 4364 }; 4365 4366 #define S_FW_EQ_ETH_CMD_PFN 8 4367 #define M_FW_EQ_ETH_CMD_PFN 0x7 4368 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 4369 #define G_FW_EQ_ETH_CMD_PFN(x) \ 4370 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 4371 4372 #define S_FW_EQ_ETH_CMD_VFN 0 4373 #define M_FW_EQ_ETH_CMD_VFN 0xff 4374 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 4375 #define G_FW_EQ_ETH_CMD_VFN(x) \ 4376 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 4377 4378 #define S_FW_EQ_ETH_CMD_ALLOC 31 4379 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 4380 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 4381 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 4382 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 4383 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 4384 4385 #define S_FW_EQ_ETH_CMD_FREE 30 4386 #define M_FW_EQ_ETH_CMD_FREE 0x1 4387 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 4388 #define G_FW_EQ_ETH_CMD_FREE(x) \ 4389 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 4390 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 4391 4392 #define S_FW_EQ_ETH_CMD_MODIFY 29 4393 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 4394 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 4395 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 4396 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 4397 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 4398 4399 #define S_FW_EQ_ETH_CMD_EQSTART 28 4400 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 4401 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 4402 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 4403 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 4404 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 4405 4406 #define S_FW_EQ_ETH_CMD_EQSTOP 27 4407 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 4408 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 4409 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 4410 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 4411 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 4412 4413 #define S_FW_EQ_ETH_CMD_EQID 0 4414 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 4415 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 4416 #define G_FW_EQ_ETH_CMD_EQID(x) \ 4417 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 4418 4419 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 4420 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 4421 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 4422 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 4423 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 4424 4425 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 4426 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 4427 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 4428 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 4429 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 4430 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 4431 4432 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 4433 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 4434 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 4435 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 4436 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 4437 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 4438 4439 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 4440 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 4441 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 4442 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 4443 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 4444 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 4445 4446 #define S_FW_EQ_ETH_CMD_FETCHNS 23 4447 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 4448 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 4449 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 4450 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 4451 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 4452 4453 #define S_FW_EQ_ETH_CMD_FETCHRO 22 4454 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 4455 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 4456 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 4457 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 4458 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 4459 4460 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 4461 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 4462 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 4463 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 4464 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 4465 4466 #define S_FW_EQ_ETH_CMD_CPRIO 19 4467 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 4468 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 4469 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 4470 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 4471 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 4472 4473 #define S_FW_EQ_ETH_CMD_ONCHIP 18 4474 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 4475 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 4476 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 4477 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 4478 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 4479 4480 #define S_FW_EQ_ETH_CMD_PCIECHN 16 4481 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 4482 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 4483 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 4484 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 4485 4486 #define S_FW_EQ_ETH_CMD_IQID 0 4487 #define M_FW_EQ_ETH_CMD_IQID 0xffff 4488 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 4489 #define G_FW_EQ_ETH_CMD_IQID(x) \ 4490 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 4491 4492 #define S_FW_EQ_ETH_CMD_DCAEN 31 4493 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 4494 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 4495 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 4496 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 4497 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 4498 4499 #define S_FW_EQ_ETH_CMD_DCACPU 26 4500 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 4501 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 4502 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 4503 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 4504 4505 #define S_FW_EQ_ETH_CMD_FBMIN 23 4506 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 4507 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 4508 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 4509 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 4510 4511 #define S_FW_EQ_ETH_CMD_FBMAX 20 4512 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 4513 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 4514 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 4515 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 4516 4517 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 4518 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 4519 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4520 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 4521 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 4522 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 4523 4524 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 4525 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 4526 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 4527 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 4528 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 4529 4530 #define S_FW_EQ_ETH_CMD_EQSIZE 0 4531 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 4532 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 4533 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 4534 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 4535 4536 #define S_FW_EQ_ETH_CMD_VIID 16 4537 #define M_FW_EQ_ETH_CMD_VIID 0xfff 4538 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 4539 #define G_FW_EQ_ETH_CMD_VIID(x) \ 4540 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 4541 4542 struct fw_eq_ctrl_cmd { 4543 __be32 op_to_vfn; 4544 __be32 alloc_to_len16; 4545 __be32 cmpliqid_eqid; 4546 __be32 physeqid_pkd; 4547 __be32 fetchszm_to_iqid; 4548 __be32 dcaen_to_eqsize; 4549 __be64 eqaddr; 4550 }; 4551 4552 #define S_FW_EQ_CTRL_CMD_PFN 8 4553 #define M_FW_EQ_CTRL_CMD_PFN 0x7 4554 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 4555 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 4556 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 4557 4558 #define S_FW_EQ_CTRL_CMD_VFN 0 4559 #define M_FW_EQ_CTRL_CMD_VFN 0xff 4560 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 4561 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 4562 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 4563 4564 #define S_FW_EQ_CTRL_CMD_ALLOC 31 4565 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 4566 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 4567 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 4568 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 4569 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 4570 4571 #define S_FW_EQ_CTRL_CMD_FREE 30 4572 #define M_FW_EQ_CTRL_CMD_FREE 0x1 4573 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 4574 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 4575 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 4576 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 4577 4578 #define S_FW_EQ_CTRL_CMD_MODIFY 29 4579 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 4580 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 4581 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 4582 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 4583 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 4584 4585 #define S_FW_EQ_CTRL_CMD_EQSTART 28 4586 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 4587 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 4588 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 4589 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 4590 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 4591 4592 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 4593 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 4594 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 4595 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 4596 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 4597 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 4598 4599 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 4600 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 4601 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 4602 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 4603 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 4604 4605 #define S_FW_EQ_CTRL_CMD_EQID 0 4606 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 4607 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 4608 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 4609 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 4610 4611 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 4612 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 4613 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 4614 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 4615 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 4616 4617 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 4618 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 4619 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 4620 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 4621 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 4622 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 4623 4624 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 4625 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 4626 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 4627 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 4628 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 4629 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 4630 4631 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 4632 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 4633 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 4634 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 4635 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 4636 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 4637 4638 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 4639 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 4640 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 4641 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 4642 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 4643 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 4644 4645 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 4646 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 4647 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 4648 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 4649 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 4650 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 4651 4652 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 4653 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 4654 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 4655 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 4656 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 4657 4658 #define S_FW_EQ_CTRL_CMD_CPRIO 19 4659 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 4660 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 4661 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 4662 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 4663 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 4664 4665 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 4666 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 4667 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 4668 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 4669 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 4670 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 4671 4672 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 4673 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 4674 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 4675 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 4676 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 4677 4678 #define S_FW_EQ_CTRL_CMD_IQID 0 4679 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 4680 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 4681 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 4682 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 4683 4684 #define S_FW_EQ_CTRL_CMD_DCAEN 31 4685 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 4686 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 4687 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 4688 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 4689 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 4690 4691 #define S_FW_EQ_CTRL_CMD_DCACPU 26 4692 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 4693 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 4694 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 4695 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 4696 4697 #define S_FW_EQ_CTRL_CMD_FBMIN 23 4698 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 4699 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 4700 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 4701 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 4702 4703 #define S_FW_EQ_CTRL_CMD_FBMAX 20 4704 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 4705 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 4706 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 4707 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 4708 4709 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 4710 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 4711 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4712 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4713 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 4714 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 4715 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 4716 4717 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 4718 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 4719 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4720 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 4721 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 4722 4723 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 4724 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 4725 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 4726 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 4727 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 4728 4729 struct fw_eq_ofld_cmd { 4730 __be32 op_to_vfn; 4731 __be32 alloc_to_len16; 4732 __be32 eqid_pkd; 4733 __be32 physeqid_pkd; 4734 __be32 fetchszm_to_iqid; 4735 __be32 dcaen_to_eqsize; 4736 __be64 eqaddr; 4737 }; 4738 4739 #define S_FW_EQ_OFLD_CMD_PFN 8 4740 #define M_FW_EQ_OFLD_CMD_PFN 0x7 4741 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 4742 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 4743 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 4744 4745 #define S_FW_EQ_OFLD_CMD_VFN 0 4746 #define M_FW_EQ_OFLD_CMD_VFN 0xff 4747 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 4748 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 4749 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 4750 4751 #define S_FW_EQ_OFLD_CMD_ALLOC 31 4752 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 4753 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 4754 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 4755 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 4756 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 4757 4758 #define S_FW_EQ_OFLD_CMD_FREE 30 4759 #define M_FW_EQ_OFLD_CMD_FREE 0x1 4760 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 4761 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 4762 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 4763 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 4764 4765 #define S_FW_EQ_OFLD_CMD_MODIFY 29 4766 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 4767 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 4768 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 4769 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 4770 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 4771 4772 #define S_FW_EQ_OFLD_CMD_EQSTART 28 4773 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 4774 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 4775 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 4776 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 4777 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 4778 4779 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 4780 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 4781 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 4782 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 4783 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 4784 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 4785 4786 #define S_FW_EQ_OFLD_CMD_EQID 0 4787 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 4788 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 4789 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 4790 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 4791 4792 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 4793 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 4794 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 4795 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 4796 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 4797 4798 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 4799 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 4800 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 4801 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 4802 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 4803 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 4804 4805 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 4806 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 4807 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 4808 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 4809 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 4810 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 4811 4812 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 4813 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 4814 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 4815 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 4816 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 4817 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 4818 4819 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 4820 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 4821 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 4822 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 4823 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 4824 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 4825 4826 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 4827 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 4828 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 4829 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 4830 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 4831 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 4832 4833 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 4834 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 4835 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 4836 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 4837 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 4838 4839 #define S_FW_EQ_OFLD_CMD_CPRIO 19 4840 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 4841 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 4842 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 4843 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 4844 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 4845 4846 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 4847 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 4848 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 4849 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 4850 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 4851 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 4852 4853 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 4854 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 4855 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 4856 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 4857 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 4858 4859 #define S_FW_EQ_OFLD_CMD_IQID 0 4860 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 4861 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 4862 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 4863 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 4864 4865 #define S_FW_EQ_OFLD_CMD_DCAEN 31 4866 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 4867 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 4868 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 4869 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 4870 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 4871 4872 #define S_FW_EQ_OFLD_CMD_DCACPU 26 4873 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 4874 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 4875 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 4876 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 4877 4878 #define S_FW_EQ_OFLD_CMD_FBMIN 23 4879 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 4880 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 4881 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 4882 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 4883 4884 #define S_FW_EQ_OFLD_CMD_FBMAX 20 4885 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 4886 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 4887 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 4888 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 4889 4890 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 4891 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 4892 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 4893 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 4894 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 4895 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 4896 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 4897 4898 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 4899 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 4900 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 4901 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 4902 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 4903 4904 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 4905 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 4906 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 4907 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 4908 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 4909 4910 /* Macros for VIID parsing: 4911 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 4912 #define S_FW_VIID_PFN 8 4913 #define M_FW_VIID_PFN 0x7 4914 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 4915 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 4916 4917 #define S_FW_VIID_VIVLD 7 4918 #define M_FW_VIID_VIVLD 0x1 4919 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 4920 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 4921 4922 #define S_FW_VIID_VIN 0 4923 #define M_FW_VIID_VIN 0x7F 4924 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 4925 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 4926 4927 enum fw_vi_func { 4928 FW_VI_FUNC_ETH, 4929 FW_VI_FUNC_OFLD, 4930 FW_VI_FUNC_IWARP, 4931 FW_VI_FUNC_OPENISCSI, 4932 FW_VI_FUNC_OPENFCOE, 4933 FW_VI_FUNC_FOISCSI, 4934 FW_VI_FUNC_FOFCOE, 4935 FW_VI_FUNC_FW, 4936 }; 4937 4938 struct fw_vi_cmd { 4939 __be32 op_to_vfn; 4940 __be32 alloc_to_len16; 4941 __be16 type_to_viid; 4942 __u8 mac[6]; 4943 __u8 portid_pkd; 4944 __u8 nmac; 4945 __u8 nmac0[6]; 4946 __be16 rsssize_pkd; 4947 __u8 nmac1[6]; 4948 __be16 idsiiq_pkd; 4949 __u8 nmac2[6]; 4950 __be16 idseiq_pkd; 4951 __u8 nmac3[6]; 4952 __be64 r9; 4953 __be64 r10; 4954 }; 4955 4956 #define S_FW_VI_CMD_PFN 8 4957 #define M_FW_VI_CMD_PFN 0x7 4958 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 4959 #define G_FW_VI_CMD_PFN(x) (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 4960 4961 #define S_FW_VI_CMD_VFN 0 4962 #define M_FW_VI_CMD_VFN 0xff 4963 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 4964 #define G_FW_VI_CMD_VFN(x) (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 4965 4966 #define S_FW_VI_CMD_ALLOC 31 4967 #define M_FW_VI_CMD_ALLOC 0x1 4968 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 4969 #define G_FW_VI_CMD_ALLOC(x) \ 4970 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 4971 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 4972 4973 #define S_FW_VI_CMD_FREE 30 4974 #define M_FW_VI_CMD_FREE 0x1 4975 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 4976 #define G_FW_VI_CMD_FREE(x) (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 4977 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 4978 4979 #define S_FW_VI_CMD_TYPE 15 4980 #define M_FW_VI_CMD_TYPE 0x1 4981 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 4982 #define G_FW_VI_CMD_TYPE(x) (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 4983 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 4984 4985 #define S_FW_VI_CMD_FUNC 12 4986 #define M_FW_VI_CMD_FUNC 0x7 4987 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 4988 #define G_FW_VI_CMD_FUNC(x) (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 4989 4990 #define S_FW_VI_CMD_VIID 0 4991 #define M_FW_VI_CMD_VIID 0xfff 4992 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 4993 #define G_FW_VI_CMD_VIID(x) (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 4994 4995 #define S_FW_VI_CMD_PORTID 4 4996 #define M_FW_VI_CMD_PORTID 0xf 4997 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 4998 #define G_FW_VI_CMD_PORTID(x) \ 4999 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 5000 5001 #define S_FW_VI_CMD_RSSSIZE 0 5002 #define M_FW_VI_CMD_RSSSIZE 0x7ff 5003 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 5004 #define G_FW_VI_CMD_RSSSIZE(x) \ 5005 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 5006 5007 #define S_FW_VI_CMD_IDSIIQ 0 5008 #define M_FW_VI_CMD_IDSIIQ 0x3ff 5009 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 5010 #define G_FW_VI_CMD_IDSIIQ(x) \ 5011 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 5012 5013 #define S_FW_VI_CMD_IDSEIQ 0 5014 #define M_FW_VI_CMD_IDSEIQ 0x3ff 5015 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 5016 #define G_FW_VI_CMD_IDSEIQ(x) \ 5017 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 5018 5019 /* Special VI_MAC command index ids */ 5020 #define FW_VI_MAC_ADD_MAC 0x3FF 5021 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 5022 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 5023 5024 enum fw_vi_mac_smac { 5025 FW_VI_MAC_MPS_TCAM_ENTRY, 5026 FW_VI_MAC_MPS_TCAM_ONLY, 5027 FW_VI_MAC_SMT_ONLY, 5028 FW_VI_MAC_SMT_AND_MPSTCAM 5029 }; 5030 5031 enum fw_vi_mac_result { 5032 FW_VI_MAC_R_SUCCESS, 5033 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 5034 FW_VI_MAC_R_SMAC_FAIL, 5035 FW_VI_MAC_R_F_ACL_CHECK 5036 }; 5037 5038 struct fw_vi_mac_cmd { 5039 __be32 op_to_viid; 5040 __be32 freemacs_to_len16; 5041 union fw_vi_mac { 5042 struct fw_vi_mac_exact { 5043 __be16 valid_to_idx; 5044 __u8 macaddr[6]; 5045 } exact[7]; 5046 struct fw_vi_mac_hash { 5047 __be64 hashvec; 5048 } hash; 5049 } u; 5050 }; 5051 5052 #define S_FW_VI_MAC_CMD_VIID 0 5053 #define M_FW_VI_MAC_CMD_VIID 0xfff 5054 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 5055 #define G_FW_VI_MAC_CMD_VIID(x) \ 5056 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 5057 5058 #define S_FW_VI_MAC_CMD_FREEMACS 31 5059 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 5060 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 5061 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 5062 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 5063 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 5064 5065 #define S_FW_VI_MAC_CMD_HASHVECEN 23 5066 #define M_FW_VI_MAC_CMD_HASHVECEN 0x1 5067 #define V_FW_VI_MAC_CMD_HASHVECEN(x) ((x) << S_FW_VI_MAC_CMD_HASHVECEN) 5068 #define G_FW_VI_MAC_CMD_HASHVECEN(x) \ 5069 (((x) >> S_FW_VI_MAC_CMD_HASHVECEN) & M_FW_VI_MAC_CMD_HASHVECEN) 5070 #define F_FW_VI_MAC_CMD_HASHVECEN V_FW_VI_MAC_CMD_HASHVECEN(1U) 5071 5072 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 5073 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 5074 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 5075 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 5076 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 5077 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 5078 5079 #define S_FW_VI_MAC_CMD_VALID 15 5080 #define M_FW_VI_MAC_CMD_VALID 0x1 5081 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 5082 #define G_FW_VI_MAC_CMD_VALID(x) \ 5083 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 5084 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 5085 5086 #define S_FW_VI_MAC_CMD_PRIO 12 5087 #define M_FW_VI_MAC_CMD_PRIO 0x7 5088 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 5089 #define G_FW_VI_MAC_CMD_PRIO(x) \ 5090 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 5091 5092 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 5093 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 5094 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 5095 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 5096 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 5097 5098 #define S_FW_VI_MAC_CMD_IDX 0 5099 #define M_FW_VI_MAC_CMD_IDX 0x3ff 5100 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 5101 #define G_FW_VI_MAC_CMD_IDX(x) \ 5102 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 5103 5104 /* T4 max MTU supported */ 5105 #define T4_MAX_MTU_SUPPORTED 9600 5106 #define FW_RXMODE_MTU_NO_CHG 65535 5107 5108 struct fw_vi_rxmode_cmd { 5109 __be32 op_to_viid; 5110 __be32 retval_len16; 5111 __be32 mtu_to_vlanexen; 5112 __be32 r4_lo; 5113 }; 5114 5115 #define S_FW_VI_RXMODE_CMD_VIID 0 5116 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 5117 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 5118 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 5119 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 5120 5121 #define S_FW_VI_RXMODE_CMD_MTU 16 5122 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 5123 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 5124 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 5125 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 5126 5127 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 5128 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 5129 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 5130 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 5131 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 5132 5133 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 5134 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 5135 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5136 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 5137 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 5138 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 5139 5140 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 5141 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 5142 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5143 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 5144 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 5145 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 5146 5147 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 5148 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 5149 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 5150 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 5151 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 5152 5153 struct fw_vi_enable_cmd { 5154 __be32 op_to_viid; 5155 __be32 ien_to_len16; 5156 __be16 blinkdur; 5157 __be16 r3; 5158 __be32 r4; 5159 }; 5160 5161 #define S_FW_VI_ENABLE_CMD_VIID 0 5162 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 5163 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 5164 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 5165 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 5166 5167 #define S_FW_VI_ENABLE_CMD_IEN 31 5168 #define M_FW_VI_ENABLE_CMD_IEN 0x1 5169 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 5170 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 5171 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 5172 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 5173 5174 #define S_FW_VI_ENABLE_CMD_EEN 30 5175 #define M_FW_VI_ENABLE_CMD_EEN 0x1 5176 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 5177 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 5178 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 5179 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 5180 5181 #define S_FW_VI_ENABLE_CMD_LED 29 5182 #define M_FW_VI_ENABLE_CMD_LED 0x1 5183 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 5184 #define G_FW_VI_ENABLE_CMD_LED(x) \ 5185 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 5186 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 5187 5188 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 5189 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 5190 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 5191 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 5192 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 5193 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 5194 5195 /* VI VF stats offset definitions */ 5196 #define VI_VF_NUM_STATS 16 5197 enum fw_vi_stats_vf_index { 5198 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 5199 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 5200 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 5201 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 5202 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 5203 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 5204 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 5205 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 5206 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 5207 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 5208 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 5209 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 5210 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 5211 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 5212 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 5213 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 5214 }; 5215 5216 /* VI PF stats offset definitions */ 5217 #define VI_PF_NUM_STATS 17 5218 enum fw_vi_stats_pf_index { 5219 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 5220 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 5221 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 5222 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 5223 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 5224 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 5225 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 5226 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 5227 FW_VI_PF_STAT_RX_BYTES_IX, 5228 FW_VI_PF_STAT_RX_FRAMES_IX, 5229 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 5230 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 5231 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 5232 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 5233 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 5234 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 5235 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 5236 }; 5237 5238 struct fw_vi_stats_cmd { 5239 __be32 op_to_viid; 5240 __be32 retval_len16; 5241 union fw_vi_stats { 5242 struct fw_vi_stats_ctl { 5243 __be16 nstats_ix; 5244 __be16 r6; 5245 __be32 r7; 5246 __be64 stat0; 5247 __be64 stat1; 5248 __be64 stat2; 5249 __be64 stat3; 5250 __be64 stat4; 5251 __be64 stat5; 5252 } ctl; 5253 struct fw_vi_stats_pf { 5254 __be64 tx_bcast_bytes; 5255 __be64 tx_bcast_frames; 5256 __be64 tx_mcast_bytes; 5257 __be64 tx_mcast_frames; 5258 __be64 tx_ucast_bytes; 5259 __be64 tx_ucast_frames; 5260 __be64 tx_offload_bytes; 5261 __be64 tx_offload_frames; 5262 __be64 rx_pf_bytes; 5263 __be64 rx_pf_frames; 5264 __be64 rx_bcast_bytes; 5265 __be64 rx_bcast_frames; 5266 __be64 rx_mcast_bytes; 5267 __be64 rx_mcast_frames; 5268 __be64 rx_ucast_bytes; 5269 __be64 rx_ucast_frames; 5270 __be64 rx_err_frames; 5271 } pf; 5272 struct fw_vi_stats_vf { 5273 __be64 tx_bcast_bytes; 5274 __be64 tx_bcast_frames; 5275 __be64 tx_mcast_bytes; 5276 __be64 tx_mcast_frames; 5277 __be64 tx_ucast_bytes; 5278 __be64 tx_ucast_frames; 5279 __be64 tx_drop_frames; 5280 __be64 tx_offload_bytes; 5281 __be64 tx_offload_frames; 5282 __be64 rx_bcast_bytes; 5283 __be64 rx_bcast_frames; 5284 __be64 rx_mcast_bytes; 5285 __be64 rx_mcast_frames; 5286 __be64 rx_ucast_bytes; 5287 __be64 rx_ucast_frames; 5288 __be64 rx_err_frames; 5289 } vf; 5290 } u; 5291 }; 5292 5293 #define S_FW_VI_STATS_CMD_VIID 0 5294 #define M_FW_VI_STATS_CMD_VIID 0xfff 5295 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 5296 #define G_FW_VI_STATS_CMD_VIID(x) \ 5297 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 5298 5299 #define S_FW_VI_STATS_CMD_NSTATS 12 5300 #define M_FW_VI_STATS_CMD_NSTATS 0x7 5301 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 5302 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 5303 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 5304 5305 #define S_FW_VI_STATS_CMD_IX 0 5306 #define M_FW_VI_STATS_CMD_IX 0x1f 5307 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 5308 #define G_FW_VI_STATS_CMD_IX(x) \ 5309 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 5310 5311 struct fw_acl_mac_cmd { 5312 __be32 op_to_vfn; 5313 __be32 en_to_len16; 5314 __u8 nmac; 5315 __u8 r3[7]; 5316 __be16 r4; 5317 __u8 macaddr0[6]; 5318 __be16 r5; 5319 __u8 macaddr1[6]; 5320 __be16 r6; 5321 __u8 macaddr2[6]; 5322 __be16 r7; 5323 __u8 macaddr3[6]; 5324 }; 5325 5326 #define S_FW_ACL_MAC_CMD_PFN 8 5327 #define M_FW_ACL_MAC_CMD_PFN 0x7 5328 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 5329 #define G_FW_ACL_MAC_CMD_PFN(x) \ 5330 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 5331 5332 #define S_FW_ACL_MAC_CMD_VFN 0 5333 #define M_FW_ACL_MAC_CMD_VFN 0xff 5334 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 5335 #define G_FW_ACL_MAC_CMD_VFN(x) \ 5336 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 5337 5338 #define S_FW_ACL_MAC_CMD_EN 31 5339 #define M_FW_ACL_MAC_CMD_EN 0x1 5340 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 5341 #define G_FW_ACL_MAC_CMD_EN(x) \ 5342 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 5343 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 5344 5345 struct fw_acl_vlan_cmd { 5346 __be32 op_to_vfn; 5347 __be32 en_to_len16; 5348 __u8 nvlan; 5349 __u8 dropnovlan_fm; 5350 __u8 r3_lo[6]; 5351 __be16 vlanid[16]; 5352 }; 5353 5354 #define S_FW_ACL_VLAN_CMD_PFN 8 5355 #define M_FW_ACL_VLAN_CMD_PFN 0x7 5356 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 5357 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 5358 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 5359 5360 #define S_FW_ACL_VLAN_CMD_VFN 0 5361 #define M_FW_ACL_VLAN_CMD_VFN 0xff 5362 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 5363 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 5364 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 5365 5366 #define S_FW_ACL_VLAN_CMD_EN 31 5367 #define M_FW_ACL_VLAN_CMD_EN 0x1 5368 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 5369 #define G_FW_ACL_VLAN_CMD_EN(x) \ 5370 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 5371 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 5372 5373 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 5374 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 5375 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 5376 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 5377 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 5378 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 5379 5380 #define S_FW_ACL_VLAN_CMD_FM 6 5381 #define M_FW_ACL_VLAN_CMD_FM 0x1 5382 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 5383 #define G_FW_ACL_VLAN_CMD_FM(x) \ 5384 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 5385 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 5386 5387 /* port capabilities bitmap */ 5388 enum fw_port_cap { 5389 FW_PORT_CAP_SPEED_100M = 0x0001, 5390 FW_PORT_CAP_SPEED_1G = 0x0002, 5391 FW_PORT_CAP_SPEED_2_5G = 0x0004, 5392 FW_PORT_CAP_SPEED_10G = 0x0008, 5393 FW_PORT_CAP_SPEED_40G = 0x0010, 5394 FW_PORT_CAP_SPEED_100G = 0x0020, 5395 FW_PORT_CAP_FC_RX = 0x0040, 5396 FW_PORT_CAP_FC_TX = 0x0080, 5397 FW_PORT_CAP_ANEG = 0x0100, 5398 FW_PORT_CAP_MDIX = 0x0200, 5399 FW_PORT_CAP_MDIAUTO = 0x0400, 5400 FW_PORT_CAP_FEC = 0x0800, 5401 FW_PORT_CAP_TECHKR = 0x1000, 5402 FW_PORT_CAP_TECHKX4 = 0x2000, 5403 }; 5404 5405 #define S_FW_PORT_AUXLINFO_MDI 3 5406 #define M_FW_PORT_AUXLINFO_MDI 0x3 5407 #define V_FW_PORT_AUXLINFO_MDI(x) ((x) << S_FW_PORT_AUXLINFO_MDI) 5408 #define G_FW_PORT_AUXLINFO_MDI(x) \ 5409 (((x) >> S_FW_PORT_AUXLINFO_MDI) & M_FW_PORT_AUXLINFO_MDI) 5410 5411 #define S_FW_PORT_AUXLINFO_KX4 2 5412 #define M_FW_PORT_AUXLINFO_KX4 0x1 5413 #define V_FW_PORT_AUXLINFO_KX4(x) ((x) << S_FW_PORT_AUXLINFO_KX4) 5414 #define G_FW_PORT_AUXLINFO_KX4(x) \ 5415 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 5416 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 5417 5418 #define S_FW_PORT_AUXLINFO_KR 1 5419 #define M_FW_PORT_AUXLINFO_KR 0x1 5420 #define V_FW_PORT_AUXLINFO_KR(x) ((x) << S_FW_PORT_AUXLINFO_KR) 5421 #define G_FW_PORT_AUXLINFO_KR(x) \ 5422 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 5423 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 5424 5425 #define S_FW_PORT_AUXLINFO_FEC 0 5426 #define M_FW_PORT_AUXLINFO_FEC 0x1 5427 #define V_FW_PORT_AUXLINFO_FEC(x) ((x) << S_FW_PORT_AUXLINFO_FEC) 5428 #define G_FW_PORT_AUXLINFO_FEC(x) \ 5429 (((x) >> S_FW_PORT_AUXLINFO_FEC) & M_FW_PORT_AUXLINFO_FEC) 5430 #define F_FW_PORT_AUXLINFO_FEC V_FW_PORT_AUXLINFO_FEC(1U) 5431 5432 #define S_FW_PORT_RCAP_AUX 11 5433 #define M_FW_PORT_RCAP_AUX 0x7 5434 #define V_FW_PORT_RCAP_AUX(x) ((x) << S_FW_PORT_RCAP_AUX) 5435 #define G_FW_PORT_RCAP_AUX(x) \ 5436 (((x) >> S_FW_PORT_RCAP_AUX) & M_FW_PORT_RCAP_AUX) 5437 5438 #define S_FW_PORT_CAP_SPEED 0 5439 #define M_FW_PORT_CAP_SPEED 0x3f 5440 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 5441 #define G_FW_PORT_CAP_SPEED(x) \ 5442 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 5443 5444 #define S_FW_PORT_CAP_FC 6 5445 #define M_FW_PORT_CAP_FC 0x3 5446 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 5447 #define G_FW_PORT_CAP_FC(x) \ 5448 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 5449 5450 #define S_FW_PORT_CAP_ANEG 8 5451 #define M_FW_PORT_CAP_ANEG 0x1 5452 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 5453 #define G_FW_PORT_CAP_ANEG(x) \ 5454 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 5455 5456 enum fw_port_mdi { 5457 FW_PORT_CAP_MDI_UNCHANGED, 5458 FW_PORT_CAP_MDI_AUTO, 5459 FW_PORT_CAP_MDI_F_STRAIGHT, 5460 FW_PORT_CAP_MDI_F_CROSSOVER 5461 }; 5462 5463 #define S_FW_PORT_CAP_MDI 9 5464 #define M_FW_PORT_CAP_MDI 3 5465 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 5466 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 5467 5468 enum fw_port_action { 5469 FW_PORT_ACTION_L1_CFG = 0x0001, 5470 FW_PORT_ACTION_L2_CFG = 0x0002, 5471 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 5472 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 5473 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 5474 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 5475 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 5476 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 5477 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 5478 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 5479 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 5480 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 5481 FW_PORT_ACTION_L1_SS_LPBK_ASIC = 0x0021, 5482 FW_PORT_ACTION_MAC_LPBK = 0x0022, 5483 FW_PORT_ACTION_L1_WS_LPBK_ASIC = 0x0023, 5484 FW_PORT_ACTION_L1_EXT_LPBK = 0x0026, 5485 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 5486 FW_PORT_ACTION_PCS_LPBK = 0x0028, 5487 FW_PORT_ACTION_PHY_RESET = 0x0040, 5488 FW_PORT_ACTION_PMA_RESET = 0x0041, 5489 FW_PORT_ACTION_PCS_RESET = 0x0042, 5490 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 5491 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 5492 FW_PORT_ACTION_AN_RESET = 0x0045, 5493 }; 5494 5495 enum fw_port_l2cfg_ctlbf { 5496 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 5497 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 5498 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 5499 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 5500 FW_PORT_L2_CTLBF_IVLAN = 0x10, 5501 FW_PORT_L2_CTLBF_TXIPG = 0x20, 5502 FW_PORT_L2_CTLBF_MTU = 0x40 5503 }; 5504 5505 enum fw_port_dcb_cfg { 5506 FW_PORT_DCB_CFG_PG = 0x01, 5507 FW_PORT_DCB_CFG_PFC = 0x02, 5508 FW_PORT_DCB_CFG_APPL = 0x04 5509 }; 5510 5511 enum fw_port_dcb_cfg_rc { 5512 FW_PORT_DCB_CFG_SUCCESS = 0x0, 5513 FW_PORT_DCB_CFG_ERROR = 0x1 5514 }; 5515 5516 enum fw_port_dcb_type { 5517 FW_PORT_DCB_TYPE_PGID = 0x00, 5518 FW_PORT_DCB_TYPE_PGRATE = 0x01, 5519 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 5520 FW_PORT_DCB_TYPE_PFC = 0x03, 5521 FW_PORT_DCB_TYPE_APP_ID = 0x04, 5522 FW_PORT_DCB_TYPE_CONTROL = 0x05, 5523 }; 5524 5525 enum fw_port_diag_ops { 5526 FW_PORT_DIAGS_TEMP = 0x00, 5527 }; 5528 5529 struct fw_port_cmd { 5530 __be32 op_to_portid; 5531 __be32 action_to_len16; 5532 union fw_port { 5533 struct fw_port_l1cfg { 5534 __be32 rcap; 5535 __be32 r; 5536 } l1cfg; 5537 struct fw_port_l2cfg { 5538 __u8 ctlbf; 5539 __u8 ovlan3_to_ivlan0; 5540 __be16 ivlantype; 5541 __be16 txipg_force_pinfo; 5542 __be16 mtu; 5543 __be16 ovlan0mask; 5544 __be16 ovlan0type; 5545 __be16 ovlan1mask; 5546 __be16 ovlan1type; 5547 __be16 ovlan2mask; 5548 __be16 ovlan2type; 5549 __be16 ovlan3mask; 5550 __be16 ovlan3type; 5551 } l2cfg; 5552 struct fw_port_info { 5553 __be32 lstatus_to_modtype; 5554 __be16 pcap; 5555 __be16 acap; 5556 __be16 mtu; 5557 __u8 cbllen; 5558 __u8 auxlinfo; 5559 __be32 r8; 5560 __be64 r9; 5561 } info; 5562 struct fw_port_diags { 5563 __be32 diagop_diagval; 5564 __be32 r; 5565 } diags; 5566 union fw_port_dcb { 5567 struct fw_port_dcb_pgid { 5568 __u8 type; 5569 __u8 apply_pkd; 5570 __u8 r10_lo[2]; 5571 __be32 pgid; 5572 __be64 r11; 5573 } pgid; 5574 struct fw_port_dcb_pgrate { 5575 __u8 type; 5576 __u8 apply_pkd; 5577 __u8 r10_lo[5]; 5578 __u8 num_tcs_supported; 5579 __u8 pgrate[8]; 5580 } pgrate; 5581 struct fw_port_dcb_priorate { 5582 __u8 type; 5583 __u8 apply_pkd; 5584 __u8 r10_lo[6]; 5585 __u8 strict_priorate[8]; 5586 } priorate; 5587 struct fw_port_dcb_pfc { 5588 __u8 type; 5589 __u8 pfcen; 5590 __be16 r10[3]; 5591 __be64 r11; 5592 } pfc; 5593 struct fw_port_app_priority { 5594 __u8 type; 5595 __u8 r10[2]; 5596 __u8 idx; 5597 __u8 user_prio_map; 5598 __u8 sel_field; 5599 __be16 protocolid; 5600 __be64 r12; 5601 } app_priority; 5602 struct fw_port_dcb_control { 5603 __u8 type; 5604 __u8 all_syncd_pkd; 5605 __be16 r10_lo[3]; 5606 __be64 r11; 5607 } control; 5608 } dcb; 5609 } u; 5610 }; 5611 5612 #define S_FW_PORT_CMD_READ 22 5613 #define M_FW_PORT_CMD_READ 0x1 5614 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 5615 #define G_FW_PORT_CMD_READ(x) \ 5616 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 5617 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 5618 5619 #define S_FW_PORT_CMD_PORTID 0 5620 #define M_FW_PORT_CMD_PORTID 0xf 5621 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 5622 #define G_FW_PORT_CMD_PORTID(x) \ 5623 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 5624 5625 #define S_FW_PORT_CMD_ACTION 16 5626 #define M_FW_PORT_CMD_ACTION 0xffff 5627 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 5628 #define G_FW_PORT_CMD_ACTION(x) \ 5629 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 5630 5631 #define S_FW_PORT_CMD_OVLAN3 7 5632 #define M_FW_PORT_CMD_OVLAN3 0x1 5633 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 5634 #define G_FW_PORT_CMD_OVLAN3(x) \ 5635 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 5636 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 5637 5638 #define S_FW_PORT_CMD_OVLAN2 6 5639 #define M_FW_PORT_CMD_OVLAN2 0x1 5640 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 5641 #define G_FW_PORT_CMD_OVLAN2(x) \ 5642 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 5643 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 5644 5645 #define S_FW_PORT_CMD_OVLAN1 5 5646 #define M_FW_PORT_CMD_OVLAN1 0x1 5647 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 5648 #define G_FW_PORT_CMD_OVLAN1(x) \ 5649 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 5650 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 5651 5652 #define S_FW_PORT_CMD_OVLAN0 4 5653 #define M_FW_PORT_CMD_OVLAN0 0x1 5654 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 5655 #define G_FW_PORT_CMD_OVLAN0(x) \ 5656 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 5657 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 5658 5659 #define S_FW_PORT_CMD_IVLAN0 3 5660 #define M_FW_PORT_CMD_IVLAN0 0x1 5661 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 5662 #define G_FW_PORT_CMD_IVLAN0(x) \ 5663 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 5664 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 5665 5666 #define S_FW_PORT_CMD_TXIPG 3 5667 #define M_FW_PORT_CMD_TXIPG 0x1fff 5668 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 5669 #define G_FW_PORT_CMD_TXIPG(x) \ 5670 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 5671 5672 #define S_FW_PORT_CMD_FORCE_PINFO 0 5673 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 5674 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 5675 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 5676 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 5677 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 5678 5679 #define S_FW_PORT_CMD_LSTATUS 31 5680 #define M_FW_PORT_CMD_LSTATUS 0x1 5681 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 5682 #define G_FW_PORT_CMD_LSTATUS(x) \ 5683 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 5684 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 5685 5686 #define S_FW_PORT_CMD_LSPEED 24 5687 #define M_FW_PORT_CMD_LSPEED 0x3f 5688 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 5689 #define G_FW_PORT_CMD_LSPEED(x) \ 5690 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 5691 5692 #define S_FW_PORT_CMD_TXPAUSE 23 5693 #define M_FW_PORT_CMD_TXPAUSE 0x1 5694 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 5695 #define G_FW_PORT_CMD_TXPAUSE(x) \ 5696 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 5697 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 5698 5699 #define S_FW_PORT_CMD_RXPAUSE 22 5700 #define M_FW_PORT_CMD_RXPAUSE 0x1 5701 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 5702 #define G_FW_PORT_CMD_RXPAUSE(x) \ 5703 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 5704 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 5705 5706 #define S_FW_PORT_CMD_MDIOCAP 21 5707 #define M_FW_PORT_CMD_MDIOCAP 0x1 5708 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 5709 #define G_FW_PORT_CMD_MDIOCAP(x) \ 5710 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 5711 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 5712 5713 #define S_FW_PORT_CMD_MDIOADDR 16 5714 #define M_FW_PORT_CMD_MDIOADDR 0x1f 5715 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 5716 #define G_FW_PORT_CMD_MDIOADDR(x) \ 5717 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 5718 5719 #define S_FW_PORT_CMD_LPTXPAUSE 15 5720 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 5721 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 5722 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 5723 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 5724 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 5725 5726 #define S_FW_PORT_CMD_LPRXPAUSE 14 5727 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 5728 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 5729 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 5730 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 5731 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 5732 5733 #define S_FW_PORT_CMD_PTYPE 8 5734 #define M_FW_PORT_CMD_PTYPE 0x1f 5735 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 5736 #define G_FW_PORT_CMD_PTYPE(x) \ 5737 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 5738 5739 #define S_FW_PORT_CMD_LINKDNRC 5 5740 #define M_FW_PORT_CMD_LINKDNRC 0x7 5741 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 5742 #define G_FW_PORT_CMD_LINKDNRC(x) \ 5743 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 5744 5745 #define S_FW_PORT_CMD_MODTYPE 0 5746 #define M_FW_PORT_CMD_MODTYPE 0x1f 5747 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 5748 #define G_FW_PORT_CMD_MODTYPE(x) \ 5749 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 5750 5751 #define S_FW_PORT_CMD_DIAGOP 24 5752 #define M_FW_PORT_CMD_DIAGOP 0xff 5753 #define V_FW_PORT_CMD_DIAGOP(x) ((x) << S_FW_PORT_CMD_DIAGOP) 5754 #define G_FW_PORT_CMD_DIAGOP(x) \ 5755 (((x) >> S_FW_PORT_CMD_DIAGOP) & M_FW_PORT_CMD_DIAGOP) 5756 5757 #define S_FW_PORT_CMD_DIAGVAL 0 5758 #define M_FW_PORT_CMD_DIAGVAL 0xffffff 5759 #define V_FW_PORT_CMD_DIAGVAL(x) ((x) << S_FW_PORT_CMD_DIAGVAL) 5760 #define G_FW_PORT_CMD_DIAGVAL(x) \ 5761 (((x) >> S_FW_PORT_CMD_DIAGVAL) & M_FW_PORT_CMD_DIAGVAL) 5762 5763 #define S_FW_PORT_CMD_APPLY 7 5764 #define M_FW_PORT_CMD_APPLY 0x1 5765 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 5766 #define G_FW_PORT_CMD_APPLY(x) \ 5767 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 5768 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 5769 5770 #define S_FW_PORT_CMD_ALL_SYNCD 7 5771 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 5772 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 5773 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 5774 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 5775 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 5776 5777 /* 5778 * These are configured into the VPD and hence tools that generate 5779 * VPD may use this enumeration. 5780 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 5781 */ 5782 enum fw_port_type { 5783 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 5784 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 5785 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 5786 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G */ 5787 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M? */ 5788 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 5789 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 5790 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 5791 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G */ 5792 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 5793 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP ANGE */ 5794 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP ANGE */ 5795 5796 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PTYPE 5797 }; 5798 5799 /* These are read from module's EEPROM and determined once the 5800 module is inserted. */ 5801 enum fw_port_module_type { 5802 FW_PORT_MOD_TYPE_NA = 0x0, 5803 FW_PORT_MOD_TYPE_LR = 0x1, 5804 FW_PORT_MOD_TYPE_SR = 0x2, 5805 FW_PORT_MOD_TYPE_ER = 0x3, 5806 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 5807 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 5808 FW_PORT_MOD_TYPE_LRM = 0x6, 5809 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 5810 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 5811 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 5812 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 5813 }; 5814 5815 /* used by FW and tools may use this to generate VPD */ 5816 enum fw_port_mod_sub_type { 5817 FW_PORT_MOD_SUB_TYPE_NA, 5818 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 5819 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 5820 5821 /* 5822 * The following will never been in the VPD. They are TWINAX cable 5823 * lengths decoded from SFP+ module i2c PROMs. These should almost 5824 * certainly go somewhere else ... 5825 */ 5826 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 5827 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 5828 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 5829 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 5830 }; 5831 5832 /* link down reason codes (3b) */ 5833 enum fw_port_link_dn_rc { 5834 FW_PORT_LINK_DN_RC_NONE, 5835 FW_PORT_LINK_DN_RC_REMFLT, 5836 FW_PORT_LINK_DN_ANEG_F, 5837 FW_PORT_LINK_DN_MS_RES_F, 5838 FW_PORT_LINK_DN_OVERHEAT, 5839 FW_PORT_LINK_DN_UNKNOWN 5840 }; 5841 5842 /* port stats */ 5843 #define FW_NUM_PORT_STATS 50 5844 #define FW_NUM_PORT_TX_STATS 23 5845 #define FW_NUM_PORT_RX_STATS 27 5846 5847 enum fw_port_stats_tx_index { 5848 FW_STAT_TX_PORT_BYTES_IX, 5849 FW_STAT_TX_PORT_FRAMES_IX, 5850 FW_STAT_TX_PORT_BCAST_IX, 5851 FW_STAT_TX_PORT_MCAST_IX, 5852 FW_STAT_TX_PORT_UCAST_IX, 5853 FW_STAT_TX_PORT_ERROR_IX, 5854 FW_STAT_TX_PORT_64B_IX, 5855 FW_STAT_TX_PORT_65B_127B_IX, 5856 FW_STAT_TX_PORT_128B_255B_IX, 5857 FW_STAT_TX_PORT_256B_511B_IX, 5858 FW_STAT_TX_PORT_512B_1023B_IX, 5859 FW_STAT_TX_PORT_1024B_1518B_IX, 5860 FW_STAT_TX_PORT_1519B_MAX_IX, 5861 FW_STAT_TX_PORT_DROP_IX, 5862 FW_STAT_TX_PORT_PAUSE_IX, 5863 FW_STAT_TX_PORT_PPP0_IX, 5864 FW_STAT_TX_PORT_PPP1_IX, 5865 FW_STAT_TX_PORT_PPP2_IX, 5866 FW_STAT_TX_PORT_PPP3_IX, 5867 FW_STAT_TX_PORT_PPP4_IX, 5868 FW_STAT_TX_PORT_PPP5_IX, 5869 FW_STAT_TX_PORT_PPP6_IX, 5870 FW_STAT_TX_PORT_PPP7_IX 5871 }; 5872 5873 enum fw_port_stat_rx_index { 5874 FW_STAT_RX_PORT_BYTES_IX, 5875 FW_STAT_RX_PORT_FRAMES_IX, 5876 FW_STAT_RX_PORT_BCAST_IX, 5877 FW_STAT_RX_PORT_MCAST_IX, 5878 FW_STAT_RX_PORT_UCAST_IX, 5879 FW_STAT_RX_PORT_MTU_ERROR_IX, 5880 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 5881 FW_STAT_RX_PORT_CRC_ERROR_IX, 5882 FW_STAT_RX_PORT_LEN_ERROR_IX, 5883 FW_STAT_RX_PORT_SYM_ERROR_IX, 5884 FW_STAT_RX_PORT_64B_IX, 5885 FW_STAT_RX_PORT_65B_127B_IX, 5886 FW_STAT_RX_PORT_128B_255B_IX, 5887 FW_STAT_RX_PORT_256B_511B_IX, 5888 FW_STAT_RX_PORT_512B_1023B_IX, 5889 FW_STAT_RX_PORT_1024B_1518B_IX, 5890 FW_STAT_RX_PORT_1519B_MAX_IX, 5891 FW_STAT_RX_PORT_PAUSE_IX, 5892 FW_STAT_RX_PORT_PPP0_IX, 5893 FW_STAT_RX_PORT_PPP1_IX, 5894 FW_STAT_RX_PORT_PPP2_IX, 5895 FW_STAT_RX_PORT_PPP3_IX, 5896 FW_STAT_RX_PORT_PPP4_IX, 5897 FW_STAT_RX_PORT_PPP5_IX, 5898 FW_STAT_RX_PORT_PPP6_IX, 5899 FW_STAT_RX_PORT_PPP7_IX, 5900 FW_STAT_RX_PORT_LESS_64B_IX 5901 }; 5902 5903 struct fw_port_stats_cmd { 5904 __be32 op_to_portid; 5905 __be32 retval_len16; 5906 union fw_port_stats { 5907 struct fw_port_stats_ctl { 5908 __u8 nstats_bg_bm; 5909 __u8 tx_ix; 5910 __be16 r6; 5911 __be32 r7; 5912 __be64 stat0; 5913 __be64 stat1; 5914 __be64 stat2; 5915 __be64 stat3; 5916 __be64 stat4; 5917 __be64 stat5; 5918 } ctl; 5919 struct fw_port_stats_all { 5920 __be64 tx_bytes; 5921 __be64 tx_frames; 5922 __be64 tx_bcast; 5923 __be64 tx_mcast; 5924 __be64 tx_ucast; 5925 __be64 tx_error; 5926 __be64 tx_64b; 5927 __be64 tx_65b_127b; 5928 __be64 tx_128b_255b; 5929 __be64 tx_256b_511b; 5930 __be64 tx_512b_1023b; 5931 __be64 tx_1024b_1518b; 5932 __be64 tx_1519b_max; 5933 __be64 tx_drop; 5934 __be64 tx_pause; 5935 __be64 tx_ppp0; 5936 __be64 tx_ppp1; 5937 __be64 tx_ppp2; 5938 __be64 tx_ppp3; 5939 __be64 tx_ppp4; 5940 __be64 tx_ppp5; 5941 __be64 tx_ppp6; 5942 __be64 tx_ppp7; 5943 __be64 rx_bytes; 5944 __be64 rx_frames; 5945 __be64 rx_bcast; 5946 __be64 rx_mcast; 5947 __be64 rx_ucast; 5948 __be64 rx_mtu_error; 5949 __be64 rx_mtu_crc_error; 5950 __be64 rx_crc_error; 5951 __be64 rx_len_error; 5952 __be64 rx_sym_error; 5953 __be64 rx_64b; 5954 __be64 rx_65b_127b; 5955 __be64 rx_128b_255b; 5956 __be64 rx_256b_511b; 5957 __be64 rx_512b_1023b; 5958 __be64 rx_1024b_1518b; 5959 __be64 rx_1519b_max; 5960 __be64 rx_pause; 5961 __be64 rx_ppp0; 5962 __be64 rx_ppp1; 5963 __be64 rx_ppp2; 5964 __be64 rx_ppp3; 5965 __be64 rx_ppp4; 5966 __be64 rx_ppp5; 5967 __be64 rx_ppp6; 5968 __be64 rx_ppp7; 5969 __be64 rx_less_64b; 5970 __be64 rx_bg_drop; 5971 __be64 rx_bg_trunc; 5972 } all; 5973 } u; 5974 }; 5975 5976 #define S_FW_PORT_STATS_CMD_NSTATS 4 5977 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 5978 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 5979 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 5980 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 5981 5982 #define S_FW_PORT_STATS_CMD_BG_BM 0 5983 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 5984 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 5985 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 5986 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 5987 5988 #define S_FW_PORT_STATS_CMD_TX 7 5989 #define M_FW_PORT_STATS_CMD_TX 0x1 5990 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 5991 #define G_FW_PORT_STATS_CMD_TX(x) \ 5992 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 5993 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 5994 5995 #define S_FW_PORT_STATS_CMD_IX 0 5996 #define M_FW_PORT_STATS_CMD_IX 0x3f 5997 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 5998 #define G_FW_PORT_STATS_CMD_IX(x) \ 5999 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 6000 6001 /* port loopback stats */ 6002 #define FW_NUM_LB_STATS 14 6003 enum fw_port_lb_stats_index { 6004 FW_STAT_LB_PORT_BYTES_IX, 6005 FW_STAT_LB_PORT_FRAMES_IX, 6006 FW_STAT_LB_PORT_BCAST_IX, 6007 FW_STAT_LB_PORT_MCAST_IX, 6008 FW_STAT_LB_PORT_UCAST_IX, 6009 FW_STAT_LB_PORT_ERROR_IX, 6010 FW_STAT_LB_PORT_64B_IX, 6011 FW_STAT_LB_PORT_65B_127B_IX, 6012 FW_STAT_LB_PORT_128B_255B_IX, 6013 FW_STAT_LB_PORT_256B_511B_IX, 6014 FW_STAT_LB_PORT_512B_1023B_IX, 6015 FW_STAT_LB_PORT_1024B_1518B_IX, 6016 FW_STAT_LB_PORT_1519B_MAX_IX, 6017 FW_STAT_LB_PORT_DROP_FRAMES_IX 6018 }; 6019 6020 struct fw_port_lb_stats_cmd { 6021 __be32 op_to_lbport; 6022 __be32 retval_len16; 6023 union fw_port_lb_stats { 6024 struct fw_port_lb_stats_ctl { 6025 __u8 nstats_bg_bm; 6026 __u8 ix_pkd; 6027 __be16 r6; 6028 __be32 r7; 6029 __be64 stat0; 6030 __be64 stat1; 6031 __be64 stat2; 6032 __be64 stat3; 6033 __be64 stat4; 6034 __be64 stat5; 6035 } ctl; 6036 struct fw_port_lb_stats_all { 6037 __be64 tx_bytes; 6038 __be64 tx_frames; 6039 __be64 tx_bcast; 6040 __be64 tx_mcast; 6041 __be64 tx_ucast; 6042 __be64 tx_error; 6043 __be64 tx_64b; 6044 __be64 tx_65b_127b; 6045 __be64 tx_128b_255b; 6046 __be64 tx_256b_511b; 6047 __be64 tx_512b_1023b; 6048 __be64 tx_1024b_1518b; 6049 __be64 tx_1519b_max; 6050 __be64 rx_lb_drop; 6051 __be64 rx_lb_trunc; 6052 } all; 6053 } u; 6054 }; 6055 6056 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 6057 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 6058 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6059 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 6060 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 6061 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 6062 6063 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 6064 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 6065 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6066 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 6067 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 6068 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 6069 6070 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 6071 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 6072 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 6073 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 6074 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 6075 6076 #define S_FW_PORT_LB_STATS_CMD_IX 0 6077 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 6078 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 6079 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 6080 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 6081 6082 /* Trace related defines */ 6083 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 6084 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 6085 6086 struct fw_port_trace_cmd { 6087 __be32 op_to_portid; 6088 __be32 retval_len16; 6089 __be16 traceen_to_pciech; 6090 __be16 qnum; 6091 __be32 r5; 6092 }; 6093 6094 #define S_FW_PORT_TRACE_CMD_PORTID 0 6095 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 6096 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 6097 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 6098 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 6099 6100 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 6101 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 6102 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 6103 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 6104 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 6105 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 6106 6107 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 6108 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 6109 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 6110 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 6111 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 6112 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 6113 6114 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 6115 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 6116 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 6117 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 6118 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 6119 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 6120 6121 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 6122 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 6123 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6124 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6125 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 6126 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 6127 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 6128 6129 #define S_FW_PORT_TRACE_CMD_PCIECH 6 6130 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 6131 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 6132 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 6133 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 6134 6135 struct fw_port_trace_mmap_cmd { 6136 __be32 op_to_portid; 6137 __be32 retval_len16; 6138 __be32 fid_to_skipoffset; 6139 __be32 minpktsize_capturemax; 6140 __u8 map[224]; 6141 }; 6142 6143 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 6144 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 6145 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6146 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 6147 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 6148 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 6149 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 6150 6151 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 6152 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 6153 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 6154 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 6155 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 6156 6157 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 6158 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 6159 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6160 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6161 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 6162 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 6163 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 6164 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 6165 6166 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 6167 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 6168 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6169 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6170 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 6171 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 6172 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 6173 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN \ 6174 V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 6175 6176 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 6177 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 6178 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6179 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6180 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 6181 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 6182 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 6183 6184 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 6185 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 6186 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6187 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6188 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 6189 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 6190 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 6191 6192 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 6193 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 6194 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6195 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6196 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 6197 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 6198 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 6199 6200 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 6201 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 6202 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6203 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6204 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 6205 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 6206 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 6207 6208 struct fw_rss_ind_tbl_cmd { 6209 __be32 op_to_viid; 6210 __be32 retval_len16; 6211 __be16 niqid; 6212 __be16 startidx; 6213 __be32 r3; 6214 __be32 iq0_to_iq2; 6215 __be32 iq3_to_iq5; 6216 __be32 iq6_to_iq8; 6217 __be32 iq9_to_iq11; 6218 __be32 iq12_to_iq14; 6219 __be32 iq15_to_iq17; 6220 __be32 iq18_to_iq20; 6221 __be32 iq21_to_iq23; 6222 __be32 iq24_to_iq26; 6223 __be32 iq27_to_iq29; 6224 __be32 iq30_iq31; 6225 __be32 r15_lo; 6226 }; 6227 6228 #define S_FW_RSS_IND_TBL_CMD_VIID 0 6229 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 6230 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 6231 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 6232 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 6233 6234 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 6235 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 6236 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 6237 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 6238 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 6239 6240 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 6241 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 6242 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 6243 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 6244 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 6245 6246 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 6247 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 6248 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 6249 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 6250 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 6251 6252 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 6253 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 6254 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 6255 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 6256 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 6257 6258 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 6259 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 6260 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 6261 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 6262 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 6263 6264 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 6265 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 6266 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 6267 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 6268 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 6269 6270 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 6271 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 6272 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 6273 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 6274 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 6275 6276 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 6277 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 6278 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 6279 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 6280 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 6281 6282 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 6283 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 6284 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 6285 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 6286 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 6287 6288 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 6289 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 6290 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 6291 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 6292 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 6293 6294 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 6295 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 6296 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 6297 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 6298 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 6299 6300 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 6301 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 6302 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 6303 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 6304 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 6305 6306 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 6307 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 6308 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 6309 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 6310 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 6311 6312 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 6313 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 6314 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 6315 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 6316 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 6317 6318 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 6319 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 6320 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 6321 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 6322 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 6323 6324 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 6325 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 6326 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 6327 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 6328 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 6329 6330 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 6331 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 6332 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 6333 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 6334 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 6335 6336 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 6337 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 6338 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 6339 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 6340 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 6341 6342 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 6343 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 6344 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 6345 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 6346 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 6347 6348 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 6349 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 6350 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 6351 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 6352 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 6353 6354 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 6355 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 6356 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 6357 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 6358 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 6359 6360 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 6361 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 6362 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 6363 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 6364 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 6365 6366 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 6367 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 6368 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 6369 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 6370 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 6371 6372 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 6373 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 6374 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 6375 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 6376 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 6377 6378 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 6379 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 6380 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 6381 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 6382 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 6383 6384 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 6385 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 6386 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 6387 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 6388 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 6389 6390 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 6391 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 6392 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 6393 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 6394 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 6395 6396 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 6397 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 6398 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 6399 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 6400 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 6401 6402 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 6403 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 6404 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 6405 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 6406 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 6407 6408 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 6409 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 6410 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 6411 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 6412 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 6413 6414 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 6415 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 6416 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 6417 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 6418 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 6419 6420 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 6421 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 6422 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 6423 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 6424 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 6425 6426 struct fw_rss_glb_config_cmd { 6427 __be32 op_to_write; 6428 __be32 retval_len16; 6429 union fw_rss_glb_config { 6430 struct fw_rss_glb_config_manual { 6431 __be32 mode_pkd; 6432 __be32 r3; 6433 __be64 r4; 6434 __be64 r5; 6435 } manual; 6436 struct fw_rss_glb_config_basicvirtual { 6437 __be32 mode_pkd; 6438 __be32 synmapen_to_hashtoeplitz; 6439 __be64 r8; 6440 __be64 r9; 6441 } basicvirtual; 6442 } u; 6443 }; 6444 6445 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 6446 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 6447 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 6448 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 6449 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 6450 6451 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 6452 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 6453 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 6454 6455 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 6456 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 6457 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6458 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6459 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 6460 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 6461 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 6462 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN \ 6463 V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 6464 6465 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 6466 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 6467 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6468 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6469 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 6470 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 6471 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 6472 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 6473 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 6474 6475 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 6476 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 6477 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6478 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6479 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 6480 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 6481 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 6482 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 6483 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 6484 6485 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 6486 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 6487 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6488 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6489 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 6490 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 6491 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 6492 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 6493 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 6494 6495 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 6496 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 6497 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6498 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6499 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 6500 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 6501 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 6502 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 6503 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 6504 6505 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 6506 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 6507 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6508 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6509 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 6510 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 6511 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 6512 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN \ 6513 V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 6514 6515 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 6516 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 6517 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6518 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6519 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 6520 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 6521 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 6522 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN \ 6523 V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 6524 6525 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 6526 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 6527 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6528 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6529 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 6530 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 6531 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 6532 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 6533 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 6534 6535 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 6536 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 6537 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6538 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6539 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 6540 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 6541 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 6542 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 6543 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 6544 6545 struct fw_rss_vi_config_cmd { 6546 __be32 op_to_viid; 6547 __be32 retval_len16; 6548 union fw_rss_vi_config { 6549 struct fw_rss_vi_config_manual { 6550 __be64 r3; 6551 __be64 r4; 6552 __be64 r5; 6553 } manual; 6554 struct fw_rss_vi_config_basicvirtual { 6555 __be32 r6; 6556 __be32 defaultq_to_udpen; 6557 __be64 r9; 6558 __be64 r10; 6559 } basicvirtual; 6560 } u; 6561 }; 6562 6563 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 6564 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 6565 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 6566 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 6567 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 6568 6569 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 6570 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 6571 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6572 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6573 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 6574 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 6575 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 6576 6577 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 6578 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 6579 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6580 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6581 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 6582 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 6583 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 6584 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 6585 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 6586 6587 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 6588 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 6589 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6590 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6591 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 6592 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 6593 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 6594 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 6595 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 6596 6597 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 6598 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 6599 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6600 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6601 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 6602 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 6603 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 6604 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 6605 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 6606 6607 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 6608 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 6609 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6610 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6611 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 6612 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 6613 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 6614 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 6615 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 6616 6617 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 6618 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 6619 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 6620 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 6621 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 6622 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 6623 6624 enum fw_sched_sc { 6625 FW_SCHED_SC_CONFIG = 0, 6626 FW_SCHED_SC_PARAMS = 1, 6627 }; 6628 6629 enum fw_sched_type { 6630 FW_SCHED_TYPE_PKTSCHED = 0, 6631 FW_SCHED_TYPE_STREAMSCHED = 1, 6632 }; 6633 6634 enum fw_sched_params_level { 6635 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 6636 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 6637 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 6638 FW_SCHED_PARAMS_LEVEL_CH_WRR = 3, 6639 }; 6640 6641 enum fw_sched_params_mode { 6642 FW_SCHED_PARAMS_MODE_CLASS = 0, 6643 FW_SCHED_PARAMS_MODE_FLOW = 1, 6644 }; 6645 6646 enum fw_sched_params_unit { 6647 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 6648 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 6649 }; 6650 6651 enum fw_sched_params_rate { 6652 FW_SCHED_PARAMS_RATE_REL = 0, 6653 FW_SCHED_PARAMS_RATE_ABS = 1, 6654 }; 6655 6656 struct fw_sched_cmd { 6657 __be32 op_to_write; 6658 __be32 retval_len16; 6659 union fw_sched { 6660 struct fw_sched_config { 6661 __u8 sc; 6662 __u8 type; 6663 __u8 minmaxen; 6664 __u8 r3[5]; 6665 } config; 6666 struct fw_sched_params { 6667 __u8 sc; 6668 __u8 type; 6669 __u8 level; 6670 __u8 mode; 6671 __u8 unit; 6672 __u8 rate; 6673 __u8 ch; 6674 __u8 cl; 6675 __be32 min; 6676 __be32 max; 6677 __be16 weight; 6678 __be16 pktsize; 6679 __be32 r4; 6680 } params; 6681 } u; 6682 }; 6683 6684 /* 6685 * length of the formatting string 6686 */ 6687 #define FW_DEVLOG_FMT_LEN 192 6688 6689 /* 6690 * maximum number of the formatting string parameters 6691 */ 6692 #define FW_DEVLOG_FMT_PARAMS_NUM 8 6693 6694 /* 6695 * priority levels 6696 */ 6697 enum fw_devlog_level { 6698 FW_DEVLOG_LEVEL_EMERG = 0x0, 6699 FW_DEVLOG_LEVEL_CRIT = 0x1, 6700 FW_DEVLOG_LEVEL_ERR = 0x2, 6701 FW_DEVLOG_LEVEL_NOTICE = 0x3, 6702 FW_DEVLOG_LEVEL_INFO = 0x4, 6703 FW_DEVLOG_LEVEL_DEBUG = 0x5, 6704 FW_DEVLOG_LEVEL_MAX = 0x5, 6705 }; 6706 6707 /* 6708 * facilities that may send a log message 6709 */ 6710 enum fw_devlog_facility { 6711 FW_DEVLOG_FACILITY_CORE = 0x00, 6712 FW_DEVLOG_FACILITY_SCHED = 0x02, 6713 FW_DEVLOG_FACILITY_TIMER = 0x04, 6714 FW_DEVLOG_FACILITY_RES = 0x06, 6715 FW_DEVLOG_FACILITY_HW = 0x08, 6716 FW_DEVLOG_FACILITY_FLR = 0x10, 6717 FW_DEVLOG_FACILITY_DMAQ = 0x12, 6718 FW_DEVLOG_FACILITY_PHY = 0x14, 6719 FW_DEVLOG_FACILITY_MAC = 0x16, 6720 FW_DEVLOG_FACILITY_PORT = 0x18, 6721 FW_DEVLOG_FACILITY_VI = 0x1A, 6722 FW_DEVLOG_FACILITY_FILTER = 0x1C, 6723 FW_DEVLOG_FACILITY_ACL = 0x1E, 6724 FW_DEVLOG_FACILITY_TM = 0x20, 6725 FW_DEVLOG_FACILITY_QFC = 0x22, 6726 FW_DEVLOG_FACILITY_DCB = 0x24, 6727 FW_DEVLOG_FACILITY_ETH = 0x26, 6728 FW_DEVLOG_FACILITY_OFLD = 0x28, 6729 FW_DEVLOG_FACILITY_RI = 0x2A, 6730 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 6731 FW_DEVLOG_FACILITY_FCOE = 0x2E, 6732 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 6733 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 6734 FW_DEVLOG_FACILITY_MAX = 0x32, 6735 }; 6736 6737 /* 6738 * log message format 6739 */ 6740 struct fw_devlog_e { 6741 __be64 timestamp; 6742 __be32 seqno; 6743 __be16 reserved1; 6744 __u8 level; 6745 __u8 facility; 6746 __u8 fmt[FW_DEVLOG_FMT_LEN]; 6747 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 6748 __be32 reserved3[4]; 6749 }; 6750 6751 struct fw_devlog_cmd { 6752 __be32 op_to_write; 6753 __be32 retval_len16; 6754 __u8 level; 6755 __u8 r2[7]; 6756 __be32 memtype_devlog_memaddr16_devlog; 6757 __be32 memsize_devlog; 6758 __be32 r3[2]; 6759 }; 6760 6761 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 6762 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 6763 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 6764 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 6765 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 6766 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 6767 6768 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 6769 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 6770 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 6771 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 6772 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 6773 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 6774 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 6775 6776 enum fw_watchdog_actions { 6777 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 6778 FW_WATCHDOG_ACTION_FLR = 1, 6779 FW_WATCHDOG_ACTION_BYPASS = 2, 6780 FW_WATCHDOG_ACTION_TMPCHK = 3, 6781 6782 FW_WATCHDOG_ACTION_MAX = 4, 6783 }; 6784 6785 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 6786 6787 struct fw_watchdog_cmd { 6788 __be32 op_to_vfn; 6789 __be32 retval_len16; 6790 __be32 timeout; 6791 __be32 action; 6792 }; 6793 6794 #define S_FW_WATCHDOG_CMD_PFN 8 6795 #define M_FW_WATCHDOG_CMD_PFN 0x7 6796 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 6797 #define G_FW_WATCHDOG_CMD_PFN(x) \ 6798 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 6799 6800 #define S_FW_WATCHDOG_CMD_VFN 0 6801 #define M_FW_WATCHDOG_CMD_VFN 0xff 6802 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 6803 #define G_FW_WATCHDOG_CMD_VFN(x) \ 6804 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 6805 6806 struct fw_clip_cmd { 6807 __be32 op_to_write; 6808 __be32 alloc_to_len16; 6809 __be64 ip_hi; 6810 __be64 ip_lo; 6811 __be32 r4[2]; 6812 }; 6813 6814 #define S_FW_CLIP_CMD_ALLOC 31 6815 #define M_FW_CLIP_CMD_ALLOC 0x1 6816 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 6817 #define G_FW_CLIP_CMD_ALLOC(x) \ 6818 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 6819 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 6820 6821 #define S_FW_CLIP_CMD_FREE 30 6822 #define M_FW_CLIP_CMD_FREE 0x1 6823 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 6824 #define G_FW_CLIP_CMD_FREE(x) \ 6825 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 6826 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 6827 6828 /****************************************************************************** 6829 * F O i S C S I C O M M A N D s 6830 **************************************/ 6831 6832 #define FW_CHNET_IFACE_ADDR_MAX 3 6833 6834 enum fw_chnet_iface_cmd_subop { 6835 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 6836 6837 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 6838 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 6839 6840 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 6841 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 6842 6843 FW_CHNET_IFACE_CMD_SUBOP_MAX, 6844 }; 6845 6846 struct fw_chnet_iface_cmd { 6847 __be32 op_to_portid; 6848 __be32 retval_len16; 6849 __u8 subop; 6850 __u8 r2[3]; 6851 __be32 ifid_ifstate; 6852 __be16 mtu; 6853 __be16 vlanid; 6854 __be32 r3; 6855 __be16 r4; 6856 __u8 mac[6]; 6857 }; 6858 6859 #define S_FW_CHNET_IFACE_CMD_PORTID 0 6860 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 6861 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 6862 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 6863 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 6864 6865 #define S_FW_CHNET_IFACE_CMD_IFID 8 6866 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 6867 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 6868 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 6869 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 6870 6871 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 6872 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 6873 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 6874 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 6875 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 6876 6877 /****************************************************************************** 6878 * F O F C O E C O M M A N D s 6879 ************************************/ 6880 6881 struct fw_fcoe_res_info_cmd { 6882 __be32 op_to_read; 6883 __be32 retval_len16; 6884 __be16 e_d_tov; 6885 __be16 r_a_tov_seq; 6886 __be16 r_a_tov_els; 6887 __be16 r_r_tov; 6888 __be32 max_xchgs; 6889 __be32 max_ssns; 6890 __be32 used_xchgs; 6891 __be32 used_ssns; 6892 __be32 max_fcfs; 6893 __be32 max_vnps; 6894 __be32 used_fcfs; 6895 __be32 used_vnps; 6896 }; 6897 6898 struct fw_fcoe_link_cmd { 6899 __be32 op_to_portid; 6900 __be32 retval_len16; 6901 __be32 sub_opcode_fcfi; 6902 __u8 r3; 6903 __u8 lstatus; 6904 __be16 flags; 6905 __u8 r4; 6906 __u8 set_vlan; 6907 __be16 vlan_id; 6908 __be32 vnpi_pkd; 6909 __be16 r6; 6910 __u8 phy_mac[6]; 6911 __u8 vnport_wwnn[8]; 6912 __u8 vnport_wwpn[8]; 6913 }; 6914 6915 #define S_FW_FCOE_LINK_CMD_PORTID 0 6916 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 6917 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 6918 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 6919 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 6920 6921 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 6922 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 6923 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 6924 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 6925 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 6926 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 6927 6928 #define S_FW_FCOE_LINK_CMD_FCFI 0 6929 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 6930 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 6931 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 6932 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 6933 6934 #define S_FW_FCOE_LINK_CMD_VNPI 0 6935 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 6936 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 6937 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 6938 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 6939 6940 struct fw_fcoe_vnp_cmd { 6941 __be32 op_to_fcfi; 6942 __be32 alloc_to_len16; 6943 __be32 gen_wwn_to_vnpi; 6944 __be32 vf_id; 6945 __be16 iqid; 6946 __u8 vnport_mac[6]; 6947 __u8 vnport_wwnn[8]; 6948 __u8 vnport_wwpn[8]; 6949 __u8 cmn_srv_parms[16]; 6950 __u8 clsp_word_0_1[8]; 6951 }; 6952 6953 #define S_FW_FCOE_VNP_CMD_FCFI 0 6954 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 6955 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 6956 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 6957 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 6958 6959 #define S_FW_FCOE_VNP_CMD_ALLOC 31 6960 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 6961 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 6962 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 6963 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 6964 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 6965 6966 #define S_FW_FCOE_VNP_CMD_FREE 30 6967 #define M_FW_FCOE_VNP_CMD_FREE 0x1 6968 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 6969 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 6970 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 6971 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 6972 6973 #define S_FW_FCOE_VNP_CMD_MODIFY 29 6974 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 6975 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 6976 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 6977 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 6978 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 6979 6980 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 6981 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 6982 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 6983 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 6984 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 6985 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 6986 6987 #define S_FW_FCOE_VNP_CMD_PERSIST 21 6988 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 6989 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 6990 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 6991 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 6992 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 6993 6994 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 6995 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 6996 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 6997 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 6998 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 6999 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 7000 7001 #define S_FW_FCOE_VNP_CMD_VNPI 0 7002 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 7003 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 7004 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 7005 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 7006 7007 struct fw_fcoe_sparams_cmd { 7008 __be32 op_to_portid; 7009 __be32 retval_len16; 7010 __u8 r3[7]; 7011 __u8 cos; 7012 __u8 lport_wwnn[8]; 7013 __u8 lport_wwpn[8]; 7014 __u8 cmn_srv_parms[16]; 7015 __u8 cls_srv_parms[16]; 7016 }; 7017 7018 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 7019 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 7020 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 7021 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 7022 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 7023 7024 struct fw_fcoe_stats_cmd { 7025 __be32 op_to_flowid; 7026 __be32 free_to_len16; 7027 union fw_fcoe_stats { 7028 struct fw_fcoe_stats_ctl { 7029 __u8 nstats_port; 7030 __u8 port_valid_ix; 7031 __be16 r6; 7032 __be32 r7; 7033 __be64 stat0; 7034 __be64 stat1; 7035 __be64 stat2; 7036 __be64 stat3; 7037 __be64 stat4; 7038 __be64 stat5; 7039 } ctl; 7040 struct fw_fcoe_port_stats { 7041 __be64 tx_bcast_bytes; 7042 __be64 tx_bcast_frames; 7043 __be64 tx_mcast_bytes; 7044 __be64 tx_mcast_frames; 7045 __be64 tx_ucast_bytes; 7046 __be64 tx_ucast_frames; 7047 __be64 tx_drop_frames; 7048 __be64 tx_offload_bytes; 7049 __be64 tx_offload_frames; 7050 __be64 rx_bcast_bytes; 7051 __be64 rx_bcast_frames; 7052 __be64 rx_mcast_bytes; 7053 __be64 rx_mcast_frames; 7054 __be64 rx_ucast_bytes; 7055 __be64 rx_ucast_frames; 7056 __be64 rx_err_frames; 7057 } port_stats; 7058 struct fw_fcoe_fcf_stats { 7059 __be32 fip_tx_bytes; 7060 __be32 fip_tx_fr; 7061 __be64 fcf_ka; 7062 __be64 mcast_adv_rcvd; 7063 __be16 ucast_adv_rcvd; 7064 __be16 sol_sent; 7065 __be16 vlan_req; 7066 __be16 vlan_rpl; 7067 __be16 clr_vlink; 7068 __be16 link_down; 7069 __be16 link_up; 7070 __be16 logo; 7071 __be16 flogi_req; 7072 __be16 flogi_rpl; 7073 __be16 fdisc_req; 7074 __be16 fdisc_rpl; 7075 __be16 fka_prd_chg; 7076 __be16 fc_map_chg; 7077 __be16 vfid_chg; 7078 __u8 no_fka_req; 7079 __u8 no_vnp; 7080 } fcf_stats; 7081 struct fw_fcoe_pcb_stats { 7082 __be64 tx_bytes; 7083 __be64 tx_frames; 7084 __be64 rx_bytes; 7085 __be64 rx_frames; 7086 __be32 vnp_ka; 7087 __be32 unsol_els_rcvd; 7088 __be64 unsol_cmd_rcvd; 7089 __be16 implicit_logo; 7090 __be16 flogi_inv_sparm; 7091 __be16 fdisc_inv_sparm; 7092 __be16 flogi_rjt; 7093 __be16 fdisc_rjt; 7094 __be16 no_ssn; 7095 __be16 mac_flt_fail; 7096 __be16 inv_fr_rcvd; 7097 } pcb_stats; 7098 struct fw_fcoe_scb_stats { 7099 __be64 tx_bytes; 7100 __be64 tx_frames; 7101 __be64 rx_bytes; 7102 __be64 rx_frames; 7103 __be32 host_abrt_req; 7104 __be32 adap_auto_abrt; 7105 __be32 adap_abrt_rsp; 7106 __be32 host_ios_req; 7107 __be16 ssn_offl_ios; 7108 __be16 ssn_not_rdy_ios; 7109 __u8 rx_data_ddp_err; 7110 __u8 ddp_flt_set_err; 7111 __be16 rx_data_fr_err; 7112 __u8 bad_st_abrt_req; 7113 __u8 no_io_abrt_req; 7114 __u8 abort_tmo; 7115 __u8 abort_tmo_2; 7116 __be32 abort_req; 7117 __u8 no_ppod_res_tmo; 7118 __u8 bp_tmo; 7119 __u8 adap_auto_cls; 7120 __u8 no_io_cls_req; 7121 __be32 host_cls_req; 7122 __be64 unsol_cmd_rcvd; 7123 __be32 plogi_req_rcvd; 7124 __be32 prli_req_rcvd; 7125 __be16 logo_req_rcvd; 7126 __be16 prlo_req_rcvd; 7127 __be16 plogi_rjt_rcvd; 7128 __be16 prli_rjt_rcvd; 7129 __be32 adisc_req_rcvd; 7130 __be32 rscn_rcvd; 7131 __be32 rrq_req_rcvd; 7132 __be32 unsol_els_rcvd; 7133 __u8 adisc_rjt_rcvd; 7134 __u8 scr_rjt; 7135 __u8 ct_rjt; 7136 __u8 inval_bls_rcvd; 7137 __be32 ba_rjt_rcvd; 7138 } scb_stats; 7139 } u; 7140 }; 7141 7142 #define S_FW_FCOE_STATS_CMD_FLOWID 0 7143 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 7144 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 7145 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 7146 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 7147 7148 #define S_FW_FCOE_STATS_CMD_FREE 30 7149 #define M_FW_FCOE_STATS_CMD_FREE 0x1 7150 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 7151 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 7152 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 7153 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 7154 7155 #define S_FW_FCOE_STATS_CMD_NSTATS 4 7156 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 7157 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 7158 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 7159 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 7160 7161 #define S_FW_FCOE_STATS_CMD_PORT 0 7162 #define M_FW_FCOE_STATS_CMD_PORT 0x3 7163 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 7164 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 7165 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 7166 7167 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 7168 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 7169 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7170 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 7171 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 7172 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 7173 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 7174 7175 #define S_FW_FCOE_STATS_CMD_IX 0 7176 #define M_FW_FCOE_STATS_CMD_IX 0x3f 7177 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 7178 #define G_FW_FCOE_STATS_CMD_IX(x) \ 7179 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 7180 7181 struct fw_fcoe_fcf_cmd { 7182 __be32 op_to_fcfi; 7183 __be32 retval_len16; 7184 __be16 priority_pkd; 7185 __u8 mac[6]; 7186 __u8 name_id[8]; 7187 __u8 fabric[8]; 7188 __be16 vf_id; 7189 __be16 max_fcoe_size; 7190 __u8 vlan_id; 7191 __u8 fc_map[3]; 7192 __be32 fka_adv; 7193 __be32 r6; 7194 __u8 r7_hi; 7195 __u8 fpma_to_portid; 7196 __u8 spma_mac[6]; 7197 __be64 r8; 7198 }; 7199 7200 #define S_FW_FCOE_FCF_CMD_FCFI 0 7201 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 7202 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 7203 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 7204 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 7205 7206 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 7207 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 7208 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 7209 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 7210 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 7211 7212 #define S_FW_FCOE_FCF_CMD_FPMA 6 7213 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 7214 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 7215 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 7216 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 7217 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 7218 7219 #define S_FW_FCOE_FCF_CMD_SPMA 5 7220 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 7221 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 7222 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 7223 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 7224 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 7225 7226 #define S_FW_FCOE_FCF_CMD_LOGIN 4 7227 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 7228 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 7229 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 7230 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 7231 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 7232 7233 #define S_FW_FCOE_FCF_CMD_PORTID 0 7234 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 7235 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 7236 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 7237 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 7238 7239 /****************************************************************************** 7240 * E R R O R a n d D E B U G C O M M A N D s 7241 ******************************************************/ 7242 7243 enum fw_error_type { 7244 FW_ERROR_TYPE_EXCEPTION = 0x0, 7245 FW_ERROR_TYPE_HWMODULE = 0x1, 7246 FW_ERROR_TYPE_WR = 0x2, 7247 FW_ERROR_TYPE_ACL = 0x3, 7248 }; 7249 7250 struct fw_error_cmd { 7251 __be32 op_to_type; 7252 __be32 len16_pkd; 7253 union fw_error { 7254 struct fw_error_exception { 7255 __be32 info[6]; 7256 } exception; 7257 struct fw_error_hwmodule { 7258 __be32 regaddr; 7259 __be32 regval; 7260 } hwmodule; 7261 struct fw_error_wr { 7262 __be16 cidx; 7263 __be16 pfn_vfn; 7264 __be32 eqid; 7265 __u8 wrhdr[16]; 7266 } wr; 7267 struct fw_error_acl { 7268 __be16 cidx; 7269 __be16 pfn_vfn; 7270 __be32 eqid; 7271 __be16 mv_pkd; 7272 __u8 val[6]; 7273 __be64 r4; 7274 } acl; 7275 } u; 7276 }; 7277 7278 #define S_FW_ERROR_CMD_FATAL 4 7279 #define M_FW_ERROR_CMD_FATAL 0x1 7280 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 7281 #define G_FW_ERROR_CMD_FATAL(x) \ 7282 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 7283 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 7284 7285 #define S_FW_ERROR_CMD_TYPE 0 7286 #define M_FW_ERROR_CMD_TYPE 0xf 7287 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 7288 #define G_FW_ERROR_CMD_TYPE(x) \ 7289 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 7290 7291 #define S_FW_ERROR_CMD_PFN 8 7292 #define M_FW_ERROR_CMD_PFN 0x7 7293 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7294 #define G_FW_ERROR_CMD_PFN(x) \ 7295 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7296 7297 #define S_FW_ERROR_CMD_VFN 0 7298 #define M_FW_ERROR_CMD_VFN 0xff 7299 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7300 #define G_FW_ERROR_CMD_VFN(x) \ 7301 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7302 7303 #define S_FW_ERROR_CMD_PFN 8 7304 #define M_FW_ERROR_CMD_PFN 0x7 7305 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 7306 #define G_FW_ERROR_CMD_PFN(x) \ 7307 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 7308 7309 #define S_FW_ERROR_CMD_VFN 0 7310 #define M_FW_ERROR_CMD_VFN 0xff 7311 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 7312 #define G_FW_ERROR_CMD_VFN(x) \ 7313 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 7314 7315 #define S_FW_ERROR_CMD_MV 15 7316 #define M_FW_ERROR_CMD_MV 0x1 7317 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 7318 #define G_FW_ERROR_CMD_MV(x) \ 7319 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 7320 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 7321 7322 struct fw_debug_cmd { 7323 __be32 op_type; 7324 __be32 len16_pkd; 7325 union fw_debug { 7326 struct fw_debug_assert { 7327 __be32 fcid; 7328 __be32 line; 7329 __be32 x; 7330 __be32 y; 7331 __u8 filename_0_7[8]; 7332 __u8 filename_8_15[8]; 7333 __be64 r3; 7334 } assert; 7335 struct fw_debug_prt { 7336 __be16 dprtstridx; 7337 __be16 r3[3]; 7338 __be32 dprtstrparam0; 7339 __be32 dprtstrparam1; 7340 __be32 dprtstrparam2; 7341 __be32 dprtstrparam3; 7342 } prt; 7343 } u; 7344 }; 7345 7346 #define S_FW_DEBUG_CMD_TYPE 0 7347 #define M_FW_DEBUG_CMD_TYPE 0xff 7348 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 7349 #define G_FW_DEBUG_CMD_TYPE(x) \ 7350 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 7351 7352 /****************************************************************************** 7353 * P C I E F W R E G I S T E R 7354 **************************************/ 7355 7356 /** 7357 * Register definitions for the PCIE_FW register which the firmware uses 7358 * to retain status across RESETs. This register should be considered 7359 * as a READ-ONLY register for Host Software and only to be used to 7360 * track firmware initialization/error state, etc. 7361 */ 7362 #define S_PCIE_FW_ERR 31 7363 #define M_PCIE_FW_ERR 0x1 7364 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 7365 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 7366 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 7367 7368 #define S_PCIE_FW_INIT 30 7369 #define M_PCIE_FW_INIT 0x1 7370 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 7371 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 7372 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 7373 7374 #define S_PCIE_FW_HALT 29 7375 #define M_PCIE_FW_HALT 0x1 7376 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 7377 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 7378 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 7379 7380 #define S_PCIE_FW_STAGE 21 7381 #define M_PCIE_FW_STAGE 0x7 7382 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 7383 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 7384 7385 #define S_PCIE_FW_ASYNCNOT_VLD 20 7386 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 7387 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 7388 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 7389 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 7390 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 7391 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 7392 7393 #define S_PCIE_FW_ASYNCNOTINT 19 7394 #define M_PCIE_FW_ASYNCNOTINT 0x1 7395 #define V_PCIE_FW_ASYNCNOTINT(x) \ 7396 ((x) << S_PCIE_FW_ASYNCNOTINT) 7397 #define G_PCIE_FW_ASYNCNOTINT(x) \ 7398 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 7399 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 7400 7401 #define S_PCIE_FW_ASYNCNOT 16 7402 #define M_PCIE_FW_ASYNCNOT 0x7 7403 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 7404 #define G_PCIE_FW_ASYNCNOT(x) \ 7405 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 7406 7407 #define S_PCIE_FW_MASTER_VLD 15 7408 #define M_PCIE_FW_MASTER_VLD 0x1 7409 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 7410 #define G_PCIE_FW_MASTER_VLD(x) \ 7411 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 7412 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 7413 7414 #define S_PCIE_FW_MASTER 12 7415 #define M_PCIE_FW_MASTER 0x7 7416 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 7417 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 7418 7419 #define S_PCIE_FW_RESET_VLD 11 7420 #define M_PCIE_FW_RESET_VLD 0x1 7421 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 7422 #define G_PCIE_FW_RESET_VLD(x) \ 7423 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 7424 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 7425 7426 #define S_PCIE_FW_RESET 8 7427 #define M_PCIE_FW_RESET 0x7 7428 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 7429 #define G_PCIE_FW_RESET(x) \ 7430 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 7431 7432 #define S_PCIE_FW_REGISTERED 0 7433 #define M_PCIE_FW_REGISTERED 0xff 7434 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 7435 #define G_PCIE_FW_REGISTERED(x) \ 7436 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 7437 7438 7439 /****************************************************************************** 7440 * B I N A R Y H E A D E R F O R M A T 7441 **********************************************/ 7442 7443 /* 7444 * firmware binary header format 7445 */ 7446 struct fw_hdr { 7447 __u8 ver; 7448 __u8 chip; /* terminator chip family */ 7449 __be16 len512; /* bin length in units of 512-bytes */ 7450 __be32 fw_ver; /* firmware version */ 7451 __be32 tp_microcode_ver; /* tcp processor microcode version */ 7452 __u8 intfver_nic; 7453 __u8 intfver_vnic; 7454 __u8 intfver_ofld; 7455 __u8 intfver_ri; 7456 __u8 intfver_iscsipdu; 7457 __u8 intfver_iscsi; 7458 __u8 intfver_fcoe; 7459 __u8 reserved2; 7460 __u32 reserved3; 7461 __u32 reserved4; 7462 __u32 reserved5; 7463 __be32 flags; 7464 __be32 reserved6[23]; 7465 }; 7466 7467 enum fw_hdr_chip { 7468 FW_HDR_CHIP_T4, 7469 FW_HDR_CHIP_T5 7470 }; 7471 7472 #define S_FW_HDR_FW_VER_MAJOR 24 7473 #define M_FW_HDR_FW_VER_MAJOR 0xff 7474 #define V_FW_HDR_FW_VER_MAJOR(x) \ 7475 ((x) << S_FW_HDR_FW_VER_MAJOR) 7476 #define G_FW_HDR_FW_VER_MAJOR(x) \ 7477 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 7478 7479 #define S_FW_HDR_FW_VER_MINOR 16 7480 #define M_FW_HDR_FW_VER_MINOR 0xff 7481 #define V_FW_HDR_FW_VER_MINOR(x) \ 7482 ((x) << S_FW_HDR_FW_VER_MINOR) 7483 #define G_FW_HDR_FW_VER_MINOR(x) \ 7484 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 7485 7486 #define S_FW_HDR_FW_VER_MICRO 8 7487 #define M_FW_HDR_FW_VER_MICRO 0xff 7488 #define V_FW_HDR_FW_VER_MICRO(x) \ 7489 ((x) << S_FW_HDR_FW_VER_MICRO) 7490 #define G_FW_HDR_FW_VER_MICRO(x) \ 7491 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 7492 7493 #define S_FW_HDR_FW_VER_BUILD 0 7494 #define M_FW_HDR_FW_VER_BUILD 0xff 7495 #define V_FW_HDR_FW_VER_BUILD(x) \ 7496 ((x) << S_FW_HDR_FW_VER_BUILD) 7497 #define G_FW_HDR_FW_VER_BUILD(x) \ 7498 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 7499 7500 enum { 7501 FW_HDR_INTFVER_NIC = 0x00, 7502 FW_HDR_INTFVER_VNIC = 0x00, 7503 FW_HDR_INTFVER_OFLD = 0x00, 7504 FW_HDR_INTFVER_RI = 0x00, 7505 FW_HDR_INTFVER_ISCSIPDU = 0x00, 7506 FW_HDR_INTFVER_ISCSI = 0x00, 7507 FW_HDR_INTFVER_FCOE = 0x00, 7508 }; 7509 7510 enum fw_hdr_flags { 7511 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 7512 }; 7513 7514 #endif /* _T4FW_INTERFACE_H_ */ 7515