1 /*- 2 * Copyright (c) 2012-2017, 2025 Chelsio Communications. 3 * 4 * Redistribution and use in source and binary forms, with or without 5 * modification, are permitted provided that the following conditions 6 * are met: 7 * 1. Redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer. 9 * 2. Redistributions in binary form must reproduce the above copyright 10 * notice, this list of conditions and the following disclaimer in the 11 * documentation and/or other materials provided with the distribution. 12 * 13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 14 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 17 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23 * SUCH DAMAGE. 24 * 25 */ 26 27 #ifndef _T4FW_INTERFACE_H_ 28 #define _T4FW_INTERFACE_H_ 29 30 /****************************************************************************** 31 * R E T U R N V A L U E S 32 ********************************/ 33 34 enum fw_retval { 35 FW_SUCCESS = 0, /* completed successfully */ 36 FW_EPERM = 1, /* operation not permitted */ 37 FW_ENOENT = 2, /* no such file or directory */ 38 FW_EIO = 5, /* input/output error; hw bad */ 39 FW_ENOEXEC = 8, /* exec format error; inv microcode */ 40 FW_EAGAIN = 11, /* try again */ 41 FW_ENOMEM = 12, /* out of memory */ 42 FW_EFAULT = 14, /* bad address; fw bad */ 43 FW_EBUSY = 16, /* resource busy */ 44 FW_EEXIST = 17, /* file exists */ 45 FW_ENODEV = 19, /* no such device */ 46 FW_EINVAL = 22, /* invalid argument */ 47 FW_ENOSPC = 28, /* no space left on device */ 48 FW_ENOSYS = 38, /* functionality not implemented */ 49 FW_ENODATA = 61, /* no data available */ 50 FW_EPROTO = 71, /* protocol error */ 51 FW_EADDRINUSE = 98, /* address already in use */ 52 FW_EADDRNOTAVAIL = 99, /* cannot assigned requested address */ 53 FW_ENETDOWN = 100, /* network is down */ 54 FW_ENETUNREACH = 101, /* network is unreachable */ 55 FW_ENOBUFS = 105, /* no buffer space available */ 56 FW_ETIMEDOUT = 110, /* timeout */ 57 FW_EINPROGRESS = 115, /* fw internal */ 58 FW_SCSI_ABORT_REQUESTED = 128, /* */ 59 FW_SCSI_ABORT_TIMEDOUT = 129, /* */ 60 FW_SCSI_ABORTED = 130, /* */ 61 FW_SCSI_CLOSE_REQUESTED = 131, /* */ 62 FW_ERR_LINK_DOWN = 132, /* */ 63 FW_RDEV_NOT_READY = 133, /* */ 64 FW_ERR_RDEV_LOST = 134, /* */ 65 FW_ERR_RDEV_LOGO = 135, /* */ 66 FW_FCOE_NO_XCHG = 136, /* */ 67 FW_SCSI_RSP_ERR = 137, /* */ 68 FW_ERR_RDEV_IMPL_LOGO = 138, /* */ 69 FW_SCSI_UNDER_FLOW_ERR = 139, /* */ 70 FW_SCSI_OVER_FLOW_ERR = 140, /* */ 71 FW_SCSI_DDP_ERR = 141, /* DDP error*/ 72 FW_SCSI_TASK_ERR = 142, /* No SCSI tasks available */ 73 FW_SCSI_IO_BLOCK = 143, /* IO is going to be blocked due to resource failure */ 74 }; 75 76 /****************************************************************************** 77 * M E M O R Y T Y P E s 78 ******************************/ 79 80 enum fw_memtype { 81 FW_MEMTYPE_EDC0 = 0x0, 82 FW_MEMTYPE_EDC1 = 0x1, 83 FW_MEMTYPE_EXTMEM = 0x2, 84 FW_MEMTYPE_FLASH = 0x4, 85 FW_MEMTYPE_INTERNAL = 0x5, 86 FW_MEMTYPE_EXTMEM1 = 0x6, 87 FW_MEMTYPE_HMA = 0x7, 88 }; 89 90 /****************************************************************************** 91 * W O R K R E Q U E S T s 92 ********************************/ 93 94 enum fw_wr_opcodes { 95 FW_FRAG_WR = 0x1d, 96 FW_FILTER_WR = 0x02, 97 FW_ULPTX_WR = 0x04, 98 FW_TP_WR = 0x05, 99 FW_ETH_TX_PKT_WR = 0x08, 100 FW_ETH_TX_PKT2_WR = 0x44, 101 FW_ETH_TX_PKTS_WR = 0x09, 102 FW_ETH_TX_PKTS2_WR = 0x78, 103 FW_ETH_TX_EO_WR = 0x1c, 104 FW_EQ_FLUSH_WR = 0x1b, 105 FW_OFLD_CONNECTION_WR = 0x2f, 106 FW_FLOWC_WR = 0x0a, 107 FW_OFLD_TX_DATA_WR = 0x0b, 108 FW_OFLD_TX_DATA_V2_WR = 0x0f, 109 FW_CMD_WR = 0x10, 110 FW_ETH_TX_PKT_VM_WR = 0x11, 111 FW_ETH_TX_PKTS_VM_WR = 0x12, 112 FW_RI_RES_WR = 0x0c, 113 FW_QP_RES_WR = FW_RI_RES_WR, 114 /* iwarp wr used from rdma kernel and user space */ 115 FW_V2_NVMET_TX_DATA_WR = 0x13, 116 FW_RI_RDMA_WRITE_WR = 0x14, 117 FW_RI_SEND_WR = 0x15, 118 FW_RI_RDMA_READ_WR = 0x16, 119 FW_RI_RECV_WR = 0x17, 120 FW_RI_BIND_MW_WR = 0x18, 121 FW_RI_FR_NSMR_WR = 0x19, 122 FW_RI_FR_NSMR_TPTE_WR = 0x20, 123 FW_RI_RDMA_WRITE_CMPL_WR = 0x21, 124 /* rocev2 wr used from rdma kernel and user space */ 125 FW_RI_V2_RDMA_WRITE_WR = 0x22, 126 FW_RI_V2_SEND_WR = 0x23, 127 FW_RI_V2_RDMA_READ_WR = 0x24, 128 FW_RI_V2_BIND_MW_WR = 0x25, 129 FW_RI_V2_FR_NSMR_WR = 0x26, 130 FW_RI_V2_ATOMIC_WR = 0x27, 131 FW_NVMET_V2_FR_NSMR_WR = 0x28, 132 FW_RI_V2_INV_LSTAG_WR = 0x1e, 133 FW_RI_INV_LSTAG_WR = 0x1a, 134 FW_RI_SEND_IMMEDIATE_WR = 0x15, 135 FW_RI_ATOMIC_WR = 0x16, 136 FW_RI_WR = 0x0d, 137 FW_CHNET_IFCONF_WR = 0x6b, 138 FW_RDEV_WR = 0x38, 139 FW_FOISCSI_NODE_WR = 0x60, 140 FW_FOISCSI_CTRL_WR = 0x6a, 141 FW_FOISCSI_CHAP_WR = 0x6c, 142 FW_FCOE_ELS_CT_WR = 0x30, 143 FW_SCSI_WRITE_WR = 0x31, 144 FW_SCSI_READ_WR = 0x32, 145 FW_SCSI_CMD_WR = 0x33, 146 FW_SCSI_ABRT_CLS_WR = 0x34, 147 FW_SCSI_TGT_ACC_WR = 0x35, 148 FW_SCSI_TGT_XMIT_WR = 0x36, 149 FW_SCSI_TGT_RSP_WR = 0x37, 150 FW_POFCOE_TCB_WR = 0x42, 151 FW_POFCOE_ULPTX_WR = 0x43, 152 FW_ISCSI_TX_DATA_WR = 0x45, 153 FW_PTP_TX_PKT_WR = 0x46, 154 FW_TLSTX_DATA_WR = 0x68, 155 FW_TLS_TUNNEL_OFLD_WR = 0x69, 156 FW_CRYPTO_LOOKASIDE_WR = 0x6d, 157 FW_CRYPTO_UPDATE_SA_WR = 0x6e, 158 FW_COISCSI_TGT_WR = 0x70, 159 FW_COISCSI_TGT_CONN_WR = 0x71, 160 FW_COISCSI_TGT_XMIT_WR = 0x72, 161 FW_COISCSI_STATS_WR = 0x73, 162 FW_ISNS_WR = 0x75, 163 FW_ISNS_XMIT_WR = 0x76, 164 FW_FILTER2_WR = 0x77, 165 /* FW_LASTC2E_WR = 0x80 */ 166 FW_LASTC2E_WR = 0xB0 167 }; 168 169 /* 170 * Generic work request header flit0 171 */ 172 struct fw_wr_hdr { 173 __be32 hi; 174 __be32 lo; 175 }; 176 177 /* work request opcode (hi) 178 */ 179 #define S_FW_WR_OP 24 180 #define M_FW_WR_OP 0xff 181 #define V_FW_WR_OP(x) ((x) << S_FW_WR_OP) 182 #define G_FW_WR_OP(x) (((x) >> S_FW_WR_OP) & M_FW_WR_OP) 183 184 /* atomic flag (hi) - firmware encapsulates CPLs in CPL_BARRIER 185 */ 186 #define S_FW_WR_ATOMIC 23 187 #define M_FW_WR_ATOMIC 0x1 188 #define V_FW_WR_ATOMIC(x) ((x) << S_FW_WR_ATOMIC) 189 #define G_FW_WR_ATOMIC(x) \ 190 (((x) >> S_FW_WR_ATOMIC) & M_FW_WR_ATOMIC) 191 #define F_FW_WR_ATOMIC V_FW_WR_ATOMIC(1U) 192 193 /* flush flag (hi) - firmware flushes flushable work request buffered 194 * in the flow context. 195 */ 196 #define S_FW_WR_FLUSH 22 197 #define M_FW_WR_FLUSH 0x1 198 #define V_FW_WR_FLUSH(x) ((x) << S_FW_WR_FLUSH) 199 #define G_FW_WR_FLUSH(x) \ 200 (((x) >> S_FW_WR_FLUSH) & M_FW_WR_FLUSH) 201 #define F_FW_WR_FLUSH V_FW_WR_FLUSH(1U) 202 203 /* completion flag (hi) - firmware generates a cpl_fw6_ack 204 */ 205 #define S_FW_WR_COMPL 21 206 #define M_FW_WR_COMPL 0x1 207 #define V_FW_WR_COMPL(x) ((x) << S_FW_WR_COMPL) 208 #define G_FW_WR_COMPL(x) \ 209 (((x) >> S_FW_WR_COMPL) & M_FW_WR_COMPL) 210 #define F_FW_WR_COMPL V_FW_WR_COMPL(1U) 211 212 213 /* work request immediate data lengh (hi) 214 */ 215 #define S_FW_WR_IMMDLEN 0 216 #define M_FW_WR_IMMDLEN 0xff 217 #define V_FW_WR_IMMDLEN(x) ((x) << S_FW_WR_IMMDLEN) 218 #define G_FW_WR_IMMDLEN(x) \ 219 (((x) >> S_FW_WR_IMMDLEN) & M_FW_WR_IMMDLEN) 220 221 /* egress queue status update to associated ingress queue entry (lo) 222 */ 223 #define S_FW_WR_EQUIQ 31 224 #define M_FW_WR_EQUIQ 0x1 225 #define V_FW_WR_EQUIQ(x) ((x) << S_FW_WR_EQUIQ) 226 #define G_FW_WR_EQUIQ(x) (((x) >> S_FW_WR_EQUIQ) & M_FW_WR_EQUIQ) 227 #define F_FW_WR_EQUIQ V_FW_WR_EQUIQ(1U) 228 229 /* egress queue status update to egress queue status entry (lo) 230 */ 231 #define S_FW_WR_EQUEQ 30 232 #define M_FW_WR_EQUEQ 0x1 233 #define V_FW_WR_EQUEQ(x) ((x) << S_FW_WR_EQUEQ) 234 #define G_FW_WR_EQUEQ(x) (((x) >> S_FW_WR_EQUEQ) & M_FW_WR_EQUEQ) 235 #define F_FW_WR_EQUEQ V_FW_WR_EQUEQ(1U) 236 237 /* flow context identifier (lo) 238 */ 239 #define S_FW_WR_FLOWID 8 240 #define M_FW_WR_FLOWID 0xfffff 241 #define V_FW_WR_FLOWID(x) ((x) << S_FW_WR_FLOWID) 242 #define G_FW_WR_FLOWID(x) (((x) >> S_FW_WR_FLOWID) & M_FW_WR_FLOWID) 243 244 /* length in units of 16-bytes (lo) 245 */ 246 #define S_FW_WR_LEN16 0 247 #define M_FW_WR_LEN16 0xff 248 #define V_FW_WR_LEN16(x) ((x) << S_FW_WR_LEN16) 249 #define G_FW_WR_LEN16(x) (((x) >> S_FW_WR_LEN16) & M_FW_WR_LEN16) 250 251 struct fw_frag_wr { 252 __be32 op_to_fragoff16; 253 __be32 flowid_len16; 254 __be64 r4; 255 }; 256 257 #define S_FW_FRAG_WR_EOF 15 258 #define M_FW_FRAG_WR_EOF 0x1 259 #define V_FW_FRAG_WR_EOF(x) ((x) << S_FW_FRAG_WR_EOF) 260 #define G_FW_FRAG_WR_EOF(x) (((x) >> S_FW_FRAG_WR_EOF) & M_FW_FRAG_WR_EOF) 261 #define F_FW_FRAG_WR_EOF V_FW_FRAG_WR_EOF(1U) 262 263 #define S_FW_FRAG_WR_FRAGOFF16 8 264 #define M_FW_FRAG_WR_FRAGOFF16 0x7f 265 #define V_FW_FRAG_WR_FRAGOFF16(x) ((x) << S_FW_FRAG_WR_FRAGOFF16) 266 #define G_FW_FRAG_WR_FRAGOFF16(x) \ 267 (((x) >> S_FW_FRAG_WR_FRAGOFF16) & M_FW_FRAG_WR_FRAGOFF16) 268 269 /* valid filter configurations for compressed tuple 270 * Encodings: TPL - Compressed TUPLE for filter in addition to 4-tuple 271 * FR - FRAGMENT, FC - FCoE, MT - MPS MATCH TYPE, M - MPS MATCH, 272 * E - Ethertype, P - Port, PR - Protocol, T - TOS, IV - Inner VLAN, 273 * OV - Outer VLAN/VNIC_ID, 274 */ 275 #define HW_TPL_FR_MT_M_E_P_FC 0x3C3 276 #define HW_TPL_FR_MT_M_PR_T_FC 0x3B3 277 #define HW_TPL_FR_MT_M_IV_P_FC 0x38B 278 #define HW_TPL_FR_MT_M_OV_P_FC 0x387 279 #define HW_TPL_FR_MT_E_PR_T 0x370 280 #define HW_TPL_FR_MT_E_PR_P_FC 0X363 281 #define HW_TPL_FR_MT_E_T_P_FC 0X353 282 #define HW_TPL_FR_MT_PR_IV_P_FC 0X32B 283 #define HW_TPL_FR_MT_PR_OV_P_FC 0X327 284 #define HW_TPL_FR_MT_T_IV_P_FC 0X31B 285 #define HW_TPL_FR_MT_T_OV_P_FC 0X317 286 #define HW_TPL_FR_M_E_PR_FC 0X2E1 287 #define HW_TPL_FR_M_E_T_FC 0X2D1 288 #define HW_TPL_FR_M_PR_IV_FC 0X2A9 289 #define HW_TPL_FR_M_PR_OV_FC 0X2A5 290 #define HW_TPL_FR_M_T_IV_FC 0X299 291 #define HW_TPL_FR_M_T_OV_FC 0X295 292 #define HW_TPL_FR_E_PR_T_P 0X272 293 #define HW_TPL_FR_E_PR_T_FC 0X271 294 #define HW_TPL_FR_E_IV_FC 0X249 295 #define HW_TPL_FR_E_OV_FC 0X245 296 #define HW_TPL_FR_PR_T_IV_FC 0X239 297 #define HW_TPL_FR_PR_T_OV_FC 0X235 298 #define HW_TPL_FR_IV_OV_FC 0X20D 299 #define HW_TPL_MT_M_E_PR 0X1E0 300 #define HW_TPL_MT_M_E_T 0X1D0 301 #define HW_TPL_MT_E_PR_T_FC 0X171 302 #define HW_TPL_MT_E_IV 0X148 303 #define HW_TPL_MT_E_OV 0X144 304 #define HW_TPL_MT_PR_T_IV 0X138 305 #define HW_TPL_MT_PR_T_OV 0X134 306 #define HW_TPL_M_E_PR_P 0X0E2 307 #define HW_TPL_M_E_T_P 0X0D2 308 #define HW_TPL_E_PR_T_P_FC 0X073 309 #define HW_TPL_E_IV_P 0X04A 310 #define HW_TPL_E_OV_P 0X046 311 #define HW_TPL_PR_T_IV_P 0X03A 312 #define HW_TPL_PR_T_OV_P 0X036 313 314 /* filter wr reply code in cookie in CPL_SET_TCB_RPL */ 315 enum fw_filter_wr_cookie { 316 FW_FILTER_WR_SUCCESS, 317 FW_FILTER_WR_FLT_ADDED, 318 FW_FILTER_WR_FLT_DELETED, 319 FW_FILTER_WR_SMT_TBL_FULL, 320 FW_FILTER_WR_EINVAL, 321 }; 322 323 enum fw_filter_wr_nat_mode { 324 FW_FILTER_WR_NATMODE_NONE = 0, 325 FW_FILTER_WR_NATMODE_DIP, 326 FW_FILTER_WR_NATMODE_DIPDP, 327 FW_FILTER_WR_NATMODE_DIPDPSIP, 328 FW_FILTER_WR_NATMODE_DIPDPSP, 329 FW_FILTER_WR_NATMODE_SIPSP, 330 FW_FILTER_WR_NATMODE_DIPSIPSP, 331 FW_FILTER_WR_NATMODE_FOURTUPLE, 332 }; 333 334 struct fw_filter_wr { 335 __be32 op_pkd; 336 __be32 len16_pkd; 337 __be64 r3; 338 __be32 tid_to_iq; 339 __be32 del_filter_to_l2tix; 340 __be16 ethtype; 341 __be16 ethtypem; 342 __u8 frag_to_ovlan_vldm; 343 __u8 smac_sel; 344 __be16 rx_chan_rx_rpl_iq; 345 __be32 maci_to_matchtypem; 346 __u8 ptcl; 347 __u8 ptclm; 348 __u8 ttyp; 349 __u8 ttypm; 350 __be16 ivlan; 351 __be16 ivlanm; 352 __be16 ovlan; 353 __be16 ovlanm; 354 __u8 lip[16]; 355 __u8 lipm[16]; 356 __u8 fip[16]; 357 __u8 fipm[16]; 358 __be16 lp; 359 __be16 lpm; 360 __be16 fp; 361 __be16 fpm; 362 __be16 r7; 363 __u8 sma[6]; 364 }; 365 366 struct fw_filter2_wr { 367 __be32 op_pkd; 368 __be32 len16_pkd; 369 __be64 r3; 370 __be32 tid_to_iq; 371 __be32 del_filter_to_l2tix; 372 __be16 ethtype; 373 __be16 ethtypem; 374 __u8 frag_to_ovlan_vldm; 375 __u8 smac_sel; 376 __be16 rx_chan_rx_rpl_iq; 377 __be32 maci_to_matchtypem; 378 __u8 ptcl; 379 __u8 ptclm; 380 __u8 ttyp; 381 __u8 ttypm; 382 __be16 ivlan; 383 __be16 ivlanm; 384 __be16 ovlan; 385 __be16 ovlanm; 386 __u8 lip[16]; 387 __u8 lipm[16]; 388 __u8 fip[16]; 389 __u8 fipm[16]; 390 __be16 lp; 391 __be16 lpm; 392 __be16 fp; 393 __be16 fpm; 394 __be16 r7; 395 __u8 sma[6]; 396 __be16 r8; 397 __u8 filter_type_swapmac; 398 __u8 natmode_to_ulp_type; 399 __be16 newlport; 400 __be16 newfport; 401 __u8 newlip[16]; 402 __u8 newfip[16]; 403 __be32 natseqcheck; 404 __be32 rocev2_qpn; 405 __be64 r10; 406 __be64 r11; 407 __be64 r12; 408 __be64 r13; 409 }; 410 411 #define S_FW_FILTER_WR_TID 12 412 #define M_FW_FILTER_WR_TID 0xfffff 413 #define V_FW_FILTER_WR_TID(x) ((x) << S_FW_FILTER_WR_TID) 414 #define G_FW_FILTER_WR_TID(x) \ 415 (((x) >> S_FW_FILTER_WR_TID) & M_FW_FILTER_WR_TID) 416 417 #define S_FW_FILTER_WR_RQTYPE 11 418 #define M_FW_FILTER_WR_RQTYPE 0x1 419 #define V_FW_FILTER_WR_RQTYPE(x) ((x) << S_FW_FILTER_WR_RQTYPE) 420 #define G_FW_FILTER_WR_RQTYPE(x) \ 421 (((x) >> S_FW_FILTER_WR_RQTYPE) & M_FW_FILTER_WR_RQTYPE) 422 #define F_FW_FILTER_WR_RQTYPE V_FW_FILTER_WR_RQTYPE(1U) 423 424 #define S_FW_FILTER_WR_NOREPLY 10 425 #define M_FW_FILTER_WR_NOREPLY 0x1 426 #define V_FW_FILTER_WR_NOREPLY(x) ((x) << S_FW_FILTER_WR_NOREPLY) 427 #define G_FW_FILTER_WR_NOREPLY(x) \ 428 (((x) >> S_FW_FILTER_WR_NOREPLY) & M_FW_FILTER_WR_NOREPLY) 429 #define F_FW_FILTER_WR_NOREPLY V_FW_FILTER_WR_NOREPLY(1U) 430 431 #define S_FW_FILTER_WR_IQ 0 432 #define M_FW_FILTER_WR_IQ 0x3ff 433 #define V_FW_FILTER_WR_IQ(x) ((x) << S_FW_FILTER_WR_IQ) 434 #define G_FW_FILTER_WR_IQ(x) \ 435 (((x) >> S_FW_FILTER_WR_IQ) & M_FW_FILTER_WR_IQ) 436 437 #define S_FW_FILTER_WR_DEL_FILTER 31 438 #define M_FW_FILTER_WR_DEL_FILTER 0x1 439 #define V_FW_FILTER_WR_DEL_FILTER(x) ((x) << S_FW_FILTER_WR_DEL_FILTER) 440 #define G_FW_FILTER_WR_DEL_FILTER(x) \ 441 (((x) >> S_FW_FILTER_WR_DEL_FILTER) & M_FW_FILTER_WR_DEL_FILTER) 442 #define F_FW_FILTER_WR_DEL_FILTER V_FW_FILTER_WR_DEL_FILTER(1U) 443 444 #define S_FW_FILTER2_WR_DROP_ENCAP 30 445 #define M_FW_FILTER2_WR_DROP_ENCAP 0x1 446 #define V_FW_FILTER2_WR_DROP_ENCAP(x) ((x) << S_FW_FILTER2_WR_DROP_ENCAP) 447 #define G_FW_FILTER2_WR_DROP_ENCAP(x) \ 448 (((x) >> S_FW_FILTER2_WR_DROP_ENCAP) & M_FW_FILTER2_WR_DROP_ENCAP) 449 #define F_FW_FILTER2_WR_DROP_ENCAP V_FW_FILTER2_WR_DROP_ENCAP(1U) 450 451 #define S_FW_FILTER2_WR_TX_LOOP 29 452 #define M_FW_FILTER2_WR_TX_LOOP 0x1 453 #define V_FW_FILTER2_WR_TX_LOOP(x) ((x) << S_FW_FILTER2_WR_TX_LOOP) 454 #define G_FW_FILTER2_WR_TX_LOOP(x) \ 455 (((x) >> S_FW_FILTER2_WR_TX_LOOP) & M_FW_FILTER2_WR_TX_LOOP) 456 #define F_FW_FILTER2_WR_TX_LOOP V_FW_FILTER2_WR_TX_LOOP(1U) 457 458 #define S_FW_FILTER_WR_RPTTID 25 459 #define M_FW_FILTER_WR_RPTTID 0x1 460 #define V_FW_FILTER_WR_RPTTID(x) ((x) << S_FW_FILTER_WR_RPTTID) 461 #define G_FW_FILTER_WR_RPTTID(x) \ 462 (((x) >> S_FW_FILTER_WR_RPTTID) & M_FW_FILTER_WR_RPTTID) 463 #define F_FW_FILTER_WR_RPTTID V_FW_FILTER_WR_RPTTID(1U) 464 465 #define S_FW_FILTER_WR_DROP 24 466 #define M_FW_FILTER_WR_DROP 0x1 467 #define V_FW_FILTER_WR_DROP(x) ((x) << S_FW_FILTER_WR_DROP) 468 #define G_FW_FILTER_WR_DROP(x) \ 469 (((x) >> S_FW_FILTER_WR_DROP) & M_FW_FILTER_WR_DROP) 470 #define F_FW_FILTER_WR_DROP V_FW_FILTER_WR_DROP(1U) 471 472 #define S_FW_FILTER_WR_DIRSTEER 23 473 #define M_FW_FILTER_WR_DIRSTEER 0x1 474 #define V_FW_FILTER_WR_DIRSTEER(x) ((x) << S_FW_FILTER_WR_DIRSTEER) 475 #define G_FW_FILTER_WR_DIRSTEER(x) \ 476 (((x) >> S_FW_FILTER_WR_DIRSTEER) & M_FW_FILTER_WR_DIRSTEER) 477 #define F_FW_FILTER_WR_DIRSTEER V_FW_FILTER_WR_DIRSTEER(1U) 478 479 #define S_FW_FILTER_WR_MASKHASH 22 480 #define M_FW_FILTER_WR_MASKHASH 0x1 481 #define V_FW_FILTER_WR_MASKHASH(x) ((x) << S_FW_FILTER_WR_MASKHASH) 482 #define G_FW_FILTER_WR_MASKHASH(x) \ 483 (((x) >> S_FW_FILTER_WR_MASKHASH) & M_FW_FILTER_WR_MASKHASH) 484 #define F_FW_FILTER_WR_MASKHASH V_FW_FILTER_WR_MASKHASH(1U) 485 486 #define S_FW_FILTER_WR_DIRSTEERHASH 21 487 #define M_FW_FILTER_WR_DIRSTEERHASH 0x1 488 #define V_FW_FILTER_WR_DIRSTEERHASH(x) ((x) << S_FW_FILTER_WR_DIRSTEERHASH) 489 #define G_FW_FILTER_WR_DIRSTEERHASH(x) \ 490 (((x) >> S_FW_FILTER_WR_DIRSTEERHASH) & M_FW_FILTER_WR_DIRSTEERHASH) 491 #define F_FW_FILTER_WR_DIRSTEERHASH V_FW_FILTER_WR_DIRSTEERHASH(1U) 492 493 #define S_FW_FILTER_WR_LPBK 20 494 #define M_FW_FILTER_WR_LPBK 0x1 495 #define V_FW_FILTER_WR_LPBK(x) ((x) << S_FW_FILTER_WR_LPBK) 496 #define G_FW_FILTER_WR_LPBK(x) \ 497 (((x) >> S_FW_FILTER_WR_LPBK) & M_FW_FILTER_WR_LPBK) 498 #define F_FW_FILTER_WR_LPBK V_FW_FILTER_WR_LPBK(1U) 499 500 #define S_FW_FILTER_WR_DMAC 19 501 #define M_FW_FILTER_WR_DMAC 0x1 502 #define V_FW_FILTER_WR_DMAC(x) ((x) << S_FW_FILTER_WR_DMAC) 503 #define G_FW_FILTER_WR_DMAC(x) \ 504 (((x) >> S_FW_FILTER_WR_DMAC) & M_FW_FILTER_WR_DMAC) 505 #define F_FW_FILTER_WR_DMAC V_FW_FILTER_WR_DMAC(1U) 506 507 #define S_FW_FILTER_WR_SMAC 18 508 #define M_FW_FILTER_WR_SMAC 0x1 509 #define V_FW_FILTER_WR_SMAC(x) ((x) << S_FW_FILTER_WR_SMAC) 510 #define G_FW_FILTER_WR_SMAC(x) \ 511 (((x) >> S_FW_FILTER_WR_SMAC) & M_FW_FILTER_WR_SMAC) 512 #define F_FW_FILTER_WR_SMAC V_FW_FILTER_WR_SMAC(1U) 513 514 #define S_FW_FILTER_WR_INSVLAN 17 515 #define M_FW_FILTER_WR_INSVLAN 0x1 516 #define V_FW_FILTER_WR_INSVLAN(x) ((x) << S_FW_FILTER_WR_INSVLAN) 517 #define G_FW_FILTER_WR_INSVLAN(x) \ 518 (((x) >> S_FW_FILTER_WR_INSVLAN) & M_FW_FILTER_WR_INSVLAN) 519 #define F_FW_FILTER_WR_INSVLAN V_FW_FILTER_WR_INSVLAN(1U) 520 521 #define S_FW_FILTER_WR_RMVLAN 16 522 #define M_FW_FILTER_WR_RMVLAN 0x1 523 #define V_FW_FILTER_WR_RMVLAN(x) ((x) << S_FW_FILTER_WR_RMVLAN) 524 #define G_FW_FILTER_WR_RMVLAN(x) \ 525 (((x) >> S_FW_FILTER_WR_RMVLAN) & M_FW_FILTER_WR_RMVLAN) 526 #define F_FW_FILTER_WR_RMVLAN V_FW_FILTER_WR_RMVLAN(1U) 527 528 #define S_FW_FILTER_WR_HITCNTS 15 529 #define M_FW_FILTER_WR_HITCNTS 0x1 530 #define V_FW_FILTER_WR_HITCNTS(x) ((x) << S_FW_FILTER_WR_HITCNTS) 531 #define G_FW_FILTER_WR_HITCNTS(x) \ 532 (((x) >> S_FW_FILTER_WR_HITCNTS) & M_FW_FILTER_WR_HITCNTS) 533 #define F_FW_FILTER_WR_HITCNTS V_FW_FILTER_WR_HITCNTS(1U) 534 535 #define S_FW_FILTER_WR_TXCHAN 13 536 #define M_FW_FILTER_WR_TXCHAN 0x3 537 #define V_FW_FILTER_WR_TXCHAN(x) ((x) << S_FW_FILTER_WR_TXCHAN) 538 #define G_FW_FILTER_WR_TXCHAN(x) \ 539 (((x) >> S_FW_FILTER_WR_TXCHAN) & M_FW_FILTER_WR_TXCHAN) 540 541 #define S_FW_FILTER_WR_PRIO 12 542 #define M_FW_FILTER_WR_PRIO 0x1 543 #define V_FW_FILTER_WR_PRIO(x) ((x) << S_FW_FILTER_WR_PRIO) 544 #define G_FW_FILTER_WR_PRIO(x) \ 545 (((x) >> S_FW_FILTER_WR_PRIO) & M_FW_FILTER_WR_PRIO) 546 #define F_FW_FILTER_WR_PRIO V_FW_FILTER_WR_PRIO(1U) 547 548 #define S_FW_FILTER_WR_L2TIX 0 549 #define M_FW_FILTER_WR_L2TIX 0xfff 550 #define V_FW_FILTER_WR_L2TIX(x) ((x) << S_FW_FILTER_WR_L2TIX) 551 #define G_FW_FILTER_WR_L2TIX(x) \ 552 (((x) >> S_FW_FILTER_WR_L2TIX) & M_FW_FILTER_WR_L2TIX) 553 554 #define S_FW_FILTER_WR_FRAG 7 555 #define M_FW_FILTER_WR_FRAG 0x1 556 #define V_FW_FILTER_WR_FRAG(x) ((x) << S_FW_FILTER_WR_FRAG) 557 #define G_FW_FILTER_WR_FRAG(x) \ 558 (((x) >> S_FW_FILTER_WR_FRAG) & M_FW_FILTER_WR_FRAG) 559 #define F_FW_FILTER_WR_FRAG V_FW_FILTER_WR_FRAG(1U) 560 561 #define S_FW_FILTER_WR_FRAGM 6 562 #define M_FW_FILTER_WR_FRAGM 0x1 563 #define V_FW_FILTER_WR_FRAGM(x) ((x) << S_FW_FILTER_WR_FRAGM) 564 #define G_FW_FILTER_WR_FRAGM(x) \ 565 (((x) >> S_FW_FILTER_WR_FRAGM) & M_FW_FILTER_WR_FRAGM) 566 #define F_FW_FILTER_WR_FRAGM V_FW_FILTER_WR_FRAGM(1U) 567 568 #define S_FW_FILTER_WR_IVLAN_VLD 5 569 #define M_FW_FILTER_WR_IVLAN_VLD 0x1 570 #define V_FW_FILTER_WR_IVLAN_VLD(x) ((x) << S_FW_FILTER_WR_IVLAN_VLD) 571 #define G_FW_FILTER_WR_IVLAN_VLD(x) \ 572 (((x) >> S_FW_FILTER_WR_IVLAN_VLD) & M_FW_FILTER_WR_IVLAN_VLD) 573 #define F_FW_FILTER_WR_IVLAN_VLD V_FW_FILTER_WR_IVLAN_VLD(1U) 574 575 #define S_FW_FILTER_WR_OVLAN_VLD 4 576 #define M_FW_FILTER_WR_OVLAN_VLD 0x1 577 #define V_FW_FILTER_WR_OVLAN_VLD(x) ((x) << S_FW_FILTER_WR_OVLAN_VLD) 578 #define G_FW_FILTER_WR_OVLAN_VLD(x) \ 579 (((x) >> S_FW_FILTER_WR_OVLAN_VLD) & M_FW_FILTER_WR_OVLAN_VLD) 580 #define F_FW_FILTER_WR_OVLAN_VLD V_FW_FILTER_WR_OVLAN_VLD(1U) 581 582 #define S_FW_FILTER_WR_IVLAN_VLDM 3 583 #define M_FW_FILTER_WR_IVLAN_VLDM 0x1 584 #define V_FW_FILTER_WR_IVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_IVLAN_VLDM) 585 #define G_FW_FILTER_WR_IVLAN_VLDM(x) \ 586 (((x) >> S_FW_FILTER_WR_IVLAN_VLDM) & M_FW_FILTER_WR_IVLAN_VLDM) 587 #define F_FW_FILTER_WR_IVLAN_VLDM V_FW_FILTER_WR_IVLAN_VLDM(1U) 588 589 #define S_FW_FILTER_WR_OVLAN_VLDM 2 590 #define M_FW_FILTER_WR_OVLAN_VLDM 0x1 591 #define V_FW_FILTER_WR_OVLAN_VLDM(x) ((x) << S_FW_FILTER_WR_OVLAN_VLDM) 592 #define G_FW_FILTER_WR_OVLAN_VLDM(x) \ 593 (((x) >> S_FW_FILTER_WR_OVLAN_VLDM) & M_FW_FILTER_WR_OVLAN_VLDM) 594 #define F_FW_FILTER_WR_OVLAN_VLDM V_FW_FILTER_WR_OVLAN_VLDM(1U) 595 596 #define S_FW_FILTER_WR_RX_CHAN 15 597 #define M_FW_FILTER_WR_RX_CHAN 0x1 598 #define V_FW_FILTER_WR_RX_CHAN(x) ((x) << S_FW_FILTER_WR_RX_CHAN) 599 #define G_FW_FILTER_WR_RX_CHAN(x) \ 600 (((x) >> S_FW_FILTER_WR_RX_CHAN) & M_FW_FILTER_WR_RX_CHAN) 601 #define F_FW_FILTER_WR_RX_CHAN V_FW_FILTER_WR_RX_CHAN(1U) 602 603 #define S_FW_FILTER_WR_RX_RPL_IQ 0 604 #define M_FW_FILTER_WR_RX_RPL_IQ 0x3ff 605 #define V_FW_FILTER_WR_RX_RPL_IQ(x) ((x) << S_FW_FILTER_WR_RX_RPL_IQ) 606 #define G_FW_FILTER_WR_RX_RPL_IQ(x) \ 607 (((x) >> S_FW_FILTER_WR_RX_RPL_IQ) & M_FW_FILTER_WR_RX_RPL_IQ) 608 609 #define S_FW_FILTER2_WR_FILTER_TYPE 1 610 #define M_FW_FILTER2_WR_FILTER_TYPE 0x1 611 #define V_FW_FILTER2_WR_FILTER_TYPE(x) ((x) << S_FW_FILTER2_WR_FILTER_TYPE) 612 #define G_FW_FILTER2_WR_FILTER_TYPE(x) \ 613 (((x) >> S_FW_FILTER2_WR_FILTER_TYPE) & M_FW_FILTER2_WR_FILTER_TYPE) 614 #define F_FW_FILTER2_WR_FILTER_TYPE V_FW_FILTER2_WR_FILTER_TYPE(1U) 615 616 #define S_FW_FILTER2_WR_SWAPMAC 0 617 #define M_FW_FILTER2_WR_SWAPMAC 0x1 618 #define V_FW_FILTER2_WR_SWAPMAC(x) ((x) << S_FW_FILTER2_WR_SWAPMAC) 619 #define G_FW_FILTER2_WR_SWAPMAC(x) \ 620 (((x) >> S_FW_FILTER2_WR_SWAPMAC) & M_FW_FILTER2_WR_SWAPMAC) 621 #define F_FW_FILTER2_WR_SWAPMAC V_FW_FILTER2_WR_SWAPMAC(1U) 622 623 #define S_FW_FILTER2_WR_NATMODE 5 624 #define M_FW_FILTER2_WR_NATMODE 0x7 625 #define V_FW_FILTER2_WR_NATMODE(x) ((x) << S_FW_FILTER2_WR_NATMODE) 626 #define G_FW_FILTER2_WR_NATMODE(x) \ 627 (((x) >> S_FW_FILTER2_WR_NATMODE) & M_FW_FILTER2_WR_NATMODE) 628 629 #define S_FW_FILTER2_WR_NATFLAGCHECK 4 630 #define M_FW_FILTER2_WR_NATFLAGCHECK 0x1 631 #define V_FW_FILTER2_WR_NATFLAGCHECK(x) ((x) << S_FW_FILTER2_WR_NATFLAGCHECK) 632 #define G_FW_FILTER2_WR_NATFLAGCHECK(x) \ 633 (((x) >> S_FW_FILTER2_WR_NATFLAGCHECK) & M_FW_FILTER2_WR_NATFLAGCHECK) 634 #define F_FW_FILTER2_WR_NATFLAGCHECK V_FW_FILTER2_WR_NATFLAGCHECK(1U) 635 636 #define S_FW_FILTER2_WR_ULP_TYPE 0 637 #define M_FW_FILTER2_WR_ULP_TYPE 0xf 638 #define V_FW_FILTER2_WR_ULP_TYPE(x) ((x) << S_FW_FILTER2_WR_ULP_TYPE) 639 #define G_FW_FILTER2_WR_ULP_TYPE(x) \ 640 (((x) >> S_FW_FILTER2_WR_ULP_TYPE) & M_FW_FILTER2_WR_ULP_TYPE) 641 642 #define S_FW_FILTER_WR_MACI 23 643 #define M_FW_FILTER_WR_MACI 0x1ff 644 #define V_FW_FILTER_WR_MACI(x) ((x) << S_FW_FILTER_WR_MACI) 645 #define G_FW_FILTER_WR_MACI(x) \ 646 (((x) >> S_FW_FILTER_WR_MACI) & M_FW_FILTER_WR_MACI) 647 648 #define S_FW_FILTER_WR_MACIM 14 649 #define M_FW_FILTER_WR_MACIM 0x1ff 650 #define V_FW_FILTER_WR_MACIM(x) ((x) << S_FW_FILTER_WR_MACIM) 651 #define G_FW_FILTER_WR_MACIM(x) \ 652 (((x) >> S_FW_FILTER_WR_MACIM) & M_FW_FILTER_WR_MACIM) 653 654 #define S_FW_FILTER_WR_FCOE 13 655 #define M_FW_FILTER_WR_FCOE 0x1 656 #define V_FW_FILTER_WR_FCOE(x) ((x) << S_FW_FILTER_WR_FCOE) 657 #define G_FW_FILTER_WR_FCOE(x) \ 658 (((x) >> S_FW_FILTER_WR_FCOE) & M_FW_FILTER_WR_FCOE) 659 #define F_FW_FILTER_WR_FCOE V_FW_FILTER_WR_FCOE(1U) 660 661 #define S_FW_FILTER_WR_FCOEM 12 662 #define M_FW_FILTER_WR_FCOEM 0x1 663 #define V_FW_FILTER_WR_FCOEM(x) ((x) << S_FW_FILTER_WR_FCOEM) 664 #define G_FW_FILTER_WR_FCOEM(x) \ 665 (((x) >> S_FW_FILTER_WR_FCOEM) & M_FW_FILTER_WR_FCOEM) 666 #define F_FW_FILTER_WR_FCOEM V_FW_FILTER_WR_FCOEM(1U) 667 668 #define S_FW_FILTER_WR_PORT 9 669 #define M_FW_FILTER_WR_PORT 0x7 670 #define V_FW_FILTER_WR_PORT(x) ((x) << S_FW_FILTER_WR_PORT) 671 #define G_FW_FILTER_WR_PORT(x) \ 672 (((x) >> S_FW_FILTER_WR_PORT) & M_FW_FILTER_WR_PORT) 673 674 #define S_FW_FILTER_WR_PORTM 6 675 #define M_FW_FILTER_WR_PORTM 0x7 676 #define V_FW_FILTER_WR_PORTM(x) ((x) << S_FW_FILTER_WR_PORTM) 677 #define G_FW_FILTER_WR_PORTM(x) \ 678 (((x) >> S_FW_FILTER_WR_PORTM) & M_FW_FILTER_WR_PORTM) 679 680 #define S_FW_FILTER_WR_MATCHTYPE 3 681 #define M_FW_FILTER_WR_MATCHTYPE 0x7 682 #define V_FW_FILTER_WR_MATCHTYPE(x) ((x) << S_FW_FILTER_WR_MATCHTYPE) 683 #define G_FW_FILTER_WR_MATCHTYPE(x) \ 684 (((x) >> S_FW_FILTER_WR_MATCHTYPE) & M_FW_FILTER_WR_MATCHTYPE) 685 686 #define S_FW_FILTER_WR_MATCHTYPEM 0 687 #define M_FW_FILTER_WR_MATCHTYPEM 0x7 688 #define V_FW_FILTER_WR_MATCHTYPEM(x) ((x) << S_FW_FILTER_WR_MATCHTYPEM) 689 #define G_FW_FILTER_WR_MATCHTYPEM(x) \ 690 (((x) >> S_FW_FILTER_WR_MATCHTYPEM) & M_FW_FILTER_WR_MATCHTYPEM) 691 692 #define S_FW_FILTER2_WR_ROCEV2 31 693 #define M_FW_FILTER2_WR_ROCEV2 0x1 694 #define V_FW_FILTER2_WR_ROCEV2(x) ((x) << S_FW_FILTER2_WR_ROCEV2) 695 #define G_FW_FILTER2_WR_ROCEV2(x) \ 696 (((x) >> S_FW_FILTER2_WR_ROCEV2) & M_FW_FILTER2_WR_ROCEV2) 697 #define F_FW_FILTER2_WR_ROCEV2 V_FW_FILTER2_WR_ROCEV2(1U) 698 699 #define S_FW_FILTER2_WR_QPN 0 700 #define M_FW_FILTER2_WR_QPN 0xffffff 701 #define V_FW_FILTER2_WR_QPN(x) ((x) << S_FW_FILTER2_WR_QPN) 702 #define G_FW_FILTER2_WR_QPN(x) \ 703 (((x) >> S_FW_FILTER2_WR_QPN) & M_FW_FILTER2_WR_QPN) 704 705 struct fw_ulptx_wr { 706 __be32 op_to_compl; 707 __be32 flowid_len16; 708 __u64 cookie; 709 }; 710 711 /* flag for packet type - control packet (0), data packet (1) 712 */ 713 #define S_FW_ULPTX_WR_DATA 28 714 #define M_FW_ULPTX_WR_DATA 0x1 715 #define V_FW_ULPTX_WR_DATA(x) ((x) << S_FW_ULPTX_WR_DATA) 716 #define G_FW_ULPTX_WR_DATA(x) \ 717 (((x) >> S_FW_ULPTX_WR_DATA) & M_FW_ULPTX_WR_DATA) 718 #define F_FW_ULPTX_WR_DATA V_FW_ULPTX_WR_DATA(1U) 719 720 struct fw_tp_wr { 721 __be32 op_to_immdlen; 722 __be32 flowid_len16; 723 __u64 cookie; 724 }; 725 726 struct fw_eth_tx_pkt_wr { 727 __be32 op_immdlen; 728 __be32 equiq_to_len16; 729 __be64 r3; 730 }; 731 732 #define S_FW_ETH_TX_PKT_WR_IMMDLEN 0 733 #define M_FW_ETH_TX_PKT_WR_IMMDLEN 0x1ff 734 #define V_FW_ETH_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT_WR_IMMDLEN) 735 #define G_FW_ETH_TX_PKT_WR_IMMDLEN(x) \ 736 (((x) >> S_FW_ETH_TX_PKT_WR_IMMDLEN) & M_FW_ETH_TX_PKT_WR_IMMDLEN) 737 738 struct fw_eth_tx_pkt2_wr { 739 __be32 op_immdlen; 740 __be32 equiq_to_len16; 741 __be32 r3; 742 __be32 L4ChkDisable_to_IpHdrLen; 743 }; 744 745 #define S_FW_ETH_TX_PKT2_WR_IMMDLEN 0 746 #define M_FW_ETH_TX_PKT2_WR_IMMDLEN 0x1ff 747 #define V_FW_ETH_TX_PKT2_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IMMDLEN) 748 #define G_FW_ETH_TX_PKT2_WR_IMMDLEN(x) \ 749 (((x) >> S_FW_ETH_TX_PKT2_WR_IMMDLEN) & M_FW_ETH_TX_PKT2_WR_IMMDLEN) 750 751 #define S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 31 752 #define M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE 0x1 753 #define V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 754 ((x) << S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 755 #define G_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(x) \ 756 (((x) >> S_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) & \ 757 M_FW_ETH_TX_PKT2_WR_L4CHKDISABLE) 758 #define F_FW_ETH_TX_PKT2_WR_L4CHKDISABLE \ 759 V_FW_ETH_TX_PKT2_WR_L4CHKDISABLE(1U) 760 761 #define S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 30 762 #define M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE 0x1 763 #define V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 764 ((x) << S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 765 #define G_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(x) \ 766 (((x) >> S_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) & \ 767 M_FW_ETH_TX_PKT2_WR_L3CHKDISABLE) 768 #define F_FW_ETH_TX_PKT2_WR_L3CHKDISABLE \ 769 V_FW_ETH_TX_PKT2_WR_L3CHKDISABLE(1U) 770 771 #define S_FW_ETH_TX_PKT2_WR_IVLAN 28 772 #define M_FW_ETH_TX_PKT2_WR_IVLAN 0x1 773 #define V_FW_ETH_TX_PKT2_WR_IVLAN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLAN) 774 #define G_FW_ETH_TX_PKT2_WR_IVLAN(x) \ 775 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLAN) & M_FW_ETH_TX_PKT2_WR_IVLAN) 776 #define F_FW_ETH_TX_PKT2_WR_IVLAN V_FW_ETH_TX_PKT2_WR_IVLAN(1U) 777 778 #define S_FW_ETH_TX_PKT2_WR_IVLANTAG 12 779 #define M_FW_ETH_TX_PKT2_WR_IVLANTAG 0xffff 780 #define V_FW_ETH_TX_PKT2_WR_IVLANTAG(x) ((x) << S_FW_ETH_TX_PKT2_WR_IVLANTAG) 781 #define G_FW_ETH_TX_PKT2_WR_IVLANTAG(x) \ 782 (((x) >> S_FW_ETH_TX_PKT2_WR_IVLANTAG) & M_FW_ETH_TX_PKT2_WR_IVLANTAG) 783 784 #define S_FW_ETH_TX_PKT2_WR_CHKTYPE 8 785 #define M_FW_ETH_TX_PKT2_WR_CHKTYPE 0xf 786 #define V_FW_ETH_TX_PKT2_WR_CHKTYPE(x) ((x) << S_FW_ETH_TX_PKT2_WR_CHKTYPE) 787 #define G_FW_ETH_TX_PKT2_WR_CHKTYPE(x) \ 788 (((x) >> S_FW_ETH_TX_PKT2_WR_CHKTYPE) & M_FW_ETH_TX_PKT2_WR_CHKTYPE) 789 790 #define S_FW_ETH_TX_PKT2_WR_IPHDRLEN 0 791 #define M_FW_ETH_TX_PKT2_WR_IPHDRLEN 0xff 792 #define V_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) ((x) << S_FW_ETH_TX_PKT2_WR_IPHDRLEN) 793 #define G_FW_ETH_TX_PKT2_WR_IPHDRLEN(x) \ 794 (((x) >> S_FW_ETH_TX_PKT2_WR_IPHDRLEN) & M_FW_ETH_TX_PKT2_WR_IPHDRLEN) 795 796 struct fw_eth_tx_pkts_wr { 797 __be32 op_pkd; 798 __be32 equiq_to_len16; 799 __be32 r3; 800 __be16 plen; 801 __u8 npkt; 802 __u8 type; 803 }; 804 805 #define S_FW_PTP_TX_PKT_WR_IMMDLEN 0 806 #define M_FW_PTP_TX_PKT_WR_IMMDLEN 0x1ff 807 #define V_FW_PTP_TX_PKT_WR_IMMDLEN(x) ((x) << S_FW_PTP_TX_PKT_WR_IMMDLEN) 808 #define G_FW_PTP_TX_PKT_WR_IMMDLEN(x) \ 809 (((x) >> S_FW_PTP_TX_PKT_WR_IMMDLEN) & M_FW_PTP_TX_PKT_WR_IMMDLEN) 810 811 struct fw_eth_tx_pkt_ptp_wr { 812 __be32 op_immdlen; 813 __be32 equiq_to_len16; 814 __be64 r3; 815 }; 816 817 enum fw_eth_tx_eo_type { 818 FW_ETH_TX_EO_TYPE_UDPSEG, 819 FW_ETH_TX_EO_TYPE_TCPSEG, 820 FW_ETH_TX_EO_TYPE_NVGRESEG, 821 FW_ETH_TX_EO_TYPE_VXLANSEG, 822 FW_ETH_TX_EO_TYPE_GENEVESEG, 823 }; 824 825 struct fw_eth_tx_eo_wr { 826 __be32 op_immdlen; 827 __be32 equiq_to_len16; 828 __be64 r3; 829 union fw_eth_tx_eo { 830 struct fw_eth_tx_eo_udpseg { 831 __u8 type; 832 __u8 ethlen; 833 __be16 iplen; 834 __u8 udplen; 835 __u8 rtplen; 836 __be16 r4; 837 __be16 mss; 838 __be16 schedpktsize; 839 __be32 plen; 840 } udpseg; 841 struct fw_eth_tx_eo_tcpseg { 842 __u8 type; 843 __u8 ethlen; 844 __be16 iplen; 845 __u8 tcplen; 846 __u8 tsclk_tsoff; 847 __be16 r4; 848 __be16 mss; 849 __be16 r5; 850 __be32 plen; 851 } tcpseg; 852 struct fw_eth_tx_eo_nvgreseg { 853 __u8 type; 854 __u8 iphdroffout; 855 __be16 grehdroff; 856 __be16 iphdroffin; 857 __be16 tcphdroffin; 858 __be16 mss; 859 __be16 r4; 860 __be32 plen; 861 } nvgreseg; 862 struct fw_eth_tx_eo_vxlanseg { 863 __u8 type; 864 __u8 iphdroffout; 865 __be16 vxlanhdroff; 866 __be16 iphdroffin; 867 __be16 tcphdroffin; 868 __be16 mss; 869 __be16 r4; 870 __be32 plen; 871 872 } vxlanseg; 873 struct fw_eth_tx_eo_geneveseg { 874 __u8 type; 875 __u8 iphdroffout; 876 __be16 genevehdroff; 877 __be16 iphdroffin; 878 __be16 tcphdroffin; 879 __be16 mss; 880 __be16 r4; 881 __be32 plen; 882 } geneveseg; 883 } u; 884 }; 885 886 #define S_FW_ETH_TX_EO_WR_IMMDLEN 0 887 #define M_FW_ETH_TX_EO_WR_IMMDLEN 0x1ff 888 #define V_FW_ETH_TX_EO_WR_IMMDLEN(x) ((x) << S_FW_ETH_TX_EO_WR_IMMDLEN) 889 #define G_FW_ETH_TX_EO_WR_IMMDLEN(x) \ 890 (((x) >> S_FW_ETH_TX_EO_WR_IMMDLEN) & M_FW_ETH_TX_EO_WR_IMMDLEN) 891 892 #define S_FW_ETH_TX_EO_WR_TSCLK 6 893 #define M_FW_ETH_TX_EO_WR_TSCLK 0x3 894 #define V_FW_ETH_TX_EO_WR_TSCLK(x) ((x) << S_FW_ETH_TX_EO_WR_TSCLK) 895 #define G_FW_ETH_TX_EO_WR_TSCLK(x) \ 896 (((x) >> S_FW_ETH_TX_EO_WR_TSCLK) & M_FW_ETH_TX_EO_WR_TSCLK) 897 898 #define S_FW_ETH_TX_EO_WR_TSOFF 0 899 #define M_FW_ETH_TX_EO_WR_TSOFF 0x3f 900 #define V_FW_ETH_TX_EO_WR_TSOFF(x) ((x) << S_FW_ETH_TX_EO_WR_TSOFF) 901 #define G_FW_ETH_TX_EO_WR_TSOFF(x) \ 902 (((x) >> S_FW_ETH_TX_EO_WR_TSOFF) & M_FW_ETH_TX_EO_WR_TSOFF) 903 904 struct fw_eq_flush_wr { 905 __u8 opcode; 906 __u8 r1[3]; 907 __be32 equiq_to_len16; 908 __be64 r3; 909 }; 910 911 struct fw_ofld_connection_wr { 912 __be32 op_compl; 913 __be32 len16_pkd; 914 __u64 cookie; 915 __be64 r2; 916 __be64 r3; 917 struct fw_ofld_connection_le { 918 __be32 version_cpl; 919 __be32 filter; 920 __be32 r1; 921 __be16 lport; 922 __be16 pport; 923 union fw_ofld_connection_leip { 924 struct fw_ofld_connection_le_ipv4 { 925 __be32 pip; 926 __be32 lip; 927 __be64 r0; 928 __be64 r1; 929 __be64 r2; 930 } ipv4; 931 struct fw_ofld_connection_le_ipv6 { 932 __be64 pip_hi; 933 __be64 pip_lo; 934 __be64 lip_hi; 935 __be64 lip_lo; 936 } ipv6; 937 } u; 938 } le; 939 struct fw_ofld_connection_tcb { 940 __be32 t_state_to_astid; 941 __be16 cplrxdataack_cplpassacceptrpl; 942 __be16 rcv_adv; 943 __be32 rcv_nxt; 944 __be32 tx_max; 945 __be64 opt0; 946 __be32 opt2; 947 __be32 r1; 948 __be64 r2; 949 __be64 r3; 950 } tcb; 951 }; 952 953 #define S_FW_OFLD_CONNECTION_WR_VERSION 31 954 #define M_FW_OFLD_CONNECTION_WR_VERSION 0x1 955 #define V_FW_OFLD_CONNECTION_WR_VERSION(x) \ 956 ((x) << S_FW_OFLD_CONNECTION_WR_VERSION) 957 #define G_FW_OFLD_CONNECTION_WR_VERSION(x) \ 958 (((x) >> S_FW_OFLD_CONNECTION_WR_VERSION) & \ 959 M_FW_OFLD_CONNECTION_WR_VERSION) 960 #define F_FW_OFLD_CONNECTION_WR_VERSION V_FW_OFLD_CONNECTION_WR_VERSION(1U) 961 962 #define S_FW_OFLD_CONNECTION_WR_CPL 30 963 #define M_FW_OFLD_CONNECTION_WR_CPL 0x1 964 #define V_FW_OFLD_CONNECTION_WR_CPL(x) ((x) << S_FW_OFLD_CONNECTION_WR_CPL) 965 #define G_FW_OFLD_CONNECTION_WR_CPL(x) \ 966 (((x) >> S_FW_OFLD_CONNECTION_WR_CPL) & M_FW_OFLD_CONNECTION_WR_CPL) 967 #define F_FW_OFLD_CONNECTION_WR_CPL V_FW_OFLD_CONNECTION_WR_CPL(1U) 968 969 #define S_FW_OFLD_CONNECTION_WR_T_STATE 28 970 #define M_FW_OFLD_CONNECTION_WR_T_STATE 0xf 971 #define V_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 972 ((x) << S_FW_OFLD_CONNECTION_WR_T_STATE) 973 #define G_FW_OFLD_CONNECTION_WR_T_STATE(x) \ 974 (((x) >> S_FW_OFLD_CONNECTION_WR_T_STATE) & \ 975 M_FW_OFLD_CONNECTION_WR_T_STATE) 976 977 #define S_FW_OFLD_CONNECTION_WR_RCV_SCALE 24 978 #define M_FW_OFLD_CONNECTION_WR_RCV_SCALE 0xf 979 #define V_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 980 ((x) << S_FW_OFLD_CONNECTION_WR_RCV_SCALE) 981 #define G_FW_OFLD_CONNECTION_WR_RCV_SCALE(x) \ 982 (((x) >> S_FW_OFLD_CONNECTION_WR_RCV_SCALE) & \ 983 M_FW_OFLD_CONNECTION_WR_RCV_SCALE) 984 985 #define S_FW_OFLD_CONNECTION_WR_ASTID 0 986 #define M_FW_OFLD_CONNECTION_WR_ASTID 0xffffff 987 #define V_FW_OFLD_CONNECTION_WR_ASTID(x) \ 988 ((x) << S_FW_OFLD_CONNECTION_WR_ASTID) 989 #define G_FW_OFLD_CONNECTION_WR_ASTID(x) \ 990 (((x) >> S_FW_OFLD_CONNECTION_WR_ASTID) & M_FW_OFLD_CONNECTION_WR_ASTID) 991 992 #define S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 15 993 #define M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK 0x1 994 #define V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 995 ((x) << S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 996 #define G_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(x) \ 997 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) & \ 998 M_FW_OFLD_CONNECTION_WR_CPLRXDATAACK) 999 #define F_FW_OFLD_CONNECTION_WR_CPLRXDATAACK \ 1000 V_FW_OFLD_CONNECTION_WR_CPLRXDATAACK(1U) 1001 1002 #define S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 14 1003 #define M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL 0x1 1004 #define V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 1005 ((x) << S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 1006 #define G_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(x) \ 1007 (((x) >> S_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) & \ 1008 M_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL) 1009 #define F_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL \ 1010 V_FW_OFLD_CONNECTION_WR_CPLPASSACCEPTRPL(1U) 1011 1012 enum fw_flowc_mnem_tcpstate { 1013 FW_FLOWC_MNEM_TCPSTATE_CLOSED = 0, /* illegal */ 1014 FW_FLOWC_MNEM_TCPSTATE_LISTEN = 1, /* illegal */ 1015 FW_FLOWC_MNEM_TCPSTATE_SYNSENT = 2, /* illegal */ 1016 FW_FLOWC_MNEM_TCPSTATE_SYNRECEIVED = 3, /* illegal */ 1017 FW_FLOWC_MNEM_TCPSTATE_ESTABLISHED = 4, /* default */ 1018 FW_FLOWC_MNEM_TCPSTATE_CLOSEWAIT = 5, /* got peer close already */ 1019 FW_FLOWC_MNEM_TCPSTATE_FINWAIT1 = 6, /* haven't gotten ACK for FIN and 1020 * will resend FIN - equiv ESTAB 1021 */ 1022 FW_FLOWC_MNEM_TCPSTATE_CLOSING = 7, /* haven't gotten ACK for FIN and 1023 * will resend FIN but have 1024 * received FIN 1025 */ 1026 FW_FLOWC_MNEM_TCPSTATE_LASTACK = 8, /* haven't gotten ACK for FIN and 1027 * will resend FIN but have 1028 * received FIN 1029 */ 1030 FW_FLOWC_MNEM_TCPSTATE_FINWAIT2 = 9, /* sent FIN and got FIN + ACK, 1031 * waiting for FIN 1032 */ 1033 FW_FLOWC_MNEM_TCPSTATE_TIMEWAIT = 10, /* not expected */ 1034 }; 1035 1036 enum fw_flowc_mnem_eostate { 1037 FW_FLOWC_MNEM_EOSTATE_CLOSED = 0, /* illegal */ 1038 FW_FLOWC_MNEM_EOSTATE_ESTABLISHED = 1, /* default */ 1039 FW_FLOWC_MNEM_EOSTATE_CLOSING = 2, /* graceful close, after sending 1040 * outstanding payload 1041 */ 1042 FW_FLOWC_MNEM_EOSTATE_ABORTING = 3, /* immediate close, after 1043 * discarding outstanding payload 1044 */ 1045 }; 1046 1047 enum fw_flowc_mnem { 1048 FW_FLOWC_MNEM_PFNVFN = 0, /* PFN [15:8] VFN [7:0] */ 1049 FW_FLOWC_MNEM_CH = 1, 1050 FW_FLOWC_MNEM_PORT = 2, 1051 FW_FLOWC_MNEM_IQID = 3, 1052 FW_FLOWC_MNEM_SNDNXT = 4, 1053 FW_FLOWC_MNEM_RCVNXT = 5, 1054 FW_FLOWC_MNEM_SNDBUF = 6, 1055 FW_FLOWC_MNEM_MSS = 7, 1056 FW_FLOWC_MNEM_TXDATAPLEN_MAX = 8, 1057 FW_FLOWC_MNEM_TCPSTATE = 9, 1058 FW_FLOWC_MNEM_EOSTATE = 10, 1059 FW_FLOWC_MNEM_SCHEDCLASS = 11, 1060 FW_FLOWC_MNEM_DCBPRIO = 12, 1061 FW_FLOWC_MNEM_SND_SCALE = 13, 1062 FW_FLOWC_MNEM_RCV_SCALE = 14, 1063 FW_FLOWC_MNEM_ULP_MODE = 15, 1064 FW_FLOWC_MNEM_EQID = 16, 1065 FW_FLOWC_MNEM_CONG_ALG = 17, 1066 FW_FLOWC_MNEM_TXDATAPLEN_MIN = 18, 1067 FW_FLOWC_MNEM_MAX = 19, 1068 }; 1069 1070 struct fw_flowc_mnemval { 1071 __u8 mnemonic; 1072 __u8 r4[3]; 1073 __be32 val; 1074 }; 1075 1076 struct fw_flowc_wr { 1077 __be32 op_to_nparams; 1078 __be32 flowid_len16; 1079 #ifndef C99_NOT_SUPPORTED 1080 struct fw_flowc_mnemval mnemval[0]; 1081 #endif 1082 }; 1083 1084 #define S_FW_FLOWC_WR_NPARAMS 0 1085 #define M_FW_FLOWC_WR_NPARAMS 0xff 1086 #define V_FW_FLOWC_WR_NPARAMS(x) ((x) << S_FW_FLOWC_WR_NPARAMS) 1087 #define G_FW_FLOWC_WR_NPARAMS(x) \ 1088 (((x) >> S_FW_FLOWC_WR_NPARAMS) & M_FW_FLOWC_WR_NPARAMS) 1089 1090 struct fw_ofld_tx_data_wr { 1091 __be32 op_to_immdlen; 1092 __be32 flowid_len16; 1093 __be32 plen; 1094 __be32 lsodisable_to_flags; 1095 }; 1096 1097 #define S_FW_OFLD_TX_DATA_WR_LSODISABLE 31 1098 #define M_FW_OFLD_TX_DATA_WR_LSODISABLE 0x1 1099 #define V_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1100 ((x) << S_FW_OFLD_TX_DATA_WR_LSODISABLE) 1101 #define G_FW_OFLD_TX_DATA_WR_LSODISABLE(x) \ 1102 (((x) >> S_FW_OFLD_TX_DATA_WR_LSODISABLE) & \ 1103 M_FW_OFLD_TX_DATA_WR_LSODISABLE) 1104 #define F_FW_OFLD_TX_DATA_WR_LSODISABLE V_FW_OFLD_TX_DATA_WR_LSODISABLE(1U) 1105 1106 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLD 30 1107 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLD 0x1 1108 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1109 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1110 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLD(x) \ 1111 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLD) & M_FW_OFLD_TX_DATA_WR_ALIGNPLD) 1112 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLD V_FW_OFLD_TX_DATA_WR_ALIGNPLD(1U) 1113 1114 #define S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 29 1115 #define M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE 0x1 1116 #define V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1117 ((x) << S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1118 #define G_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(x) \ 1119 (((x) >> S_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) & \ 1120 M_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE) 1121 #define F_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE \ 1122 V_FW_OFLD_TX_DATA_WR_ALIGNPLDSHOVE(1U) 1123 1124 #define S_FW_OFLD_TX_DATA_WR_FLAGS 0 1125 #define M_FW_OFLD_TX_DATA_WR_FLAGS 0xfffffff 1126 #define V_FW_OFLD_TX_DATA_WR_FLAGS(x) ((x) << S_FW_OFLD_TX_DATA_WR_FLAGS) 1127 #define G_FW_OFLD_TX_DATA_WR_FLAGS(x) \ 1128 (((x) >> S_FW_OFLD_TX_DATA_WR_FLAGS) & M_FW_OFLD_TX_DATA_WR_FLAGS) 1129 1130 1131 /* Use fw_ofld_tx_data_wr structure */ 1132 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_HI 10 1133 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_HI 0x3fffff 1134 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1135 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1136 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_HI(x) \ 1137 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_HI) & M_FW_ISCSI_TX_DATA_WR_FLAGS_HI) 1138 1139 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 9 1140 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO 0x1 1141 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1142 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1143 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 1144 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) & \ 1145 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO) 1146 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO \ 1147 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_ISO(1U) 1148 1149 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 8 1150 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI 0x1 1151 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1152 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1153 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(x) \ 1154 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) & \ 1155 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI) 1156 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI \ 1157 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_PI(1U) 1158 1159 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 7 1160 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 1161 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1162 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1163 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 1164 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 1165 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC) 1166 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC \ 1167 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 1168 1169 #define S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 6 1170 #define M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 1171 #define V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1172 ((x) << S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1173 #define G_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 1174 (((x) >> S_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 1175 M_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC) 1176 #define F_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC \ 1177 V_FW_ISCSI_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 1178 1179 #define S_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0 1180 #define M_FW_ISCSI_TX_DATA_WR_FLAGS_LO 0x3f 1181 #define V_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1182 ((x) << S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1183 #define G_FW_ISCSI_TX_DATA_WR_FLAGS_LO(x) \ 1184 (((x) >> S_FW_ISCSI_TX_DATA_WR_FLAGS_LO) & M_FW_ISCSI_TX_DATA_WR_FLAGS_LO) 1185 1186 struct fw_ofld_tx_data_v2_wr { 1187 __be32 op_to_immdlen; 1188 __be32 flowid_len16; 1189 __be32 r4; 1190 __be16 r5; 1191 __be16 wrid; 1192 __be32 r6; 1193 __be32 seqno; 1194 __be32 plen; 1195 __be32 lsodisable_to_flags; 1196 }; 1197 1198 #define S_FW_OFLD_TX_DATA_V2_WR_LSODISABLE 31 1199 #define M_FW_OFLD_TX_DATA_V2_WR_LSODISABLE 0x1 1200 #define V_FW_OFLD_TX_DATA_V2_WR_LSODISABLE(x) \ 1201 ((x) << S_FW_OFLD_TX_DATA_V2_WR_LSODISABLE) 1202 #define G_FW_OFLD_TX_DATA_V2_WR_LSODISABLE(x) \ 1203 (((x) >> S_FW_OFLD_TX_DATA_V2_WR_LSODISABLE) & \ 1204 M_FW_OFLD_TX_DATA_V2_WR_LSODISABLE) 1205 #define F_FW_OFLD_TX_DATA_V2_WR_LSODISABLE \ 1206 V_FW_OFLD_TX_DATA_V2_WR_LSODISABLE(1U) 1207 1208 #define S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD 30 1209 #define M_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD 0x1 1210 #define V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD(x) \ 1211 ((x) << S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD) 1212 #define G_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD(x) \ 1213 (((x) >> S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD) & \ 1214 M_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD) 1215 #define F_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD \ 1216 V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLD(1U) 1217 1218 #define S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE 29 1219 #define M_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE 0x1 1220 #define V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE(x) \ 1221 ((x) << S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE) 1222 #define G_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE(x) \ 1223 (((x) >> S_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE) & \ 1224 M_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE) 1225 #define F_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE \ 1226 V_FW_OFLD_TX_DATA_V2_WR_ALIGNPLDSHOVE(1U) 1227 1228 #define S_FW_OFLD_TX_DATA_V2_WR_FLAGS 0 1229 #define M_FW_OFLD_TX_DATA_V2_WR_FLAGS 0xfffffff 1230 #define V_FW_OFLD_TX_DATA_V2_WR_FLAGS(x) \ 1231 ((x) << S_FW_OFLD_TX_DATA_V2_WR_FLAGS) 1232 #define G_FW_OFLD_TX_DATA_V2_WR_FLAGS(x) \ 1233 (((x) >> S_FW_OFLD_TX_DATA_V2_WR_FLAGS) & M_FW_OFLD_TX_DATA_V2_WR_FLAGS) 1234 1235 struct fw_cmd_wr { 1236 __be32 op_dma; 1237 __be32 len16_pkd; 1238 __be64 cookie_daddr; 1239 }; 1240 1241 #define S_FW_CMD_WR_DMA 17 1242 #define M_FW_CMD_WR_DMA 0x1 1243 #define V_FW_CMD_WR_DMA(x) ((x) << S_FW_CMD_WR_DMA) 1244 #define G_FW_CMD_WR_DMA(x) (((x) >> S_FW_CMD_WR_DMA) & M_FW_CMD_WR_DMA) 1245 #define F_FW_CMD_WR_DMA V_FW_CMD_WR_DMA(1U) 1246 1247 struct fw_eth_tx_pkt_vm_wr { 1248 __be32 op_immdlen; 1249 __be32 equiq_to_len16; 1250 __be32 r3[2]; 1251 __u8 ethmacdst[6]; 1252 __u8 ethmacsrc[6]; 1253 __be16 ethtype; 1254 __be16 vlantci; 1255 }; 1256 1257 struct fw_eth_tx_pkts_vm_wr { 1258 __be32 op_pkd; 1259 __be32 equiq_to_len16; 1260 __be32 r3; 1261 __be16 plen; 1262 __u8 npkt; 1263 __u8 r4; 1264 __u8 ethmacdst[6]; 1265 __u8 ethmacsrc[6]; 1266 __be16 ethtype; 1267 __be16 vlantci; 1268 }; 1269 1270 /****************************************************************************** 1271 * R I W O R K R E Q U E S T s 1272 **************************************/ 1273 1274 enum fw_ri_wr_opcode { 1275 FW_RI_RDMA_WRITE = 0x0, /* IETF RDMAP v1.0 ... */ 1276 FW_RI_READ_REQ = 0x1, 1277 FW_RI_READ_RESP = 0x2, 1278 FW_RI_SEND = 0x3, 1279 FW_RI_SEND_WITH_INV = 0x4, 1280 FW_RI_SEND_WITH_SE = 0x5, 1281 FW_RI_SEND_WITH_SE_INV = 0x6, 1282 FW_RI_TERMINATE = 0x7, 1283 FW_RI_RDMA_INIT = 0x8, /* CHELSIO RI specific ... */ 1284 FW_RI_BIND_MW = 0x9, 1285 FW_RI_FAST_REGISTER = 0xa, 1286 FW_RI_LOCAL_INV = 0xb, 1287 FW_RI_QP_MODIFY = 0xc, 1288 FW_RI_BYPASS = 0xd, 1289 FW_RI_RECEIVE = 0xe, 1290 #if 0 1291 FW_RI_SEND_IMMEDIATE = 0x8, 1292 FW_RI_SEND_IMMEDIATE_WITH_SE = 0x9, 1293 FW_RI_ATOMIC_REQUEST = 0xa, 1294 FW_RI_ATOMIC_RESPONSE = 0xb, 1295 1296 FW_RI_BIND_MW = 0xc, /* CHELSIO RI specific ... */ 1297 FW_RI_FAST_REGISTER = 0xd, 1298 FW_RI_LOCAL_INV = 0xe, 1299 #endif 1300 /* Chelsio specific */ 1301 FW_RI_SGE_EC_CR_RETURN = 0xf, 1302 FW_RI_WRITE_IMMEDIATE = FW_RI_RDMA_INIT, 1303 FW_RI_SEND_IMMEDIATE = FW_RI_RDMA_INIT, 1304 1305 FW_RI_ROCEV2_SEND = 0x0, 1306 FW_RI_ROCEV2_WRITE = 0x0, 1307 FW_RI_ROCEV2_SEND_WITH_INV = 0x5, 1308 FW_RI_ROCEV2_SEND_IMMEDIATE = 0xa, 1309 }; 1310 1311 enum fw_ri_wr_flags { 1312 FW_RI_COMPLETION_FLAG = 0x01, 1313 FW_RI_NOTIFICATION_FLAG = 0x02, 1314 FW_RI_SOLICITED_EVENT_FLAG = 0x04, 1315 FW_RI_READ_FENCE_FLAG = 0x08, 1316 FW_RI_LOCAL_FENCE_FLAG = 0x10, 1317 FW_RI_RDMA_READ_INVALIDATE = 0x20, 1318 FW_RI_RDMA_WRITE_WITH_IMMEDIATE = 0x40, 1319 //FW_RI_REPLAYED_WR_FLAG = 0x80, 1320 }; 1321 1322 enum fw_ri_mpa_attrs { 1323 FW_RI_MPA_RX_MARKER_ENABLE = 0x01, 1324 FW_RI_MPA_TX_MARKER_ENABLE = 0x02, 1325 FW_RI_MPA_CRC_ENABLE = 0x04, 1326 FW_RI_MPA_IETF_ENABLE = 0x08 1327 }; 1328 1329 enum fw_ri_qp_caps { 1330 FW_RI_QP_RDMA_READ_ENABLE = 0x01, 1331 FW_RI_QP_RDMA_WRITE_ENABLE = 0x02, 1332 FW_RI_QP_BIND_ENABLE = 0x04, 1333 FW_RI_QP_FAST_REGISTER_ENABLE = 0x08, 1334 FW_RI_QP_STAG0_ENABLE = 0x10, 1335 FW_RI_QP_RDMA_READ_REQ_0B_ENABLE= 0x80, 1336 }; 1337 1338 enum fw_ri_addr_type { 1339 FW_RI_ZERO_BASED_TO = 0x00, 1340 FW_RI_VA_BASED_TO = 0x01 1341 }; 1342 1343 enum fw_ri_mem_perms { 1344 FW_RI_MEM_ACCESS_REM_WRITE = 0x01, 1345 FW_RI_MEM_ACCESS_REM_READ = 0x02, 1346 FW_RI_MEM_ACCESS_REM = 0x03, 1347 FW_RI_MEM_ACCESS_LOCAL_WRITE = 0x04, 1348 FW_RI_MEM_ACCESS_LOCAL_READ = 0x08, 1349 FW_RI_MEM_ACCESS_LOCAL = 0x0C 1350 }; 1351 1352 enum fw_ri_stag_type { 1353 FW_RI_STAG_NSMR = 0x00, 1354 FW_RI_STAG_SMR = 0x01, 1355 FW_RI_STAG_MW = 0x02, 1356 FW_RI_STAG_MW_RELAXED = 0x03 1357 }; 1358 1359 enum fw_ri_data_op { 1360 FW_RI_DATA_IMMD = 0x81, 1361 FW_RI_DATA_DSGL = 0x82, 1362 FW_RI_DATA_ISGL = 0x83 1363 }; 1364 1365 enum fw_ri_sgl_depth { 1366 FW_RI_SGL_DEPTH_MAX_SQ = 16, 1367 FW_RI_SGL_DEPTH_MAX_RQ = 4 1368 }; 1369 1370 enum fw_ri_cqe_err { 1371 FW_RI_CQE_ERR_SUCCESS = 0x00, /* success, no error detected */ 1372 FW_RI_CQE_ERR_STAG = 0x01, /* STAG invalid */ 1373 FW_RI_CQE_ERR_PDID = 0x02, /* PDID mismatch */ 1374 FW_RI_CQE_ERR_QPID = 0x03, /* QPID mismatch */ 1375 FW_RI_CQE_ERR_ACCESS = 0x04, /* Invalid access right */ 1376 FW_RI_CQE_ERR_WRAP = 0x05, /* Wrap error */ 1377 FW_RI_CQE_ERR_BOUND = 0x06, /* base and bounds violation */ 1378 FW_RI_CQE_ERR_INVALIDATE_SHARED_MR = 0x07, /* attempt to invalidate a SMR */ 1379 FW_RI_CQE_ERR_INVALIDATE_MR_WITH_MW_BOUND = 0x08, /* attempt to invalidate a MR w MW */ 1380 FW_RI_CQE_ERR_ECC = 0x09, /* ECC error detected */ 1381 FW_RI_CQE_ERR_ECC_PSTAG = 0x0A, /* ECC error detected when reading the PSTAG for a MW Invalidate */ 1382 FW_RI_CQE_ERR_PBL_ADDR_BOUND = 0x0B, /* pbl address out of bound : software error */ 1383 FW_RI_CQE_ERR_CRC = 0x10, /* CRC error */ 1384 FW_RI_CQE_ERR_MARKER = 0x11, /* Marker error */ 1385 FW_RI_CQE_ERR_PDU_LEN_ERR = 0x12, /* invalid PDU length */ 1386 FW_RI_CQE_ERR_OUT_OF_RQE = 0x13, /* out of RQE */ 1387 FW_RI_CQE_ERR_DDP_VERSION = 0x14, /* wrong DDP version */ 1388 FW_RI_CQE_ERR_RDMA_VERSION = 0x15, /* wrong RDMA version */ 1389 FW_RI_CQE_ERR_OPCODE = 0x16, /* invalid rdma opcode */ 1390 FW_RI_CQE_ERR_DDP_QUEUE_NUM = 0x17, /* invalid ddp queue number */ 1391 FW_RI_CQE_ERR_MSN = 0x18, /* MSN error */ 1392 FW_RI_CQE_ERR_TBIT = 0x19, /* tag bit not set correctly */ 1393 FW_RI_CQE_ERR_MO = 0x1A, /* MO not zero for TERMINATE or READ_REQ */ 1394 FW_RI_CQE_ERR_MSN_GAP = 0x1B, /* */ 1395 FW_RI_CQE_ERR_MSN_RANGE = 0x1C, /* */ 1396 FW_RI_CQE_ERR_IRD_OVERFLOW = 0x1D, /* */ 1397 FW_RI_CQE_ERR_RQE_ADDR_BOUND = 0x1E, /* RQE address out of bound : software error */ 1398 FW_RI_CQE_ERR_INTERNAL_ERR = 0x1F /* internel error (opcode mismatch) */ 1399 1400 }; 1401 1402 struct fw_ri_dsge_pair { 1403 __be32 len[2]; 1404 __be64 addr[2]; 1405 }; 1406 1407 struct fw_ri_dsgl { 1408 __u8 op; 1409 __u8 r1; 1410 __be16 nsge; 1411 __be32 len0; 1412 __be64 addr0; 1413 #ifndef C99_NOT_SUPPORTED 1414 struct fw_ri_dsge_pair sge[0]; 1415 #endif 1416 }; 1417 1418 struct fw_ri_sge { 1419 __be32 stag; 1420 __be32 len; 1421 __be64 to; 1422 }; 1423 1424 struct fw_ri_isgl { 1425 __u8 op; 1426 __u8 r1; 1427 __be16 nsge; 1428 __be32 r2; 1429 #ifndef C99_NOT_SUPPORTED 1430 struct fw_ri_sge sge[0]; 1431 #endif 1432 }; 1433 1434 struct fw_ri_immd { 1435 __u8 op; 1436 __u8 r1; 1437 __be16 r2; 1438 __be32 immdlen; 1439 #ifndef C99_NOT_SUPPORTED 1440 __u8 data[0]; 1441 #endif 1442 }; 1443 1444 struct fw_ri_tpte { 1445 __be32 valid_to_pdid; 1446 __be32 locread_to_qpid; 1447 __be32 nosnoop_pbladdr; 1448 __be32 len_lo; 1449 __be32 va_hi; 1450 __be32 va_lo_fbo; 1451 __be32 dca_mwbcnt_pstag; 1452 __be32 len_hi; 1453 }; 1454 1455 #define S_FW_RI_TPTE_VALID 31 1456 #define M_FW_RI_TPTE_VALID 0x1 1457 #define V_FW_RI_TPTE_VALID(x) ((x) << S_FW_RI_TPTE_VALID) 1458 #define G_FW_RI_TPTE_VALID(x) \ 1459 (((x) >> S_FW_RI_TPTE_VALID) & M_FW_RI_TPTE_VALID) 1460 #define F_FW_RI_TPTE_VALID V_FW_RI_TPTE_VALID(1U) 1461 1462 #define S_FW_RI_TPTE_STAGKEY 23 1463 #define M_FW_RI_TPTE_STAGKEY 0xff 1464 #define V_FW_RI_TPTE_STAGKEY(x) ((x) << S_FW_RI_TPTE_STAGKEY) 1465 #define G_FW_RI_TPTE_STAGKEY(x) \ 1466 (((x) >> S_FW_RI_TPTE_STAGKEY) & M_FW_RI_TPTE_STAGKEY) 1467 1468 #define S_FW_RI_TPTE_STAGSTATE 22 1469 #define M_FW_RI_TPTE_STAGSTATE 0x1 1470 #define V_FW_RI_TPTE_STAGSTATE(x) ((x) << S_FW_RI_TPTE_STAGSTATE) 1471 #define G_FW_RI_TPTE_STAGSTATE(x) \ 1472 (((x) >> S_FW_RI_TPTE_STAGSTATE) & M_FW_RI_TPTE_STAGSTATE) 1473 #define F_FW_RI_TPTE_STAGSTATE V_FW_RI_TPTE_STAGSTATE(1U) 1474 1475 #define S_FW_RI_TPTE_STAGTYPE 20 1476 #define M_FW_RI_TPTE_STAGTYPE 0x3 1477 #define V_FW_RI_TPTE_STAGTYPE(x) ((x) << S_FW_RI_TPTE_STAGTYPE) 1478 #define G_FW_RI_TPTE_STAGTYPE(x) \ 1479 (((x) >> S_FW_RI_TPTE_STAGTYPE) & M_FW_RI_TPTE_STAGTYPE) 1480 1481 #define S_FW_RI_TPTE_PDID 0 1482 #define M_FW_RI_TPTE_PDID 0xfffff 1483 #define V_FW_RI_TPTE_PDID(x) ((x) << S_FW_RI_TPTE_PDID) 1484 #define G_FW_RI_TPTE_PDID(x) \ 1485 (((x) >> S_FW_RI_TPTE_PDID) & M_FW_RI_TPTE_PDID) 1486 1487 #define S_FW_RI_TPTE_PERM 28 1488 #define M_FW_RI_TPTE_PERM 0xf 1489 #define V_FW_RI_TPTE_PERM(x) ((x) << S_FW_RI_TPTE_PERM) 1490 #define G_FW_RI_TPTE_PERM(x) \ 1491 (((x) >> S_FW_RI_TPTE_PERM) & M_FW_RI_TPTE_PERM) 1492 1493 #define S_FW_RI_TPTE_REMINVDIS 27 1494 #define M_FW_RI_TPTE_REMINVDIS 0x1 1495 #define V_FW_RI_TPTE_REMINVDIS(x) ((x) << S_FW_RI_TPTE_REMINVDIS) 1496 #define G_FW_RI_TPTE_REMINVDIS(x) \ 1497 (((x) >> S_FW_RI_TPTE_REMINVDIS) & M_FW_RI_TPTE_REMINVDIS) 1498 #define F_FW_RI_TPTE_REMINVDIS V_FW_RI_TPTE_REMINVDIS(1U) 1499 1500 #define S_FW_RI_TPTE_ADDRTYPE 26 1501 #define M_FW_RI_TPTE_ADDRTYPE 1 1502 #define V_FW_RI_TPTE_ADDRTYPE(x) ((x) << S_FW_RI_TPTE_ADDRTYPE) 1503 #define G_FW_RI_TPTE_ADDRTYPE(x) \ 1504 (((x) >> S_FW_RI_TPTE_ADDRTYPE) & M_FW_RI_TPTE_ADDRTYPE) 1505 #define F_FW_RI_TPTE_ADDRTYPE V_FW_RI_TPTE_ADDRTYPE(1U) 1506 1507 #define S_FW_RI_TPTE_MWBINDEN 25 1508 #define M_FW_RI_TPTE_MWBINDEN 0x1 1509 #define V_FW_RI_TPTE_MWBINDEN(x) ((x) << S_FW_RI_TPTE_MWBINDEN) 1510 #define G_FW_RI_TPTE_MWBINDEN(x) \ 1511 (((x) >> S_FW_RI_TPTE_MWBINDEN) & M_FW_RI_TPTE_MWBINDEN) 1512 #define F_FW_RI_TPTE_MWBINDEN V_FW_RI_TPTE_MWBINDEN(1U) 1513 1514 #define S_FW_RI_TPTE_PS 20 1515 #define M_FW_RI_TPTE_PS 0x1f 1516 #define V_FW_RI_TPTE_PS(x) ((x) << S_FW_RI_TPTE_PS) 1517 #define G_FW_RI_TPTE_PS(x) \ 1518 (((x) >> S_FW_RI_TPTE_PS) & M_FW_RI_TPTE_PS) 1519 1520 #define S_FW_RI_TPTE_QPID 0 1521 #define M_FW_RI_TPTE_QPID 0xfffff 1522 #define V_FW_RI_TPTE_QPID(x) ((x) << S_FW_RI_TPTE_QPID) 1523 #define G_FW_RI_TPTE_QPID(x) \ 1524 (((x) >> S_FW_RI_TPTE_QPID) & M_FW_RI_TPTE_QPID) 1525 1526 #define S_FW_RI_TPTE_NOSNOOP 31 1527 #define M_FW_RI_TPTE_NOSNOOP 0x1 1528 #define V_FW_RI_TPTE_NOSNOOP(x) ((x) << S_FW_RI_TPTE_NOSNOOP) 1529 #define G_FW_RI_TPTE_NOSNOOP(x) \ 1530 (((x) >> S_FW_RI_TPTE_NOSNOOP) & M_FW_RI_TPTE_NOSNOOP) 1531 #define F_FW_RI_TPTE_NOSNOOP V_FW_RI_TPTE_NOSNOOP(1U) 1532 1533 #define S_FW_RI_TPTE_PBLADDR 0 1534 #define M_FW_RI_TPTE_PBLADDR 0x1fffffff 1535 #define V_FW_RI_TPTE_PBLADDR(x) ((x) << S_FW_RI_TPTE_PBLADDR) 1536 #define G_FW_RI_TPTE_PBLADDR(x) \ 1537 (((x) >> S_FW_RI_TPTE_PBLADDR) & M_FW_RI_TPTE_PBLADDR) 1538 1539 #define S_FW_RI_TPTE_DCA 24 1540 #define M_FW_RI_TPTE_DCA 0x1f 1541 #define V_FW_RI_TPTE_DCA(x) ((x) << S_FW_RI_TPTE_DCA) 1542 #define G_FW_RI_TPTE_DCA(x) \ 1543 (((x) >> S_FW_RI_TPTE_DCA) & M_FW_RI_TPTE_DCA) 1544 1545 #define S_FW_RI_TPTE_MWBCNT_PSTAG 0 1546 #define M_FW_RI_TPTE_MWBCNT_PSTAG 0xffffff 1547 #define V_FW_RI_TPTE_MWBCNT_PSTAT(x) \ 1548 ((x) << S_FW_RI_TPTE_MWBCNT_PSTAG) 1549 #define G_FW_RI_TPTE_MWBCNT_PSTAG(x) \ 1550 (((x) >> S_FW_RI_TPTE_MWBCNT_PSTAG) & M_FW_RI_TPTE_MWBCNT_PSTAG) 1551 1552 enum fw_ri_cqe_rxtx { 1553 FW_RI_CQE_RXTX_RX = 0x0, 1554 FW_RI_CQE_RXTX_TX = 0x1, 1555 }; 1556 1557 struct fw_ri_cqe { 1558 union fw_ri_rxtx { 1559 struct fw_ri_scqe { 1560 __be32 qpid_n_stat_rxtx_type; 1561 __be32 plen; 1562 __be32 stag; 1563 __be32 wrid; 1564 } scqe; 1565 struct fw_ri_rcqe { 1566 __be32 qpid_n_stat_rxtx_type; 1567 __be32 plen; 1568 __be32 stag; 1569 __be32 msn; 1570 } rcqe; 1571 struct fw_ri_rcqe_imm { 1572 __be32 qpid_n_stat_rxtx_type; 1573 __be32 plen; 1574 __be32 mo; 1575 __be32 msn; 1576 __u64 imm_data; 1577 } imm_data_rcqe; 1578 } u; 1579 }; 1580 1581 #define S_FW_RI_CQE_QPID 12 1582 #define M_FW_RI_CQE_QPID 0xfffff 1583 #define V_FW_RI_CQE_QPID(x) ((x) << S_FW_RI_CQE_QPID) 1584 #define G_FW_RI_CQE_QPID(x) \ 1585 (((x) >> S_FW_RI_CQE_QPID) & M_FW_RI_CQE_QPID) 1586 1587 #define S_FW_RI_CQE_NOTIFY 10 1588 #define M_FW_RI_CQE_NOTIFY 0x1 1589 #define V_FW_RI_CQE_NOTIFY(x) ((x) << S_FW_RI_CQE_NOTIFY) 1590 #define G_FW_RI_CQE_NOTIFY(x) \ 1591 (((x) >> S_FW_RI_CQE_NOTIFY) & M_FW_RI_CQE_NOTIFY) 1592 1593 #define S_FW_RI_CQE_STATUS 5 1594 #define M_FW_RI_CQE_STATUS 0x1f 1595 #define V_FW_RI_CQE_STATUS(x) ((x) << S_FW_RI_CQE_STATUS) 1596 #define G_FW_RI_CQE_STATUS(x) \ 1597 (((x) >> S_FW_RI_CQE_STATUS) & M_FW_RI_CQE_STATUS) 1598 1599 1600 #define S_FW_RI_CQE_RXTX 4 1601 #define M_FW_RI_CQE_RXTX 0x1 1602 #define V_FW_RI_CQE_RXTX(x) ((x) << S_FW_RI_CQE_RXTX) 1603 #define G_FW_RI_CQE_RXTX(x) \ 1604 (((x) >> S_FW_RI_CQE_RXTX) & M_FW_RI_CQE_RXTX) 1605 1606 #define S_FW_RI_CQE_TYPE 0 1607 #define M_FW_RI_CQE_TYPE 0xf 1608 #define V_FW_RI_CQE_TYPE(x) ((x) << S_FW_RI_CQE_TYPE) 1609 #define G_FW_RI_CQE_TYPE(x) \ 1610 (((x) >> S_FW_RI_CQE_TYPE) & M_FW_RI_CQE_TYPE) 1611 1612 enum fw_res_type { 1613 FW_RI_RES_TYPE_SQ, 1614 FW_RI_RES_TYPE_RQ, 1615 FW_RI_RES_TYPE_CQ, 1616 FW_RI_RES_TYPE_SRQ, 1617 FW_QP_RES_TYPE_SQ = FW_RI_RES_TYPE_SQ, 1618 FW_QP_RES_TYPE_CQ = FW_RI_RES_TYPE_CQ, 1619 }; 1620 1621 enum fw_res_op { 1622 FW_RI_RES_OP_WRITE, 1623 FW_RI_RES_OP_RESET, 1624 FW_QP_RES_OP_WRITE = FW_RI_RES_OP_WRITE, 1625 FW_QP_RES_OP_RESET = FW_RI_RES_OP_RESET, 1626 }; 1627 1628 enum fw_qp_transport_type { 1629 FW_QP_TRANSPORT_TYPE_IWARP, 1630 FW_QP_TRANSPORT_TYPE_ROCEV2_UD, 1631 FW_QP_TRANSPORT_TYPE_ROCEV2_RC, 1632 FW_QP_TRANSPORT_TYPE_ROCEV2_XRC_INI, 1633 FW_QP_TRANSPORT_TYPE_ROCEV2_XRC_TGT, 1634 FW_QP_TRANSPORT_TYPE_NVMET, 1635 FW_QP_TRANSPORT_TYPE_TOE, 1636 FW_QP_TRANSPORT_TYPE_ISCSI, 1637 }; 1638 1639 struct fw_qp_res { 1640 union fw_qp_restype { 1641 struct fw_qp_res_sqrq { 1642 __u8 restype; 1643 __u8 op; 1644 __be16 r3; 1645 __be32 eqid; 1646 __be32 r4[2]; 1647 __be32 fetchszm_to_iqid; 1648 __be32 dcaen_to_eqsize; 1649 __be64 eqaddr; 1650 } sqrq; 1651 struct fw_qp_res_cq { 1652 __u8 restype; 1653 __u8 op; 1654 __be16 r3; 1655 __be32 iqid; 1656 __be32 r4[2]; 1657 __be32 iqandst_to_iqandstindex; 1658 __be16 iqdroprss_to_iqesize; 1659 __be16 iqsize; 1660 __be64 iqaddr; 1661 __be32 iqns_iqro; 1662 __be32 r6_lo; 1663 __be64 r7; 1664 } cq; 1665 } u; 1666 }; 1667 1668 struct fw_qp_res_wr { 1669 __be32 op_to_nres; 1670 __be32 len16_pkd; 1671 __u64 cookie; 1672 #ifndef C99_NOT_SUPPORTED 1673 struct fw_qp_res res[0]; 1674 #endif 1675 }; 1676 1677 #define S_FW_QP_RES_WR_TRANSPORT_TYPE 16 1678 #define M_FW_QP_RES_WR_TRANSPORT_TYPE 0x7 1679 #define V_FW_QP_RES_WR_TRANSPORT_TYPE(x) \ 1680 ((x) << S_FW_QP_RES_WR_TRANSPORT_TYPE) 1681 #define G_FW_QP_RES_WR_TRANSPORT_TYPE(x) \ 1682 (((x) >> S_FW_QP_RES_WR_TRANSPORT_TYPE) & M_FW_QP_RES_WR_TRANSPORT_TYPE) 1683 1684 #define S_FW_QP_RES_WR_VFN 8 1685 #define M_FW_QP_RES_WR_VFN 0xff 1686 #define V_FW_QP_RES_WR_VFN(x) ((x) << S_FW_QP_RES_WR_VFN) 1687 #define G_FW_QP_RES_WR_VFN(x) \ 1688 (((x) >> S_FW_QP_RES_WR_VFN) & M_FW_QP_RES_WR_VFN) 1689 1690 #define S_FW_QP_RES_WR_NRES 0 1691 #define M_FW_QP_RES_WR_NRES 0xff 1692 #define V_FW_QP_RES_WR_NRES(x) ((x) << S_FW_QP_RES_WR_NRES) 1693 #define G_FW_QP_RES_WR_NRES(x) \ 1694 (((x) >> S_FW_QP_RES_WR_NRES) & M_FW_QP_RES_WR_NRES) 1695 1696 #define S_FW_QP_RES_WR_FETCHSZM 26 1697 #define M_FW_QP_RES_WR_FETCHSZM 0x1 1698 #define V_FW_QP_RES_WR_FETCHSZM(x) ((x) << S_FW_QP_RES_WR_FETCHSZM) 1699 #define G_FW_QP_RES_WR_FETCHSZM(x) \ 1700 (((x) >> S_FW_QP_RES_WR_FETCHSZM) & M_FW_QP_RES_WR_FETCHSZM) 1701 #define F_FW_QP_RES_WR_FETCHSZM V_FW_QP_RES_WR_FETCHSZM(1U) 1702 1703 #define S_FW_QP_RES_WR_STATUSPGNS 25 1704 #define M_FW_QP_RES_WR_STATUSPGNS 0x1 1705 #define V_FW_QP_RES_WR_STATUSPGNS(x) ((x) << S_FW_QP_RES_WR_STATUSPGNS) 1706 #define G_FW_QP_RES_WR_STATUSPGNS(x) \ 1707 (((x) >> S_FW_QP_RES_WR_STATUSPGNS) & M_FW_QP_RES_WR_STATUSPGNS) 1708 #define F_FW_QP_RES_WR_STATUSPGNS V_FW_QP_RES_WR_STATUSPGNS(1U) 1709 1710 #define S_FW_QP_RES_WR_STATUSPGRO 24 1711 #define M_FW_QP_RES_WR_STATUSPGRO 0x1 1712 #define V_FW_QP_RES_WR_STATUSPGRO(x) ((x) << S_FW_QP_RES_WR_STATUSPGRO) 1713 #define G_FW_QP_RES_WR_STATUSPGRO(x) \ 1714 (((x) >> S_FW_QP_RES_WR_STATUSPGRO) & M_FW_QP_RES_WR_STATUSPGRO) 1715 #define F_FW_QP_RES_WR_STATUSPGRO V_FW_QP_RES_WR_STATUSPGRO(1U) 1716 1717 #define S_FW_QP_RES_WR_FETCHNS 23 1718 #define M_FW_QP_RES_WR_FETCHNS 0x1 1719 #define V_FW_QP_RES_WR_FETCHNS(x) ((x) << S_FW_QP_RES_WR_FETCHNS) 1720 #define G_FW_QP_RES_WR_FETCHNS(x) \ 1721 (((x) >> S_FW_QP_RES_WR_FETCHNS) & M_FW_QP_RES_WR_FETCHNS) 1722 #define F_FW_QP_RES_WR_FETCHNS V_FW_QP_RES_WR_FETCHNS(1U) 1723 1724 #define S_FW_QP_RES_WR_FETCHRO 22 1725 #define M_FW_QP_RES_WR_FETCHRO 0x1 1726 #define V_FW_QP_RES_WR_FETCHRO(x) ((x) << S_FW_QP_RES_WR_FETCHRO) 1727 #define G_FW_QP_RES_WR_FETCHRO(x) \ 1728 (((x) >> S_FW_QP_RES_WR_FETCHRO) & M_FW_QP_RES_WR_FETCHRO) 1729 #define F_FW_QP_RES_WR_FETCHRO V_FW_QP_RES_WR_FETCHRO(1U) 1730 1731 #define S_FW_QP_RES_WR_HOSTFCMODE 20 1732 #define M_FW_QP_RES_WR_HOSTFCMODE 0x3 1733 #define V_FW_QP_RES_WR_HOSTFCMODE(x) ((x) << S_FW_QP_RES_WR_HOSTFCMODE) 1734 #define G_FW_QP_RES_WR_HOSTFCMODE(x) \ 1735 (((x) >> S_FW_QP_RES_WR_HOSTFCMODE) & M_FW_QP_RES_WR_HOSTFCMODE) 1736 1737 #define S_FW_QP_RES_WR_CPRIO 19 1738 #define M_FW_QP_RES_WR_CPRIO 0x1 1739 #define V_FW_QP_RES_WR_CPRIO(x) ((x) << S_FW_QP_RES_WR_CPRIO) 1740 #define G_FW_QP_RES_WR_CPRIO(x) \ 1741 (((x) >> S_FW_QP_RES_WR_CPRIO) & M_FW_QP_RES_WR_CPRIO) 1742 #define F_FW_QP_RES_WR_CPRIO V_FW_QP_RES_WR_CPRIO(1U) 1743 1744 #define S_FW_QP_RES_WR_ONCHIP 18 1745 #define M_FW_QP_RES_WR_ONCHIP 0x1 1746 #define V_FW_QP_RES_WR_ONCHIP(x) ((x) << S_FW_QP_RES_WR_ONCHIP) 1747 #define G_FW_QP_RES_WR_ONCHIP(x) \ 1748 (((x) >> S_FW_QP_RES_WR_ONCHIP) & M_FW_QP_RES_WR_ONCHIP) 1749 #define F_FW_QP_RES_WR_ONCHIP V_FW_QP_RES_WR_ONCHIP(1U) 1750 1751 #define S_FW_QP_RES_WR_PCIECHN 16 1752 #define M_FW_QP_RES_WR_PCIECHN 0x3 1753 #define V_FW_QP_RES_WR_PCIECHN(x) ((x) << S_FW_QP_RES_WR_PCIECHN) 1754 #define G_FW_QP_RES_WR_PCIECHN(x) \ 1755 (((x) >> S_FW_QP_RES_WR_PCIECHN) & M_FW_QP_RES_WR_PCIECHN) 1756 1757 #define S_FW_QP_RES_WR_IQID 0 1758 #define M_FW_QP_RES_WR_IQID 0xffff 1759 #define V_FW_QP_RES_WR_IQID(x) ((x) << S_FW_QP_RES_WR_IQID) 1760 #define G_FW_QP_RES_WR_IQID(x) \ 1761 (((x) >> S_FW_QP_RES_WR_IQID) & M_FW_QP_RES_WR_IQID) 1762 1763 #define S_FW_QP_RES_WR_DCAEN 31 1764 #define M_FW_QP_RES_WR_DCAEN 0x1 1765 #define V_FW_QP_RES_WR_DCAEN(x) ((x) << S_FW_QP_RES_WR_DCAEN) 1766 #define G_FW_QP_RES_WR_DCAEN(x) \ 1767 (((x) >> S_FW_QP_RES_WR_DCAEN) & M_FW_QP_RES_WR_DCAEN) 1768 #define F_FW_QP_RES_WR_DCAEN V_FW_QP_RES_WR_DCAEN(1U) 1769 1770 #define S_FW_QP_RES_WR_DCACPU 26 1771 #define M_FW_QP_RES_WR_DCACPU 0x1f 1772 #define V_FW_QP_RES_WR_DCACPU(x) ((x) << S_FW_QP_RES_WR_DCACPU) 1773 #define G_FW_QP_RES_WR_DCACPU(x) \ 1774 (((x) >> S_FW_QP_RES_WR_DCACPU) & M_FW_QP_RES_WR_DCACPU) 1775 1776 #define S_FW_QP_RES_WR_FBMIN 23 1777 #define M_FW_QP_RES_WR_FBMIN 0x7 1778 #define V_FW_QP_RES_WR_FBMIN(x) ((x) << S_FW_QP_RES_WR_FBMIN) 1779 #define G_FW_QP_RES_WR_FBMIN(x) \ 1780 (((x) >> S_FW_QP_RES_WR_FBMIN) & M_FW_QP_RES_WR_FBMIN) 1781 1782 #define S_FW_QP_RES_WR_FBMAX 20 1783 #define M_FW_QP_RES_WR_FBMAX 0x7 1784 #define V_FW_QP_RES_WR_FBMAX(x) ((x) << S_FW_QP_RES_WR_FBMAX) 1785 #define G_FW_QP_RES_WR_FBMAX(x) \ 1786 (((x) >> S_FW_QP_RES_WR_FBMAX) & M_FW_QP_RES_WR_FBMAX) 1787 1788 #define S_FW_QP_RES_WR_CIDXFTHRESHO 19 1789 #define M_FW_QP_RES_WR_CIDXFTHRESHO 0x1 1790 #define V_FW_QP_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_QP_RES_WR_CIDXFTHRESHO) 1791 #define G_FW_QP_RES_WR_CIDXFTHRESHO(x) \ 1792 (((x) >> S_FW_QP_RES_WR_CIDXFTHRESHO) & M_FW_QP_RES_WR_CIDXFTHRESHO) 1793 #define F_FW_QP_RES_WR_CIDXFTHRESHO V_FW_QP_RES_WR_CIDXFTHRESHO(1U) 1794 1795 #define S_FW_QP_RES_WR_CIDXFTHRESH 16 1796 #define M_FW_QP_RES_WR_CIDXFTHRESH 0x7 1797 #define V_FW_QP_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_QP_RES_WR_CIDXFTHRESH) 1798 #define G_FW_QP_RES_WR_CIDXFTHRESH(x) \ 1799 (((x) >> S_FW_QP_RES_WR_CIDXFTHRESH) & M_FW_QP_RES_WR_CIDXFTHRESH) 1800 1801 #define S_FW_QP_RES_WR_EQSIZE 0 1802 #define M_FW_QP_RES_WR_EQSIZE 0xffff 1803 #define V_FW_QP_RES_WR_EQSIZE(x) ((x) << S_FW_QP_RES_WR_EQSIZE) 1804 #define G_FW_QP_RES_WR_EQSIZE(x) \ 1805 (((x) >> S_FW_QP_RES_WR_EQSIZE) & M_FW_QP_RES_WR_EQSIZE) 1806 1807 #define S_FW_QP_RES_WR_IQANDST 15 1808 #define M_FW_QP_RES_WR_IQANDST 0x1 1809 #define V_FW_QP_RES_WR_IQANDST(x) ((x) << S_FW_QP_RES_WR_IQANDST) 1810 #define G_FW_QP_RES_WR_IQANDST(x) \ 1811 (((x) >> S_FW_QP_RES_WR_IQANDST) & M_FW_QP_RES_WR_IQANDST) 1812 #define F_FW_QP_RES_WR_IQANDST V_FW_QP_RES_WR_IQANDST(1U) 1813 1814 #define S_FW_QP_RES_WR_IQANUS 14 1815 #define M_FW_QP_RES_WR_IQANUS 0x1 1816 #define V_FW_QP_RES_WR_IQANUS(x) ((x) << S_FW_QP_RES_WR_IQANUS) 1817 #define G_FW_QP_RES_WR_IQANUS(x) \ 1818 (((x) >> S_FW_QP_RES_WR_IQANUS) & M_FW_QP_RES_WR_IQANUS) 1819 #define F_FW_QP_RES_WR_IQANUS V_FW_QP_RES_WR_IQANUS(1U) 1820 1821 #define S_FW_QP_RES_WR_IQANUD 12 1822 #define M_FW_QP_RES_WR_IQANUD 0x3 1823 #define V_FW_QP_RES_WR_IQANUD(x) ((x) << S_FW_QP_RES_WR_IQANUD) 1824 #define G_FW_QP_RES_WR_IQANUD(x) \ 1825 (((x) >> S_FW_QP_RES_WR_IQANUD) & M_FW_QP_RES_WR_IQANUD) 1826 1827 #define S_FW_QP_RES_WR_IQANDSTINDEX 0 1828 #define M_FW_QP_RES_WR_IQANDSTINDEX 0xfff 1829 #define V_FW_QP_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_QP_RES_WR_IQANDSTINDEX) 1830 #define G_FW_QP_RES_WR_IQANDSTINDEX(x) \ 1831 (((x) >> S_FW_QP_RES_WR_IQANDSTINDEX) & M_FW_QP_RES_WR_IQANDSTINDEX) 1832 1833 #define S_FW_QP_RES_WR_IQDROPRSS 15 1834 #define M_FW_QP_RES_WR_IQDROPRSS 0x1 1835 #define V_FW_QP_RES_WR_IQDROPRSS(x) ((x) << S_FW_QP_RES_WR_IQDROPRSS) 1836 #define G_FW_QP_RES_WR_IQDROPRSS(x) \ 1837 (((x) >> S_FW_QP_RES_WR_IQDROPRSS) & M_FW_QP_RES_WR_IQDROPRSS) 1838 #define F_FW_QP_RES_WR_IQDROPRSS V_FW_QP_RES_WR_IQDROPRSS(1U) 1839 1840 #define S_FW_QP_RES_WR_IQGTSMODE 14 1841 #define M_FW_QP_RES_WR_IQGTSMODE 0x1 1842 #define V_FW_QP_RES_WR_IQGTSMODE(x) ((x) << S_FW_QP_RES_WR_IQGTSMODE) 1843 #define G_FW_QP_RES_WR_IQGTSMODE(x) \ 1844 (((x) >> S_FW_QP_RES_WR_IQGTSMODE) & M_FW_QP_RES_WR_IQGTSMODE) 1845 #define F_FW_QP_RES_WR_IQGTSMODE V_FW_QP_RES_WR_IQGTSMODE(1U) 1846 1847 #define S_FW_QP_RES_WR_IQPCIECH 12 1848 #define M_FW_QP_RES_WR_IQPCIECH 0x3 1849 #define V_FW_QP_RES_WR_IQPCIECH(x) ((x) << S_FW_QP_RES_WR_IQPCIECH) 1850 #define G_FW_QP_RES_WR_IQPCIECH(x) \ 1851 (((x) >> S_FW_QP_RES_WR_IQPCIECH) & M_FW_QP_RES_WR_IQPCIECH) 1852 1853 #define S_FW_QP_RES_WR_IQDCAEN 11 1854 #define M_FW_QP_RES_WR_IQDCAEN 0x1 1855 #define V_FW_QP_RES_WR_IQDCAEN(x) ((x) << S_FW_QP_RES_WR_IQDCAEN) 1856 #define G_FW_QP_RES_WR_IQDCAEN(x) \ 1857 (((x) >> S_FW_QP_RES_WR_IQDCAEN) & M_FW_QP_RES_WR_IQDCAEN) 1858 #define F_FW_QP_RES_WR_IQDCAEN V_FW_QP_RES_WR_IQDCAEN(1U) 1859 1860 #define S_FW_QP_RES_WR_IQDCACPU 6 1861 #define M_FW_QP_RES_WR_IQDCACPU 0x1f 1862 #define V_FW_QP_RES_WR_IQDCACPU(x) ((x) << S_FW_QP_RES_WR_IQDCACPU) 1863 #define G_FW_QP_RES_WR_IQDCACPU(x) \ 1864 (((x) >> S_FW_QP_RES_WR_IQDCACPU) & M_FW_QP_RES_WR_IQDCACPU) 1865 1866 #define S_FW_QP_RES_WR_IQINTCNTTHRESH 4 1867 #define M_FW_QP_RES_WR_IQINTCNTTHRESH 0x3 1868 #define V_FW_QP_RES_WR_IQINTCNTTHRESH(x) \ 1869 ((x) << S_FW_QP_RES_WR_IQINTCNTTHRESH) 1870 #define G_FW_QP_RES_WR_IQINTCNTTHRESH(x) \ 1871 (((x) >> S_FW_QP_RES_WR_IQINTCNTTHRESH) & M_FW_QP_RES_WR_IQINTCNTTHRESH) 1872 1873 #define S_FW_QP_RES_WR_IQO 3 1874 #define M_FW_QP_RES_WR_IQO 0x1 1875 #define V_FW_QP_RES_WR_IQO(x) ((x) << S_FW_QP_RES_WR_IQO) 1876 #define G_FW_QP_RES_WR_IQO(x) \ 1877 (((x) >> S_FW_QP_RES_WR_IQO) & M_FW_QP_RES_WR_IQO) 1878 #define F_FW_QP_RES_WR_IQO V_FW_QP_RES_WR_IQO(1U) 1879 1880 #define S_FW_QP_RES_WR_IQCPRIO 2 1881 #define M_FW_QP_RES_WR_IQCPRIO 0x1 1882 #define V_FW_QP_RES_WR_IQCPRIO(x) ((x) << S_FW_QP_RES_WR_IQCPRIO) 1883 #define G_FW_QP_RES_WR_IQCPRIO(x) \ 1884 (((x) >> S_FW_QP_RES_WR_IQCPRIO) & M_FW_QP_RES_WR_IQCPRIO) 1885 #define F_FW_QP_RES_WR_IQCPRIO V_FW_QP_RES_WR_IQCPRIO(1U) 1886 1887 #define S_FW_QP_RES_WR_IQESIZE 0 1888 #define M_FW_QP_RES_WR_IQESIZE 0x3 1889 #define V_FW_QP_RES_WR_IQESIZE(x) ((x) << S_FW_QP_RES_WR_IQESIZE) 1890 #define G_FW_QP_RES_WR_IQESIZE(x) \ 1891 (((x) >> S_FW_QP_RES_WR_IQESIZE) & M_FW_QP_RES_WR_IQESIZE) 1892 1893 #define S_FW_QP_RES_WR_IQNS 31 1894 #define M_FW_QP_RES_WR_IQNS 0x1 1895 #define V_FW_QP_RES_WR_IQNS(x) ((x) << S_FW_QP_RES_WR_IQNS) 1896 #define G_FW_QP_RES_WR_IQNS(x) \ 1897 (((x) >> S_FW_QP_RES_WR_IQNS) & M_FW_QP_RES_WR_IQNS) 1898 #define F_FW_QP_RES_WR_IQNS V_FW_QP_RES_WR_IQNS(1U) 1899 1900 #define S_FW_QP_RES_WR_IQRO 30 1901 #define M_FW_QP_RES_WR_IQRO 0x1 1902 #define V_FW_QP_RES_WR_IQRO(x) ((x) << S_FW_QP_RES_WR_IQRO) 1903 #define G_FW_QP_RES_WR_IQRO(x) \ 1904 (((x) >> S_FW_QP_RES_WR_IQRO) & M_FW_QP_RES_WR_IQRO) 1905 #define F_FW_QP_RES_WR_IQRO V_FW_QP_RES_WR_IQRO(1U) 1906 1907 1908 struct fw_ri_res { 1909 union fw_ri_restype { 1910 struct fw_ri_res_sqrq { 1911 __u8 restype; 1912 __u8 op; 1913 __be16 r3; 1914 __be32 eqid; 1915 __be32 r4[2]; 1916 __be32 fetchszm_to_iqid; 1917 __be32 dcaen_to_eqsize; 1918 __be64 eqaddr; 1919 } sqrq; 1920 struct fw_ri_res_cq { 1921 __u8 restype; 1922 __u8 op; 1923 __be16 r3; 1924 __be32 iqid; 1925 __be32 r4[2]; 1926 __be32 iqandst_to_iqandstindex; 1927 __be16 iqdroprss_to_iqesize; 1928 __be16 iqsize; 1929 __be64 iqaddr; 1930 __be32 iqns_iqro; 1931 __be32 r6_lo; 1932 __be64 r7; 1933 } cq; 1934 struct fw_ri_res_srq { 1935 __u8 restype; 1936 __u8 op; 1937 __be16 r3; 1938 __be32 eqid; 1939 __be32 r4[2]; 1940 __be32 fetchszm_to_iqid; 1941 __be32 dcaen_to_eqsize; 1942 __be64 eqaddr; 1943 __be32 srqid; 1944 __be32 pdid; 1945 __be32 hwsrqsize; 1946 __be32 hwsrqaddr; 1947 } srq; 1948 } u; 1949 }; 1950 1951 struct fw_ri_res_wr { 1952 __be32 op_nres; 1953 __be32 len16_pkd; 1954 __u64 cookie; 1955 #ifndef C99_NOT_SUPPORTED 1956 struct fw_ri_res res[0]; 1957 #endif 1958 }; 1959 1960 #define S_FW_RI_RES_WR_TRANSPORT_TYPE 16 1961 #define M_FW_RI_RES_WR_TRANSPORT_TYPE 0x7 1962 #define V_FW_RI_RES_WR_TRANSPORT_TYPE(x) \ 1963 ((x) << S_FW_RI_RES_WR_TRANSPORT_TYPE) 1964 #define G_FW_RI_RES_WR_TRANSPORT_TYPE(x) \ 1965 (((x) >> S_FW_RI_RES_WR_TRANSPORT_TYPE) & M_FW_RI_RES_WR_TRANSPORT_TYPE) 1966 1967 #define S_FW_RI_RES_WR_VFN 8 1968 #define M_FW_RI_RES_WR_VFN 0xff 1969 #define V_FW_RI_RES_WR_VFN(x) ((x) << S_FW_RI_RES_WR_VFN) 1970 #define G_FW_RI_RES_WR_VFN(x) \ 1971 (((x) >> S_FW_RI_RES_WR_VFN) & M_FW_RI_RES_WR_VFN) 1972 1973 #define S_FW_RI_RES_WR_NRES 0 1974 #define M_FW_RI_RES_WR_NRES 0xff 1975 #define V_FW_RI_RES_WR_NRES(x) ((x) << S_FW_RI_RES_WR_NRES) 1976 #define G_FW_RI_RES_WR_NRES(x) \ 1977 (((x) >> S_FW_RI_RES_WR_NRES) & M_FW_RI_RES_WR_NRES) 1978 1979 #define S_FW_RI_RES_WR_FETCHSZM 26 1980 #define M_FW_RI_RES_WR_FETCHSZM 0x1 1981 #define V_FW_RI_RES_WR_FETCHSZM(x) ((x) << S_FW_RI_RES_WR_FETCHSZM) 1982 #define G_FW_RI_RES_WR_FETCHSZM(x) \ 1983 (((x) >> S_FW_RI_RES_WR_FETCHSZM) & M_FW_RI_RES_WR_FETCHSZM) 1984 #define F_FW_RI_RES_WR_FETCHSZM V_FW_RI_RES_WR_FETCHSZM(1U) 1985 1986 #define S_FW_RI_RES_WR_STATUSPGNS 25 1987 #define M_FW_RI_RES_WR_STATUSPGNS 0x1 1988 #define V_FW_RI_RES_WR_STATUSPGNS(x) ((x) << S_FW_RI_RES_WR_STATUSPGNS) 1989 #define G_FW_RI_RES_WR_STATUSPGNS(x) \ 1990 (((x) >> S_FW_RI_RES_WR_STATUSPGNS) & M_FW_RI_RES_WR_STATUSPGNS) 1991 #define F_FW_RI_RES_WR_STATUSPGNS V_FW_RI_RES_WR_STATUSPGNS(1U) 1992 1993 #define S_FW_RI_RES_WR_STATUSPGRO 24 1994 #define M_FW_RI_RES_WR_STATUSPGRO 0x1 1995 #define V_FW_RI_RES_WR_STATUSPGRO(x) ((x) << S_FW_RI_RES_WR_STATUSPGRO) 1996 #define G_FW_RI_RES_WR_STATUSPGRO(x) \ 1997 (((x) >> S_FW_RI_RES_WR_STATUSPGRO) & M_FW_RI_RES_WR_STATUSPGRO) 1998 #define F_FW_RI_RES_WR_STATUSPGRO V_FW_RI_RES_WR_STATUSPGRO(1U) 1999 2000 #define S_FW_RI_RES_WR_FETCHNS 23 2001 #define M_FW_RI_RES_WR_FETCHNS 0x1 2002 #define V_FW_RI_RES_WR_FETCHNS(x) ((x) << S_FW_RI_RES_WR_FETCHNS) 2003 #define G_FW_RI_RES_WR_FETCHNS(x) \ 2004 (((x) >> S_FW_RI_RES_WR_FETCHNS) & M_FW_RI_RES_WR_FETCHNS) 2005 #define F_FW_RI_RES_WR_FETCHNS V_FW_RI_RES_WR_FETCHNS(1U) 2006 2007 #define S_FW_RI_RES_WR_FETCHRO 22 2008 #define M_FW_RI_RES_WR_FETCHRO 0x1 2009 #define V_FW_RI_RES_WR_FETCHRO(x) ((x) << S_FW_RI_RES_WR_FETCHRO) 2010 #define G_FW_RI_RES_WR_FETCHRO(x) \ 2011 (((x) >> S_FW_RI_RES_WR_FETCHRO) & M_FW_RI_RES_WR_FETCHRO) 2012 #define F_FW_RI_RES_WR_FETCHRO V_FW_RI_RES_WR_FETCHRO(1U) 2013 2014 #define S_FW_RI_RES_WR_HOSTFCMODE 20 2015 #define M_FW_RI_RES_WR_HOSTFCMODE 0x3 2016 #define V_FW_RI_RES_WR_HOSTFCMODE(x) ((x) << S_FW_RI_RES_WR_HOSTFCMODE) 2017 #define G_FW_RI_RES_WR_HOSTFCMODE(x) \ 2018 (((x) >> S_FW_RI_RES_WR_HOSTFCMODE) & M_FW_RI_RES_WR_HOSTFCMODE) 2019 2020 #define S_FW_RI_RES_WR_CPRIO 19 2021 #define M_FW_RI_RES_WR_CPRIO 0x1 2022 #define V_FW_RI_RES_WR_CPRIO(x) ((x) << S_FW_RI_RES_WR_CPRIO) 2023 #define G_FW_RI_RES_WR_CPRIO(x) \ 2024 (((x) >> S_FW_RI_RES_WR_CPRIO) & M_FW_RI_RES_WR_CPRIO) 2025 #define F_FW_RI_RES_WR_CPRIO V_FW_RI_RES_WR_CPRIO(1U) 2026 2027 #define S_FW_RI_RES_WR_ONCHIP 18 2028 #define M_FW_RI_RES_WR_ONCHIP 0x1 2029 #define V_FW_RI_RES_WR_ONCHIP(x) ((x) << S_FW_RI_RES_WR_ONCHIP) 2030 #define G_FW_RI_RES_WR_ONCHIP(x) \ 2031 (((x) >> S_FW_RI_RES_WR_ONCHIP) & M_FW_RI_RES_WR_ONCHIP) 2032 #define F_FW_RI_RES_WR_ONCHIP V_FW_RI_RES_WR_ONCHIP(1U) 2033 2034 #define S_FW_RI_RES_WR_PCIECHN 16 2035 #define M_FW_RI_RES_WR_PCIECHN 0x3 2036 #define V_FW_RI_RES_WR_PCIECHN(x) ((x) << S_FW_RI_RES_WR_PCIECHN) 2037 #define G_FW_RI_RES_WR_PCIECHN(x) \ 2038 (((x) >> S_FW_RI_RES_WR_PCIECHN) & M_FW_RI_RES_WR_PCIECHN) 2039 2040 #define S_FW_RI_RES_WR_IQID 0 2041 #define M_FW_RI_RES_WR_IQID 0xffff 2042 #define V_FW_RI_RES_WR_IQID(x) ((x) << S_FW_RI_RES_WR_IQID) 2043 #define G_FW_RI_RES_WR_IQID(x) \ 2044 (((x) >> S_FW_RI_RES_WR_IQID) & M_FW_RI_RES_WR_IQID) 2045 2046 #define S_FW_RI_RES_WR_DCAEN 31 2047 #define M_FW_RI_RES_WR_DCAEN 0x1 2048 #define V_FW_RI_RES_WR_DCAEN(x) ((x) << S_FW_RI_RES_WR_DCAEN) 2049 #define G_FW_RI_RES_WR_DCAEN(x) \ 2050 (((x) >> S_FW_RI_RES_WR_DCAEN) & M_FW_RI_RES_WR_DCAEN) 2051 #define F_FW_RI_RES_WR_DCAEN V_FW_RI_RES_WR_DCAEN(1U) 2052 2053 #define S_FW_RI_RES_WR_DCACPU 26 2054 #define M_FW_RI_RES_WR_DCACPU 0x1f 2055 #define V_FW_RI_RES_WR_DCACPU(x) ((x) << S_FW_RI_RES_WR_DCACPU) 2056 #define G_FW_RI_RES_WR_DCACPU(x) \ 2057 (((x) >> S_FW_RI_RES_WR_DCACPU) & M_FW_RI_RES_WR_DCACPU) 2058 2059 #define S_FW_RI_RES_WR_FBMIN 23 2060 #define M_FW_RI_RES_WR_FBMIN 0x7 2061 #define V_FW_RI_RES_WR_FBMIN(x) ((x) << S_FW_RI_RES_WR_FBMIN) 2062 #define G_FW_RI_RES_WR_FBMIN(x) \ 2063 (((x) >> S_FW_RI_RES_WR_FBMIN) & M_FW_RI_RES_WR_FBMIN) 2064 2065 #define S_FW_RI_RES_WR_FBMAX 20 2066 #define M_FW_RI_RES_WR_FBMAX 0x7 2067 #define V_FW_RI_RES_WR_FBMAX(x) ((x) << S_FW_RI_RES_WR_FBMAX) 2068 #define G_FW_RI_RES_WR_FBMAX(x) \ 2069 (((x) >> S_FW_RI_RES_WR_FBMAX) & M_FW_RI_RES_WR_FBMAX) 2070 2071 #define S_FW_RI_RES_WR_CIDXFTHRESHO 19 2072 #define M_FW_RI_RES_WR_CIDXFTHRESHO 0x1 2073 #define V_FW_RI_RES_WR_CIDXFTHRESHO(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESHO) 2074 #define G_FW_RI_RES_WR_CIDXFTHRESHO(x) \ 2075 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESHO) & M_FW_RI_RES_WR_CIDXFTHRESHO) 2076 #define F_FW_RI_RES_WR_CIDXFTHRESHO V_FW_RI_RES_WR_CIDXFTHRESHO(1U) 2077 2078 #define S_FW_RI_RES_WR_CIDXFTHRESH 16 2079 #define M_FW_RI_RES_WR_CIDXFTHRESH 0x7 2080 #define V_FW_RI_RES_WR_CIDXFTHRESH(x) ((x) << S_FW_RI_RES_WR_CIDXFTHRESH) 2081 #define G_FW_RI_RES_WR_CIDXFTHRESH(x) \ 2082 (((x) >> S_FW_RI_RES_WR_CIDXFTHRESH) & M_FW_RI_RES_WR_CIDXFTHRESH) 2083 2084 #define S_FW_RI_RES_WR_EQSIZE 0 2085 #define M_FW_RI_RES_WR_EQSIZE 0xffff 2086 #define V_FW_RI_RES_WR_EQSIZE(x) ((x) << S_FW_RI_RES_WR_EQSIZE) 2087 #define G_FW_RI_RES_WR_EQSIZE(x) \ 2088 (((x) >> S_FW_RI_RES_WR_EQSIZE) & M_FW_RI_RES_WR_EQSIZE) 2089 2090 #define S_FW_RI_RES_WR_IQANDST 15 2091 #define M_FW_RI_RES_WR_IQANDST 0x1 2092 #define V_FW_RI_RES_WR_IQANDST(x) ((x) << S_FW_RI_RES_WR_IQANDST) 2093 #define G_FW_RI_RES_WR_IQANDST(x) \ 2094 (((x) >> S_FW_RI_RES_WR_IQANDST) & M_FW_RI_RES_WR_IQANDST) 2095 #define F_FW_RI_RES_WR_IQANDST V_FW_RI_RES_WR_IQANDST(1U) 2096 2097 #define S_FW_RI_RES_WR_IQANUS 14 2098 #define M_FW_RI_RES_WR_IQANUS 0x1 2099 #define V_FW_RI_RES_WR_IQANUS(x) ((x) << S_FW_RI_RES_WR_IQANUS) 2100 #define G_FW_RI_RES_WR_IQANUS(x) \ 2101 (((x) >> S_FW_RI_RES_WR_IQANUS) & M_FW_RI_RES_WR_IQANUS) 2102 #define F_FW_RI_RES_WR_IQANUS V_FW_RI_RES_WR_IQANUS(1U) 2103 2104 #define S_FW_RI_RES_WR_IQANUD 12 2105 #define M_FW_RI_RES_WR_IQANUD 0x3 2106 #define V_FW_RI_RES_WR_IQANUD(x) ((x) << S_FW_RI_RES_WR_IQANUD) 2107 #define G_FW_RI_RES_WR_IQANUD(x) \ 2108 (((x) >> S_FW_RI_RES_WR_IQANUD) & M_FW_RI_RES_WR_IQANUD) 2109 2110 #define S_FW_RI_RES_WR_IQANDSTINDEX 0 2111 #define M_FW_RI_RES_WR_IQANDSTINDEX 0xfff 2112 #define V_FW_RI_RES_WR_IQANDSTINDEX(x) ((x) << S_FW_RI_RES_WR_IQANDSTINDEX) 2113 #define G_FW_RI_RES_WR_IQANDSTINDEX(x) \ 2114 (((x) >> S_FW_RI_RES_WR_IQANDSTINDEX) & M_FW_RI_RES_WR_IQANDSTINDEX) 2115 2116 #define S_FW_RI_RES_WR_IQDROPRSS 15 2117 #define M_FW_RI_RES_WR_IQDROPRSS 0x1 2118 #define V_FW_RI_RES_WR_IQDROPRSS(x) ((x) << S_FW_RI_RES_WR_IQDROPRSS) 2119 #define G_FW_RI_RES_WR_IQDROPRSS(x) \ 2120 (((x) >> S_FW_RI_RES_WR_IQDROPRSS) & M_FW_RI_RES_WR_IQDROPRSS) 2121 #define F_FW_RI_RES_WR_IQDROPRSS V_FW_RI_RES_WR_IQDROPRSS(1U) 2122 2123 #define S_FW_RI_RES_WR_IQGTSMODE 14 2124 #define M_FW_RI_RES_WR_IQGTSMODE 0x1 2125 #define V_FW_RI_RES_WR_IQGTSMODE(x) ((x) << S_FW_RI_RES_WR_IQGTSMODE) 2126 #define G_FW_RI_RES_WR_IQGTSMODE(x) \ 2127 (((x) >> S_FW_RI_RES_WR_IQGTSMODE) & M_FW_RI_RES_WR_IQGTSMODE) 2128 #define F_FW_RI_RES_WR_IQGTSMODE V_FW_RI_RES_WR_IQGTSMODE(1U) 2129 2130 #define S_FW_RI_RES_WR_IQPCIECH 12 2131 #define M_FW_RI_RES_WR_IQPCIECH 0x3 2132 #define V_FW_RI_RES_WR_IQPCIECH(x) ((x) << S_FW_RI_RES_WR_IQPCIECH) 2133 #define G_FW_RI_RES_WR_IQPCIECH(x) \ 2134 (((x) >> S_FW_RI_RES_WR_IQPCIECH) & M_FW_RI_RES_WR_IQPCIECH) 2135 2136 #define S_FW_RI_RES_WR_IQDCAEN 11 2137 #define M_FW_RI_RES_WR_IQDCAEN 0x1 2138 #define V_FW_RI_RES_WR_IQDCAEN(x) ((x) << S_FW_RI_RES_WR_IQDCAEN) 2139 #define G_FW_RI_RES_WR_IQDCAEN(x) \ 2140 (((x) >> S_FW_RI_RES_WR_IQDCAEN) & M_FW_RI_RES_WR_IQDCAEN) 2141 #define F_FW_RI_RES_WR_IQDCAEN V_FW_RI_RES_WR_IQDCAEN(1U) 2142 2143 #define S_FW_RI_RES_WR_IQDCACPU 6 2144 #define M_FW_RI_RES_WR_IQDCACPU 0x1f 2145 #define V_FW_RI_RES_WR_IQDCACPU(x) ((x) << S_FW_RI_RES_WR_IQDCACPU) 2146 #define G_FW_RI_RES_WR_IQDCACPU(x) \ 2147 (((x) >> S_FW_RI_RES_WR_IQDCACPU) & M_FW_RI_RES_WR_IQDCACPU) 2148 2149 #define S_FW_RI_RES_WR_IQINTCNTTHRESH 4 2150 #define M_FW_RI_RES_WR_IQINTCNTTHRESH 0x3 2151 #define V_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 2152 ((x) << S_FW_RI_RES_WR_IQINTCNTTHRESH) 2153 #define G_FW_RI_RES_WR_IQINTCNTTHRESH(x) \ 2154 (((x) >> S_FW_RI_RES_WR_IQINTCNTTHRESH) & M_FW_RI_RES_WR_IQINTCNTTHRESH) 2155 2156 #define S_FW_RI_RES_WR_IQO 3 2157 #define M_FW_RI_RES_WR_IQO 0x1 2158 #define V_FW_RI_RES_WR_IQO(x) ((x) << S_FW_RI_RES_WR_IQO) 2159 #define G_FW_RI_RES_WR_IQO(x) \ 2160 (((x) >> S_FW_RI_RES_WR_IQO) & M_FW_RI_RES_WR_IQO) 2161 #define F_FW_RI_RES_WR_IQO V_FW_RI_RES_WR_IQO(1U) 2162 2163 #define S_FW_RI_RES_WR_IQCPRIO 2 2164 #define M_FW_RI_RES_WR_IQCPRIO 0x1 2165 #define V_FW_RI_RES_WR_IQCPRIO(x) ((x) << S_FW_RI_RES_WR_IQCPRIO) 2166 #define G_FW_RI_RES_WR_IQCPRIO(x) \ 2167 (((x) >> S_FW_RI_RES_WR_IQCPRIO) & M_FW_RI_RES_WR_IQCPRIO) 2168 #define F_FW_RI_RES_WR_IQCPRIO V_FW_RI_RES_WR_IQCPRIO(1U) 2169 2170 #define S_FW_RI_RES_WR_IQESIZE 0 2171 #define M_FW_RI_RES_WR_IQESIZE 0x3 2172 #define V_FW_RI_RES_WR_IQESIZE(x) ((x) << S_FW_RI_RES_WR_IQESIZE) 2173 #define G_FW_RI_RES_WR_IQESIZE(x) \ 2174 (((x) >> S_FW_RI_RES_WR_IQESIZE) & M_FW_RI_RES_WR_IQESIZE) 2175 2176 #define S_FW_RI_RES_WR_IQNS 31 2177 #define M_FW_RI_RES_WR_IQNS 0x1 2178 #define V_FW_RI_RES_WR_IQNS(x) ((x) << S_FW_RI_RES_WR_IQNS) 2179 #define G_FW_RI_RES_WR_IQNS(x) \ 2180 (((x) >> S_FW_RI_RES_WR_IQNS) & M_FW_RI_RES_WR_IQNS) 2181 #define F_FW_RI_RES_WR_IQNS V_FW_RI_RES_WR_IQNS(1U) 2182 2183 #define S_FW_RI_RES_WR_IQRO 30 2184 #define M_FW_RI_RES_WR_IQRO 0x1 2185 #define V_FW_RI_RES_WR_IQRO(x) ((x) << S_FW_RI_RES_WR_IQRO) 2186 #define G_FW_RI_RES_WR_IQRO(x) \ 2187 (((x) >> S_FW_RI_RES_WR_IQRO) & M_FW_RI_RES_WR_IQRO) 2188 #define F_FW_RI_RES_WR_IQRO V_FW_RI_RES_WR_IQRO(1U) 2189 2190 struct fw_ri_rdma_write_wr { 2191 __u8 opcode; 2192 __u8 flags; 2193 __u16 wrid; 2194 __u8 r1[3]; 2195 __u8 len16; 2196 __u64 immd_data; 2197 __be32 plen; 2198 __be32 stag_sink; 2199 __be64 to_sink; 2200 #ifndef C99_NOT_SUPPORTED 2201 union { 2202 struct fw_ri_immd immd_src[0]; 2203 struct fw_ri_isgl isgl_src[0]; 2204 } u; 2205 #endif 2206 }; 2207 2208 struct fw_ri_send_wr { 2209 __u8 opcode; 2210 __u8 flags; 2211 __u16 wrid; 2212 __u8 r1[3]; 2213 __u8 len16; 2214 __be32 sendop_pkd; 2215 __be32 stag_inv; 2216 __be32 plen; 2217 __be32 r3; 2218 __be64 r4; 2219 #ifndef C99_NOT_SUPPORTED 2220 union { 2221 struct fw_ri_immd immd_src[0]; 2222 struct fw_ri_isgl isgl_src[0]; 2223 } u; 2224 #endif 2225 }; 2226 2227 #define S_FW_RI_SEND_WR_SENDOP 0 2228 #define M_FW_RI_SEND_WR_SENDOP 0xf 2229 #define V_FW_RI_SEND_WR_SENDOP(x) ((x) << S_FW_RI_SEND_WR_SENDOP) 2230 #define G_FW_RI_SEND_WR_SENDOP(x) \ 2231 (((x) >> S_FW_RI_SEND_WR_SENDOP) & M_FW_RI_SEND_WR_SENDOP) 2232 2233 struct fw_ri_rdma_write_cmpl_wr { 2234 __u8 opcode; 2235 __u8 flags; 2236 __u16 wrid; 2237 __u8 r1[3]; 2238 __u8 len16; 2239 __u8 r2; 2240 __u8 flags_send; 2241 __u16 wrid_send; 2242 __be32 stag_inv; 2243 __be32 plen; 2244 __be32 stag_sink; 2245 __be64 to_sink; 2246 union fw_ri_cmpl { 2247 struct fw_ri_immd_cmpl { 2248 __u8 op; 2249 __u8 r1[6]; 2250 __u8 immdlen; 2251 __u8 data[16]; 2252 } immd_src; 2253 struct fw_ri_isgl isgl_src; 2254 } u_cmpl; 2255 __be64 r3; 2256 #ifndef C99_NOT_SUPPORTED 2257 union fw_ri_write { 2258 struct fw_ri_immd immd_src[0]; 2259 struct fw_ri_isgl isgl_src[0]; 2260 } u; 2261 #endif 2262 }; 2263 2264 struct fw_ri_rdma_read_wr { 2265 __u8 opcode; 2266 __u8 flags; 2267 __u16 wrid; 2268 __u8 r1[3]; 2269 __u8 len16; 2270 __be64 r2; 2271 __be32 stag_sink; 2272 __be32 to_sink_hi; 2273 __be32 to_sink_lo; 2274 __be32 plen; 2275 __be32 stag_src; 2276 __be32 to_src_hi; 2277 __be32 to_src_lo; 2278 __be32 r5; 2279 }; 2280 2281 struct fw_ri_recv_wr { 2282 __u8 opcode; 2283 __u8 r1; 2284 __u16 wrid; 2285 __u8 r2[3]; 2286 __u8 len16; 2287 struct fw_ri_isgl isgl; 2288 }; 2289 2290 struct fw_ri_bind_mw_wr { 2291 __u8 opcode; 2292 __u8 flags; 2293 __u16 wrid; 2294 __u8 r1[3]; 2295 __u8 len16; 2296 __u8 qpbinde_to_dcacpu; 2297 __u8 pgsz_shift; 2298 __u8 addr_type; 2299 __u8 mem_perms; 2300 __be32 stag_mr; 2301 __be32 stag_mw; 2302 __be32 r3; 2303 __be64 len_mw; 2304 __be64 va_fbo; 2305 __be64 r4; 2306 }; 2307 2308 #define S_FW_RI_BIND_MW_WR_QPBINDE 6 2309 #define M_FW_RI_BIND_MW_WR_QPBINDE 0x1 2310 #define V_FW_RI_BIND_MW_WR_QPBINDE(x) ((x) << S_FW_RI_BIND_MW_WR_QPBINDE) 2311 #define G_FW_RI_BIND_MW_WR_QPBINDE(x) \ 2312 (((x) >> S_FW_RI_BIND_MW_WR_QPBINDE) & M_FW_RI_BIND_MW_WR_QPBINDE) 2313 #define F_FW_RI_BIND_MW_WR_QPBINDE V_FW_RI_BIND_MW_WR_QPBINDE(1U) 2314 2315 #define S_FW_RI_BIND_MW_WR_NS 5 2316 #define M_FW_RI_BIND_MW_WR_NS 0x1 2317 #define V_FW_RI_BIND_MW_WR_NS(x) ((x) << S_FW_RI_BIND_MW_WR_NS) 2318 #define G_FW_RI_BIND_MW_WR_NS(x) \ 2319 (((x) >> S_FW_RI_BIND_MW_WR_NS) & M_FW_RI_BIND_MW_WR_NS) 2320 #define F_FW_RI_BIND_MW_WR_NS V_FW_RI_BIND_MW_WR_NS(1U) 2321 2322 #define S_FW_RI_BIND_MW_WR_DCACPU 0 2323 #define M_FW_RI_BIND_MW_WR_DCACPU 0x1f 2324 #define V_FW_RI_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_BIND_MW_WR_DCACPU) 2325 #define G_FW_RI_BIND_MW_WR_DCACPU(x) \ 2326 (((x) >> S_FW_RI_BIND_MW_WR_DCACPU) & M_FW_RI_BIND_MW_WR_DCACPU) 2327 2328 struct fw_ri_fr_nsmr_wr { 2329 __u8 opcode; 2330 __u8 flags; 2331 __u16 wrid; 2332 __u8 r1[3]; 2333 __u8 len16; 2334 __u8 qpbinde_to_dcacpu; 2335 __u8 pgsz_shift; 2336 __u8 addr_type; 2337 __u8 mem_perms; 2338 __be32 stag; 2339 __be32 len_hi; 2340 __be32 len_lo; 2341 __be32 va_hi; 2342 __be32 va_lo_fbo; 2343 }; 2344 2345 #define S_FW_RI_FR_NSMR_WR_QPBINDE 6 2346 #define M_FW_RI_FR_NSMR_WR_QPBINDE 0x1 2347 #define V_FW_RI_FR_NSMR_WR_QPBINDE(x) ((x) << S_FW_RI_FR_NSMR_WR_QPBINDE) 2348 #define G_FW_RI_FR_NSMR_WR_QPBINDE(x) \ 2349 (((x) >> S_FW_RI_FR_NSMR_WR_QPBINDE) & M_FW_RI_FR_NSMR_WR_QPBINDE) 2350 #define F_FW_RI_FR_NSMR_WR_QPBINDE V_FW_RI_FR_NSMR_WR_QPBINDE(1U) 2351 2352 #define S_FW_RI_FR_NSMR_WR_NS 5 2353 #define M_FW_RI_FR_NSMR_WR_NS 0x1 2354 #define V_FW_RI_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_FR_NSMR_WR_NS) 2355 #define G_FW_RI_FR_NSMR_WR_NS(x) \ 2356 (((x) >> S_FW_RI_FR_NSMR_WR_NS) & M_FW_RI_FR_NSMR_WR_NS) 2357 #define F_FW_RI_FR_NSMR_WR_NS V_FW_RI_FR_NSMR_WR_NS(1U) 2358 2359 #define S_FW_RI_FR_NSMR_WR_DCACPU 0 2360 #define M_FW_RI_FR_NSMR_WR_DCACPU 0x1f 2361 #define V_FW_RI_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_FR_NSMR_WR_DCACPU) 2362 #define G_FW_RI_FR_NSMR_WR_DCACPU(x) \ 2363 (((x) >> S_FW_RI_FR_NSMR_WR_DCACPU) & M_FW_RI_FR_NSMR_WR_DCACPU) 2364 2365 struct fw_ri_fr_nsmr_tpte_wr { 2366 __u8 opcode; 2367 __u8 flags; 2368 __u16 wrid; 2369 __u8 r1[3]; 2370 __u8 len16; 2371 __be32 r2; 2372 __be32 stag; 2373 struct fw_ri_tpte tpte; 2374 __be64 pbl[2]; 2375 }; 2376 2377 struct fw_ri_inv_lstag_wr { 2378 __u8 opcode; 2379 __u8 flags; 2380 __u16 wrid; 2381 __u8 r1[3]; 2382 __u8 len16; 2383 __be32 r2; 2384 __be32 stag_inv; 2385 }; 2386 2387 struct fw_ri_send_immediate_wr { 2388 __u8 opcode; 2389 __u8 flags; 2390 __u16 wrid; 2391 __u8 r1[3]; 2392 __u8 len16; 2393 __be32 sendimmop_pkd; 2394 __be32 r3; 2395 __be32 plen; 2396 __be32 r4; 2397 __be64 r5; 2398 #ifndef C99_NOT_SUPPORTED 2399 struct fw_ri_immd immd_src[0]; 2400 #endif 2401 }; 2402 2403 #define S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0 2404 #define M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP 0xf 2405 #define V_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2406 ((x) << S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2407 #define G_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP(x) \ 2408 (((x) >> S_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) & \ 2409 M_FW_RI_SEND_IMMEDIATE_WR_SENDIMMOP) 2410 2411 enum fw_ri_atomic_op { 2412 FW_RI_ATOMIC_OP_FETCHADD, 2413 FW_RI_ATOMIC_OP_SWAP, 2414 FW_RI_ATOMIC_OP_CMDSWAP, 2415 }; 2416 2417 struct fw_ri_atomic_wr { 2418 __u8 opcode; 2419 __u8 flags; 2420 __u16 wrid; 2421 __u8 r1[3]; 2422 __u8 len16; 2423 __be32 atomicop_pkd; 2424 __be64 r3; 2425 __be32 aopcode_pkd; 2426 __be32 reqid; 2427 __be32 stag; 2428 __be32 to_hi; 2429 __be32 to_lo; 2430 __be32 addswap_data_hi; 2431 __be32 addswap_data_lo; 2432 __be32 addswap_mask_hi; 2433 __be32 addswap_mask_lo; 2434 __be32 compare_data_hi; 2435 __be32 compare_data_lo; 2436 __be32 compare_mask_hi; 2437 __be32 compare_mask_lo; 2438 __be32 r5; 2439 }; 2440 2441 #define S_FW_RI_ATOMIC_WR_ATOMICOP 0 2442 #define M_FW_RI_ATOMIC_WR_ATOMICOP 0xf 2443 #define V_FW_RI_ATOMIC_WR_ATOMICOP(x) ((x) << S_FW_RI_ATOMIC_WR_ATOMICOP) 2444 #define G_FW_RI_ATOMIC_WR_ATOMICOP(x) \ 2445 (((x) >> S_FW_RI_ATOMIC_WR_ATOMICOP) & M_FW_RI_ATOMIC_WR_ATOMICOP) 2446 2447 #define S_FW_RI_ATOMIC_WR_AOPCODE 0 2448 #define M_FW_RI_ATOMIC_WR_AOPCODE 0xf 2449 #define V_FW_RI_ATOMIC_WR_AOPCODE(x) ((x) << S_FW_RI_ATOMIC_WR_AOPCODE) 2450 #define G_FW_RI_ATOMIC_WR_AOPCODE(x) \ 2451 (((x) >> S_FW_RI_ATOMIC_WR_AOPCODE) & M_FW_RI_ATOMIC_WR_AOPCODE) 2452 2453 enum fw_ri_type { 2454 FW_RI_TYPE_INIT, 2455 FW_RI_TYPE_FINI, 2456 FW_RI_TYPE_TERMINATE 2457 }; 2458 2459 enum fw_ri_init_p2ptype { 2460 FW_RI_INIT_P2PTYPE_RDMA_WRITE = FW_RI_RDMA_WRITE, 2461 FW_RI_INIT_P2PTYPE_READ_REQ = FW_RI_READ_REQ, 2462 FW_RI_INIT_P2PTYPE_SEND = FW_RI_SEND, 2463 FW_RI_INIT_P2PTYPE_SEND_WITH_INV = FW_RI_SEND_WITH_INV, 2464 FW_RI_INIT_P2PTYPE_SEND_WITH_SE = FW_RI_SEND_WITH_SE, 2465 FW_RI_INIT_P2PTYPE_SEND_WITH_SE_INV = FW_RI_SEND_WITH_SE_INV, 2466 FW_RI_INIT_P2PTYPE_DISABLED = 0xf, 2467 }; 2468 2469 enum fw_ri_init_rqeqid_srq { 2470 FW_RI_INIT_RQEQID_SRQ = 1 << 31, 2471 }; 2472 2473 enum fw_nvmet_ulpsubmode { 2474 FW_NVMET_ULPSUBMODE_HCRC = 0x1<<0, 2475 FW_NVMET_ULPSUBMODE_DCRC = 0x1<<1, 2476 FW_NVMET_ULPSUBMODE_ING_DIR = 0x1<<2, 2477 FW_NVMET_ULPSUBMODE_SRQ_ENABLE = 0x1<<3, 2478 FW_NVMET_ULPSUBMODE_PER_PDU_CMP = 0x1<<4, 2479 FW_NVMET_ULPSUBMODE_PI_ENABLE = 0x1<<5, 2480 FW_NVMET_ULPSUBMODE_USER_MODE = 0x1<<6, 2481 }; 2482 2483 struct fw_ri_wr { 2484 __be32 op_compl; /* op_to_transport_type */ 2485 __be32 flowid_len16; 2486 __u64 cookie; 2487 union fw_ri { 2488 struct fw_ri_init { 2489 __u8 type; 2490 __u8 mpareqbit_p2ptype; 2491 __u8 r4[2]; 2492 __u8 mpa_attrs; 2493 __u8 qp_caps; 2494 __be16 nrqe; 2495 __be32 pdid; 2496 __be32 qpid; 2497 __be32 sq_eqid; 2498 __be32 rq_eqid; 2499 __be32 scqid; 2500 __be32 rcqid; 2501 __be32 ord_max; 2502 __be32 ird_max; 2503 __be32 iss; 2504 __be32 irs; 2505 __be32 hwrqsize; 2506 __be32 hwrqaddr; 2507 __be64 r5; 2508 union fw_ri_init_p2p { 2509 struct fw_ri_rdma_write_wr write; 2510 struct fw_ri_rdma_read_wr read; 2511 struct fw_ri_send_wr send; 2512 } u; 2513 } init; 2514 struct fw_ri_rocev2_init { 2515 __u8 type; 2516 __u8 r3[3]; 2517 __u8 rocev2_flags; 2518 __u8 qp_caps; 2519 __be16 nrqe; 2520 __be32 pdid; 2521 __be32 qpid; 2522 __be32 sq_eqid; 2523 __be32 rq_eqid; 2524 __be32 scqid; 2525 __be32 rcqid; 2526 __be32 ord_max; 2527 __be32 ird_max; 2528 __be32 psn_pkd; 2529 __be32 epsn_pkd; 2530 __be32 hwrqsize; 2531 __be32 hwrqaddr; 2532 __be32 q_key; 2533 __u8 pkthdrsize; 2534 __u8 r; 2535 __be16 p_key; 2536 //struct cpl_tx_tnl_lso tnl_lso; 2537 __u8 tnl_lso[48]; /* cpl_tx_tnl_lso + cpl_tx_pkt_xt */ 2538 #ifndef C99_NOT_SUPPORTED 2539 struct fw_ri_immd pkthdr[0]; 2540 #endif 2541 } rocev2_init; 2542 struct fw_ri_nvmet_init { 2543 __u8 type; 2544 __u8 r3[3]; 2545 __u8 nvmt_flags; 2546 __u8 qp_caps; 2547 __be16 nrqe; 2548 __be32 pdid; 2549 __be32 qpid; 2550 __be32 sq_eqid; 2551 __be32 rq_eqid; 2552 __be32 scqid; 2553 __be32 rcqid; 2554 __be32 r4[4]; 2555 __be32 hwrqsize; 2556 __be32 hwrqaddr; 2557 __u8 ulpsubmode; 2558 __u8 nvmt_pda_cmp_imm_sz; 2559 __be16 r7; 2560 __be32 tpt_offset_t10_config; 2561 __be32 r8[2]; 2562 } nvmet_init; 2563 struct fw_ri_iscsi_init { 2564 __u8 type; 2565 __u8 dcrc_dis_to_hcrc; 2566 __u8 r4[3]; 2567 __u8 qp_caps; 2568 __be16 r5; 2569 __be32 pdid; 2570 __be32 qpid; 2571 __be32 sq_eqid; 2572 __be32 r6; 2573 __be32 scqid; 2574 __be32 rcqid; 2575 __be32 r7[4]; 2576 __be32 r8[2]; 2577 __be64 r9; 2578 } iscsi_init; 2579 struct fw_ri_fini { 2580 __u8 type; 2581 __u8 r3[7]; 2582 __be64 r4; 2583 } fini; 2584 struct fw_ri_terminate { 2585 __u8 type; 2586 __u8 r3[3]; 2587 __be32 immdlen; 2588 __u8 termmsg[40]; 2589 } terminate; 2590 } u; 2591 }; 2592 2593 #define S_FW_RI_WR_TRANSPORT_TYPE 16 2594 #define M_FW_RI_WR_TRANSPORT_TYPE 0x7 2595 #define V_FW_RI_WR_TRANSPORT_TYPE(x) ((x) << S_FW_RI_WR_TRANSPORT_TYPE) 2596 #define G_FW_RI_WR_TRANSPORT_TYPE(x) \ 2597 (((x) >> S_FW_RI_WR_TRANSPORT_TYPE) & M_FW_RI_WR_TRANSPORT_TYPE) 2598 2599 #define S_FW_RI_WR_MPAREQBIT 7 2600 #define M_FW_RI_WR_MPAREQBIT 0x1 2601 #define V_FW_RI_WR_MPAREQBIT(x) ((x) << S_FW_RI_WR_MPAREQBIT) 2602 #define G_FW_RI_WR_MPAREQBIT(x) \ 2603 (((x) >> S_FW_RI_WR_MPAREQBIT) & M_FW_RI_WR_MPAREQBIT) 2604 #define F_FW_RI_WR_MPAREQBIT V_FW_RI_WR_MPAREQBIT(1U) 2605 2606 #define S_FW_RI_WR_0BRRBIT 6 2607 #define M_FW_RI_WR_0BRRBIT 0x1 2608 #define V_FW_RI_WR_0BRRBIT(x) ((x) << S_FW_RI_WR_0BRRBIT) 2609 #define G_FW_RI_WR_0BRRBIT(x) \ 2610 (((x) >> S_FW_RI_WR_0BRRBIT) & M_FW_RI_WR_0BRRBIT) 2611 #define F_FW_RI_WR_0BRRBIT V_FW_RI_WR_0BRRBIT(1U) 2612 2613 #define S_FW_RI_WR_P2PTYPE 0 2614 #define M_FW_RI_WR_P2PTYPE 0xf 2615 #define V_FW_RI_WR_P2PTYPE(x) ((x) << S_FW_RI_WR_P2PTYPE) 2616 #define G_FW_RI_WR_P2PTYPE(x) \ 2617 (((x) >> S_FW_RI_WR_P2PTYPE) & M_FW_RI_WR_P2PTYPE) 2618 2619 #define S_FW_RI_WR_PSN 0 2620 #define M_FW_RI_WR_PSN 0xffffff 2621 #define V_FW_RI_WR_PSN(x) ((x) << S_FW_RI_WR_PSN) 2622 #define G_FW_RI_WR_PSN(x) (((x) >> S_FW_RI_WR_PSN) & M_FW_RI_WR_PSN) 2623 2624 #define S_FW_RI_WR_EPSN 0 2625 #define M_FW_RI_WR_EPSN 0xffffff 2626 #define V_FW_RI_WR_EPSN(x) ((x) << S_FW_RI_WR_EPSN) 2627 #define G_FW_RI_WR_EPSN(x) (((x) >> S_FW_RI_WR_EPSN) & M_FW_RI_WR_EPSN) 2628 2629 #define S_FW_RI_WR_NVMT_PDA 3 2630 #define M_FW_RI_WR_NVMT_PDA 0x1f 2631 #define V_FW_RI_WR_NVMT_PDA(x) ((x) << S_FW_RI_WR_NVMT_PDA) 2632 #define G_FW_RI_WR_NVMT_PDA(x) \ 2633 (((x) >> S_FW_RI_WR_NVMT_PDA) & M_FW_RI_WR_NVMT_PDA) 2634 2635 #define S_FW_RI_WR_CMP_IMM_SZ 1 2636 #define M_FW_RI_WR_CMP_IMM_SZ 0x3 2637 #define V_FW_RI_WR_CMP_IMM_SZ(x) ((x) << S_FW_RI_WR_CMP_IMM_SZ) 2638 #define G_FW_RI_WR_CMP_IMM_SZ(x) \ 2639 (((x) >> S_FW_RI_WR_CMP_IMM_SZ) & M_FW_RI_WR_CMP_IMM_SZ) 2640 2641 #define S_FW_RI_WR_TPT_OFFSET 10 2642 #define M_FW_RI_WR_TPT_OFFSET 0x3fffff 2643 #define V_FW_RI_WR_TPT_OFFSET(x) ((x) << S_FW_RI_WR_TPT_OFFSET) 2644 #define G_FW_RI_WR_TPT_OFFSET(x) \ 2645 (((x) >> S_FW_RI_WR_TPT_OFFSET) & M_FW_RI_WR_TPT_OFFSET) 2646 2647 #define S_FW_RI_WR_T10_CONFIG 0 2648 #define M_FW_RI_WR_T10_CONFIG 0x3ff 2649 #define V_FW_RI_WR_T10_CONFIG(x) ((x) << S_FW_RI_WR_T10_CONFIG) 2650 #define G_FW_RI_WR_T10_CONFIG(x) \ 2651 (((x) >> S_FW_RI_WR_T10_CONFIG) & M_FW_RI_WR_T10_CONFIG) 2652 2653 #define S_FW_RI_WR_DCRC_DIS 7 2654 #define M_FW_RI_WR_DCRC_DIS 0x1 2655 #define V_FW_RI_WR_DCRC_DIS(x) ((x) << S_FW_RI_WR_DCRC_DIS) 2656 #define G_FW_RI_WR_DCRC_DIS(x) \ 2657 (((x) >> S_FW_RI_WR_DCRC_DIS) & M_FW_RI_WR_DCRC_DIS) 2658 #define F_FW_RI_WR_DCRC_DIS V_FW_RI_WR_DCRC_DIS(1U) 2659 2660 #define S_FW_RI_WR_HCRC_DIS 6 2661 #define M_FW_RI_WR_HCRC_DIS 0x1 2662 #define V_FW_RI_WR_HCRC_DIS(x) ((x) << S_FW_RI_WR_HCRC_DIS) 2663 #define G_FW_RI_WR_HCRC_DIS(x) \ 2664 (((x) >> S_FW_RI_WR_HCRC_DIS) & M_FW_RI_WR_HCRC_DIS) 2665 #define F_FW_RI_WR_HCRC_DIS V_FW_RI_WR_HCRC_DIS(1U) 2666 2667 #define S_FW_RI_WR_PSZ_IDX 4 2668 #define M_FW_RI_WR_PSZ_IDX 0x3 2669 #define V_FW_RI_WR_PSZ_IDX(x) ((x) << S_FW_RI_WR_PSZ_IDX) 2670 #define G_FW_RI_WR_PSZ_IDX(x) \ 2671 (((x) >> S_FW_RI_WR_PSZ_IDX) & M_FW_RI_WR_PSZ_IDX) 2672 2673 #define S_FW_RI_WR_DCRC 1 2674 #define M_FW_RI_WR_DCRC 0x1 2675 #define V_FW_RI_WR_DCRC(x) ((x) << S_FW_RI_WR_DCRC) 2676 #define G_FW_RI_WR_DCRC(x) (((x) >> S_FW_RI_WR_DCRC) & M_FW_RI_WR_DCRC) 2677 #define F_FW_RI_WR_DCRC V_FW_RI_WR_DCRC(1U) 2678 2679 #define S_FW_RI_WR_HCRC 0 2680 #define M_FW_RI_WR_HCRC 0x1 2681 #define V_FW_RI_WR_HCRC(x) ((x) << S_FW_RI_WR_HCRC) 2682 #define G_FW_RI_WR_HCRC(x) (((x) >> S_FW_RI_WR_HCRC) & M_FW_RI_WR_HCRC) 2683 #define F_FW_RI_WR_HCRC V_FW_RI_WR_HCRC(1U) 2684 2685 /****************************************************************************** 2686 * R o C E V 2 W O R K R E Q U E S T s 2687 **************************************/ 2688 enum fw_rocev2_wr_opcode { 2689 /* RC */ 2690 FW_ROCEV2_RC_SEND_FIRST = 0x00, 2691 FW_ROCEV2_RC_SEND_MIDDLE = 0x01, 2692 FW_ROCEV2_RC_SEND_LAST = 0x02, 2693 FW_ROCEV2_RC_SEND_LAST_WITH_IMMD = 0x03, 2694 FW_ROCEV2_RC_SEND_ONLY = 0x04, 2695 FW_ROCEV2_RC_SEND_ONLY_WITH_IMMD = 0x05, 2696 FW_ROCEV2_RC_RDMA_WRITE_FIRST = 0x06, 2697 FW_ROCEV2_RC_RDMA_WRITE_MIDDLE = 0x07, 2698 FW_ROCEV2_RC_RDMA_WRITE_LAST = 0x08, 2699 FW_ROCEV2_RC_RDMA_WRITE_LAST_WITH_IMMD = 0x09, 2700 FW_ROCEV2_RC_RDMA_WRITE_ONLY = 0x0a, 2701 FW_ROCEV2_RC_RDMA_WRITE_ONLY_WITH_IMMD = 0x0b, 2702 FW_ROCEV2_RC_RDMA_READ_REQ = 0x0c, 2703 FW_ROCEV2_RC_RDMA_READ_RESP_FIRST = 0x0d, 2704 FW_ROCEV2_RC_RDMA_READ_RESP_MIDDLE = 0x0e, 2705 FW_ROCEV2_RC_RDMA_READ_RESP_LAST = 0x0f, 2706 FW_ROCEV2_RC_RDMA_READ_RESP_ONLY = 0x10, 2707 FW_ROCEV2_RC_ACK = 0x11, 2708 FW_ROCEV2_RC_ATOMIC_ACK = 0x12, 2709 FW_ROCEV2_RC_CMP_SWAP = 0x13, 2710 FW_ROCEV2_RC_FETCH_ADD = 0x14, 2711 FW_ROCEV2_RC_SEND_LAST_WITH_INV = 0x16, 2712 FW_ROCEV2_RC_SEND_ONLY_WITH_INV = 0x17, 2713 2714 /* XRC */ 2715 FW_ROCEV2_XRC_SEND_FIRST = 0xa0, 2716 FW_ROCEV2_XRC_SEND_MIDDLE = 0xa1, 2717 FW_ROCEV2_XRC_SEND_LAST = 0xa2, 2718 FW_ROCEV2_XRC_SEND_LAST_WITH_IMMD = 0xa3, 2719 FW_ROCEV2_XRC_SEND_ONLY = 0xa4, 2720 FW_ROCEV2_XRC_SEND_ONLY_WITH_IMMD = 0xa5, 2721 FW_ROCEV2_XRC_RDMA_WRITE_FIRST = 0xa6, 2722 FW_ROCEV2_XRC_RDMA_WRITE_MIDDLE = 0xa7, 2723 FW_ROCEV2_XRC_RDMA_WRITE_LAST = 0xa8, 2724 FW_ROCEV2_XRC_RDMA_WRITE_LAST_WITH_IMMD = 0xa9, 2725 FW_ROCEV2_XRC_RDMA_WRITE_ONLY = 0xaa, 2726 FW_ROCEV2_XRC_RDMA_WRITE_ONLY_WITH_IMMD = 0xab, 2727 FW_ROCEV2_XRC_RDMA_READ_REQ = 0xac, 2728 FW_ROCEV2_XRC_RDMA_READ_RESP_FIRST = 0xad, 2729 FW_ROCEV2_XRC_RDMA_READ_RESP_MIDDLE = 0xae, 2730 FW_ROCEV2_XRC_RDMA_READ_RESP_LAST = 0xaf, 2731 FW_ROCEV2_XRC_RDMA_READ_RESP_ONLY = 0xb0, 2732 FW_ROCEV2_XRC_ACK = 0xb1, 2733 FW_ROCEV2_XRC_ATOMIC_ACK = 0xb2, 2734 FW_ROCEV2_XRC_CMP_SWAP = 0xb3, 2735 FW_ROCEV2_XRC_FETCH_ADD = 0xb4, 2736 FW_ROCEV2_XRC_SEND_LAST_WITH_INV = 0xb6, 2737 FW_ROCEV2_XRC_SEND_ONLY_WITH_INV = 0xb7, 2738 }; 2739 2740 #if 0 2741 enum fw_rocev2_cqe_err { 2742 /* TODO */ 2743 }; 2744 #endif 2745 2746 struct fw_ri_v2_rdma_write_wr { 2747 __u8 opcode; 2748 __u8 v2_flags; 2749 __u16 wrid; 2750 __u8 r1[3]; 2751 __u8 len16; 2752 __be32 r2; /* set to 0 */ 2753 __be32 psn_pkd; 2754 __be32 r4[2]; 2755 __be32 r5; 2756 __be32 immd_data; 2757 __be64 to_sink; 2758 __be32 stag_sink; 2759 __be32 plen; 2760 #ifndef C99_NOT_SUPPORTED 2761 union { 2762 struct fw_ri_immd immd_src[0]; 2763 struct fw_ri_isgl isgl_src[0]; 2764 } u; 2765 #endif 2766 }; 2767 2768 #define S_FW_RI_V2_RDMA_WRITE_WR_PSN 0 2769 #define M_FW_RI_V2_RDMA_WRITE_WR_PSN 0xffffff 2770 #define V_FW_RI_V2_RDMA_WRITE_WR_PSN(x) ((x) << S_FW_RI_V2_RDMA_WRITE_WR_PSN) 2771 #define G_FW_RI_V2_RDMA_WRITE_WR_PSN(x) \ 2772 (((x) >> S_FW_RI_V2_RDMA_WRITE_WR_PSN) & M_FW_RI_V2_RDMA_WRITE_WR_PSN) 2773 2774 struct fw_ri_v2_send_wr { 2775 __u8 opcode; 2776 __u8 v2_flags; 2777 __u16 wrid; 2778 __u8 r1[3]; 2779 __u8 len16; 2780 __be32 r2; /* set to 0 */ 2781 __be32 stag_inv; 2782 __be32 plen; 2783 __be32 sendop_psn; 2784 __u8 immdlen; 2785 __u8 r3[3]; 2786 __be32 r4; 2787 /* CPL_TX_TNL_LSO, CPL_TX_PKT_XT and Eth/IP/UDP/BTH 2788 * headers in UD QP case, align size to 16B */ 2789 #ifndef C99_NOT_SUPPORTED 2790 union { 2791 struct fw_ri_immd immd_src[0]; 2792 struct fw_ri_isgl isgl_src[0]; 2793 } u; 2794 #endif 2795 }; 2796 2797 #define S_FW_RI_V2_SEND_WR_SENDOP 24 2798 #define M_FW_RI_V2_SEND_WR_SENDOP 0xff 2799 #define V_FW_RI_V2_SEND_WR_SENDOP(x) ((x) << S_FW_RI_V2_SEND_WR_SENDOP) 2800 #define G_FW_RI_V2_SEND_WR_SENDOP(x) \ 2801 (((x) >> S_FW_RI_V2_SEND_WR_SENDOP) & M_FW_RI_V2_SEND_WR_SENDOP) 2802 2803 #define S_FW_RI_V2_SEND_WR_PSN 0 2804 #define M_FW_RI_V2_SEND_WR_PSN 0xffffff 2805 #define V_FW_RI_V2_SEND_WR_PSN(x) ((x) << S_FW_RI_V2_SEND_WR_PSN) 2806 #define G_FW_RI_V2_SEND_WR_PSN(x) \ 2807 (((x) >> S_FW_RI_V2_SEND_WR_PSN) & M_FW_RI_V2_SEND_WR_PSN) 2808 2809 struct fw_ri_v2_rdma_read_wr { 2810 __u8 opcode; 2811 __u8 v2_flags; 2812 __u16 wrid; 2813 __u8 r1[3]; 2814 __u8 len16; 2815 __be32 r2; /* set to 0 */ 2816 __be32 psn_pkd; 2817 __be64 to_src; 2818 __be32 stag_src; 2819 __be32 plen; 2820 struct fw_ri_isgl isgl_sink; /* RRQ, max 4 nsge in rocev2, 1 in iwarp */ 2821 }; 2822 2823 #define S_FW_RI_V2_RDMA_READ_WR_PSN 0 2824 #define M_FW_RI_V2_RDMA_READ_WR_PSN 0xffffff 2825 #define V_FW_RI_V2_RDMA_READ_WR_PSN(x) ((x) << S_FW_RI_V2_RDMA_READ_WR_PSN) 2826 #define G_FW_RI_V2_RDMA_READ_WR_PSN(x) \ 2827 (((x) >> S_FW_RI_V2_RDMA_READ_WR_PSN) & M_FW_RI_V2_RDMA_READ_WR_PSN) 2828 2829 struct fw_ri_v2_atomic_wr { 2830 __u8 opcode; 2831 __u8 v2_flags; 2832 __u16 wrid; 2833 __u8 r1[3]; 2834 __u8 len16; 2835 __be32 r2; /* set to 0 */ 2836 __be32 atomicop_psn; 2837 }; 2838 2839 #define S_FW_RI_V2_ATOMIC_WR_ATOMICOP 28 2840 #define M_FW_RI_V2_ATOMIC_WR_ATOMICOP 0xf 2841 #define V_FW_RI_V2_ATOMIC_WR_ATOMICOP(x) \ 2842 ((x) << S_FW_RI_V2_ATOMIC_WR_ATOMICOP) 2843 #define G_FW_RI_V2_ATOMIC_WR_ATOMICOP(x) \ 2844 (((x) >> S_FW_RI_V2_ATOMIC_WR_ATOMICOP) & M_FW_RI_V2_ATOMIC_WR_ATOMICOP) 2845 2846 #define S_FW_RI_V2_ATOMIC_WR_PSN 0 2847 #define M_FW_RI_V2_ATOMIC_WR_PSN 0xffffff 2848 #define V_FW_RI_V2_ATOMIC_WR_PSN(x) ((x) << S_FW_RI_V2_ATOMIC_WR_PSN) 2849 #define G_FW_RI_V2_ATOMIC_WR_PSN(x) \ 2850 (((x) >> S_FW_RI_V2_ATOMIC_WR_PSN) & M_FW_RI_V2_ATOMIC_WR_PSN) 2851 2852 struct fw_ri_v2_bind_mw_wr { 2853 __u8 opcode; 2854 __u8 flags; 2855 __u16 wrid; 2856 __u8 r1[3]; 2857 __u8 len16; 2858 __be32 r2; 2859 __be32 r5; 2860 __be32 r6[2]; 2861 __u8 qpbinde_to_dcacpu; 2862 __u8 pgsz_shift; 2863 __u8 addr_type; 2864 __u8 mem_perms; 2865 __be32 stag_mr; 2866 __be32 stag_mw; 2867 __be32 r3; 2868 __be64 len_mw; 2869 __be64 va_fbo; 2870 __be64 r4; 2871 }; 2872 2873 2874 #define S_FW_RI_V2_BIND_MW_WR_QPBINDE 6 2875 #define M_FW_RI_V2_BIND_MW_WR_QPBINDE 0x1 2876 #define V_FW_RI_V2_BIND_MW_WR_QPBINDE(x) \ 2877 ((x) << S_FW_RI_V2_BIND_MW_WR_QPBINDE) 2878 #define G_FW_RI_V2_BIND_MW_WR_QPBINDE(x) \ 2879 (((x) >> S_FW_RI_V2_BIND_MW_WR_QPBINDE) & M_FW_RI_V2_BIND_MW_WR_QPBINDE) 2880 #define F_FW_RI_V2_BIND_MW_WR_QPBINDE V_FW_RI_V2_BIND_MW_WR_QPBINDE(1U) 2881 2882 #define S_FW_RI_V2_BIND_MW_WR_NS 5 2883 #define M_FW_RI_V2_BIND_MW_WR_NS 0x1 2884 #define V_FW_RI_V2_BIND_MW_WR_NS(x) ((x) << S_FW_RI_V2_BIND_MW_WR_NS) 2885 #define G_FW_RI_V2_BIND_MW_WR_NS(x) \ 2886 (((x) >> S_FW_RI_V2_BIND_MW_WR_NS) & M_FW_RI_V2_BIND_MW_WR_NS) 2887 #define F_FW_RI_V2_BIND_MW_WR_NS V_FW_RI_V2_BIND_MW_WR_NS(1U) 2888 2889 #define S_FW_RI_V2_BIND_MW_WR_DCACPU 0 2890 #define M_FW_RI_V2_BIND_MW_WR_DCACPU 0x1f 2891 #define V_FW_RI_V2_BIND_MW_WR_DCACPU(x) ((x) << S_FW_RI_V2_BIND_MW_WR_DCACPU) 2892 #define G_FW_RI_V2_BIND_MW_WR_DCACPU(x) \ 2893 (((x) >> S_FW_RI_V2_BIND_MW_WR_DCACPU) & M_FW_RI_V2_BIND_MW_WR_DCACPU) 2894 2895 struct fw_ri_v2_fr_nsmr_wr { 2896 __u8 opcode; 2897 __u8 v2_flags; 2898 __u16 wrid; 2899 __u8 r1[3]; 2900 __u8 len16; 2901 __be32 r2; 2902 __be32 r3; 2903 __be32 r4[2]; 2904 __u8 qpbinde_to_dcacpu; 2905 __u8 pgsz_shift; 2906 __u8 addr_type; 2907 __u8 mem_perms; 2908 __be32 stag; 2909 __be32 len_hi; 2910 __be32 len_lo; 2911 __be32 va_hi; 2912 __be32 va_lo_fbo; 2913 }; 2914 2915 #define S_FW_RI_V2_FR_NSMR_WR_QPBINDE 6 2916 #define M_FW_RI_V2_FR_NSMR_WR_QPBINDE 0x1 2917 #define V_FW_RI_V2_FR_NSMR_WR_QPBINDE(x) \ 2918 ((x) << S_FW_RI_V2_FR_NSMR_WR_QPBINDE) 2919 #define G_FW_RI_V2_FR_NSMR_WR_QPBINDE(x) \ 2920 (((x) >> S_FW_RI_V2_FR_NSMR_WR_QPBINDE) & M_FW_RI_V2_FR_NSMR_WR_QPBINDE) 2921 #define F_FW_RI_V2_FR_NSMR_WR_QPBINDE V_FW_RI_V2_FR_NSMR_WR_QPBINDE(1U) 2922 2923 #define S_FW_RI_V2_FR_NSMR_WR_NS 5 2924 #define M_FW_RI_V2_FR_NSMR_WR_NS 0x1 2925 #define V_FW_RI_V2_FR_NSMR_WR_NS(x) ((x) << S_FW_RI_V2_FR_NSMR_WR_NS) 2926 #define G_FW_RI_V2_FR_NSMR_WR_NS(x) \ 2927 (((x) >> S_FW_RI_V2_FR_NSMR_WR_NS) & M_FW_RI_V2_FR_NSMR_WR_NS) 2928 #define F_FW_RI_V2_FR_NSMR_WR_NS V_FW_RI_V2_FR_NSMR_WR_NS(1U) 2929 2930 #define S_FW_RI_V2_FR_NSMR_WR_DCACPU 0 2931 #define M_FW_RI_V2_FR_NSMR_WR_DCACPU 0x1f 2932 #define V_FW_RI_V2_FR_NSMR_WR_DCACPU(x) ((x) << S_FW_RI_V2_FR_NSMR_WR_DCACPU) 2933 #define G_FW_RI_V2_FR_NSMR_WR_DCACPU(x) \ 2934 (((x) >> S_FW_RI_V2_FR_NSMR_WR_DCACPU) & M_FW_RI_V2_FR_NSMR_WR_DCACPU) 2935 2936 /****************************************************************************** 2937 * N V M E - T C P W O R K R E Q U E S T s 2938 *****************************************************************************/ 2939 2940 struct fw_nvmet_v2_fr_nsmr_wr { 2941 __be32 op_to_wrid; 2942 __be32 flowid_len16; 2943 __be32 r3; 2944 __be32 r4; 2945 __be32 mem_write_addr32; 2946 __u8 r5; 2947 __u8 imm_data_len32; 2948 union { 2949 __be16 dsgl_data_len32; 2950 __be16 reset_mem_len32; 2951 }; 2952 __be64 r6; 2953 }; 2954 2955 #define S_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL 23 2956 #define M_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL 0x1 2957 #define V_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL(x) \ 2958 ((x) << S_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL) 2959 #define G_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL(x) \ 2960 (((x) >> S_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL) & \ 2961 M_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL) 2962 #define F_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL \ 2963 V_FW_NVMET_V2_FR_NSMR_WR_TPTE_PBL(1U) 2964 2965 #define S_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM 22 2966 #define M_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM 0x1 2967 #define V_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM(x) \ 2968 ((x) << S_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM) 2969 #define G_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM(x) \ 2970 (((x) >> S_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM) & \ 2971 M_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM) 2972 #define F_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM \ 2973 V_FW_NVMET_V2_FR_NSMR_WR_RESET_MEM(1U) 2974 2975 #define S_FW_NVMET_V2_FR_NSMR_WR_WRID 0 2976 #define M_FW_NVMET_V2_FR_NSMR_WR_WRID 0xffff 2977 #define V_FW_NVMET_V2_FR_NSMR_WR_WRID(x) \ 2978 ((x) << S_FW_NVMET_V2_FR_NSMR_WR_WRID) 2979 #define G_FW_NVMET_V2_FR_NSMR_WR_WRID(x) \ 2980 (((x) >> S_FW_NVMET_V2_FR_NSMR_WR_WRID) & M_FW_NVMET_V2_FR_NSMR_WR_WRID) 2981 2982 struct fw_v2_nvmet_tx_data_wr { 2983 __be32 op_to_immdlen; 2984 __be32 flowid_len16; 2985 __be32 r4; 2986 __be16 r5; 2987 __be16 wrid; 2988 __be32 r6; 2989 __be32 seqno; 2990 __be32 plen; 2991 __be32 flags_hi_to_flags_lo; 2992 /* optional immdlen data (fw_tx_pi_hdr, iso cpl, nvmet header etc) */ 2993 #ifndef C99_NOT_SUPPORTED 2994 union { 2995 struct fw_ri_dsgl dsgl_src[0]; 2996 struct fw_ri_isgl isgl_src[0]; 2997 } u; 2998 #endif 2999 }; 3000 3001 #define S_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE 20 3002 #define M_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE 0x1 3003 #define V_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE(x) \ 3004 ((x) << S_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE) 3005 #define G_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE(x) \ 3006 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE) & \ 3007 M_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE) 3008 #define F_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE \ 3009 V_FW_V2_NVMET_TX_DATA_WR_DACK_CHANGE(1U) 3010 3011 #define S_FW_V2_NVMET_TX_DATA_WR_DACK_MODE 18 3012 #define M_FW_V2_NVMET_TX_DATA_WR_DACK_MODE 0x3 3013 #define V_FW_V2_NVMET_TX_DATA_WR_DACK_MODE(x) \ 3014 ((x) << S_FW_V2_NVMET_TX_DATA_WR_DACK_MODE) 3015 #define G_FW_V2_NVMET_TX_DATA_WR_DACK_MODE(x) \ 3016 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_DACK_MODE) & \ 3017 M_FW_V2_NVMET_TX_DATA_WR_DACK_MODE) 3018 3019 #define S_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI 10 3020 #define M_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI 0x3fffff 3021 #define V_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI(x) \ 3022 ((x) << S_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI) 3023 #define G_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI(x) \ 3024 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI) & \ 3025 M_FW_V2_NVMET_TX_DATA_WR_FLAGS_HI) 3026 3027 #define S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO 9 3028 #define M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO 0x1 3029 #define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 3030 ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO) 3031 #define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO(x) \ 3032 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO) & \ 3033 M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO) 3034 #define F_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO \ 3035 V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_ISO(1U) 3036 3037 #define S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI 8 3038 #define M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI 0x1 3039 #define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI(x) \ 3040 ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI) 3041 #define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI(x) \ 3042 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI) & \ 3043 M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI) 3044 #define F_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI \ 3045 V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_PI(1U) 3046 3047 #define S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC 7 3048 #define M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC 0x1 3049 #define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 3050 ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC) 3051 #define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC(x) \ 3052 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC) & \ 3053 M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC) 3054 #define F_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC \ 3055 V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_DCRC(1U) 3056 3057 #define S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC 6 3058 #define M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC 0x1 3059 #define V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 3060 ((x) << S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC) 3061 #define G_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC(x) \ 3062 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC) & \ 3063 M_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC) 3064 #define F_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC \ 3065 V_FW_V2_NVMET_TX_DATA_WR_ULPSUBMODE_HCRC(1U) 3066 3067 #define S_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO 0 3068 #define M_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO 0x3f 3069 #define V_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO(x) \ 3070 ((x) << S_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO) 3071 #define G_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO(x) \ 3072 (((x) >> S_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO) & \ 3073 M_FW_V2_NVMET_TX_DATA_WR_FLAGS_LO) 3074 3075 3076 /****************************************************************************** 3077 * F O i S C S I W O R K R E Q U E S T s 3078 *********************************************/ 3079 3080 #define FW_FOISCSI_NAME_MAX_LEN 224 3081 #define FW_FOISCSI_ALIAS_MAX_LEN 224 3082 #define FW_FOISCSI_KEY_MAX_LEN 64 3083 #define FW_FOISCSI_VAL_MAX_LEN 256 3084 #define FW_FOISCSI_CHAP_SEC_MAX_LEN 128 3085 #define FW_FOISCSI_INIT_NODE_MAX 8 3086 3087 enum fw_chnet_ifconf_wr_subop { 3088 FW_CHNET_IFCONF_WR_SUBOP_NONE = 0, 3089 3090 FW_CHNET_IFCONF_WR_SUBOP_IPV4_SET, 3091 FW_CHNET_IFCONF_WR_SUBOP_IPV4_GET, 3092 3093 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_SET, 3094 FW_CHNET_IFCONF_WR_SUBOP_VLAN_IPV4_GET, 3095 3096 FW_CHNET_IFCONF_WR_SUBOP_IPV6_SET, 3097 FW_CHNET_IFCONF_WR_SUBOP_IPV6_GET, 3098 3099 FW_CHNET_IFCONF_WR_SUBOP_VLAN_SET, 3100 FW_CHNET_IFCONF_WR_SUBOP_VLAN_GET, 3101 3102 FW_CHNET_IFCONF_WR_SUBOP_MTU_SET, 3103 FW_CHNET_IFCONF_WR_SUBOP_MTU_GET, 3104 3105 FW_CHNET_IFCONF_WR_SUBOP_DHCP_SET, 3106 FW_CHNET_IFCONF_WR_SUBOP_DHCP_GET, 3107 3108 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_SET, 3109 FW_CHNET_IFCONF_WR_SUBOP_DHCPV6_GET, 3110 3111 FW_CHNET_IFCONF_WR_SUBOP_LINKLOCAL_ADDR_SET, 3112 FW_CHNET_IFCONF_WR_SUBOP_RA_BASED_ADDR_SET, 3113 FW_CHNET_IFCONF_WR_SUBOP_ADDR_EXPIRED, 3114 3115 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING4, 3116 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PING6, 3117 3118 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING4, 3119 FW_CHNET_IFCONF_WR_SUBOP_ICMP_PLD_PING6, 3120 3121 FW_CHNET_IFCONF_WR_SUBOP_PMTU6_CLEAR, 3122 3123 FW_CHNET_IFCONF_WR_SUBOP_MAX, 3124 }; 3125 3126 struct fw_chnet_ifconf_wr { 3127 __be32 op_compl; 3128 __be32 flowid_len16; 3129 __u64 cookie; 3130 __be32 if_flowid; 3131 __u8 idx; 3132 __u8 subop; 3133 __u8 retval; 3134 __u8 r2; 3135 union { 3136 __be64 r3; 3137 struct fw_chnet_ifconf_ping { 3138 __be16 ping_time; 3139 __u8 ping_rsptype; 3140 __u8 ping_param_rspcode_to_fin_bit; 3141 __u8 ping_pktsize; 3142 __u8 ping_ttl; 3143 __be16 ping_seq; 3144 } ping; 3145 struct fw_chnet_ifconf_mac { 3146 __u8 peer_mac[6]; 3147 __u8 smac_idx; 3148 } mac; 3149 } u; 3150 struct fw_chnet_ifconf_params { 3151 __be16 ping_pldsize; 3152 __be16 r0; 3153 __be16 vlanid; 3154 __be16 mtu; 3155 union fw_chnet_ifconf_addr_type { 3156 struct fw_chnet_ifconf_ipv4 { 3157 __be32 addr; 3158 __be32 mask; 3159 __be32 router; 3160 __be32 r0; 3161 __be64 r1; 3162 } ipv4; 3163 struct fw_chnet_ifconf_ipv6 { 3164 __u8 prefix_len; 3165 __u8 r0; 3166 __be16 r1; 3167 __be32 r2; 3168 __be64 addr_hi; 3169 __be64 addr_lo; 3170 __be64 router_hi; 3171 __be64 router_lo; 3172 } ipv6; 3173 } in_attr; 3174 } param; 3175 }; 3176 3177 #define S_FW_CHNET_IFCONF_WR_PING_MACBIT 1 3178 #define M_FW_CHNET_IFCONF_WR_PING_MACBIT 0x1 3179 #define V_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 3180 ((x) << S_FW_CHNET_IFCONF_WR_PING_MACBIT) 3181 #define G_FW_CHNET_IFCONF_WR_PING_MACBIT(x) \ 3182 (((x) >> S_FW_CHNET_IFCONF_WR_PING_MACBIT) & \ 3183 M_FW_CHNET_IFCONF_WR_PING_MACBIT) 3184 #define F_FW_CHNET_IFCONF_WR_PING_MACBIT \ 3185 V_FW_CHNET_IFCONF_WR_PING_MACBIT(1U) 3186 3187 #define S_FW_CHNET_IFCONF_WR_FIN_BIT 0 3188 #define M_FW_CHNET_IFCONF_WR_FIN_BIT 0x1 3189 #define V_FW_CHNET_IFCONF_WR_FIN_BIT(x) ((x) << S_FW_CHNET_IFCONF_WR_FIN_BIT) 3190 #define G_FW_CHNET_IFCONF_WR_FIN_BIT(x) \ 3191 (((x) >> S_FW_CHNET_IFCONF_WR_FIN_BIT) & M_FW_CHNET_IFCONF_WR_FIN_BIT) 3192 #define F_FW_CHNET_IFCONF_WR_FIN_BIT V_FW_CHNET_IFCONF_WR_FIN_BIT(1U) 3193 3194 enum fw_foiscsi_node_type { 3195 FW_FOISCSI_NODE_TYPE_INITIATOR = 0, 3196 FW_FOISCSI_NODE_TYPE_TARGET, 3197 }; 3198 3199 enum fw_foiscsi_session_type { 3200 FW_FOISCSI_SESSION_TYPE_DISCOVERY = 0, 3201 FW_FOISCSI_SESSION_TYPE_NORMAL, 3202 }; 3203 3204 enum fw_foiscsi_auth_policy { 3205 FW_FOISCSI_AUTH_POLICY_ONEWAY = 0, 3206 FW_FOISCSI_AUTH_POLICY_MUTUAL, 3207 }; 3208 3209 enum fw_foiscsi_auth_method { 3210 FW_FOISCSI_AUTH_METHOD_NONE = 0, 3211 FW_FOISCSI_AUTH_METHOD_CHAP, 3212 FW_FOISCSI_AUTH_METHOD_CHAP_FST, 3213 FW_FOISCSI_AUTH_METHOD_CHAP_SEC, 3214 }; 3215 3216 enum fw_foiscsi_digest_type { 3217 FW_FOISCSI_DIGEST_TYPE_NONE = 0, 3218 FW_FOISCSI_DIGEST_TYPE_CRC32, 3219 FW_FOISCSI_DIGEST_TYPE_CRC32_FST, 3220 FW_FOISCSI_DIGEST_TYPE_CRC32_SEC, 3221 }; 3222 3223 enum fw_foiscsi_wr_subop { 3224 FW_FOISCSI_WR_SUBOP_ADD = 1, 3225 FW_FOISCSI_WR_SUBOP_DEL = 2, 3226 FW_FOISCSI_WR_SUBOP_MOD = 4, 3227 }; 3228 3229 enum fw_coiscsi_stats_wr_subop { 3230 FW_COISCSI_WR_SUBOP_TOT = 1, 3231 FW_COISCSI_WR_SUBOP_MAX = 2, 3232 FW_COISCSI_WR_SUBOP_CUR = 3, 3233 FW_COISCSI_WR_SUBOP_CLR = 4, 3234 }; 3235 3236 enum fw_foiscsi_ctrl_state { 3237 FW_FOISCSI_CTRL_STATE_FREE = 0, 3238 FW_FOISCSI_CTRL_STATE_ONLINE = 1, 3239 FW_FOISCSI_CTRL_STATE_FAILED, 3240 FW_FOISCSI_CTRL_STATE_IN_RECOVERY, 3241 FW_FOISCSI_CTRL_STATE_REDIRECT, 3242 }; 3243 3244 struct fw_rdev_wr { 3245 __be32 op_to_immdlen; 3246 __be32 alloc_to_len16; 3247 __be64 cookie; 3248 __u8 protocol; 3249 __u8 event_cause; 3250 __u8 cur_state; 3251 __u8 prev_state; 3252 __be32 flags_to_assoc_flowid; 3253 union rdev_entry { 3254 struct fcoe_rdev_entry { 3255 __be32 flowid; 3256 __u8 protocol; 3257 __u8 event_cause; 3258 __u8 flags; 3259 __u8 rjt_reason; 3260 __u8 cur_login_st; 3261 __u8 prev_login_st; 3262 __be16 rcv_fr_sz; 3263 __u8 rd_xfer_rdy_to_rport_type; 3264 __u8 vft_to_qos; 3265 __u8 org_proc_assoc_to_acc_rsp_code; 3266 __u8 enh_disc_to_tgt; 3267 __u8 wwnn[8]; 3268 __u8 wwpn[8]; 3269 __be16 iqid; 3270 __u8 fc_oui[3]; 3271 __u8 r_id[3]; 3272 } fcoe_rdev; 3273 struct iscsi_rdev_entry { 3274 __be32 flowid; 3275 __u8 protocol; 3276 __u8 event_cause; 3277 __u8 flags; 3278 __u8 r3; 3279 __be16 iscsi_opts; 3280 __be16 tcp_opts; 3281 __be16 ip_opts; 3282 __be16 max_rcv_len; 3283 __be16 max_snd_len; 3284 __be16 first_brst_len; 3285 __be16 max_brst_len; 3286 __be16 r4; 3287 __be16 def_time2wait; 3288 __be16 def_time2ret; 3289 __be16 nop_out_intrvl; 3290 __be16 non_scsi_to; 3291 __be16 isid; 3292 __be16 tsid; 3293 __be16 port; 3294 __be16 tpgt; 3295 __u8 r5[6]; 3296 __be16 iqid; 3297 } iscsi_rdev; 3298 } u; 3299 }; 3300 3301 #define S_FW_RDEV_WR_IMMDLEN 0 3302 #define M_FW_RDEV_WR_IMMDLEN 0xff 3303 #define V_FW_RDEV_WR_IMMDLEN(x) ((x) << S_FW_RDEV_WR_IMMDLEN) 3304 #define G_FW_RDEV_WR_IMMDLEN(x) \ 3305 (((x) >> S_FW_RDEV_WR_IMMDLEN) & M_FW_RDEV_WR_IMMDLEN) 3306 3307 #define S_FW_RDEV_WR_ALLOC 31 3308 #define M_FW_RDEV_WR_ALLOC 0x1 3309 #define V_FW_RDEV_WR_ALLOC(x) ((x) << S_FW_RDEV_WR_ALLOC) 3310 #define G_FW_RDEV_WR_ALLOC(x) \ 3311 (((x) >> S_FW_RDEV_WR_ALLOC) & M_FW_RDEV_WR_ALLOC) 3312 #define F_FW_RDEV_WR_ALLOC V_FW_RDEV_WR_ALLOC(1U) 3313 3314 #define S_FW_RDEV_WR_FREE 30 3315 #define M_FW_RDEV_WR_FREE 0x1 3316 #define V_FW_RDEV_WR_FREE(x) ((x) << S_FW_RDEV_WR_FREE) 3317 #define G_FW_RDEV_WR_FREE(x) \ 3318 (((x) >> S_FW_RDEV_WR_FREE) & M_FW_RDEV_WR_FREE) 3319 #define F_FW_RDEV_WR_FREE V_FW_RDEV_WR_FREE(1U) 3320 3321 #define S_FW_RDEV_WR_MODIFY 29 3322 #define M_FW_RDEV_WR_MODIFY 0x1 3323 #define V_FW_RDEV_WR_MODIFY(x) ((x) << S_FW_RDEV_WR_MODIFY) 3324 #define G_FW_RDEV_WR_MODIFY(x) \ 3325 (((x) >> S_FW_RDEV_WR_MODIFY) & M_FW_RDEV_WR_MODIFY) 3326 #define F_FW_RDEV_WR_MODIFY V_FW_RDEV_WR_MODIFY(1U) 3327 3328 #define S_FW_RDEV_WR_FLOWID 8 3329 #define M_FW_RDEV_WR_FLOWID 0xfffff 3330 #define V_FW_RDEV_WR_FLOWID(x) ((x) << S_FW_RDEV_WR_FLOWID) 3331 #define G_FW_RDEV_WR_FLOWID(x) \ 3332 (((x) >> S_FW_RDEV_WR_FLOWID) & M_FW_RDEV_WR_FLOWID) 3333 3334 #define S_FW_RDEV_WR_LEN16 0 3335 #define M_FW_RDEV_WR_LEN16 0xff 3336 #define V_FW_RDEV_WR_LEN16(x) ((x) << S_FW_RDEV_WR_LEN16) 3337 #define G_FW_RDEV_WR_LEN16(x) \ 3338 (((x) >> S_FW_RDEV_WR_LEN16) & M_FW_RDEV_WR_LEN16) 3339 3340 #define S_FW_RDEV_WR_FLAGS 24 3341 #define M_FW_RDEV_WR_FLAGS 0xff 3342 #define V_FW_RDEV_WR_FLAGS(x) ((x) << S_FW_RDEV_WR_FLAGS) 3343 #define G_FW_RDEV_WR_FLAGS(x) \ 3344 (((x) >> S_FW_RDEV_WR_FLAGS) & M_FW_RDEV_WR_FLAGS) 3345 3346 #define S_FW_RDEV_WR_GET_NEXT 20 3347 #define M_FW_RDEV_WR_GET_NEXT 0xf 3348 #define V_FW_RDEV_WR_GET_NEXT(x) ((x) << S_FW_RDEV_WR_GET_NEXT) 3349 #define G_FW_RDEV_WR_GET_NEXT(x) \ 3350 (((x) >> S_FW_RDEV_WR_GET_NEXT) & M_FW_RDEV_WR_GET_NEXT) 3351 3352 #define S_FW_RDEV_WR_ASSOC_FLOWID 0 3353 #define M_FW_RDEV_WR_ASSOC_FLOWID 0xfffff 3354 #define V_FW_RDEV_WR_ASSOC_FLOWID(x) ((x) << S_FW_RDEV_WR_ASSOC_FLOWID) 3355 #define G_FW_RDEV_WR_ASSOC_FLOWID(x) \ 3356 (((x) >> S_FW_RDEV_WR_ASSOC_FLOWID) & M_FW_RDEV_WR_ASSOC_FLOWID) 3357 3358 #define S_FW_RDEV_WR_RJT 7 3359 #define M_FW_RDEV_WR_RJT 0x1 3360 #define V_FW_RDEV_WR_RJT(x) ((x) << S_FW_RDEV_WR_RJT) 3361 #define G_FW_RDEV_WR_RJT(x) (((x) >> S_FW_RDEV_WR_RJT) & M_FW_RDEV_WR_RJT) 3362 #define F_FW_RDEV_WR_RJT V_FW_RDEV_WR_RJT(1U) 3363 3364 #define S_FW_RDEV_WR_REASON 0 3365 #define M_FW_RDEV_WR_REASON 0x7f 3366 #define V_FW_RDEV_WR_REASON(x) ((x) << S_FW_RDEV_WR_REASON) 3367 #define G_FW_RDEV_WR_REASON(x) \ 3368 (((x) >> S_FW_RDEV_WR_REASON) & M_FW_RDEV_WR_REASON) 3369 3370 #define S_FW_RDEV_WR_RD_XFER_RDY 7 3371 #define M_FW_RDEV_WR_RD_XFER_RDY 0x1 3372 #define V_FW_RDEV_WR_RD_XFER_RDY(x) ((x) << S_FW_RDEV_WR_RD_XFER_RDY) 3373 #define G_FW_RDEV_WR_RD_XFER_RDY(x) \ 3374 (((x) >> S_FW_RDEV_WR_RD_XFER_RDY) & M_FW_RDEV_WR_RD_XFER_RDY) 3375 #define F_FW_RDEV_WR_RD_XFER_RDY V_FW_RDEV_WR_RD_XFER_RDY(1U) 3376 3377 #define S_FW_RDEV_WR_WR_XFER_RDY 6 3378 #define M_FW_RDEV_WR_WR_XFER_RDY 0x1 3379 #define V_FW_RDEV_WR_WR_XFER_RDY(x) ((x) << S_FW_RDEV_WR_WR_XFER_RDY) 3380 #define G_FW_RDEV_WR_WR_XFER_RDY(x) \ 3381 (((x) >> S_FW_RDEV_WR_WR_XFER_RDY) & M_FW_RDEV_WR_WR_XFER_RDY) 3382 #define F_FW_RDEV_WR_WR_XFER_RDY V_FW_RDEV_WR_WR_XFER_RDY(1U) 3383 3384 #define S_FW_RDEV_WR_FC_SP 5 3385 #define M_FW_RDEV_WR_FC_SP 0x1 3386 #define V_FW_RDEV_WR_FC_SP(x) ((x) << S_FW_RDEV_WR_FC_SP) 3387 #define G_FW_RDEV_WR_FC_SP(x) \ 3388 (((x) >> S_FW_RDEV_WR_FC_SP) & M_FW_RDEV_WR_FC_SP) 3389 #define F_FW_RDEV_WR_FC_SP V_FW_RDEV_WR_FC_SP(1U) 3390 3391 #define S_FW_RDEV_WR_RPORT_TYPE 0 3392 #define M_FW_RDEV_WR_RPORT_TYPE 0x1f 3393 #define V_FW_RDEV_WR_RPORT_TYPE(x) ((x) << S_FW_RDEV_WR_RPORT_TYPE) 3394 #define G_FW_RDEV_WR_RPORT_TYPE(x) \ 3395 (((x) >> S_FW_RDEV_WR_RPORT_TYPE) & M_FW_RDEV_WR_RPORT_TYPE) 3396 3397 #define S_FW_RDEV_WR_VFT 7 3398 #define M_FW_RDEV_WR_VFT 0x1 3399 #define V_FW_RDEV_WR_VFT(x) ((x) << S_FW_RDEV_WR_VFT) 3400 #define G_FW_RDEV_WR_VFT(x) (((x) >> S_FW_RDEV_WR_VFT) & M_FW_RDEV_WR_VFT) 3401 #define F_FW_RDEV_WR_VFT V_FW_RDEV_WR_VFT(1U) 3402 3403 #define S_FW_RDEV_WR_NPIV 6 3404 #define M_FW_RDEV_WR_NPIV 0x1 3405 #define V_FW_RDEV_WR_NPIV(x) ((x) << S_FW_RDEV_WR_NPIV) 3406 #define G_FW_RDEV_WR_NPIV(x) \ 3407 (((x) >> S_FW_RDEV_WR_NPIV) & M_FW_RDEV_WR_NPIV) 3408 #define F_FW_RDEV_WR_NPIV V_FW_RDEV_WR_NPIV(1U) 3409 3410 #define S_FW_RDEV_WR_CLASS 4 3411 #define M_FW_RDEV_WR_CLASS 0x3 3412 #define V_FW_RDEV_WR_CLASS(x) ((x) << S_FW_RDEV_WR_CLASS) 3413 #define G_FW_RDEV_WR_CLASS(x) \ 3414 (((x) >> S_FW_RDEV_WR_CLASS) & M_FW_RDEV_WR_CLASS) 3415 3416 #define S_FW_RDEV_WR_SEQ_DEL 3 3417 #define M_FW_RDEV_WR_SEQ_DEL 0x1 3418 #define V_FW_RDEV_WR_SEQ_DEL(x) ((x) << S_FW_RDEV_WR_SEQ_DEL) 3419 #define G_FW_RDEV_WR_SEQ_DEL(x) \ 3420 (((x) >> S_FW_RDEV_WR_SEQ_DEL) & M_FW_RDEV_WR_SEQ_DEL) 3421 #define F_FW_RDEV_WR_SEQ_DEL V_FW_RDEV_WR_SEQ_DEL(1U) 3422 3423 #define S_FW_RDEV_WR_PRIO_PREEMP 2 3424 #define M_FW_RDEV_WR_PRIO_PREEMP 0x1 3425 #define V_FW_RDEV_WR_PRIO_PREEMP(x) ((x) << S_FW_RDEV_WR_PRIO_PREEMP) 3426 #define G_FW_RDEV_WR_PRIO_PREEMP(x) \ 3427 (((x) >> S_FW_RDEV_WR_PRIO_PREEMP) & M_FW_RDEV_WR_PRIO_PREEMP) 3428 #define F_FW_RDEV_WR_PRIO_PREEMP V_FW_RDEV_WR_PRIO_PREEMP(1U) 3429 3430 #define S_FW_RDEV_WR_PREF 1 3431 #define M_FW_RDEV_WR_PREF 0x1 3432 #define V_FW_RDEV_WR_PREF(x) ((x) << S_FW_RDEV_WR_PREF) 3433 #define G_FW_RDEV_WR_PREF(x) \ 3434 (((x) >> S_FW_RDEV_WR_PREF) & M_FW_RDEV_WR_PREF) 3435 #define F_FW_RDEV_WR_PREF V_FW_RDEV_WR_PREF(1U) 3436 3437 #define S_FW_RDEV_WR_QOS 0 3438 #define M_FW_RDEV_WR_QOS 0x1 3439 #define V_FW_RDEV_WR_QOS(x) ((x) << S_FW_RDEV_WR_QOS) 3440 #define G_FW_RDEV_WR_QOS(x) (((x) >> S_FW_RDEV_WR_QOS) & M_FW_RDEV_WR_QOS) 3441 #define F_FW_RDEV_WR_QOS V_FW_RDEV_WR_QOS(1U) 3442 3443 #define S_FW_RDEV_WR_ORG_PROC_ASSOC 7 3444 #define M_FW_RDEV_WR_ORG_PROC_ASSOC 0x1 3445 #define V_FW_RDEV_WR_ORG_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_ORG_PROC_ASSOC) 3446 #define G_FW_RDEV_WR_ORG_PROC_ASSOC(x) \ 3447 (((x) >> S_FW_RDEV_WR_ORG_PROC_ASSOC) & M_FW_RDEV_WR_ORG_PROC_ASSOC) 3448 #define F_FW_RDEV_WR_ORG_PROC_ASSOC V_FW_RDEV_WR_ORG_PROC_ASSOC(1U) 3449 3450 #define S_FW_RDEV_WR_RSP_PROC_ASSOC 6 3451 #define M_FW_RDEV_WR_RSP_PROC_ASSOC 0x1 3452 #define V_FW_RDEV_WR_RSP_PROC_ASSOC(x) ((x) << S_FW_RDEV_WR_RSP_PROC_ASSOC) 3453 #define G_FW_RDEV_WR_RSP_PROC_ASSOC(x) \ 3454 (((x) >> S_FW_RDEV_WR_RSP_PROC_ASSOC) & M_FW_RDEV_WR_RSP_PROC_ASSOC) 3455 #define F_FW_RDEV_WR_RSP_PROC_ASSOC V_FW_RDEV_WR_RSP_PROC_ASSOC(1U) 3456 3457 #define S_FW_RDEV_WR_IMAGE_PAIR 5 3458 #define M_FW_RDEV_WR_IMAGE_PAIR 0x1 3459 #define V_FW_RDEV_WR_IMAGE_PAIR(x) ((x) << S_FW_RDEV_WR_IMAGE_PAIR) 3460 #define G_FW_RDEV_WR_IMAGE_PAIR(x) \ 3461 (((x) >> S_FW_RDEV_WR_IMAGE_PAIR) & M_FW_RDEV_WR_IMAGE_PAIR) 3462 #define F_FW_RDEV_WR_IMAGE_PAIR V_FW_RDEV_WR_IMAGE_PAIR(1U) 3463 3464 #define S_FW_RDEV_WR_ACC_RSP_CODE 0 3465 #define M_FW_RDEV_WR_ACC_RSP_CODE 0x1f 3466 #define V_FW_RDEV_WR_ACC_RSP_CODE(x) ((x) << S_FW_RDEV_WR_ACC_RSP_CODE) 3467 #define G_FW_RDEV_WR_ACC_RSP_CODE(x) \ 3468 (((x) >> S_FW_RDEV_WR_ACC_RSP_CODE) & M_FW_RDEV_WR_ACC_RSP_CODE) 3469 3470 #define S_FW_RDEV_WR_ENH_DISC 7 3471 #define M_FW_RDEV_WR_ENH_DISC 0x1 3472 #define V_FW_RDEV_WR_ENH_DISC(x) ((x) << S_FW_RDEV_WR_ENH_DISC) 3473 #define G_FW_RDEV_WR_ENH_DISC(x) \ 3474 (((x) >> S_FW_RDEV_WR_ENH_DISC) & M_FW_RDEV_WR_ENH_DISC) 3475 #define F_FW_RDEV_WR_ENH_DISC V_FW_RDEV_WR_ENH_DISC(1U) 3476 3477 #define S_FW_RDEV_WR_REC 6 3478 #define M_FW_RDEV_WR_REC 0x1 3479 #define V_FW_RDEV_WR_REC(x) ((x) << S_FW_RDEV_WR_REC) 3480 #define G_FW_RDEV_WR_REC(x) (((x) >> S_FW_RDEV_WR_REC) & M_FW_RDEV_WR_REC) 3481 #define F_FW_RDEV_WR_REC V_FW_RDEV_WR_REC(1U) 3482 3483 #define S_FW_RDEV_WR_TASK_RETRY_ID 5 3484 #define M_FW_RDEV_WR_TASK_RETRY_ID 0x1 3485 #define V_FW_RDEV_WR_TASK_RETRY_ID(x) ((x) << S_FW_RDEV_WR_TASK_RETRY_ID) 3486 #define G_FW_RDEV_WR_TASK_RETRY_ID(x) \ 3487 (((x) >> S_FW_RDEV_WR_TASK_RETRY_ID) & M_FW_RDEV_WR_TASK_RETRY_ID) 3488 #define F_FW_RDEV_WR_TASK_RETRY_ID V_FW_RDEV_WR_TASK_RETRY_ID(1U) 3489 3490 #define S_FW_RDEV_WR_RETRY 4 3491 #define M_FW_RDEV_WR_RETRY 0x1 3492 #define V_FW_RDEV_WR_RETRY(x) ((x) << S_FW_RDEV_WR_RETRY) 3493 #define G_FW_RDEV_WR_RETRY(x) \ 3494 (((x) >> S_FW_RDEV_WR_RETRY) & M_FW_RDEV_WR_RETRY) 3495 #define F_FW_RDEV_WR_RETRY V_FW_RDEV_WR_RETRY(1U) 3496 3497 #define S_FW_RDEV_WR_CONF_CMPL 3 3498 #define M_FW_RDEV_WR_CONF_CMPL 0x1 3499 #define V_FW_RDEV_WR_CONF_CMPL(x) ((x) << S_FW_RDEV_WR_CONF_CMPL) 3500 #define G_FW_RDEV_WR_CONF_CMPL(x) \ 3501 (((x) >> S_FW_RDEV_WR_CONF_CMPL) & M_FW_RDEV_WR_CONF_CMPL) 3502 #define F_FW_RDEV_WR_CONF_CMPL V_FW_RDEV_WR_CONF_CMPL(1U) 3503 3504 #define S_FW_RDEV_WR_DATA_OVLY 2 3505 #define M_FW_RDEV_WR_DATA_OVLY 0x1 3506 #define V_FW_RDEV_WR_DATA_OVLY(x) ((x) << S_FW_RDEV_WR_DATA_OVLY) 3507 #define G_FW_RDEV_WR_DATA_OVLY(x) \ 3508 (((x) >> S_FW_RDEV_WR_DATA_OVLY) & M_FW_RDEV_WR_DATA_OVLY) 3509 #define F_FW_RDEV_WR_DATA_OVLY V_FW_RDEV_WR_DATA_OVLY(1U) 3510 3511 #define S_FW_RDEV_WR_INI 1 3512 #define M_FW_RDEV_WR_INI 0x1 3513 #define V_FW_RDEV_WR_INI(x) ((x) << S_FW_RDEV_WR_INI) 3514 #define G_FW_RDEV_WR_INI(x) (((x) >> S_FW_RDEV_WR_INI) & M_FW_RDEV_WR_INI) 3515 #define F_FW_RDEV_WR_INI V_FW_RDEV_WR_INI(1U) 3516 3517 #define S_FW_RDEV_WR_TGT 0 3518 #define M_FW_RDEV_WR_TGT 0x1 3519 #define V_FW_RDEV_WR_TGT(x) ((x) << S_FW_RDEV_WR_TGT) 3520 #define G_FW_RDEV_WR_TGT(x) (((x) >> S_FW_RDEV_WR_TGT) & M_FW_RDEV_WR_TGT) 3521 #define F_FW_RDEV_WR_TGT V_FW_RDEV_WR_TGT(1U) 3522 3523 struct fw_foiscsi_node_wr { 3524 __be32 op_to_immdlen; 3525 __be32 no_sess_recv_to_len16; 3526 __u64 cookie; 3527 __u8 subop; 3528 __u8 status; 3529 __u8 alias_len; 3530 __u8 iqn_len; 3531 __be32 node_flowid; 3532 __be16 nodeid; 3533 __be16 login_retry; 3534 __be16 retry_timeout; 3535 __be16 r3; 3536 __u8 iqn[224]; 3537 __u8 alias[224]; 3538 __be32 isid_tval_to_isid_cval; 3539 }; 3540 3541 #define S_FW_FOISCSI_NODE_WR_IMMDLEN 0 3542 #define M_FW_FOISCSI_NODE_WR_IMMDLEN 0xffff 3543 #define V_FW_FOISCSI_NODE_WR_IMMDLEN(x) ((x) << S_FW_FOISCSI_NODE_WR_IMMDLEN) 3544 #define G_FW_FOISCSI_NODE_WR_IMMDLEN(x) \ 3545 (((x) >> S_FW_FOISCSI_NODE_WR_IMMDLEN) & M_FW_FOISCSI_NODE_WR_IMMDLEN) 3546 3547 #define S_FW_FOISCSI_NODE_WR_NO_SESS_RECV 28 3548 #define M_FW_FOISCSI_NODE_WR_NO_SESS_RECV 0x1 3549 #define V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 3550 ((x) << S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 3551 #define G_FW_FOISCSI_NODE_WR_NO_SESS_RECV(x) \ 3552 (((x) >> S_FW_FOISCSI_NODE_WR_NO_SESS_RECV) & \ 3553 M_FW_FOISCSI_NODE_WR_NO_SESS_RECV) 3554 #define F_FW_FOISCSI_NODE_WR_NO_SESS_RECV \ 3555 V_FW_FOISCSI_NODE_WR_NO_SESS_RECV(1U) 3556 3557 #define S_FW_FOISCSI_NODE_WR_ISID_TVAL 30 3558 #define M_FW_FOISCSI_NODE_WR_ISID_TVAL 0x3 3559 #define V_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 3560 ((x) << S_FW_FOISCSI_NODE_WR_ISID_TVAL) 3561 #define G_FW_FOISCSI_NODE_WR_ISID_TVAL(x) \ 3562 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_TVAL) & M_FW_FOISCSI_NODE_WR_ISID_TVAL) 3563 3564 #define S_FW_FOISCSI_NODE_WR_ISID_AVAL 24 3565 #define M_FW_FOISCSI_NODE_WR_ISID_AVAL 0x3f 3566 #define V_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 3567 ((x) << S_FW_FOISCSI_NODE_WR_ISID_AVAL) 3568 #define G_FW_FOISCSI_NODE_WR_ISID_AVAL(x) \ 3569 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_AVAL) & M_FW_FOISCSI_NODE_WR_ISID_AVAL) 3570 3571 #define S_FW_FOISCSI_NODE_WR_ISID_BVAL 8 3572 #define M_FW_FOISCSI_NODE_WR_ISID_BVAL 0xffff 3573 #define V_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 3574 ((x) << S_FW_FOISCSI_NODE_WR_ISID_BVAL) 3575 #define G_FW_FOISCSI_NODE_WR_ISID_BVAL(x) \ 3576 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_BVAL) & M_FW_FOISCSI_NODE_WR_ISID_BVAL) 3577 3578 #define S_FW_FOISCSI_NODE_WR_ISID_CVAL 0 3579 #define M_FW_FOISCSI_NODE_WR_ISID_CVAL 0xff 3580 #define V_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 3581 ((x) << S_FW_FOISCSI_NODE_WR_ISID_CVAL) 3582 #define G_FW_FOISCSI_NODE_WR_ISID_CVAL(x) \ 3583 (((x) >> S_FW_FOISCSI_NODE_WR_ISID_CVAL) & M_FW_FOISCSI_NODE_WR_ISID_CVAL) 3584 3585 struct fw_foiscsi_ctrl_wr { 3586 __be32 op_to_no_fin; 3587 __be32 flowid_len16; 3588 __u64 cookie; 3589 __u8 subop; 3590 __u8 status; 3591 __u8 ctrl_state; 3592 __u8 io_state; 3593 __be32 node_id; 3594 __be32 ctrl_id; 3595 __be32 io_id; 3596 struct fw_foiscsi_sess_attr { 3597 __be32 sess_type_to_erl; 3598 __be16 max_conn; 3599 __be16 max_r2t; 3600 __be16 time2wait; 3601 __be16 time2retain; 3602 __be32 max_burst; 3603 __be32 first_burst; 3604 __be32 r1; 3605 } sess_attr; 3606 struct fw_foiscsi_conn_attr { 3607 __be32 hdigest_to_tcp_ws_en; 3608 __be32 max_rcv_dsl; 3609 __be32 ping_tmo; 3610 __be16 dst_port; 3611 __be16 src_port; 3612 union fw_foiscsi_conn_attr_addr { 3613 struct fw_foiscsi_conn_attr_ipv6 { 3614 __be64 dst_addr[2]; 3615 __be64 src_addr[2]; 3616 } ipv6_addr; 3617 struct fw_foiscsi_conn_attr_ipv4 { 3618 __be32 dst_addr; 3619 __be32 src_addr; 3620 } ipv4_addr; 3621 } u; 3622 } conn_attr; 3623 __u8 tgt_name_len; 3624 __u8 r3[7]; 3625 __u8 tgt_name[FW_FOISCSI_NAME_MAX_LEN]; 3626 }; 3627 3628 #define S_FW_FOISCSI_CTRL_WR_PORTID 1 3629 #define M_FW_FOISCSI_CTRL_WR_PORTID 0x7 3630 #define V_FW_FOISCSI_CTRL_WR_PORTID(x) ((x) << S_FW_FOISCSI_CTRL_WR_PORTID) 3631 #define G_FW_FOISCSI_CTRL_WR_PORTID(x) \ 3632 (((x) >> S_FW_FOISCSI_CTRL_WR_PORTID) & M_FW_FOISCSI_CTRL_WR_PORTID) 3633 3634 #define S_FW_FOISCSI_CTRL_WR_NO_FIN 0 3635 #define M_FW_FOISCSI_CTRL_WR_NO_FIN 0x1 3636 #define V_FW_FOISCSI_CTRL_WR_NO_FIN(x) ((x) << S_FW_FOISCSI_CTRL_WR_NO_FIN) 3637 #define G_FW_FOISCSI_CTRL_WR_NO_FIN(x) \ 3638 (((x) >> S_FW_FOISCSI_CTRL_WR_NO_FIN) & M_FW_FOISCSI_CTRL_WR_NO_FIN) 3639 #define F_FW_FOISCSI_CTRL_WR_NO_FIN V_FW_FOISCSI_CTRL_WR_NO_FIN(1U) 3640 3641 #define S_FW_FOISCSI_CTRL_WR_SESS_TYPE 30 3642 #define M_FW_FOISCSI_CTRL_WR_SESS_TYPE 0x3 3643 #define V_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 3644 ((x) << S_FW_FOISCSI_CTRL_WR_SESS_TYPE) 3645 #define G_FW_FOISCSI_CTRL_WR_SESS_TYPE(x) \ 3646 (((x) >> S_FW_FOISCSI_CTRL_WR_SESS_TYPE) & M_FW_FOISCSI_CTRL_WR_SESS_TYPE) 3647 3648 #define S_FW_FOISCSI_CTRL_WR_SEQ_INORDER 29 3649 #define M_FW_FOISCSI_CTRL_WR_SEQ_INORDER 0x1 3650 #define V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 3651 ((x) << S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 3652 #define G_FW_FOISCSI_CTRL_WR_SEQ_INORDER(x) \ 3653 (((x) >> S_FW_FOISCSI_CTRL_WR_SEQ_INORDER) & \ 3654 M_FW_FOISCSI_CTRL_WR_SEQ_INORDER) 3655 #define F_FW_FOISCSI_CTRL_WR_SEQ_INORDER \ 3656 V_FW_FOISCSI_CTRL_WR_SEQ_INORDER(1U) 3657 3658 #define S_FW_FOISCSI_CTRL_WR_PDU_INORDER 28 3659 #define M_FW_FOISCSI_CTRL_WR_PDU_INORDER 0x1 3660 #define V_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 3661 ((x) << S_FW_FOISCSI_CTRL_WR_PDU_INORDER) 3662 #define G_FW_FOISCSI_CTRL_WR_PDU_INORDER(x) \ 3663 (((x) >> S_FW_FOISCSI_CTRL_WR_PDU_INORDER) & \ 3664 M_FW_FOISCSI_CTRL_WR_PDU_INORDER) 3665 #define F_FW_FOISCSI_CTRL_WR_PDU_INORDER \ 3666 V_FW_FOISCSI_CTRL_WR_PDU_INORDER(1U) 3667 3668 #define S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 27 3669 #define M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN 0x1 3670 #define V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 3671 ((x) << S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 3672 #define G_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(x) \ 3673 (((x) >> S_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) & \ 3674 M_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN) 3675 #define F_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN \ 3676 V_FW_FOISCSI_CTRL_WR_IMMD_DATA_EN(1U) 3677 3678 #define S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 26 3679 #define M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN 0x1 3680 #define V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 3681 ((x) << S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 3682 #define G_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(x) \ 3683 (((x) >> S_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) & \ 3684 M_FW_FOISCSI_CTRL_WR_INIT_R2T_EN) 3685 #define F_FW_FOISCSI_CTRL_WR_INIT_R2T_EN \ 3686 V_FW_FOISCSI_CTRL_WR_INIT_R2T_EN(1U) 3687 3688 #define S_FW_FOISCSI_CTRL_WR_ERL 24 3689 #define M_FW_FOISCSI_CTRL_WR_ERL 0x3 3690 #define V_FW_FOISCSI_CTRL_WR_ERL(x) ((x) << S_FW_FOISCSI_CTRL_WR_ERL) 3691 #define G_FW_FOISCSI_CTRL_WR_ERL(x) \ 3692 (((x) >> S_FW_FOISCSI_CTRL_WR_ERL) & M_FW_FOISCSI_CTRL_WR_ERL) 3693 3694 #define S_FW_FOISCSI_CTRL_WR_HDIGEST 30 3695 #define M_FW_FOISCSI_CTRL_WR_HDIGEST 0x3 3696 #define V_FW_FOISCSI_CTRL_WR_HDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_HDIGEST) 3697 #define G_FW_FOISCSI_CTRL_WR_HDIGEST(x) \ 3698 (((x) >> S_FW_FOISCSI_CTRL_WR_HDIGEST) & M_FW_FOISCSI_CTRL_WR_HDIGEST) 3699 3700 #define S_FW_FOISCSI_CTRL_WR_DDIGEST 28 3701 #define M_FW_FOISCSI_CTRL_WR_DDIGEST 0x3 3702 #define V_FW_FOISCSI_CTRL_WR_DDIGEST(x) ((x) << S_FW_FOISCSI_CTRL_WR_DDIGEST) 3703 #define G_FW_FOISCSI_CTRL_WR_DDIGEST(x) \ 3704 (((x) >> S_FW_FOISCSI_CTRL_WR_DDIGEST) & M_FW_FOISCSI_CTRL_WR_DDIGEST) 3705 3706 #define S_FW_FOISCSI_CTRL_WR_AUTH_METHOD 25 3707 #define M_FW_FOISCSI_CTRL_WR_AUTH_METHOD 0x7 3708 #define V_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 3709 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 3710 #define G_FW_FOISCSI_CTRL_WR_AUTH_METHOD(x) \ 3711 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_METHOD) & \ 3712 M_FW_FOISCSI_CTRL_WR_AUTH_METHOD) 3713 3714 #define S_FW_FOISCSI_CTRL_WR_AUTH_POLICY 23 3715 #define M_FW_FOISCSI_CTRL_WR_AUTH_POLICY 0x3 3716 #define V_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 3717 ((x) << S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 3718 #define G_FW_FOISCSI_CTRL_WR_AUTH_POLICY(x) \ 3719 (((x) >> S_FW_FOISCSI_CTRL_WR_AUTH_POLICY) & \ 3720 M_FW_FOISCSI_CTRL_WR_AUTH_POLICY) 3721 3722 #define S_FW_FOISCSI_CTRL_WR_DDP_PGSZ 21 3723 #define M_FW_FOISCSI_CTRL_WR_DDP_PGSZ 0x3 3724 #define V_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 3725 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 3726 #define G_FW_FOISCSI_CTRL_WR_DDP_PGSZ(x) \ 3727 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGSZ) & M_FW_FOISCSI_CTRL_WR_DDP_PGSZ) 3728 3729 #define S_FW_FOISCSI_CTRL_WR_IPV6 20 3730 #define M_FW_FOISCSI_CTRL_WR_IPV6 0x1 3731 #define V_FW_FOISCSI_CTRL_WR_IPV6(x) ((x) << S_FW_FOISCSI_CTRL_WR_IPV6) 3732 #define G_FW_FOISCSI_CTRL_WR_IPV6(x) \ 3733 (((x) >> S_FW_FOISCSI_CTRL_WR_IPV6) & M_FW_FOISCSI_CTRL_WR_IPV6) 3734 #define F_FW_FOISCSI_CTRL_WR_IPV6 V_FW_FOISCSI_CTRL_WR_IPV6(1U) 3735 3736 #define S_FW_FOISCSI_CTRL_WR_DDP_PGIDX 16 3737 #define M_FW_FOISCSI_CTRL_WR_DDP_PGIDX 0xf 3738 #define V_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 3739 ((x) << S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 3740 #define G_FW_FOISCSI_CTRL_WR_DDP_PGIDX(x) \ 3741 (((x) >> S_FW_FOISCSI_CTRL_WR_DDP_PGIDX) & M_FW_FOISCSI_CTRL_WR_DDP_PGIDX) 3742 3743 #define S_FW_FOISCSI_CTRL_WR_TCP_WS 12 3744 #define M_FW_FOISCSI_CTRL_WR_TCP_WS 0xf 3745 #define V_FW_FOISCSI_CTRL_WR_TCP_WS(x) ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS) 3746 #define G_FW_FOISCSI_CTRL_WR_TCP_WS(x) \ 3747 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS) & M_FW_FOISCSI_CTRL_WR_TCP_WS) 3748 3749 #define S_FW_FOISCSI_CTRL_WR_TCP_WS_EN 11 3750 #define M_FW_FOISCSI_CTRL_WR_TCP_WS_EN 0x1 3751 #define V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 3752 ((x) << S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 3753 #define G_FW_FOISCSI_CTRL_WR_TCP_WS_EN(x) \ 3754 (((x) >> S_FW_FOISCSI_CTRL_WR_TCP_WS_EN) & M_FW_FOISCSI_CTRL_WR_TCP_WS_EN) 3755 #define F_FW_FOISCSI_CTRL_WR_TCP_WS_EN V_FW_FOISCSI_CTRL_WR_TCP_WS_EN(1U) 3756 3757 struct fw_foiscsi_chap_wr { 3758 __be32 op_to_kv_flag; 3759 __be32 flowid_len16; 3760 __u64 cookie; 3761 __u8 status; 3762 union fw_foiscsi_len { 3763 struct fw_foiscsi_chap_lens { 3764 __u8 id_len; 3765 __u8 sec_len; 3766 } chapl; 3767 struct fw_foiscsi_vend_kv_lens { 3768 __u8 key_len; 3769 __u8 val_len; 3770 } vend_kvl; 3771 } lenu; 3772 __u8 node_type; 3773 __be16 node_id; 3774 __u8 r3[2]; 3775 union fw_foiscsi_chap_vend { 3776 struct fw_foiscsi_chap { 3777 __u8 chap_id[224]; 3778 __u8 chap_sec[128]; 3779 } chap; 3780 struct fw_foiscsi_vend_kv { 3781 __u8 vend_key[64]; 3782 __u8 vend_val[256]; 3783 } vend_kv; 3784 } u; 3785 }; 3786 3787 #define S_FW_FOISCSI_CHAP_WR_KV_FLAG 20 3788 #define M_FW_FOISCSI_CHAP_WR_KV_FLAG 0x1 3789 #define V_FW_FOISCSI_CHAP_WR_KV_FLAG(x) ((x) << S_FW_FOISCSI_CHAP_WR_KV_FLAG) 3790 #define G_FW_FOISCSI_CHAP_WR_KV_FLAG(x) \ 3791 (((x) >> S_FW_FOISCSI_CHAP_WR_KV_FLAG) & M_FW_FOISCSI_CHAP_WR_KV_FLAG) 3792 #define F_FW_FOISCSI_CHAP_WR_KV_FLAG V_FW_FOISCSI_CHAP_WR_KV_FLAG(1U) 3793 3794 /****************************************************************************** 3795 * C O i S C S I W O R K R E Q U E S T S 3796 ********************************************/ 3797 3798 enum fw_chnet_addr_type { 3799 FW_CHNET_ADDD_TYPE_NONE = 0, 3800 FW_CHNET_ADDR_TYPE_IPV4, 3801 FW_CHNET_ADDR_TYPE_IPV6, 3802 }; 3803 3804 enum fw_msg_wr_type { 3805 FW_MSG_WR_TYPE_RPL = 0, 3806 FW_MSG_WR_TYPE_ERR, 3807 FW_MSG_WR_TYPE_PLD, 3808 }; 3809 3810 struct fw_coiscsi_tgt_wr { 3811 __be32 op_compl; 3812 __be32 flowid_len16; 3813 __u64 cookie; 3814 __u8 subop; 3815 __u8 status; 3816 __be16 r4; 3817 __be32 flags; 3818 struct fw_coiscsi_tgt_conn_attr { 3819 __be32 in_tid; 3820 __be16 in_port; 3821 __u8 in_type; 3822 __u8 r6; 3823 union fw_coiscsi_tgt_conn_attr_addr { 3824 struct fw_coiscsi_tgt_conn_attr_in_addr { 3825 __be32 addr; 3826 __be32 r7; 3827 __be32 r8[2]; 3828 } in_addr; 3829 struct fw_coiscsi_tgt_conn_attr_in_addr6 { 3830 __be64 addr[2]; 3831 } in_addr6; 3832 } u; 3833 } conn_attr; 3834 }; 3835 3836 #define S_FW_COISCSI_TGT_WR_PORTID 0 3837 #define M_FW_COISCSI_TGT_WR_PORTID 0x7 3838 #define V_FW_COISCSI_TGT_WR_PORTID(x) ((x) << S_FW_COISCSI_TGT_WR_PORTID) 3839 #define G_FW_COISCSI_TGT_WR_PORTID(x) \ 3840 (((x) >> S_FW_COISCSI_TGT_WR_PORTID) & M_FW_COISCSI_TGT_WR_PORTID) 3841 3842 struct fw_coiscsi_tgt_conn_wr { 3843 __be32 op_compl; 3844 __be32 flowid_len16; 3845 __u64 cookie; 3846 __u8 subop; 3847 __u8 status; 3848 __be16 iq_id; 3849 __be32 in_stid; 3850 __be32 io_id; 3851 __be32 flags_fin; 3852 union { 3853 struct fw_coiscsi_tgt_conn_tcp { 3854 __be16 in_sport; 3855 __be16 in_dport; 3856 __u8 wscale_wsen; 3857 __u8 r4[3]; 3858 union fw_coiscsi_tgt_conn_tcp_addr { 3859 struct fw_coiscsi_tgt_conn_tcp_in_addr { 3860 __be32 saddr; 3861 __be32 daddr; 3862 } in_addr; 3863 struct fw_coiscsi_tgt_conn_tcp_in_addr6 { 3864 __be64 saddr[2]; 3865 __be64 daddr[2]; 3866 } in_addr6; 3867 } u; 3868 } conn_tcp; 3869 struct fw_coiscsi_tgt_conn_stats { 3870 __be32 ddp_reqs; 3871 __be32 ddp_cmpls; 3872 __be16 ddp_aborts; 3873 __be16 ddp_bps; 3874 } stats; 3875 } u; 3876 struct fw_coiscsi_tgt_conn_iscsi { 3877 __be32 hdigest_to_ddp_pgsz; 3878 __be32 tgt_id; 3879 __be16 max_r2t; 3880 __be16 r5; 3881 __be32 max_burst; 3882 __be32 max_rdsl; 3883 __be32 max_tdsl; 3884 __be32 cur_sn; 3885 __be32 r6; 3886 } conn_iscsi; 3887 }; 3888 3889 #define S_FW_COISCSI_TGT_CONN_WR_PORTID 0 3890 #define M_FW_COISCSI_TGT_CONN_WR_PORTID 0x7 3891 #define V_FW_COISCSI_TGT_CONN_WR_PORTID(x) \ 3892 ((x) << S_FW_COISCSI_TGT_CONN_WR_PORTID) 3893 #define G_FW_COISCSI_TGT_CONN_WR_PORTID(x) \ 3894 (((x) >> S_FW_COISCSI_TGT_CONN_WR_PORTID) & \ 3895 M_FW_COISCSI_TGT_CONN_WR_PORTID) 3896 3897 #define S_FW_COISCSI_TGT_CONN_WR_FIN 0 3898 #define M_FW_COISCSI_TGT_CONN_WR_FIN 0x1 3899 #define V_FW_COISCSI_TGT_CONN_WR_FIN(x) ((x) << S_FW_COISCSI_TGT_CONN_WR_FIN) 3900 #define G_FW_COISCSI_TGT_CONN_WR_FIN(x) \ 3901 (((x) >> S_FW_COISCSI_TGT_CONN_WR_FIN) & M_FW_COISCSI_TGT_CONN_WR_FIN) 3902 #define F_FW_COISCSI_TGT_CONN_WR_FIN V_FW_COISCSI_TGT_CONN_WR_FIN(1U) 3903 3904 #define S_FW_COISCSI_TGT_CONN_WR_WSCALE 1 3905 #define M_FW_COISCSI_TGT_CONN_WR_WSCALE 0xf 3906 #define V_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 3907 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSCALE) 3908 #define G_FW_COISCSI_TGT_CONN_WR_WSCALE(x) \ 3909 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSCALE) & \ 3910 M_FW_COISCSI_TGT_CONN_WR_WSCALE) 3911 3912 #define S_FW_COISCSI_TGT_CONN_WR_WSEN 0 3913 #define M_FW_COISCSI_TGT_CONN_WR_WSEN 0x1 3914 #define V_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 3915 ((x) << S_FW_COISCSI_TGT_CONN_WR_WSEN) 3916 #define G_FW_COISCSI_TGT_CONN_WR_WSEN(x) \ 3917 (((x) >> S_FW_COISCSI_TGT_CONN_WR_WSEN) & M_FW_COISCSI_TGT_CONN_WR_WSEN) 3918 #define F_FW_COISCSI_TGT_CONN_WR_WSEN V_FW_COISCSI_TGT_CONN_WR_WSEN(1U) 3919 3920 struct fw_coiscsi_tgt_xmit_wr { 3921 __be32 op_to_immdlen; 3922 union { 3923 struct cmpl_stat { 3924 __be32 cmpl_status_pkd; 3925 } cs; 3926 struct flowid_len { 3927 __be32 flowid_len16; 3928 } fllen; 3929 } u; 3930 __u64 cookie; 3931 __be16 iq_id; 3932 __be16 r3; 3933 __be32 pz_off; 3934 __be32 t_xfer_len; 3935 union { 3936 __be32 tag; 3937 __be32 datasn; 3938 __be32 ddp_status; 3939 } cu; 3940 }; 3941 3942 #define S_FW_COISCSI_TGT_XMIT_WR_DDGST 23 3943 #define M_FW_COISCSI_TGT_XMIT_WR_DDGST 0x1 3944 #define V_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 3945 ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDGST) 3946 #define G_FW_COISCSI_TGT_XMIT_WR_DDGST(x) \ 3947 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDGST) & M_FW_COISCSI_TGT_XMIT_WR_DDGST) 3948 #define F_FW_COISCSI_TGT_XMIT_WR_DDGST V_FW_COISCSI_TGT_XMIT_WR_DDGST(1U) 3949 3950 #define S_FW_COISCSI_TGT_XMIT_WR_HDGST 22 3951 #define M_FW_COISCSI_TGT_XMIT_WR_HDGST 0x1 3952 #define V_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 3953 ((x) << S_FW_COISCSI_TGT_XMIT_WR_HDGST) 3954 #define G_FW_COISCSI_TGT_XMIT_WR_HDGST(x) \ 3955 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_HDGST) & M_FW_COISCSI_TGT_XMIT_WR_HDGST) 3956 #define F_FW_COISCSI_TGT_XMIT_WR_HDGST V_FW_COISCSI_TGT_XMIT_WR_HDGST(1U) 3957 3958 #define S_FW_COISCSI_TGT_XMIT_WR_DDP 20 3959 #define M_FW_COISCSI_TGT_XMIT_WR_DDP 0x1 3960 #define V_FW_COISCSI_TGT_XMIT_WR_DDP(x) ((x) << S_FW_COISCSI_TGT_XMIT_WR_DDP) 3961 #define G_FW_COISCSI_TGT_XMIT_WR_DDP(x) \ 3962 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_DDP) & M_FW_COISCSI_TGT_XMIT_WR_DDP) 3963 #define F_FW_COISCSI_TGT_XMIT_WR_DDP V_FW_COISCSI_TGT_XMIT_WR_DDP(1U) 3964 3965 #define S_FW_COISCSI_TGT_XMIT_WR_ABORT 19 3966 #define M_FW_COISCSI_TGT_XMIT_WR_ABORT 0x1 3967 #define V_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 3968 ((x) << S_FW_COISCSI_TGT_XMIT_WR_ABORT) 3969 #define G_FW_COISCSI_TGT_XMIT_WR_ABORT(x) \ 3970 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_ABORT) & M_FW_COISCSI_TGT_XMIT_WR_ABORT) 3971 #define F_FW_COISCSI_TGT_XMIT_WR_ABORT V_FW_COISCSI_TGT_XMIT_WR_ABORT(1U) 3972 3973 #define S_FW_COISCSI_TGT_XMIT_WR_FINAL 18 3974 #define M_FW_COISCSI_TGT_XMIT_WR_FINAL 0x1 3975 #define V_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 3976 ((x) << S_FW_COISCSI_TGT_XMIT_WR_FINAL) 3977 #define G_FW_COISCSI_TGT_XMIT_WR_FINAL(x) \ 3978 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_FINAL) & M_FW_COISCSI_TGT_XMIT_WR_FINAL) 3979 #define F_FW_COISCSI_TGT_XMIT_WR_FINAL V_FW_COISCSI_TGT_XMIT_WR_FINAL(1U) 3980 3981 #define S_FW_COISCSI_TGT_XMIT_WR_PADLEN 16 3982 #define M_FW_COISCSI_TGT_XMIT_WR_PADLEN 0x3 3983 #define V_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 3984 ((x) << S_FW_COISCSI_TGT_XMIT_WR_PADLEN) 3985 #define G_FW_COISCSI_TGT_XMIT_WR_PADLEN(x) \ 3986 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_PADLEN) & \ 3987 M_FW_COISCSI_TGT_XMIT_WR_PADLEN) 3988 3989 #define S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 15 3990 #define M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN 0x1 3991 #define V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 3992 ((x) << S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 3993 #define G_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(x) \ 3994 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) & \ 3995 M_FW_COISCSI_TGT_XMIT_WR_INCSTATSN) 3996 #define F_FW_COISCSI_TGT_XMIT_WR_INCSTATSN \ 3997 V_FW_COISCSI_TGT_XMIT_WR_INCSTATSN(1U) 3998 3999 #define S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0 4000 #define M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN 0xff 4001 #define V_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 4002 ((x) << S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 4003 #define G_FW_COISCSI_TGT_XMIT_WR_IMMDLEN(x) \ 4004 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) & \ 4005 M_FW_COISCSI_TGT_XMIT_WR_IMMDLEN) 4006 4007 #define S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 8 4008 #define M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS 0xff 4009 #define V_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 4010 ((x) << S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 4011 #define G_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS(x) \ 4012 (((x) >> S_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) & \ 4013 M_FW_COISCSI_TGT_XMIT_WR_CMPL_STATUS) 4014 4015 struct fw_coiscsi_stats_wr { 4016 __be32 op_compl; 4017 __be32 flowid_len16; 4018 __u64 cookie; 4019 __u8 subop; 4020 __u8 status; 4021 union fw_coiscsi_stats { 4022 struct fw_coiscsi_resource { 4023 __u8 num_ipv4_tgt; 4024 __u8 num_ipv6_tgt; 4025 __be16 num_l2t_entries; 4026 __be16 num_csocks; 4027 __be16 num_tasks; 4028 __be16 num_ppods_zone[11]; 4029 __be32 num_bufll64; 4030 __u8 r2[12]; 4031 } rsrc; 4032 } u; 4033 }; 4034 4035 #define S_FW_COISCSI_STATS_WR_PORTID 0 4036 #define M_FW_COISCSI_STATS_WR_PORTID 0x7 4037 #define V_FW_COISCSI_STATS_WR_PORTID(x) ((x) << S_FW_COISCSI_STATS_WR_PORTID) 4038 #define G_FW_COISCSI_STATS_WR_PORTID(x) \ 4039 (((x) >> S_FW_COISCSI_STATS_WR_PORTID) & M_FW_COISCSI_STATS_WR_PORTID) 4040 4041 struct fw_isns_wr { 4042 __be32 op_compl; 4043 __be32 flowid_len16; 4044 __u64 cookie; 4045 __u8 subop; 4046 __u8 status; 4047 __be16 iq_id; 4048 __be16 vlanid; 4049 __be16 r4; 4050 struct fw_tcp_conn_attr { 4051 __be32 in_tid; 4052 __be16 in_port; 4053 __u8 in_type; 4054 __u8 r6; 4055 union fw_tcp_conn_attr_addr { 4056 struct fw_tcp_conn_attr_in_addr { 4057 __be32 addr; 4058 __be32 r7; 4059 __be32 r8[2]; 4060 } in_addr; 4061 struct fw_tcp_conn_attr_in_addr6 { 4062 __be64 addr[2]; 4063 } in_addr6; 4064 } u; 4065 } conn_attr; 4066 }; 4067 4068 #define S_FW_ISNS_WR_PORTID 0 4069 #define M_FW_ISNS_WR_PORTID 0x7 4070 #define V_FW_ISNS_WR_PORTID(x) ((x) << S_FW_ISNS_WR_PORTID) 4071 #define G_FW_ISNS_WR_PORTID(x) \ 4072 (((x) >> S_FW_ISNS_WR_PORTID) & M_FW_ISNS_WR_PORTID) 4073 4074 struct fw_isns_xmit_wr { 4075 __be32 op_to_immdlen; 4076 __be32 flowid_len16; 4077 __u64 cookie; 4078 __be16 iq_id; 4079 __be16 r4; 4080 __be32 xfer_len; 4081 __be64 r5; 4082 }; 4083 4084 #define S_FW_ISNS_XMIT_WR_IMMDLEN 0 4085 #define M_FW_ISNS_XMIT_WR_IMMDLEN 0xff 4086 #define V_FW_ISNS_XMIT_WR_IMMDLEN(x) ((x) << S_FW_ISNS_XMIT_WR_IMMDLEN) 4087 #define G_FW_ISNS_XMIT_WR_IMMDLEN(x) \ 4088 (((x) >> S_FW_ISNS_XMIT_WR_IMMDLEN) & M_FW_ISNS_XMIT_WR_IMMDLEN) 4089 4090 /****************************************************************************** 4091 * F O F C O E W O R K R E Q U E S T s 4092 *******************************************/ 4093 4094 struct fw_fcoe_els_ct_wr { 4095 __be32 op_immdlen; 4096 __be32 flowid_len16; 4097 __be64 cookie; 4098 __be16 iqid; 4099 __u8 tmo_val; 4100 __u8 els_ct_type; 4101 __u8 ctl_pri; 4102 __u8 cp_en_class; 4103 __be16 xfer_cnt; 4104 __u8 fl_to_sp; 4105 __u8 l_id[3]; 4106 __u8 r5; 4107 __u8 r_id[3]; 4108 __be64 rsp_dmaaddr; 4109 __be32 rsp_dmalen; 4110 __be32 r6; 4111 }; 4112 4113 #define S_FW_FCOE_ELS_CT_WR_OPCODE 24 4114 #define M_FW_FCOE_ELS_CT_WR_OPCODE 0xff 4115 #define V_FW_FCOE_ELS_CT_WR_OPCODE(x) ((x) << S_FW_FCOE_ELS_CT_WR_OPCODE) 4116 #define G_FW_FCOE_ELS_CT_WR_OPCODE(x) \ 4117 (((x) >> S_FW_FCOE_ELS_CT_WR_OPCODE) & M_FW_FCOE_ELS_CT_WR_OPCODE) 4118 4119 #define S_FW_FCOE_ELS_CT_WR_IMMDLEN 0 4120 #define M_FW_FCOE_ELS_CT_WR_IMMDLEN 0xff 4121 #define V_FW_FCOE_ELS_CT_WR_IMMDLEN(x) ((x) << S_FW_FCOE_ELS_CT_WR_IMMDLEN) 4122 #define G_FW_FCOE_ELS_CT_WR_IMMDLEN(x) \ 4123 (((x) >> S_FW_FCOE_ELS_CT_WR_IMMDLEN) & M_FW_FCOE_ELS_CT_WR_IMMDLEN) 4124 4125 #define S_FW_FCOE_ELS_CT_WR_FLOWID 8 4126 #define M_FW_FCOE_ELS_CT_WR_FLOWID 0xfffff 4127 #define V_FW_FCOE_ELS_CT_WR_FLOWID(x) ((x) << S_FW_FCOE_ELS_CT_WR_FLOWID) 4128 #define G_FW_FCOE_ELS_CT_WR_FLOWID(x) \ 4129 (((x) >> S_FW_FCOE_ELS_CT_WR_FLOWID) & M_FW_FCOE_ELS_CT_WR_FLOWID) 4130 4131 #define S_FW_FCOE_ELS_CT_WR_LEN16 0 4132 #define M_FW_FCOE_ELS_CT_WR_LEN16 0xff 4133 #define V_FW_FCOE_ELS_CT_WR_LEN16(x) ((x) << S_FW_FCOE_ELS_CT_WR_LEN16) 4134 #define G_FW_FCOE_ELS_CT_WR_LEN16(x) \ 4135 (((x) >> S_FW_FCOE_ELS_CT_WR_LEN16) & M_FW_FCOE_ELS_CT_WR_LEN16) 4136 4137 #define S_FW_FCOE_ELS_CT_WR_CP_EN 6 4138 #define M_FW_FCOE_ELS_CT_WR_CP_EN 0x3 4139 #define V_FW_FCOE_ELS_CT_WR_CP_EN(x) ((x) << S_FW_FCOE_ELS_CT_WR_CP_EN) 4140 #define G_FW_FCOE_ELS_CT_WR_CP_EN(x) \ 4141 (((x) >> S_FW_FCOE_ELS_CT_WR_CP_EN) & M_FW_FCOE_ELS_CT_WR_CP_EN) 4142 4143 #define S_FW_FCOE_ELS_CT_WR_CLASS 4 4144 #define M_FW_FCOE_ELS_CT_WR_CLASS 0x3 4145 #define V_FW_FCOE_ELS_CT_WR_CLASS(x) ((x) << S_FW_FCOE_ELS_CT_WR_CLASS) 4146 #define G_FW_FCOE_ELS_CT_WR_CLASS(x) \ 4147 (((x) >> S_FW_FCOE_ELS_CT_WR_CLASS) & M_FW_FCOE_ELS_CT_WR_CLASS) 4148 4149 #define S_FW_FCOE_ELS_CT_WR_FL 2 4150 #define M_FW_FCOE_ELS_CT_WR_FL 0x1 4151 #define V_FW_FCOE_ELS_CT_WR_FL(x) ((x) << S_FW_FCOE_ELS_CT_WR_FL) 4152 #define G_FW_FCOE_ELS_CT_WR_FL(x) \ 4153 (((x) >> S_FW_FCOE_ELS_CT_WR_FL) & M_FW_FCOE_ELS_CT_WR_FL) 4154 #define F_FW_FCOE_ELS_CT_WR_FL V_FW_FCOE_ELS_CT_WR_FL(1U) 4155 4156 #define S_FW_FCOE_ELS_CT_WR_NPIV 1 4157 #define M_FW_FCOE_ELS_CT_WR_NPIV 0x1 4158 #define V_FW_FCOE_ELS_CT_WR_NPIV(x) ((x) << S_FW_FCOE_ELS_CT_WR_NPIV) 4159 #define G_FW_FCOE_ELS_CT_WR_NPIV(x) \ 4160 (((x) >> S_FW_FCOE_ELS_CT_WR_NPIV) & M_FW_FCOE_ELS_CT_WR_NPIV) 4161 #define F_FW_FCOE_ELS_CT_WR_NPIV V_FW_FCOE_ELS_CT_WR_NPIV(1U) 4162 4163 #define S_FW_FCOE_ELS_CT_WR_SP 0 4164 #define M_FW_FCOE_ELS_CT_WR_SP 0x1 4165 #define V_FW_FCOE_ELS_CT_WR_SP(x) ((x) << S_FW_FCOE_ELS_CT_WR_SP) 4166 #define G_FW_FCOE_ELS_CT_WR_SP(x) \ 4167 (((x) >> S_FW_FCOE_ELS_CT_WR_SP) & M_FW_FCOE_ELS_CT_WR_SP) 4168 #define F_FW_FCOE_ELS_CT_WR_SP V_FW_FCOE_ELS_CT_WR_SP(1U) 4169 4170 /****************************************************************************** 4171 * S C S I W O R K R E Q U E S T s (FOiSCSI and FCOE unified data path) 4172 *****************************************************************************/ 4173 4174 struct fw_scsi_write_wr { 4175 __be32 op_immdlen; 4176 __be32 flowid_len16; 4177 __be64 cookie; 4178 __be16 iqid; 4179 __u8 tmo_val; 4180 __u8 use_xfer_cnt; 4181 union fw_scsi_write_priv { 4182 struct fcoe_write_priv { 4183 __u8 ctl_pri; 4184 __u8 cp_en_class; 4185 __u8 r3_lo[2]; 4186 } fcoe; 4187 struct iscsi_write_priv { 4188 __u8 r3[4]; 4189 } iscsi; 4190 } u; 4191 __be32 xfer_cnt; 4192 __be32 ini_xfer_cnt; 4193 __be64 rsp_dmaaddr; 4194 __be32 rsp_dmalen; 4195 __be32 r4; 4196 }; 4197 4198 #define S_FW_SCSI_WRITE_WR_OPCODE 24 4199 #define M_FW_SCSI_WRITE_WR_OPCODE 0xff 4200 #define V_FW_SCSI_WRITE_WR_OPCODE(x) ((x) << S_FW_SCSI_WRITE_WR_OPCODE) 4201 #define G_FW_SCSI_WRITE_WR_OPCODE(x) \ 4202 (((x) >> S_FW_SCSI_WRITE_WR_OPCODE) & M_FW_SCSI_WRITE_WR_OPCODE) 4203 4204 #define S_FW_SCSI_WRITE_WR_IMMDLEN 0 4205 #define M_FW_SCSI_WRITE_WR_IMMDLEN 0xff 4206 #define V_FW_SCSI_WRITE_WR_IMMDLEN(x) ((x) << S_FW_SCSI_WRITE_WR_IMMDLEN) 4207 #define G_FW_SCSI_WRITE_WR_IMMDLEN(x) \ 4208 (((x) >> S_FW_SCSI_WRITE_WR_IMMDLEN) & M_FW_SCSI_WRITE_WR_IMMDLEN) 4209 4210 #define S_FW_SCSI_WRITE_WR_FLOWID 8 4211 #define M_FW_SCSI_WRITE_WR_FLOWID 0xfffff 4212 #define V_FW_SCSI_WRITE_WR_FLOWID(x) ((x) << S_FW_SCSI_WRITE_WR_FLOWID) 4213 #define G_FW_SCSI_WRITE_WR_FLOWID(x) \ 4214 (((x) >> S_FW_SCSI_WRITE_WR_FLOWID) & M_FW_SCSI_WRITE_WR_FLOWID) 4215 4216 #define S_FW_SCSI_WRITE_WR_LEN16 0 4217 #define M_FW_SCSI_WRITE_WR_LEN16 0xff 4218 #define V_FW_SCSI_WRITE_WR_LEN16(x) ((x) << S_FW_SCSI_WRITE_WR_LEN16) 4219 #define G_FW_SCSI_WRITE_WR_LEN16(x) \ 4220 (((x) >> S_FW_SCSI_WRITE_WR_LEN16) & M_FW_SCSI_WRITE_WR_LEN16) 4221 4222 #define S_FW_SCSI_WRITE_WR_CP_EN 6 4223 #define M_FW_SCSI_WRITE_WR_CP_EN 0x3 4224 #define V_FW_SCSI_WRITE_WR_CP_EN(x) ((x) << S_FW_SCSI_WRITE_WR_CP_EN) 4225 #define G_FW_SCSI_WRITE_WR_CP_EN(x) \ 4226 (((x) >> S_FW_SCSI_WRITE_WR_CP_EN) & M_FW_SCSI_WRITE_WR_CP_EN) 4227 4228 #define S_FW_SCSI_WRITE_WR_CLASS 4 4229 #define M_FW_SCSI_WRITE_WR_CLASS 0x3 4230 #define V_FW_SCSI_WRITE_WR_CLASS(x) ((x) << S_FW_SCSI_WRITE_WR_CLASS) 4231 #define G_FW_SCSI_WRITE_WR_CLASS(x) \ 4232 (((x) >> S_FW_SCSI_WRITE_WR_CLASS) & M_FW_SCSI_WRITE_WR_CLASS) 4233 4234 struct fw_scsi_read_wr { 4235 __be32 op_immdlen; 4236 __be32 flowid_len16; 4237 __be64 cookie; 4238 __be16 iqid; 4239 __u8 tmo_val; 4240 __u8 use_xfer_cnt; 4241 union fw_scsi_read_priv { 4242 struct fcoe_read_priv { 4243 __u8 ctl_pri; 4244 __u8 cp_en_class; 4245 __u8 r3_lo[2]; 4246 } fcoe; 4247 struct iscsi_read_priv { 4248 __u8 r3[4]; 4249 } iscsi; 4250 } u; 4251 __be32 xfer_cnt; 4252 __be32 ini_xfer_cnt; 4253 __be64 rsp_dmaaddr; 4254 __be32 rsp_dmalen; 4255 __be32 r4; 4256 }; 4257 4258 #define S_FW_SCSI_READ_WR_OPCODE 24 4259 #define M_FW_SCSI_READ_WR_OPCODE 0xff 4260 #define V_FW_SCSI_READ_WR_OPCODE(x) ((x) << S_FW_SCSI_READ_WR_OPCODE) 4261 #define G_FW_SCSI_READ_WR_OPCODE(x) \ 4262 (((x) >> S_FW_SCSI_READ_WR_OPCODE) & M_FW_SCSI_READ_WR_OPCODE) 4263 4264 #define S_FW_SCSI_READ_WR_IMMDLEN 0 4265 #define M_FW_SCSI_READ_WR_IMMDLEN 0xff 4266 #define V_FW_SCSI_READ_WR_IMMDLEN(x) ((x) << S_FW_SCSI_READ_WR_IMMDLEN) 4267 #define G_FW_SCSI_READ_WR_IMMDLEN(x) \ 4268 (((x) >> S_FW_SCSI_READ_WR_IMMDLEN) & M_FW_SCSI_READ_WR_IMMDLEN) 4269 4270 #define S_FW_SCSI_READ_WR_FLOWID 8 4271 #define M_FW_SCSI_READ_WR_FLOWID 0xfffff 4272 #define V_FW_SCSI_READ_WR_FLOWID(x) ((x) << S_FW_SCSI_READ_WR_FLOWID) 4273 #define G_FW_SCSI_READ_WR_FLOWID(x) \ 4274 (((x) >> S_FW_SCSI_READ_WR_FLOWID) & M_FW_SCSI_READ_WR_FLOWID) 4275 4276 #define S_FW_SCSI_READ_WR_LEN16 0 4277 #define M_FW_SCSI_READ_WR_LEN16 0xff 4278 #define V_FW_SCSI_READ_WR_LEN16(x) ((x) << S_FW_SCSI_READ_WR_LEN16) 4279 #define G_FW_SCSI_READ_WR_LEN16(x) \ 4280 (((x) >> S_FW_SCSI_READ_WR_LEN16) & M_FW_SCSI_READ_WR_LEN16) 4281 4282 #define S_FW_SCSI_READ_WR_CP_EN 6 4283 #define M_FW_SCSI_READ_WR_CP_EN 0x3 4284 #define V_FW_SCSI_READ_WR_CP_EN(x) ((x) << S_FW_SCSI_READ_WR_CP_EN) 4285 #define G_FW_SCSI_READ_WR_CP_EN(x) \ 4286 (((x) >> S_FW_SCSI_READ_WR_CP_EN) & M_FW_SCSI_READ_WR_CP_EN) 4287 4288 #define S_FW_SCSI_READ_WR_CLASS 4 4289 #define M_FW_SCSI_READ_WR_CLASS 0x3 4290 #define V_FW_SCSI_READ_WR_CLASS(x) ((x) << S_FW_SCSI_READ_WR_CLASS) 4291 #define G_FW_SCSI_READ_WR_CLASS(x) \ 4292 (((x) >> S_FW_SCSI_READ_WR_CLASS) & M_FW_SCSI_READ_WR_CLASS) 4293 4294 struct fw_scsi_cmd_wr { 4295 __be32 op_immdlen; 4296 __be32 flowid_len16; 4297 __be64 cookie; 4298 __be16 iqid; 4299 __u8 tmo_val; 4300 __u8 r3; 4301 union fw_scsi_cmd_priv { 4302 struct fcoe_cmd_priv { 4303 __u8 ctl_pri; 4304 __u8 cp_en_class; 4305 __u8 r4_lo[2]; 4306 } fcoe; 4307 struct iscsi_cmd_priv { 4308 __u8 r4[4]; 4309 } iscsi; 4310 } u; 4311 __u8 r5[8]; 4312 __be64 rsp_dmaaddr; 4313 __be32 rsp_dmalen; 4314 __be32 r6; 4315 }; 4316 4317 #define S_FW_SCSI_CMD_WR_OPCODE 24 4318 #define M_FW_SCSI_CMD_WR_OPCODE 0xff 4319 #define V_FW_SCSI_CMD_WR_OPCODE(x) ((x) << S_FW_SCSI_CMD_WR_OPCODE) 4320 #define G_FW_SCSI_CMD_WR_OPCODE(x) \ 4321 (((x) >> S_FW_SCSI_CMD_WR_OPCODE) & M_FW_SCSI_CMD_WR_OPCODE) 4322 4323 #define S_FW_SCSI_CMD_WR_IMMDLEN 0 4324 #define M_FW_SCSI_CMD_WR_IMMDLEN 0xff 4325 #define V_FW_SCSI_CMD_WR_IMMDLEN(x) ((x) << S_FW_SCSI_CMD_WR_IMMDLEN) 4326 #define G_FW_SCSI_CMD_WR_IMMDLEN(x) \ 4327 (((x) >> S_FW_SCSI_CMD_WR_IMMDLEN) & M_FW_SCSI_CMD_WR_IMMDLEN) 4328 4329 #define S_FW_SCSI_CMD_WR_FLOWID 8 4330 #define M_FW_SCSI_CMD_WR_FLOWID 0xfffff 4331 #define V_FW_SCSI_CMD_WR_FLOWID(x) ((x) << S_FW_SCSI_CMD_WR_FLOWID) 4332 #define G_FW_SCSI_CMD_WR_FLOWID(x) \ 4333 (((x) >> S_FW_SCSI_CMD_WR_FLOWID) & M_FW_SCSI_CMD_WR_FLOWID) 4334 4335 #define S_FW_SCSI_CMD_WR_LEN16 0 4336 #define M_FW_SCSI_CMD_WR_LEN16 0xff 4337 #define V_FW_SCSI_CMD_WR_LEN16(x) ((x) << S_FW_SCSI_CMD_WR_LEN16) 4338 #define G_FW_SCSI_CMD_WR_LEN16(x) \ 4339 (((x) >> S_FW_SCSI_CMD_WR_LEN16) & M_FW_SCSI_CMD_WR_LEN16) 4340 4341 #define S_FW_SCSI_CMD_WR_CP_EN 6 4342 #define M_FW_SCSI_CMD_WR_CP_EN 0x3 4343 #define V_FW_SCSI_CMD_WR_CP_EN(x) ((x) << S_FW_SCSI_CMD_WR_CP_EN) 4344 #define G_FW_SCSI_CMD_WR_CP_EN(x) \ 4345 (((x) >> S_FW_SCSI_CMD_WR_CP_EN) & M_FW_SCSI_CMD_WR_CP_EN) 4346 4347 #define S_FW_SCSI_CMD_WR_CLASS 4 4348 #define M_FW_SCSI_CMD_WR_CLASS 0x3 4349 #define V_FW_SCSI_CMD_WR_CLASS(x) ((x) << S_FW_SCSI_CMD_WR_CLASS) 4350 #define G_FW_SCSI_CMD_WR_CLASS(x) \ 4351 (((x) >> S_FW_SCSI_CMD_WR_CLASS) & M_FW_SCSI_CMD_WR_CLASS) 4352 4353 struct fw_scsi_abrt_cls_wr { 4354 __be32 op_immdlen; 4355 __be32 flowid_len16; 4356 __be64 cookie; 4357 __be16 iqid; 4358 __u8 tmo_val; 4359 __u8 sub_opcode_to_chk_all_io; 4360 __u8 r3[4]; 4361 __be64 t_cookie; 4362 }; 4363 4364 #define S_FW_SCSI_ABRT_CLS_WR_OPCODE 24 4365 #define M_FW_SCSI_ABRT_CLS_WR_OPCODE 0xff 4366 #define V_FW_SCSI_ABRT_CLS_WR_OPCODE(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_OPCODE) 4367 #define G_FW_SCSI_ABRT_CLS_WR_OPCODE(x) \ 4368 (((x) >> S_FW_SCSI_ABRT_CLS_WR_OPCODE) & M_FW_SCSI_ABRT_CLS_WR_OPCODE) 4369 4370 #define S_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0 4371 #define M_FW_SCSI_ABRT_CLS_WR_IMMDLEN 0xff 4372 #define V_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 4373 ((x) << S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 4374 #define G_FW_SCSI_ABRT_CLS_WR_IMMDLEN(x) \ 4375 (((x) >> S_FW_SCSI_ABRT_CLS_WR_IMMDLEN) & M_FW_SCSI_ABRT_CLS_WR_IMMDLEN) 4376 4377 #define S_FW_SCSI_ABRT_CLS_WR_FLOWID 8 4378 #define M_FW_SCSI_ABRT_CLS_WR_FLOWID 0xfffff 4379 #define V_FW_SCSI_ABRT_CLS_WR_FLOWID(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_FLOWID) 4380 #define G_FW_SCSI_ABRT_CLS_WR_FLOWID(x) \ 4381 (((x) >> S_FW_SCSI_ABRT_CLS_WR_FLOWID) & M_FW_SCSI_ABRT_CLS_WR_FLOWID) 4382 4383 #define S_FW_SCSI_ABRT_CLS_WR_LEN16 0 4384 #define M_FW_SCSI_ABRT_CLS_WR_LEN16 0xff 4385 #define V_FW_SCSI_ABRT_CLS_WR_LEN16(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_LEN16) 4386 #define G_FW_SCSI_ABRT_CLS_WR_LEN16(x) \ 4387 (((x) >> S_FW_SCSI_ABRT_CLS_WR_LEN16) & M_FW_SCSI_ABRT_CLS_WR_LEN16) 4388 4389 #define S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 2 4390 #define M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE 0x3f 4391 #define V_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 4392 ((x) << S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 4393 #define G_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE(x) \ 4394 (((x) >> S_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) & \ 4395 M_FW_SCSI_ABRT_CLS_WR_SUB_OPCODE) 4396 4397 #define S_FW_SCSI_ABRT_CLS_WR_UNSOL 1 4398 #define M_FW_SCSI_ABRT_CLS_WR_UNSOL 0x1 4399 #define V_FW_SCSI_ABRT_CLS_WR_UNSOL(x) ((x) << S_FW_SCSI_ABRT_CLS_WR_UNSOL) 4400 #define G_FW_SCSI_ABRT_CLS_WR_UNSOL(x) \ 4401 (((x) >> S_FW_SCSI_ABRT_CLS_WR_UNSOL) & M_FW_SCSI_ABRT_CLS_WR_UNSOL) 4402 #define F_FW_SCSI_ABRT_CLS_WR_UNSOL V_FW_SCSI_ABRT_CLS_WR_UNSOL(1U) 4403 4404 #define S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0 4405 #define M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO 0x1 4406 #define V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 4407 ((x) << S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 4408 #define G_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(x) \ 4409 (((x) >> S_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) & \ 4410 M_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO) 4411 #define F_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO \ 4412 V_FW_SCSI_ABRT_CLS_WR_CHK_ALL_IO(1U) 4413 4414 struct fw_scsi_tgt_acc_wr { 4415 __be32 op_immdlen; 4416 __be32 flowid_len16; 4417 __be64 cookie; 4418 __be16 iqid; 4419 __u8 r3; 4420 __u8 use_burst_len; 4421 union fw_scsi_tgt_acc_priv { 4422 struct fcoe_tgt_acc_priv { 4423 __u8 ctl_pri; 4424 __u8 cp_en_class; 4425 __u8 r4_lo[2]; 4426 } fcoe; 4427 struct iscsi_tgt_acc_priv { 4428 __u8 r4[4]; 4429 } iscsi; 4430 } u; 4431 __be32 burst_len; 4432 __be32 rel_off; 4433 __be64 r5; 4434 __be32 r6; 4435 __be32 tot_xfer_len; 4436 }; 4437 4438 #define S_FW_SCSI_TGT_ACC_WR_OPCODE 24 4439 #define M_FW_SCSI_TGT_ACC_WR_OPCODE 0xff 4440 #define V_FW_SCSI_TGT_ACC_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_ACC_WR_OPCODE) 4441 #define G_FW_SCSI_TGT_ACC_WR_OPCODE(x) \ 4442 (((x) >> S_FW_SCSI_TGT_ACC_WR_OPCODE) & M_FW_SCSI_TGT_ACC_WR_OPCODE) 4443 4444 #define S_FW_SCSI_TGT_ACC_WR_IMMDLEN 0 4445 #define M_FW_SCSI_TGT_ACC_WR_IMMDLEN 0xff 4446 #define V_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_IMMDLEN) 4447 #define G_FW_SCSI_TGT_ACC_WR_IMMDLEN(x) \ 4448 (((x) >> S_FW_SCSI_TGT_ACC_WR_IMMDLEN) & M_FW_SCSI_TGT_ACC_WR_IMMDLEN) 4449 4450 #define S_FW_SCSI_TGT_ACC_WR_FLOWID 8 4451 #define M_FW_SCSI_TGT_ACC_WR_FLOWID 0xfffff 4452 #define V_FW_SCSI_TGT_ACC_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_ACC_WR_FLOWID) 4453 #define G_FW_SCSI_TGT_ACC_WR_FLOWID(x) \ 4454 (((x) >> S_FW_SCSI_TGT_ACC_WR_FLOWID) & M_FW_SCSI_TGT_ACC_WR_FLOWID) 4455 4456 #define S_FW_SCSI_TGT_ACC_WR_LEN16 0 4457 #define M_FW_SCSI_TGT_ACC_WR_LEN16 0xff 4458 #define V_FW_SCSI_TGT_ACC_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_ACC_WR_LEN16) 4459 #define G_FW_SCSI_TGT_ACC_WR_LEN16(x) \ 4460 (((x) >> S_FW_SCSI_TGT_ACC_WR_LEN16) & M_FW_SCSI_TGT_ACC_WR_LEN16) 4461 4462 #define S_FW_SCSI_TGT_ACC_WR_CP_EN 6 4463 #define M_FW_SCSI_TGT_ACC_WR_CP_EN 0x3 4464 #define V_FW_SCSI_TGT_ACC_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CP_EN) 4465 #define G_FW_SCSI_TGT_ACC_WR_CP_EN(x) \ 4466 (((x) >> S_FW_SCSI_TGT_ACC_WR_CP_EN) & M_FW_SCSI_TGT_ACC_WR_CP_EN) 4467 4468 #define S_FW_SCSI_TGT_ACC_WR_CLASS 4 4469 #define M_FW_SCSI_TGT_ACC_WR_CLASS 0x3 4470 #define V_FW_SCSI_TGT_ACC_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_ACC_WR_CLASS) 4471 #define G_FW_SCSI_TGT_ACC_WR_CLASS(x) \ 4472 (((x) >> S_FW_SCSI_TGT_ACC_WR_CLASS) & M_FW_SCSI_TGT_ACC_WR_CLASS) 4473 4474 struct fw_scsi_tgt_xmit_wr { 4475 __be32 op_immdlen; 4476 __be32 flowid_len16; 4477 __be64 cookie; 4478 __be16 iqid; 4479 __u8 auto_rsp; 4480 __u8 use_xfer_cnt; 4481 union fw_scsi_tgt_xmit_priv { 4482 struct fcoe_tgt_xmit_priv { 4483 __u8 ctl_pri; 4484 __u8 cp_en_class; 4485 __u8 r3_lo[2]; 4486 } fcoe; 4487 struct iscsi_tgt_xmit_priv { 4488 __u8 r3[4]; 4489 } iscsi; 4490 } u; 4491 __be32 xfer_cnt; 4492 __be32 r4; 4493 __be64 r5; 4494 __be32 r6; 4495 __be32 tot_xfer_len; 4496 }; 4497 4498 #define S_FW_SCSI_TGT_XMIT_WR_OPCODE 24 4499 #define M_FW_SCSI_TGT_XMIT_WR_OPCODE 0xff 4500 #define V_FW_SCSI_TGT_XMIT_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_OPCODE) 4501 #define G_FW_SCSI_TGT_XMIT_WR_OPCODE(x) \ 4502 (((x) >> S_FW_SCSI_TGT_XMIT_WR_OPCODE) & M_FW_SCSI_TGT_XMIT_WR_OPCODE) 4503 4504 #define S_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0 4505 #define M_FW_SCSI_TGT_XMIT_WR_IMMDLEN 0xff 4506 #define V_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 4507 ((x) << S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 4508 #define G_FW_SCSI_TGT_XMIT_WR_IMMDLEN(x) \ 4509 (((x) >> S_FW_SCSI_TGT_XMIT_WR_IMMDLEN) & M_FW_SCSI_TGT_XMIT_WR_IMMDLEN) 4510 4511 #define S_FW_SCSI_TGT_XMIT_WR_FLOWID 8 4512 #define M_FW_SCSI_TGT_XMIT_WR_FLOWID 0xfffff 4513 #define V_FW_SCSI_TGT_XMIT_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_FLOWID) 4514 #define G_FW_SCSI_TGT_XMIT_WR_FLOWID(x) \ 4515 (((x) >> S_FW_SCSI_TGT_XMIT_WR_FLOWID) & M_FW_SCSI_TGT_XMIT_WR_FLOWID) 4516 4517 #define S_FW_SCSI_TGT_XMIT_WR_LEN16 0 4518 #define M_FW_SCSI_TGT_XMIT_WR_LEN16 0xff 4519 #define V_FW_SCSI_TGT_XMIT_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_LEN16) 4520 #define G_FW_SCSI_TGT_XMIT_WR_LEN16(x) \ 4521 (((x) >> S_FW_SCSI_TGT_XMIT_WR_LEN16) & M_FW_SCSI_TGT_XMIT_WR_LEN16) 4522 4523 #define S_FW_SCSI_TGT_XMIT_WR_CP_EN 6 4524 #define M_FW_SCSI_TGT_XMIT_WR_CP_EN 0x3 4525 #define V_FW_SCSI_TGT_XMIT_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CP_EN) 4526 #define G_FW_SCSI_TGT_XMIT_WR_CP_EN(x) \ 4527 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CP_EN) & M_FW_SCSI_TGT_XMIT_WR_CP_EN) 4528 4529 #define S_FW_SCSI_TGT_XMIT_WR_CLASS 4 4530 #define M_FW_SCSI_TGT_XMIT_WR_CLASS 0x3 4531 #define V_FW_SCSI_TGT_XMIT_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_XMIT_WR_CLASS) 4532 #define G_FW_SCSI_TGT_XMIT_WR_CLASS(x) \ 4533 (((x) >> S_FW_SCSI_TGT_XMIT_WR_CLASS) & M_FW_SCSI_TGT_XMIT_WR_CLASS) 4534 4535 struct fw_scsi_tgt_rsp_wr { 4536 __be32 op_immdlen; 4537 __be32 flowid_len16; 4538 __be64 cookie; 4539 __be16 iqid; 4540 __u8 r3[2]; 4541 union fw_scsi_tgt_rsp_priv { 4542 struct fcoe_tgt_rsp_priv { 4543 __u8 ctl_pri; 4544 __u8 cp_en_class; 4545 __u8 r4_lo[2]; 4546 } fcoe; 4547 struct iscsi_tgt_rsp_priv { 4548 __u8 r4[4]; 4549 } iscsi; 4550 } u; 4551 __u8 r5[8]; 4552 }; 4553 4554 #define S_FW_SCSI_TGT_RSP_WR_OPCODE 24 4555 #define M_FW_SCSI_TGT_RSP_WR_OPCODE 0xff 4556 #define V_FW_SCSI_TGT_RSP_WR_OPCODE(x) ((x) << S_FW_SCSI_TGT_RSP_WR_OPCODE) 4557 #define G_FW_SCSI_TGT_RSP_WR_OPCODE(x) \ 4558 (((x) >> S_FW_SCSI_TGT_RSP_WR_OPCODE) & M_FW_SCSI_TGT_RSP_WR_OPCODE) 4559 4560 #define S_FW_SCSI_TGT_RSP_WR_IMMDLEN 0 4561 #define M_FW_SCSI_TGT_RSP_WR_IMMDLEN 0xff 4562 #define V_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_IMMDLEN) 4563 #define G_FW_SCSI_TGT_RSP_WR_IMMDLEN(x) \ 4564 (((x) >> S_FW_SCSI_TGT_RSP_WR_IMMDLEN) & M_FW_SCSI_TGT_RSP_WR_IMMDLEN) 4565 4566 #define S_FW_SCSI_TGT_RSP_WR_FLOWID 8 4567 #define M_FW_SCSI_TGT_RSP_WR_FLOWID 0xfffff 4568 #define V_FW_SCSI_TGT_RSP_WR_FLOWID(x) ((x) << S_FW_SCSI_TGT_RSP_WR_FLOWID) 4569 #define G_FW_SCSI_TGT_RSP_WR_FLOWID(x) \ 4570 (((x) >> S_FW_SCSI_TGT_RSP_WR_FLOWID) & M_FW_SCSI_TGT_RSP_WR_FLOWID) 4571 4572 #define S_FW_SCSI_TGT_RSP_WR_LEN16 0 4573 #define M_FW_SCSI_TGT_RSP_WR_LEN16 0xff 4574 #define V_FW_SCSI_TGT_RSP_WR_LEN16(x) ((x) << S_FW_SCSI_TGT_RSP_WR_LEN16) 4575 #define G_FW_SCSI_TGT_RSP_WR_LEN16(x) \ 4576 (((x) >> S_FW_SCSI_TGT_RSP_WR_LEN16) & M_FW_SCSI_TGT_RSP_WR_LEN16) 4577 4578 #define S_FW_SCSI_TGT_RSP_WR_CP_EN 6 4579 #define M_FW_SCSI_TGT_RSP_WR_CP_EN 0x3 4580 #define V_FW_SCSI_TGT_RSP_WR_CP_EN(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CP_EN) 4581 #define G_FW_SCSI_TGT_RSP_WR_CP_EN(x) \ 4582 (((x) >> S_FW_SCSI_TGT_RSP_WR_CP_EN) & M_FW_SCSI_TGT_RSP_WR_CP_EN) 4583 4584 #define S_FW_SCSI_TGT_RSP_WR_CLASS 4 4585 #define M_FW_SCSI_TGT_RSP_WR_CLASS 0x3 4586 #define V_FW_SCSI_TGT_RSP_WR_CLASS(x) ((x) << S_FW_SCSI_TGT_RSP_WR_CLASS) 4587 #define G_FW_SCSI_TGT_RSP_WR_CLASS(x) \ 4588 (((x) >> S_FW_SCSI_TGT_RSP_WR_CLASS) & M_FW_SCSI_TGT_RSP_WR_CLASS) 4589 4590 struct fw_pofcoe_tcb_wr { 4591 __be32 op_compl; 4592 __be32 equiq_to_len16; 4593 __be32 r4; 4594 __be32 xfer_len; 4595 __be32 tid_to_port; 4596 __be16 x_id; 4597 __be16 vlan_id; 4598 __be64 cookie; 4599 __be32 s_id; 4600 __be32 d_id; 4601 __be32 tag; 4602 __be16 r6; 4603 __be16 iqid; 4604 }; 4605 4606 #define S_FW_POFCOE_TCB_WR_TID 12 4607 #define M_FW_POFCOE_TCB_WR_TID 0xfffff 4608 #define V_FW_POFCOE_TCB_WR_TID(x) ((x) << S_FW_POFCOE_TCB_WR_TID) 4609 #define G_FW_POFCOE_TCB_WR_TID(x) \ 4610 (((x) >> S_FW_POFCOE_TCB_WR_TID) & M_FW_POFCOE_TCB_WR_TID) 4611 4612 #define S_FW_POFCOE_TCB_WR_ALLOC 4 4613 #define M_FW_POFCOE_TCB_WR_ALLOC 0x1 4614 #define V_FW_POFCOE_TCB_WR_ALLOC(x) ((x) << S_FW_POFCOE_TCB_WR_ALLOC) 4615 #define G_FW_POFCOE_TCB_WR_ALLOC(x) \ 4616 (((x) >> S_FW_POFCOE_TCB_WR_ALLOC) & M_FW_POFCOE_TCB_WR_ALLOC) 4617 #define F_FW_POFCOE_TCB_WR_ALLOC V_FW_POFCOE_TCB_WR_ALLOC(1U) 4618 4619 #define S_FW_POFCOE_TCB_WR_FREE 3 4620 #define M_FW_POFCOE_TCB_WR_FREE 0x1 4621 #define V_FW_POFCOE_TCB_WR_FREE(x) ((x) << S_FW_POFCOE_TCB_WR_FREE) 4622 #define G_FW_POFCOE_TCB_WR_FREE(x) \ 4623 (((x) >> S_FW_POFCOE_TCB_WR_FREE) & M_FW_POFCOE_TCB_WR_FREE) 4624 #define F_FW_POFCOE_TCB_WR_FREE V_FW_POFCOE_TCB_WR_FREE(1U) 4625 4626 #define S_FW_POFCOE_TCB_WR_PORT 0 4627 #define M_FW_POFCOE_TCB_WR_PORT 0x7 4628 #define V_FW_POFCOE_TCB_WR_PORT(x) ((x) << S_FW_POFCOE_TCB_WR_PORT) 4629 #define G_FW_POFCOE_TCB_WR_PORT(x) \ 4630 (((x) >> S_FW_POFCOE_TCB_WR_PORT) & M_FW_POFCOE_TCB_WR_PORT) 4631 4632 struct fw_pofcoe_ulptx_wr { 4633 __be32 op_pkd; 4634 __be32 equiq_to_len16; 4635 __u64 cookie; 4636 }; 4637 4638 /******************************************************************* 4639 * T10 DIF related definition 4640 *******************************************************************/ 4641 struct fw_tx_pi_header { 4642 __be16 op_to_inline; 4643 __u8 pi_interval_tag_type; 4644 __u8 num_pi; 4645 __be32 pi_start4_pi_end4; 4646 __u8 tag_gen_enabled_pkd; 4647 __u8 num_pi_dsg; 4648 __be16 app_tag; 4649 __be32 ref_tag; 4650 }; 4651 4652 #define S_FW_TX_PI_HEADER_OP 8 4653 #define M_FW_TX_PI_HEADER_OP 0xff 4654 #define V_FW_TX_PI_HEADER_OP(x) ((x) << S_FW_TX_PI_HEADER_OP) 4655 #define G_FW_TX_PI_HEADER_OP(x) \ 4656 (((x) >> S_FW_TX_PI_HEADER_OP) & M_FW_TX_PI_HEADER_OP) 4657 4658 #define S_FW_TX_PI_HEADER_ULPTXMORE 7 4659 #define M_FW_TX_PI_HEADER_ULPTXMORE 0x1 4660 #define V_FW_TX_PI_HEADER_ULPTXMORE(x) ((x) << S_FW_TX_PI_HEADER_ULPTXMORE) 4661 #define G_FW_TX_PI_HEADER_ULPTXMORE(x) \ 4662 (((x) >> S_FW_TX_PI_HEADER_ULPTXMORE) & M_FW_TX_PI_HEADER_ULPTXMORE) 4663 #define F_FW_TX_PI_HEADER_ULPTXMORE V_FW_TX_PI_HEADER_ULPTXMORE(1U) 4664 4665 #define S_FW_TX_PI_HEADER_PI_CONTROL 4 4666 #define M_FW_TX_PI_HEADER_PI_CONTROL 0x7 4667 #define V_FW_TX_PI_HEADER_PI_CONTROL(x) ((x) << S_FW_TX_PI_HEADER_PI_CONTROL) 4668 #define G_FW_TX_PI_HEADER_PI_CONTROL(x) \ 4669 (((x) >> S_FW_TX_PI_HEADER_PI_CONTROL) & M_FW_TX_PI_HEADER_PI_CONTROL) 4670 4671 #define S_FW_TX_PI_HEADER_GUARD_TYPE 2 4672 #define M_FW_TX_PI_HEADER_GUARD_TYPE 0x1 4673 #define V_FW_TX_PI_HEADER_GUARD_TYPE(x) ((x) << S_FW_TX_PI_HEADER_GUARD_TYPE) 4674 #define G_FW_TX_PI_HEADER_GUARD_TYPE(x) \ 4675 (((x) >> S_FW_TX_PI_HEADER_GUARD_TYPE) & M_FW_TX_PI_HEADER_GUARD_TYPE) 4676 #define F_FW_TX_PI_HEADER_GUARD_TYPE V_FW_TX_PI_HEADER_GUARD_TYPE(1U) 4677 4678 #define S_FW_TX_PI_HEADER_VALIDATE 1 4679 #define M_FW_TX_PI_HEADER_VALIDATE 0x1 4680 #define V_FW_TX_PI_HEADER_VALIDATE(x) ((x) << S_FW_TX_PI_HEADER_VALIDATE) 4681 #define G_FW_TX_PI_HEADER_VALIDATE(x) \ 4682 (((x) >> S_FW_TX_PI_HEADER_VALIDATE) & M_FW_TX_PI_HEADER_VALIDATE) 4683 #define F_FW_TX_PI_HEADER_VALIDATE V_FW_TX_PI_HEADER_VALIDATE(1U) 4684 4685 #define S_FW_TX_PI_HEADER_INLINE 0 4686 #define M_FW_TX_PI_HEADER_INLINE 0x1 4687 #define V_FW_TX_PI_HEADER_INLINE(x) ((x) << S_FW_TX_PI_HEADER_INLINE) 4688 #define G_FW_TX_PI_HEADER_INLINE(x) \ 4689 (((x) >> S_FW_TX_PI_HEADER_INLINE) & M_FW_TX_PI_HEADER_INLINE) 4690 #define F_FW_TX_PI_HEADER_INLINE V_FW_TX_PI_HEADER_INLINE(1U) 4691 4692 #define S_FW_TX_PI_HEADER_PI_INTERVAL 7 4693 #define M_FW_TX_PI_HEADER_PI_INTERVAL 0x1 4694 #define V_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 4695 ((x) << S_FW_TX_PI_HEADER_PI_INTERVAL) 4696 #define G_FW_TX_PI_HEADER_PI_INTERVAL(x) \ 4697 (((x) >> S_FW_TX_PI_HEADER_PI_INTERVAL) & M_FW_TX_PI_HEADER_PI_INTERVAL) 4698 #define F_FW_TX_PI_HEADER_PI_INTERVAL V_FW_TX_PI_HEADER_PI_INTERVAL(1U) 4699 4700 #define S_FW_TX_PI_HEADER_TAG_TYPE 5 4701 #define M_FW_TX_PI_HEADER_TAG_TYPE 0x3 4702 #define V_FW_TX_PI_HEADER_TAG_TYPE(x) ((x) << S_FW_TX_PI_HEADER_TAG_TYPE) 4703 #define G_FW_TX_PI_HEADER_TAG_TYPE(x) \ 4704 (((x) >> S_FW_TX_PI_HEADER_TAG_TYPE) & M_FW_TX_PI_HEADER_TAG_TYPE) 4705 4706 #define S_FW_TX_PI_HEADER_PI_START4 22 4707 #define M_FW_TX_PI_HEADER_PI_START4 0x3ff 4708 #define V_FW_TX_PI_HEADER_PI_START4(x) ((x) << S_FW_TX_PI_HEADER_PI_START4) 4709 #define G_FW_TX_PI_HEADER_PI_START4(x) \ 4710 (((x) >> S_FW_TX_PI_HEADER_PI_START4) & M_FW_TX_PI_HEADER_PI_START4) 4711 4712 #define S_FW_TX_PI_HEADER_PI_END4 0 4713 #define M_FW_TX_PI_HEADER_PI_END4 0x3fffff 4714 #define V_FW_TX_PI_HEADER_PI_END4(x) ((x) << S_FW_TX_PI_HEADER_PI_END4) 4715 #define G_FW_TX_PI_HEADER_PI_END4(x) \ 4716 (((x) >> S_FW_TX_PI_HEADER_PI_END4) & M_FW_TX_PI_HEADER_PI_END4) 4717 4718 #define S_FW_TX_PI_HEADER_TAG_GEN_ENABLED 6 4719 #define M_FW_TX_PI_HEADER_TAG_GEN_ENABLED 0x3 4720 #define V_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 4721 ((x) << S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 4722 #define G_FW_TX_PI_HEADER_TAG_GEN_ENABLED(x) \ 4723 (((x) >> S_FW_TX_PI_HEADER_TAG_GEN_ENABLED) & \ 4724 M_FW_TX_PI_HEADER_TAG_GEN_ENABLED) 4725 4726 enum fw_pi_error_type { 4727 FW_PI_ERROR_GUARD_CHECK_FAILED = 0, 4728 }; 4729 4730 struct fw_pi_error { 4731 __be32 err_type_pkd; 4732 __be32 flowid_len16; 4733 __be16 r2; 4734 __be16 app_tag; 4735 __be32 ref_tag; 4736 __be32 pisc[4]; 4737 }; 4738 4739 #define S_FW_PI_ERROR_ERR_TYPE 24 4740 #define M_FW_PI_ERROR_ERR_TYPE 0xff 4741 #define V_FW_PI_ERROR_ERR_TYPE(x) ((x) << S_FW_PI_ERROR_ERR_TYPE) 4742 #define G_FW_PI_ERROR_ERR_TYPE(x) \ 4743 (((x) >> S_FW_PI_ERROR_ERR_TYPE) & M_FW_PI_ERROR_ERR_TYPE) 4744 4745 struct fw_tlstx_data_wr { 4746 __be32 op_to_immdlen; 4747 __be32 flowid_len16; 4748 __be32 plen; 4749 __be32 lsodisable_to_flags; 4750 __be32 r5; 4751 __be32 ctxloc_to_exp; 4752 __be16 mfs; 4753 __be16 adjustedplen_pkd; 4754 __be16 expinplenmax_pkd; 4755 __u8 pdusinplenmax_pkd; 4756 __u8 r10; 4757 }; 4758 4759 #define S_FW_TLSTX_DATA_WR_OPCODE 24 4760 #define M_FW_TLSTX_DATA_WR_OPCODE 0xff 4761 #define V_FW_TLSTX_DATA_WR_OPCODE(x) ((x) << S_FW_TLSTX_DATA_WR_OPCODE) 4762 #define G_FW_TLSTX_DATA_WR_OPCODE(x) \ 4763 (((x) >> S_FW_TLSTX_DATA_WR_OPCODE) & M_FW_TLSTX_DATA_WR_OPCODE) 4764 4765 #define S_FW_TLSTX_DATA_WR_COMPL 21 4766 #define M_FW_TLSTX_DATA_WR_COMPL 0x1 4767 #define V_FW_TLSTX_DATA_WR_COMPL(x) ((x) << S_FW_TLSTX_DATA_WR_COMPL) 4768 #define G_FW_TLSTX_DATA_WR_COMPL(x) \ 4769 (((x) >> S_FW_TLSTX_DATA_WR_COMPL) & M_FW_TLSTX_DATA_WR_COMPL) 4770 #define F_FW_TLSTX_DATA_WR_COMPL V_FW_TLSTX_DATA_WR_COMPL(1U) 4771 4772 #define S_FW_TLSTX_DATA_WR_IMMDLEN 0 4773 #define M_FW_TLSTX_DATA_WR_IMMDLEN 0xff 4774 #define V_FW_TLSTX_DATA_WR_IMMDLEN(x) ((x) << S_FW_TLSTX_DATA_WR_IMMDLEN) 4775 #define G_FW_TLSTX_DATA_WR_IMMDLEN(x) \ 4776 (((x) >> S_FW_TLSTX_DATA_WR_IMMDLEN) & M_FW_TLSTX_DATA_WR_IMMDLEN) 4777 4778 #define S_FW_TLSTX_DATA_WR_FLOWID 8 4779 #define M_FW_TLSTX_DATA_WR_FLOWID 0xfffff 4780 #define V_FW_TLSTX_DATA_WR_FLOWID(x) ((x) << S_FW_TLSTX_DATA_WR_FLOWID) 4781 #define G_FW_TLSTX_DATA_WR_FLOWID(x) \ 4782 (((x) >> S_FW_TLSTX_DATA_WR_FLOWID) & M_FW_TLSTX_DATA_WR_FLOWID) 4783 4784 #define S_FW_TLSTX_DATA_WR_LEN16 0 4785 #define M_FW_TLSTX_DATA_WR_LEN16 0xff 4786 #define V_FW_TLSTX_DATA_WR_LEN16(x) ((x) << S_FW_TLSTX_DATA_WR_LEN16) 4787 #define G_FW_TLSTX_DATA_WR_LEN16(x) \ 4788 (((x) >> S_FW_TLSTX_DATA_WR_LEN16) & M_FW_TLSTX_DATA_WR_LEN16) 4789 4790 #define S_FW_TLSTX_DATA_WR_LSODISABLE 31 4791 #define M_FW_TLSTX_DATA_WR_LSODISABLE 0x1 4792 #define V_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 4793 ((x) << S_FW_TLSTX_DATA_WR_LSODISABLE) 4794 #define G_FW_TLSTX_DATA_WR_LSODISABLE(x) \ 4795 (((x) >> S_FW_TLSTX_DATA_WR_LSODISABLE) & M_FW_TLSTX_DATA_WR_LSODISABLE) 4796 #define F_FW_TLSTX_DATA_WR_LSODISABLE V_FW_TLSTX_DATA_WR_LSODISABLE(1U) 4797 4798 #define S_FW_TLSTX_DATA_WR_ALIGNPLD 30 4799 #define M_FW_TLSTX_DATA_WR_ALIGNPLD 0x1 4800 #define V_FW_TLSTX_DATA_WR_ALIGNPLD(x) ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLD) 4801 #define G_FW_TLSTX_DATA_WR_ALIGNPLD(x) \ 4802 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLD) & M_FW_TLSTX_DATA_WR_ALIGNPLD) 4803 #define F_FW_TLSTX_DATA_WR_ALIGNPLD V_FW_TLSTX_DATA_WR_ALIGNPLD(1U) 4804 4805 #define S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 29 4806 #define M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE 0x1 4807 #define V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 4808 ((x) << S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 4809 #define G_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(x) \ 4810 (((x) >> S_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) & \ 4811 M_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE) 4812 #define F_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE V_FW_TLSTX_DATA_WR_ALIGNPLDSHOVE(1U) 4813 4814 #define S_FW_TLSTX_DATA_WR_FLAGS 0 4815 #define M_FW_TLSTX_DATA_WR_FLAGS 0xfffffff 4816 #define V_FW_TLSTX_DATA_WR_FLAGS(x) ((x) << S_FW_TLSTX_DATA_WR_FLAGS) 4817 #define G_FW_TLSTX_DATA_WR_FLAGS(x) \ 4818 (((x) >> S_FW_TLSTX_DATA_WR_FLAGS) & M_FW_TLSTX_DATA_WR_FLAGS) 4819 4820 #define S_FW_TLSTX_DATA_WR_CTXLOC 30 4821 #define M_FW_TLSTX_DATA_WR_CTXLOC 0x3 4822 #define V_FW_TLSTX_DATA_WR_CTXLOC(x) ((x) << S_FW_TLSTX_DATA_WR_CTXLOC) 4823 #define G_FW_TLSTX_DATA_WR_CTXLOC(x) \ 4824 (((x) >> S_FW_TLSTX_DATA_WR_CTXLOC) & M_FW_TLSTX_DATA_WR_CTXLOC) 4825 4826 #define S_FW_TLSTX_DATA_WR_IVDSGL 29 4827 #define M_FW_TLSTX_DATA_WR_IVDSGL 0x1 4828 #define V_FW_TLSTX_DATA_WR_IVDSGL(x) ((x) << S_FW_TLSTX_DATA_WR_IVDSGL) 4829 #define G_FW_TLSTX_DATA_WR_IVDSGL(x) \ 4830 (((x) >> S_FW_TLSTX_DATA_WR_IVDSGL) & M_FW_TLSTX_DATA_WR_IVDSGL) 4831 #define F_FW_TLSTX_DATA_WR_IVDSGL V_FW_TLSTX_DATA_WR_IVDSGL(1U) 4832 4833 #define S_FW_TLSTX_DATA_WR_KEYSIZE 24 4834 #define M_FW_TLSTX_DATA_WR_KEYSIZE 0x1f 4835 #define V_FW_TLSTX_DATA_WR_KEYSIZE(x) ((x) << S_FW_TLSTX_DATA_WR_KEYSIZE) 4836 #define G_FW_TLSTX_DATA_WR_KEYSIZE(x) \ 4837 (((x) >> S_FW_TLSTX_DATA_WR_KEYSIZE) & M_FW_TLSTX_DATA_WR_KEYSIZE) 4838 4839 #define S_FW_TLSTX_DATA_WR_NUMIVS 14 4840 #define M_FW_TLSTX_DATA_WR_NUMIVS 0xff 4841 #define V_FW_TLSTX_DATA_WR_NUMIVS(x) ((x) << S_FW_TLSTX_DATA_WR_NUMIVS) 4842 #define G_FW_TLSTX_DATA_WR_NUMIVS(x) \ 4843 (((x) >> S_FW_TLSTX_DATA_WR_NUMIVS) & M_FW_TLSTX_DATA_WR_NUMIVS) 4844 4845 #define S_FW_TLSTX_DATA_WR_EXP 0 4846 #define M_FW_TLSTX_DATA_WR_EXP 0x3fff 4847 #define V_FW_TLSTX_DATA_WR_EXP(x) ((x) << S_FW_TLSTX_DATA_WR_EXP) 4848 #define G_FW_TLSTX_DATA_WR_EXP(x) \ 4849 (((x) >> S_FW_TLSTX_DATA_WR_EXP) & M_FW_TLSTX_DATA_WR_EXP) 4850 4851 #define S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 1 4852 #define M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN 0x7fff 4853 #define V_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 4854 ((x) << S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 4855 #define G_FW_TLSTX_DATA_WR_ADJUSTEDPLEN(x) \ 4856 (((x) >> S_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) & \ 4857 M_FW_TLSTX_DATA_WR_ADJUSTEDPLEN) 4858 4859 #define S_FW_TLSTX_DATA_WR_EXPINPLENMAX 4 4860 #define M_FW_TLSTX_DATA_WR_EXPINPLENMAX 0xfff 4861 #define V_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 4862 ((x) << S_FW_TLSTX_DATA_WR_EXPINPLENMAX) 4863 #define G_FW_TLSTX_DATA_WR_EXPINPLENMAX(x) \ 4864 (((x) >> S_FW_TLSTX_DATA_WR_EXPINPLENMAX) & \ 4865 M_FW_TLSTX_DATA_WR_EXPINPLENMAX) 4866 4867 #define S_FW_TLSTX_DATA_WR_PDUSINPLENMAX 2 4868 #define M_FW_TLSTX_DATA_WR_PDUSINPLENMAX 0x3f 4869 #define V_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 4870 ((x) << S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 4871 #define G_FW_TLSTX_DATA_WR_PDUSINPLENMAX(x) \ 4872 (((x) >> S_FW_TLSTX_DATA_WR_PDUSINPLENMAX) & \ 4873 M_FW_TLSTX_DATA_WR_PDUSINPLENMAX) 4874 4875 struct fw_crypto_lookaside_wr { 4876 __be32 op_to_cctx_size; 4877 __be32 len16_pkd; 4878 __be32 session_id; 4879 __be32 rx_chid_to_rx_q_id; 4880 __be32 key_addr; 4881 __be32 pld_size_hash_size; 4882 __be64 cookie; 4883 }; 4884 4885 #define S_FW_CRYPTO_LOOKASIDE_WR_OPCODE 24 4886 #define M_FW_CRYPTO_LOOKASIDE_WR_OPCODE 0xff 4887 #define V_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 4888 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 4889 #define G_FW_CRYPTO_LOOKASIDE_WR_OPCODE(x) \ 4890 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_OPCODE) & \ 4891 M_FW_CRYPTO_LOOKASIDE_WR_OPCODE) 4892 4893 #define S_FW_CRYPTO_LOOKASIDE_WR_COMPL 23 4894 #define M_FW_CRYPTO_LOOKASIDE_WR_COMPL 0x1 4895 #define V_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 4896 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_COMPL) 4897 #define G_FW_CRYPTO_LOOKASIDE_WR_COMPL(x) \ 4898 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_COMPL) & \ 4899 M_FW_CRYPTO_LOOKASIDE_WR_COMPL) 4900 #define F_FW_CRYPTO_LOOKASIDE_WR_COMPL V_FW_CRYPTO_LOOKASIDE_WR_COMPL(1U) 4901 4902 #define S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 15 4903 #define M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN 0xff 4904 #define V_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 4905 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 4906 #define G_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN(x) \ 4907 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) & \ 4908 M_FW_CRYPTO_LOOKASIDE_WR_IMM_LEN) 4909 4910 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 5 4911 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC 0x3 4912 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 4913 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 4914 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC(x) \ 4915 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) & \ 4916 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_LOC) 4917 4918 #define S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0 4919 #define M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE 0x1f 4920 #define V_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4921 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4922 #define G_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE(x) \ 4923 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) & \ 4924 M_FW_CRYPTO_LOOKASIDE_WR_CCTX_SIZE) 4925 4926 #define S_FW_CRYPTO_LOOKASIDE_WR_LEN16 0 4927 #define M_FW_CRYPTO_LOOKASIDE_WR_LEN16 0xff 4928 #define V_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4929 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4930 #define G_FW_CRYPTO_LOOKASIDE_WR_LEN16(x) \ 4931 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LEN16) & \ 4932 M_FW_CRYPTO_LOOKASIDE_WR_LEN16) 4933 4934 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 29 4935 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID 0x3 4936 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4937 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4938 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_CHID(x) \ 4939 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) & \ 4940 M_FW_CRYPTO_LOOKASIDE_WR_RX_CHID) 4941 4942 #define S_FW_CRYPTO_LOOKASIDE_WR_LCB 27 4943 #define M_FW_CRYPTO_LOOKASIDE_WR_LCB 0x3 4944 #define V_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4945 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_LCB) 4946 #define G_FW_CRYPTO_LOOKASIDE_WR_LCB(x) \ 4947 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_LCB) & M_FW_CRYPTO_LOOKASIDE_WR_LCB) 4948 4949 #define S_FW_CRYPTO_LOOKASIDE_WR_PHASH 25 4950 #define M_FW_CRYPTO_LOOKASIDE_WR_PHASH 0x3 4951 #define V_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4952 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4953 #define G_FW_CRYPTO_LOOKASIDE_WR_PHASH(x) \ 4954 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PHASH) & \ 4955 M_FW_CRYPTO_LOOKASIDE_WR_PHASH) 4956 4957 #define S_FW_CRYPTO_LOOKASIDE_WR_IV 23 4958 #define M_FW_CRYPTO_LOOKASIDE_WR_IV 0x3 4959 #define V_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4960 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_IV) 4961 #define G_FW_CRYPTO_LOOKASIDE_WR_IV(x) \ 4962 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_IV) & M_FW_CRYPTO_LOOKASIDE_WR_IV) 4963 4964 #define S_FW_CRYPTO_LOOKASIDE_WR_FQIDX 15 4965 #define M_FW_CRYPTO_LOOKASIDE_WR_FQIDX 0xff 4966 #define V_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4967 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4968 #define G_FW_CRYPTO_LOOKASIDE_WR_FQIDX(x) \ 4969 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_FQIDX) &\ 4970 M_FW_CRYPTO_LOOKASIDE_WR_FQIDX) 4971 4972 #define S_FW_CRYPTO_LOOKASIDE_WR_TX_CH 10 4973 #define M_FW_CRYPTO_LOOKASIDE_WR_TX_CH 0x3 4974 #define V_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4975 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4976 #define G_FW_CRYPTO_LOOKASIDE_WR_TX_CH(x) \ 4977 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_TX_CH) & \ 4978 M_FW_CRYPTO_LOOKASIDE_WR_TX_CH) 4979 4980 #define S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0 4981 #define M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID 0x3ff 4982 #define V_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4983 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4984 #define G_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID(x) \ 4985 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) & \ 4986 M_FW_CRYPTO_LOOKASIDE_WR_RX_Q_ID) 4987 4988 #define S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 24 4989 #define M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE 0xff 4990 #define V_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4991 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4992 #define G_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE(x) \ 4993 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) & \ 4994 M_FW_CRYPTO_LOOKASIDE_WR_PLD_SIZE) 4995 4996 #define S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 17 4997 #define M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE 0x7f 4998 #define V_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 4999 ((x) << S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 5000 #define G_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE(x) \ 5001 (((x) >> S_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) & \ 5002 M_FW_CRYPTO_LOOKASIDE_WR_HASH_SIZE) 5003 5004 struct fw_tls_tunnel_ofld_wr { 5005 __be32 op_compl; 5006 __be32 flowid_len16; 5007 __be32 plen; 5008 __be32 r4; 5009 }; 5010 5011 struct fw_crypto_update_sa_wr { 5012 __u8 opcode; 5013 __u8 saop_to_txrx; 5014 __u8 vfn; 5015 __u8 r1; 5016 __u8 r2[3]; 5017 __u8 len16; 5018 __be64 cookie; 5019 __be16 r3; 5020 __be16 ipsecidx; 5021 __be32 SPI; 5022 __be64 dip_hi; 5023 __be64 dip_lo; 5024 __be64 lip_hi; 5025 __be64 lip_lo; 5026 union fw_crypto_update_sa_sa { 5027 struct egress_sa { 5028 __be32 valid_SPI_hi; 5029 __be32 SPI_lo_eSeqNum_hi; 5030 __be32 eSeqNum_lo_Salt_hi; 5031 __be32 Salt_lo_to_keyID; 5032 } egress; 5033 struct ingress_sa { 5034 __be32 valid_to_iSeqNum_hi; 5035 __be32 iSeqNum_mi; 5036 __be32 iSeqNum_lo_Salt_hi; 5037 __be32 Salt_lo_to_IPVer; 5038 } ingress; 5039 } sa; 5040 union fw_crypto_update_sa_key { 5041 struct _aes128 { 5042 __u8 key128[16]; 5043 __u8 H128[16]; 5044 __u8 rsvd[16]; 5045 } aes128; 5046 struct _aes192 { 5047 __u8 key192[24]; 5048 __be64 r3; 5049 __u8 H192[16]; 5050 } aes192; 5051 struct _aes256 { 5052 __u8 key256[32]; 5053 __u8 H256[16]; 5054 } aes256; 5055 } key; 5056 }; 5057 5058 #define S_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER 3 5059 #define M_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER 0x1 5060 #define V_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER(x) \ 5061 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER) 5062 #define G_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER(x) \ 5063 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER) & \ 5064 M_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER) 5065 #define F_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER \ 5066 V_FW_CRYPTO_UPDATE_SA_WR_EG_IPVER(1U) 5067 5068 #define S_FW_CRYPTO_UPDATE_SA_WR_SAOP 2 5069 #define M_FW_CRYPTO_UPDATE_SA_WR_SAOP 0x1 5070 #define V_FW_CRYPTO_UPDATE_SA_WR_SAOP(x) \ 5071 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SAOP) 5072 #define G_FW_CRYPTO_UPDATE_SA_WR_SAOP(x) \ 5073 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SAOP) & M_FW_CRYPTO_UPDATE_SA_WR_SAOP) 5074 #define F_FW_CRYPTO_UPDATE_SA_WR_SAOP V_FW_CRYPTO_UPDATE_SA_WR_SAOP(1U) 5075 5076 #define S_FW_CRYPTO_UPDATE_SA_WR_MODE 1 5077 #define M_FW_CRYPTO_UPDATE_SA_WR_MODE 0x1 5078 #define V_FW_CRYPTO_UPDATE_SA_WR_MODE(x) \ 5079 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_MODE) 5080 #define G_FW_CRYPTO_UPDATE_SA_WR_MODE(x) \ 5081 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_MODE) & M_FW_CRYPTO_UPDATE_SA_WR_MODE) 5082 #define F_FW_CRYPTO_UPDATE_SA_WR_MODE V_FW_CRYPTO_UPDATE_SA_WR_MODE(1U) 5083 5084 #define S_FW_CRYPTO_UPDATE_SA_WR_TXRX 0 5085 #define M_FW_CRYPTO_UPDATE_SA_WR_TXRX 0x1 5086 #define V_FW_CRYPTO_UPDATE_SA_WR_TXRX(x) \ 5087 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_TXRX) 5088 #define G_FW_CRYPTO_UPDATE_SA_WR_TXRX(x) \ 5089 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_TXRX) & M_FW_CRYPTO_UPDATE_SA_WR_TXRX) 5090 #define F_FW_CRYPTO_UPDATE_SA_WR_TXRX V_FW_CRYPTO_UPDATE_SA_WR_TXRX(1U) 5091 5092 #define S_FW_CRYPTO_UPDATE_SA_WR_VALID 31 5093 #define M_FW_CRYPTO_UPDATE_SA_WR_VALID 0x1 5094 #define V_FW_CRYPTO_UPDATE_SA_WR_VALID(x) \ 5095 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_VALID) 5096 #define G_FW_CRYPTO_UPDATE_SA_WR_VALID(x) \ 5097 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_VALID) & M_FW_CRYPTO_UPDATE_SA_WR_VALID) 5098 #define F_FW_CRYPTO_UPDATE_SA_WR_VALID V_FW_CRYPTO_UPDATE_SA_WR_VALID(1U) 5099 5100 #define S_FW_CRYPTO_UPDATE_SA_WR_SPI_HI 0 5101 #define M_FW_CRYPTO_UPDATE_SA_WR_SPI_HI 0x7fffffff 5102 #define V_FW_CRYPTO_UPDATE_SA_WR_SPI_HI(x) \ 5103 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SPI_HI) 5104 #define G_FW_CRYPTO_UPDATE_SA_WR_SPI_HI(x) \ 5105 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SPI_HI) & \ 5106 M_FW_CRYPTO_UPDATE_SA_WR_SPI_HI) 5107 5108 #define S_FW_CRYPTO_UPDATE_SA_WR_SPI_LO 31 5109 #define M_FW_CRYPTO_UPDATE_SA_WR_SPI_LO 0x1 5110 #define V_FW_CRYPTO_UPDATE_SA_WR_SPI_LO(x) \ 5111 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SPI_LO) 5112 #define G_FW_CRYPTO_UPDATE_SA_WR_SPI_LO(x) \ 5113 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SPI_LO) & \ 5114 M_FW_CRYPTO_UPDATE_SA_WR_SPI_LO) 5115 #define F_FW_CRYPTO_UPDATE_SA_WR_SPI_LO V_FW_CRYPTO_UPDATE_SA_WR_SPI_LO(1U) 5116 5117 #define S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI 0 5118 #define M_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI 0x7fffffff 5119 #define V_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI(x) \ 5120 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI) 5121 #define G_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI(x) \ 5122 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI) & \ 5123 M_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_HI) 5124 5125 #define S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO 7 5126 #define M_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO 0x1ffffff 5127 #define V_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO(x) \ 5128 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO) 5129 #define G_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO(x) \ 5130 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO) & \ 5131 M_FW_CRYPTO_UPDATE_SA_WR_ESEQNUM_LO) 5132 5133 #define S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI 0 5134 #define M_FW_CRYPTO_UPDATE_SA_WR_SALT_HI 0x7f 5135 #define V_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x) \ 5136 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) 5137 #define G_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x) \ 5138 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) & \ 5139 M_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) 5140 5141 #define S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO 7 5142 #define M_FW_CRYPTO_UPDATE_SA_WR_SALT_LO 0x1ffffff 5143 #define V_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x) \ 5144 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) 5145 #define G_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x) \ 5146 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) & \ 5147 M_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) 5148 5149 #define S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN 5 5150 #define M_FW_CRYPTO_UPDATE_SA_WR_KEYLEN 0x3 5151 #define V_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x) \ 5152 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) 5153 #define G_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x) \ 5154 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) & \ 5155 M_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) 5156 5157 #define S_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE 4 5158 #define M_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE 0x1 5159 #define V_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE(x) \ 5160 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE) 5161 #define G_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE(x) \ 5162 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE) & \ 5163 M_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE) 5164 #define F_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE \ 5165 V_FW_CRYPTO_UPDATE_SA_WR_ESN_ENABLE(1U) 5166 5167 #define S_FW_CRYPTO_UPDATE_SA_WR_KEYID 0 5168 #define M_FW_CRYPTO_UPDATE_SA_WR_KEYID 0xf 5169 #define V_FW_CRYPTO_UPDATE_SA_WR_KEYID(x) \ 5170 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_KEYID) 5171 #define G_FW_CRYPTO_UPDATE_SA_WR_KEYID(x) \ 5172 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_KEYID) & M_FW_CRYPTO_UPDATE_SA_WR_KEYID) 5173 5174 #define S_FW_CRYPTO_UPDATE_SA_WR_VALID 31 5175 #define M_FW_CRYPTO_UPDATE_SA_WR_VALID 0x1 5176 #define V_FW_CRYPTO_UPDATE_SA_WR_VALID(x) \ 5177 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_VALID) 5178 #define G_FW_CRYPTO_UPDATE_SA_WR_VALID(x) \ 5179 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_VALID) & M_FW_CRYPTO_UPDATE_SA_WR_VALID) 5180 #define F_FW_CRYPTO_UPDATE_SA_WR_VALID V_FW_CRYPTO_UPDATE_SA_WR_VALID(1U) 5181 5182 #define S_FW_CRYPTO_UPDATE_SA_WR_EGKEYID 12 5183 #define M_FW_CRYPTO_UPDATE_SA_WR_EGKEYID 0xfff 5184 #define V_FW_CRYPTO_UPDATE_SA_WR_EGKEYID(x) \ 5185 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_EGKEYID) 5186 #define G_FW_CRYPTO_UPDATE_SA_WR_EGKEYID(x) \ 5187 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_EGKEYID) & \ 5188 M_FW_CRYPTO_UPDATE_SA_WR_EGKEYID) 5189 5190 #define S_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN 11 5191 #define M_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN 0x1 5192 #define V_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN(x) \ 5193 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN) 5194 #define G_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN(x) \ 5195 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN) & \ 5196 M_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN) 5197 #define F_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN \ 5198 V_FW_CRYPTO_UPDATE_SA_WR_PADCHKEN(1U) 5199 5200 #define S_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW 7 5201 #define M_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW 0xf 5202 #define V_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW(x) \ 5203 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW) 5204 #define G_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW(x) \ 5205 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW) & \ 5206 M_FW_CRYPTO_UPDATE_SA_WR_ESNWINDOW) 5207 5208 #define S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI 0 5209 #define M_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI 0x7f 5210 #define V_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI(x) \ 5211 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI) 5212 #define G_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI(x) \ 5213 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI) & \ 5214 M_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_HI) 5215 5216 #define S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO 7 5217 #define M_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO 0x1ffffff 5218 #define V_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO(x) \ 5219 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO) 5220 #define G_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO(x) \ 5221 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO) & \ 5222 M_FW_CRYPTO_UPDATE_SA_WR_ISEQNUM_LO) 5223 5224 #define S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI 0 5225 #define M_FW_CRYPTO_UPDATE_SA_WR_SALT_HI 0x7f 5226 #define V_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x) \ 5227 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) 5228 #define G_FW_CRYPTO_UPDATE_SA_WR_SALT_HI(x) \ 5229 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) & \ 5230 M_FW_CRYPTO_UPDATE_SA_WR_SALT_HI) 5231 5232 #define S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO 7 5233 #define M_FW_CRYPTO_UPDATE_SA_WR_SALT_LO 0x1ffffff 5234 #define V_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x) \ 5235 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) 5236 #define G_FW_CRYPTO_UPDATE_SA_WR_SALT_LO(x) \ 5237 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) & \ 5238 M_FW_CRYPTO_UPDATE_SA_WR_SALT_LO) 5239 5240 #define S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN 5 5241 #define M_FW_CRYPTO_UPDATE_SA_WR_KEYLEN 0x3 5242 #define V_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x) \ 5243 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) 5244 #define G_FW_CRYPTO_UPDATE_SA_WR_KEYLEN(x) \ 5245 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) & \ 5246 M_FW_CRYPTO_UPDATE_SA_WR_KEYLEN) 5247 5248 #define S_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH 3 5249 #define M_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH 0x3 5250 #define V_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH(x) \ 5251 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH) 5252 #define G_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH(x) \ 5253 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH) & \ 5254 M_FW_CRYPTO_UPDATE_SA_WR_ICVWIDTH) 5255 5256 #define S_FW_CRYPTO_UPDATE_SA_WR_ESNEN 2 5257 #define M_FW_CRYPTO_UPDATE_SA_WR_ESNEN 0x1 5258 #define V_FW_CRYPTO_UPDATE_SA_WR_ESNEN(x) \ 5259 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_ESNEN) 5260 #define G_FW_CRYPTO_UPDATE_SA_WR_ESNEN(x) \ 5261 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_ESNEN) & M_FW_CRYPTO_UPDATE_SA_WR_ESNEN) 5262 #define F_FW_CRYPTO_UPDATE_SA_WR_ESNEN V_FW_CRYPTO_UPDATE_SA_WR_ESNEN(1U) 5263 5264 #define S_FW_CRYPTO_UPDATE_SA_WR_MODE 1 5265 #define M_FW_CRYPTO_UPDATE_SA_WR_MODE 0x1 5266 #define V_FW_CRYPTO_UPDATE_SA_WR_MODE(x) \ 5267 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_MODE) 5268 #define G_FW_CRYPTO_UPDATE_SA_WR_MODE(x) \ 5269 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_MODE) & M_FW_CRYPTO_UPDATE_SA_WR_MODE) 5270 #define F_FW_CRYPTO_UPDATE_SA_WR_MODE V_FW_CRYPTO_UPDATE_SA_WR_MODE(1U) 5271 5272 #define S_FW_CRYPTO_UPDATE_SA_WR_IPVER 0 5273 #define M_FW_CRYPTO_UPDATE_SA_WR_IPVER 0x1 5274 #define V_FW_CRYPTO_UPDATE_SA_WR_IPVER(x) \ 5275 ((x) << S_FW_CRYPTO_UPDATE_SA_WR_IPVER) 5276 #define G_FW_CRYPTO_UPDATE_SA_WR_IPVER(x) \ 5277 (((x) >> S_FW_CRYPTO_UPDATE_SA_WR_IPVER) & M_FW_CRYPTO_UPDATE_SA_WR_IPVER) 5278 #define F_FW_CRYPTO_UPDATE_SA_WR_IPVER V_FW_CRYPTO_UPDATE_SA_WR_IPVER(1U) 5279 5280 /****************************************************************************** 5281 * C O M M A N D s 5282 *********************/ 5283 5284 /* 5285 * The maximum length of time, in miliseconds, that we expect any firmware 5286 * command to take to execute and return a reply to the host. The RESET 5287 * and INITIALIZE commands can take a fair amount of time to execute but 5288 * most execute in far less time than this maximum. This constant is used 5289 * by host software to determine how long to wait for a firmware command 5290 * reply before declaring the firmware as dead/unreachable ... 5291 */ 5292 #define FW_CMD_MAX_TIMEOUT 10000 5293 5294 /* 5295 * If a host driver does a HELLO and discovers that there's already a MASTER 5296 * selected, we may have to wait for that MASTER to finish issuing RESET, 5297 * configuration and INITIALIZE commands. Also, there's a possibility that 5298 * our own HELLO may get lost if it happens right as the MASTER is issuign a 5299 * RESET command, so we need to be willing to make a few retries of our HELLO. 5300 */ 5301 #define FW_CMD_HELLO_TIMEOUT (3 * FW_CMD_MAX_TIMEOUT) 5302 #define FW_CMD_HELLO_RETRIES 3 5303 5304 enum fw_cmd_opcodes { 5305 FW_LDST_CMD = 0x01, 5306 FW_RESET_CMD = 0x03, 5307 FW_HELLO_CMD = 0x04, 5308 FW_BYE_CMD = 0x05, 5309 FW_INITIALIZE_CMD = 0x06, 5310 FW_CAPS_CONFIG_CMD = 0x07, 5311 FW_PARAMS_CMD = 0x08, 5312 FW_PFVF_CMD = 0x09, 5313 FW_IQ_CMD = 0x10, 5314 FW_EQ_MNGT_CMD = 0x11, 5315 FW_EQ_ETH_CMD = 0x12, 5316 FW_EQ_CTRL_CMD = 0x13, 5317 FW_EQ_OFLD_CMD = 0x21, 5318 FW_VI_CMD = 0x14, 5319 FW_VI_MAC_CMD = 0x15, 5320 FW_VI_RXMODE_CMD = 0x16, 5321 FW_VI_ENABLE_CMD = 0x17, 5322 FW_VI_STATS_CMD = 0x1a, 5323 FW_ACL_MAC_CMD = 0x18, 5324 FW_ACL_VLAN_CMD = 0x19, 5325 FW_PORT_CMD = 0x1b, 5326 FW_PORT_STATS_CMD = 0x1c, 5327 FW_PORT_LB_STATS_CMD = 0x1d, 5328 FW_PORT_TRACE_CMD = 0x1e, 5329 FW_PORT_TRACE_MMAP_CMD = 0x1f, 5330 FW_RSS_IND_TBL_CMD = 0x20, 5331 FW_RSS_GLB_CONFIG_CMD = 0x22, 5332 FW_RSS_VI_CONFIG_CMD = 0x23, 5333 FW_SCHED_CMD = 0x24, 5334 FW_DEVLOG_CMD = 0x25, 5335 FW_WATCHDOG_CMD = 0x27, 5336 FW_CLIP_CMD = 0x28, 5337 FW_CLIP2_CMD = 0x29, 5338 FW_CHNET_IFACE_CMD = 0x26, 5339 FW_FCOE_RES_INFO_CMD = 0x31, 5340 FW_FCOE_LINK_CMD = 0x32, 5341 FW_FCOE_VNP_CMD = 0x33, 5342 FW_FCOE_SPARAMS_CMD = 0x35, 5343 FW_FCOE_STATS_CMD = 0x37, 5344 FW_FCOE_FCF_CMD = 0x38, 5345 FW_DCB_IEEE_CMD = 0x3a, 5346 FW_DIAG_CMD = 0x3d, 5347 FW_PTP_CMD = 0x3e, 5348 FW_HMA_CMD = 0x3f, 5349 FW_JBOF_WIN_REG_CMD = 0x40, 5350 FW_LASTC2E_CMD = 0x41, 5351 FW_ERROR_CMD = 0x80, 5352 FW_DEBUG_CMD = 0x81, 5353 }; 5354 5355 enum fw_cmd_cap { 5356 FW_CMD_CAP_PF = 0x01, 5357 FW_CMD_CAP_DMAQ = 0x02, 5358 FW_CMD_CAP_PORT = 0x04, 5359 FW_CMD_CAP_PORTPROMISC = 0x08, 5360 FW_CMD_CAP_PORTSTATS = 0x10, 5361 FW_CMD_CAP_VF = 0x80, 5362 }; 5363 5364 /* 5365 * Generic command header flit0 5366 */ 5367 struct fw_cmd_hdr { 5368 __be32 hi; 5369 __be32 lo; 5370 }; 5371 5372 #define S_FW_CMD_OP 24 5373 #define M_FW_CMD_OP 0xff 5374 #define V_FW_CMD_OP(x) ((x) << S_FW_CMD_OP) 5375 #define G_FW_CMD_OP(x) (((x) >> S_FW_CMD_OP) & M_FW_CMD_OP) 5376 5377 #define S_FW_CMD_REQUEST 23 5378 #define M_FW_CMD_REQUEST 0x1 5379 #define V_FW_CMD_REQUEST(x) ((x) << S_FW_CMD_REQUEST) 5380 #define G_FW_CMD_REQUEST(x) (((x) >> S_FW_CMD_REQUEST) & M_FW_CMD_REQUEST) 5381 #define F_FW_CMD_REQUEST V_FW_CMD_REQUEST(1U) 5382 5383 #define S_FW_CMD_READ 22 5384 #define M_FW_CMD_READ 0x1 5385 #define V_FW_CMD_READ(x) ((x) << S_FW_CMD_READ) 5386 #define G_FW_CMD_READ(x) (((x) >> S_FW_CMD_READ) & M_FW_CMD_READ) 5387 #define F_FW_CMD_READ V_FW_CMD_READ(1U) 5388 5389 #define S_FW_CMD_WRITE 21 5390 #define M_FW_CMD_WRITE 0x1 5391 #define V_FW_CMD_WRITE(x) ((x) << S_FW_CMD_WRITE) 5392 #define G_FW_CMD_WRITE(x) (((x) >> S_FW_CMD_WRITE) & M_FW_CMD_WRITE) 5393 #define F_FW_CMD_WRITE V_FW_CMD_WRITE(1U) 5394 5395 #define S_FW_CMD_EXEC 20 5396 #define M_FW_CMD_EXEC 0x1 5397 #define V_FW_CMD_EXEC(x) ((x) << S_FW_CMD_EXEC) 5398 #define G_FW_CMD_EXEC(x) (((x) >> S_FW_CMD_EXEC) & M_FW_CMD_EXEC) 5399 #define F_FW_CMD_EXEC V_FW_CMD_EXEC(1U) 5400 5401 #define S_FW_CMD_RAMASK 20 5402 #define M_FW_CMD_RAMASK 0xf 5403 #define V_FW_CMD_RAMASK(x) ((x) << S_FW_CMD_RAMASK) 5404 #define G_FW_CMD_RAMASK(x) (((x) >> S_FW_CMD_RAMASK) & M_FW_CMD_RAMASK) 5405 5406 #define S_FW_CMD_RETVAL 8 5407 #define M_FW_CMD_RETVAL 0xff 5408 #define V_FW_CMD_RETVAL(x) ((x) << S_FW_CMD_RETVAL) 5409 #define G_FW_CMD_RETVAL(x) (((x) >> S_FW_CMD_RETVAL) & M_FW_CMD_RETVAL) 5410 5411 #define S_FW_CMD_LEN16 0 5412 #define M_FW_CMD_LEN16 0xff 5413 #define V_FW_CMD_LEN16(x) ((x) << S_FW_CMD_LEN16) 5414 #define G_FW_CMD_LEN16(x) (((x) >> S_FW_CMD_LEN16) & M_FW_CMD_LEN16) 5415 5416 #define FW_LEN16(fw_struct) V_FW_CMD_LEN16(sizeof(fw_struct) / 16) 5417 5418 /* 5419 * address spaces 5420 */ 5421 enum fw_ldst_addrspc { 5422 FW_LDST_ADDRSPC_FIRMWARE = 0x0001, 5423 FW_LDST_ADDRSPC_SGE_EGRC = 0x0008, 5424 FW_LDST_ADDRSPC_SGE_INGC = 0x0009, 5425 FW_LDST_ADDRSPC_SGE_FLMC = 0x000a, 5426 FW_LDST_ADDRSPC_SGE_CONMC = 0x000b, 5427 FW_LDST_ADDRSPC_TP_PIO = 0x0010, 5428 FW_LDST_ADDRSPC_TP_TM_PIO = 0x0011, 5429 FW_LDST_ADDRSPC_TP_MIB = 0x0012, 5430 FW_LDST_ADDRSPC_MDIO = 0x0018, 5431 FW_LDST_ADDRSPC_MPS = 0x0020, 5432 FW_LDST_ADDRSPC_FUNC = 0x0028, 5433 FW_LDST_ADDRSPC_FUNC_PCIE = 0x0029, 5434 FW_LDST_ADDRSPC_FUNC_I2C = 0x002A, /* legacy */ 5435 FW_LDST_ADDRSPC_LE = 0x0030, 5436 FW_LDST_ADDRSPC_I2C = 0x0038, 5437 FW_LDST_ADDRSPC_PCIE_CFGS = 0x0040, 5438 FW_LDST_ADDRSPC_PCIE_DBG = 0x0041, 5439 FW_LDST_ADDRSPC_PCIE_PHY = 0x0042, 5440 FW_LDST_ADDRSPC_CIM_Q = 0x0048, 5441 }; 5442 5443 /* 5444 * MDIO VSC8634 register access control field 5445 */ 5446 enum fw_ldst_mdio_vsc8634_aid { 5447 FW_LDST_MDIO_VS_STANDARD, 5448 FW_LDST_MDIO_VS_EXTENDED, 5449 FW_LDST_MDIO_VS_GPIO 5450 }; 5451 5452 enum fw_ldst_mps_fid { 5453 FW_LDST_MPS_ATRB, 5454 FW_LDST_MPS_RPLC 5455 }; 5456 5457 enum fw_ldst_func_access_ctl { 5458 FW_LDST_FUNC_ACC_CTL_VIID, 5459 FW_LDST_FUNC_ACC_CTL_FID 5460 }; 5461 5462 enum fw_ldst_func_mod_index { 5463 FW_LDST_FUNC_MPS 5464 }; 5465 5466 struct fw_ldst_cmd { 5467 __be32 op_to_addrspace; 5468 __be32 cycles_to_len16; 5469 union fw_ldst { 5470 struct fw_ldst_addrval { 5471 __be32 addr; 5472 __be32 val; 5473 } addrval; 5474 struct fw_ldst_idctxt { 5475 __be32 physid; 5476 __be32 msg_ctxtflush; 5477 __be32 ctxt_data7; 5478 __be32 ctxt_data6; 5479 __be32 ctxt_data5; 5480 __be32 ctxt_data4; 5481 __be32 ctxt_data3; 5482 __be32 ctxt_data2; 5483 __be32 ctxt_data1; 5484 __be32 ctxt_data0; 5485 } idctxt; 5486 struct fw_ldst_mdio { 5487 __be16 paddr_mmd; 5488 __be16 raddr; 5489 __be16 vctl; 5490 __be16 rval; 5491 } mdio; 5492 struct fw_ldst_cim_rq { 5493 __u8 req_first64[8]; 5494 __u8 req_second64[8]; 5495 __u8 resp_first64[8]; 5496 __u8 resp_second64[8]; 5497 __be32 r3[2]; 5498 } cim_rq; 5499 union fw_ldst_mps { 5500 struct fw_ldst_mps_rplc { 5501 __be16 fid_idx; 5502 __be16 rplcpf_pkd; 5503 __be32 rplc255_224; 5504 __be32 rplc223_192; 5505 __be32 rplc191_160; 5506 __be32 rplc159_128; 5507 __be32 rplc127_96; 5508 __be32 rplc95_64; 5509 __be32 rplc63_32; 5510 __be32 rplc31_0; 5511 } rplc; 5512 struct fw_ldst_mps_atrb { 5513 __be16 fid_mpsid; 5514 __be16 r2[3]; 5515 __be32 r3[2]; 5516 __be32 r4; 5517 __be32 atrb; 5518 __be16 vlan[16]; 5519 } atrb; 5520 } mps; 5521 struct fw_ldst_func { 5522 __u8 access_ctl; 5523 __u8 mod_index; 5524 __be16 ctl_id; 5525 __be32 offset; 5526 __be64 data0; 5527 __be64 data1; 5528 } func; 5529 struct fw_ldst_pcie { 5530 __u8 ctrl_to_fn; 5531 __u8 bnum; 5532 __u8 r; 5533 __u8 ext_r; 5534 __u8 select_naccess; 5535 __u8 pcie_fn; 5536 __be16 nset_pkd; 5537 __be32 data[12]; 5538 } pcie; 5539 struct fw_ldst_i2c_deprecated { 5540 __u8 pid_pkd; 5541 __u8 base; 5542 __u8 boffset; 5543 __u8 data; 5544 __be32 r9; 5545 } i2c_deprecated; 5546 struct fw_ldst_i2c { 5547 __u8 pid; 5548 __u8 did; 5549 __u8 boffset; 5550 __u8 blen; 5551 __be32 r9; 5552 __u8 data[48]; 5553 } i2c; 5554 struct fw_ldst_le { 5555 __be32 index; 5556 __be32 r9; 5557 __u8 val[33]; 5558 __u8 r11[7]; 5559 } le; 5560 } u; 5561 }; 5562 5563 #define S_FW_LDST_CMD_ADDRSPACE 0 5564 #define M_FW_LDST_CMD_ADDRSPACE 0xff 5565 #define V_FW_LDST_CMD_ADDRSPACE(x) ((x) << S_FW_LDST_CMD_ADDRSPACE) 5566 #define G_FW_LDST_CMD_ADDRSPACE(x) \ 5567 (((x) >> S_FW_LDST_CMD_ADDRSPACE) & M_FW_LDST_CMD_ADDRSPACE) 5568 5569 #define S_FW_LDST_CMD_CYCLES 16 5570 #define M_FW_LDST_CMD_CYCLES 0xffff 5571 #define V_FW_LDST_CMD_CYCLES(x) ((x) << S_FW_LDST_CMD_CYCLES) 5572 #define G_FW_LDST_CMD_CYCLES(x) \ 5573 (((x) >> S_FW_LDST_CMD_CYCLES) & M_FW_LDST_CMD_CYCLES) 5574 5575 #define S_FW_LDST_CMD_MSG 31 5576 #define M_FW_LDST_CMD_MSG 0x1 5577 #define V_FW_LDST_CMD_MSG(x) ((x) << S_FW_LDST_CMD_MSG) 5578 #define G_FW_LDST_CMD_MSG(x) \ 5579 (((x) >> S_FW_LDST_CMD_MSG) & M_FW_LDST_CMD_MSG) 5580 #define F_FW_LDST_CMD_MSG V_FW_LDST_CMD_MSG(1U) 5581 5582 #define S_FW_LDST_CMD_CTXTFLUSH 30 5583 #define M_FW_LDST_CMD_CTXTFLUSH 0x1 5584 #define V_FW_LDST_CMD_CTXTFLUSH(x) ((x) << S_FW_LDST_CMD_CTXTFLUSH) 5585 #define G_FW_LDST_CMD_CTXTFLUSH(x) \ 5586 (((x) >> S_FW_LDST_CMD_CTXTFLUSH) & M_FW_LDST_CMD_CTXTFLUSH) 5587 #define F_FW_LDST_CMD_CTXTFLUSH V_FW_LDST_CMD_CTXTFLUSH(1U) 5588 5589 #define S_FW_LDST_CMD_PADDR 8 5590 #define M_FW_LDST_CMD_PADDR 0x1f 5591 #define V_FW_LDST_CMD_PADDR(x) ((x) << S_FW_LDST_CMD_PADDR) 5592 #define G_FW_LDST_CMD_PADDR(x) \ 5593 (((x) >> S_FW_LDST_CMD_PADDR) & M_FW_LDST_CMD_PADDR) 5594 5595 #define S_FW_LDST_CMD_MMD 0 5596 #define M_FW_LDST_CMD_MMD 0x1f 5597 #define V_FW_LDST_CMD_MMD(x) ((x) << S_FW_LDST_CMD_MMD) 5598 #define G_FW_LDST_CMD_MMD(x) \ 5599 (((x) >> S_FW_LDST_CMD_MMD) & M_FW_LDST_CMD_MMD) 5600 5601 #define S_FW_LDST_CMD_FID 15 5602 #define M_FW_LDST_CMD_FID 0x1 5603 #define V_FW_LDST_CMD_FID(x) ((x) << S_FW_LDST_CMD_FID) 5604 #define G_FW_LDST_CMD_FID(x) \ 5605 (((x) >> S_FW_LDST_CMD_FID) & M_FW_LDST_CMD_FID) 5606 #define F_FW_LDST_CMD_FID V_FW_LDST_CMD_FID(1U) 5607 5608 #define S_FW_LDST_CMD_IDX 0 5609 #define M_FW_LDST_CMD_IDX 0x7fff 5610 #define V_FW_LDST_CMD_IDX(x) ((x) << S_FW_LDST_CMD_IDX) 5611 #define G_FW_LDST_CMD_IDX(x) \ 5612 (((x) >> S_FW_LDST_CMD_IDX) & M_FW_LDST_CMD_IDX) 5613 5614 #define S_FW_LDST_CMD_RPLCPF 0 5615 #define M_FW_LDST_CMD_RPLCPF 0xff 5616 #define V_FW_LDST_CMD_RPLCPF(x) ((x) << S_FW_LDST_CMD_RPLCPF) 5617 #define G_FW_LDST_CMD_RPLCPF(x) \ 5618 (((x) >> S_FW_LDST_CMD_RPLCPF) & M_FW_LDST_CMD_RPLCPF) 5619 5620 #define S_FW_LDST_CMD_MPSID 0 5621 #define M_FW_LDST_CMD_MPSID 0x7fff 5622 #define V_FW_LDST_CMD_MPSID(x) ((x) << S_FW_LDST_CMD_MPSID) 5623 #define G_FW_LDST_CMD_MPSID(x) \ 5624 (((x) >> S_FW_LDST_CMD_MPSID) & M_FW_LDST_CMD_MPSID) 5625 5626 #define S_FW_LDST_CMD_CTRL 7 5627 #define M_FW_LDST_CMD_CTRL 0x1 5628 #define V_FW_LDST_CMD_CTRL(x) ((x) << S_FW_LDST_CMD_CTRL) 5629 #define G_FW_LDST_CMD_CTRL(x) \ 5630 (((x) >> S_FW_LDST_CMD_CTRL) & M_FW_LDST_CMD_CTRL) 5631 #define F_FW_LDST_CMD_CTRL V_FW_LDST_CMD_CTRL(1U) 5632 5633 #define S_FW_LDST_CMD_LC 4 5634 #define M_FW_LDST_CMD_LC 0x1 5635 #define V_FW_LDST_CMD_LC(x) ((x) << S_FW_LDST_CMD_LC) 5636 #define G_FW_LDST_CMD_LC(x) \ 5637 (((x) >> S_FW_LDST_CMD_LC) & M_FW_LDST_CMD_LC) 5638 #define F_FW_LDST_CMD_LC V_FW_LDST_CMD_LC(1U) 5639 5640 #define S_FW_LDST_CMD_AI 3 5641 #define M_FW_LDST_CMD_AI 0x1 5642 #define V_FW_LDST_CMD_AI(x) ((x) << S_FW_LDST_CMD_AI) 5643 #define G_FW_LDST_CMD_AI(x) \ 5644 (((x) >> S_FW_LDST_CMD_AI) & M_FW_LDST_CMD_AI) 5645 #define F_FW_LDST_CMD_AI V_FW_LDST_CMD_AI(1U) 5646 5647 #define S_FW_LDST_CMD_FN 0 5648 #define M_FW_LDST_CMD_FN 0x7 5649 #define V_FW_LDST_CMD_FN(x) ((x) << S_FW_LDST_CMD_FN) 5650 #define G_FW_LDST_CMD_FN(x) \ 5651 (((x) >> S_FW_LDST_CMD_FN) & M_FW_LDST_CMD_FN) 5652 5653 #define S_FW_LDST_CMD_SELECT 4 5654 #define M_FW_LDST_CMD_SELECT 0xf 5655 #define V_FW_LDST_CMD_SELECT(x) ((x) << S_FW_LDST_CMD_SELECT) 5656 #define G_FW_LDST_CMD_SELECT(x) \ 5657 (((x) >> S_FW_LDST_CMD_SELECT) & M_FW_LDST_CMD_SELECT) 5658 5659 #define S_FW_LDST_CMD_NACCESS 0 5660 #define M_FW_LDST_CMD_NACCESS 0xf 5661 #define V_FW_LDST_CMD_NACCESS(x) ((x) << S_FW_LDST_CMD_NACCESS) 5662 #define G_FW_LDST_CMD_NACCESS(x) \ 5663 (((x) >> S_FW_LDST_CMD_NACCESS) & M_FW_LDST_CMD_NACCESS) 5664 5665 #define S_FW_LDST_CMD_NSET 14 5666 #define M_FW_LDST_CMD_NSET 0x3 5667 #define V_FW_LDST_CMD_NSET(x) ((x) << S_FW_LDST_CMD_NSET) 5668 #define G_FW_LDST_CMD_NSET(x) \ 5669 (((x) >> S_FW_LDST_CMD_NSET) & M_FW_LDST_CMD_NSET) 5670 5671 #define S_FW_LDST_CMD_PID 6 5672 #define M_FW_LDST_CMD_PID 0x3 5673 #define V_FW_LDST_CMD_PID(x) ((x) << S_FW_LDST_CMD_PID) 5674 #define G_FW_LDST_CMD_PID(x) \ 5675 (((x) >> S_FW_LDST_CMD_PID) & M_FW_LDST_CMD_PID) 5676 5677 struct fw_reset_cmd { 5678 __be32 op_to_write; 5679 __be32 retval_len16; 5680 __be32 val; 5681 __be32 halt_pkd; 5682 }; 5683 5684 #define S_FW_RESET_CMD_HALT 31 5685 #define M_FW_RESET_CMD_HALT 0x1 5686 #define V_FW_RESET_CMD_HALT(x) ((x) << S_FW_RESET_CMD_HALT) 5687 #define G_FW_RESET_CMD_HALT(x) \ 5688 (((x) >> S_FW_RESET_CMD_HALT) & M_FW_RESET_CMD_HALT) 5689 #define F_FW_RESET_CMD_HALT V_FW_RESET_CMD_HALT(1U) 5690 5691 enum { 5692 FW_HELLO_CMD_STAGE_OS = 0, 5693 FW_HELLO_CMD_STAGE_PREOS0 = 1, 5694 FW_HELLO_CMD_STAGE_PREOS1 = 2, 5695 FW_HELLO_CMD_STAGE_POSTOS = 3, 5696 }; 5697 5698 struct fw_hello_cmd { 5699 __be32 op_to_write; 5700 __be32 retval_len16; 5701 __be32 err_to_clearinit; 5702 __be32 fwrev; 5703 }; 5704 5705 #define S_FW_HELLO_CMD_ERR 31 5706 #define M_FW_HELLO_CMD_ERR 0x1 5707 #define V_FW_HELLO_CMD_ERR(x) ((x) << S_FW_HELLO_CMD_ERR) 5708 #define G_FW_HELLO_CMD_ERR(x) \ 5709 (((x) >> S_FW_HELLO_CMD_ERR) & M_FW_HELLO_CMD_ERR) 5710 #define F_FW_HELLO_CMD_ERR V_FW_HELLO_CMD_ERR(1U) 5711 5712 #define S_FW_HELLO_CMD_INIT 30 5713 #define M_FW_HELLO_CMD_INIT 0x1 5714 #define V_FW_HELLO_CMD_INIT(x) ((x) << S_FW_HELLO_CMD_INIT) 5715 #define G_FW_HELLO_CMD_INIT(x) \ 5716 (((x) >> S_FW_HELLO_CMD_INIT) & M_FW_HELLO_CMD_INIT) 5717 #define F_FW_HELLO_CMD_INIT V_FW_HELLO_CMD_INIT(1U) 5718 5719 #define S_FW_HELLO_CMD_MASTERDIS 29 5720 #define M_FW_HELLO_CMD_MASTERDIS 0x1 5721 #define V_FW_HELLO_CMD_MASTERDIS(x) ((x) << S_FW_HELLO_CMD_MASTERDIS) 5722 #define G_FW_HELLO_CMD_MASTERDIS(x) \ 5723 (((x) >> S_FW_HELLO_CMD_MASTERDIS) & M_FW_HELLO_CMD_MASTERDIS) 5724 #define F_FW_HELLO_CMD_MASTERDIS V_FW_HELLO_CMD_MASTERDIS(1U) 5725 5726 #define S_FW_HELLO_CMD_MASTERFORCE 28 5727 #define M_FW_HELLO_CMD_MASTERFORCE 0x1 5728 #define V_FW_HELLO_CMD_MASTERFORCE(x) ((x) << S_FW_HELLO_CMD_MASTERFORCE) 5729 #define G_FW_HELLO_CMD_MASTERFORCE(x) \ 5730 (((x) >> S_FW_HELLO_CMD_MASTERFORCE) & M_FW_HELLO_CMD_MASTERFORCE) 5731 #define F_FW_HELLO_CMD_MASTERFORCE V_FW_HELLO_CMD_MASTERFORCE(1U) 5732 5733 #define S_FW_HELLO_CMD_MBMASTER 24 5734 #define M_FW_HELLO_CMD_MBMASTER 0xf 5735 #define V_FW_HELLO_CMD_MBMASTER(x) ((x) << S_FW_HELLO_CMD_MBMASTER) 5736 #define G_FW_HELLO_CMD_MBMASTER(x) \ 5737 (((x) >> S_FW_HELLO_CMD_MBMASTER) & M_FW_HELLO_CMD_MBMASTER) 5738 5739 #define S_FW_HELLO_CMD_MBASYNCNOTINT 23 5740 #define M_FW_HELLO_CMD_MBASYNCNOTINT 0x1 5741 #define V_FW_HELLO_CMD_MBASYNCNOTINT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOTINT) 5742 #define G_FW_HELLO_CMD_MBASYNCNOTINT(x) \ 5743 (((x) >> S_FW_HELLO_CMD_MBASYNCNOTINT) & M_FW_HELLO_CMD_MBASYNCNOTINT) 5744 #define F_FW_HELLO_CMD_MBASYNCNOTINT V_FW_HELLO_CMD_MBASYNCNOTINT(1U) 5745 5746 #define S_FW_HELLO_CMD_MBASYNCNOT 20 5747 #define M_FW_HELLO_CMD_MBASYNCNOT 0x7 5748 #define V_FW_HELLO_CMD_MBASYNCNOT(x) ((x) << S_FW_HELLO_CMD_MBASYNCNOT) 5749 #define G_FW_HELLO_CMD_MBASYNCNOT(x) \ 5750 (((x) >> S_FW_HELLO_CMD_MBASYNCNOT) & M_FW_HELLO_CMD_MBASYNCNOT) 5751 5752 #define S_FW_HELLO_CMD_STAGE 17 5753 #define M_FW_HELLO_CMD_STAGE 0x7 5754 #define V_FW_HELLO_CMD_STAGE(x) ((x) << S_FW_HELLO_CMD_STAGE) 5755 #define G_FW_HELLO_CMD_STAGE(x) \ 5756 (((x) >> S_FW_HELLO_CMD_STAGE) & M_FW_HELLO_CMD_STAGE) 5757 5758 #define S_FW_HELLO_CMD_CLEARINIT 16 5759 #define M_FW_HELLO_CMD_CLEARINIT 0x1 5760 #define V_FW_HELLO_CMD_CLEARINIT(x) ((x) << S_FW_HELLO_CMD_CLEARINIT) 5761 #define G_FW_HELLO_CMD_CLEARINIT(x) \ 5762 (((x) >> S_FW_HELLO_CMD_CLEARINIT) & M_FW_HELLO_CMD_CLEARINIT) 5763 #define F_FW_HELLO_CMD_CLEARINIT V_FW_HELLO_CMD_CLEARINIT(1U) 5764 5765 struct fw_bye_cmd { 5766 __be32 op_to_write; 5767 __be32 retval_len16; 5768 __be64 r3; 5769 }; 5770 5771 struct fw_initialize_cmd { 5772 __be32 op_to_write; 5773 __be32 retval_len16; 5774 __be64 r3; 5775 }; 5776 5777 enum fw_caps_config_hm { 5778 FW_CAPS_CONFIG_HM_PCIE = 0x00000001, 5779 FW_CAPS_CONFIG_HM_PL = 0x00000002, 5780 FW_CAPS_CONFIG_HM_SGE = 0x00000004, 5781 FW_CAPS_CONFIG_HM_CIM = 0x00000008, 5782 FW_CAPS_CONFIG_HM_ULPTX = 0x00000010, 5783 FW_CAPS_CONFIG_HM_TP = 0x00000020, 5784 FW_CAPS_CONFIG_HM_ULPRX = 0x00000040, 5785 FW_CAPS_CONFIG_HM_PMRX = 0x00000080, 5786 FW_CAPS_CONFIG_HM_PMTX = 0x00000100, 5787 FW_CAPS_CONFIG_HM_MC = 0x00000200, 5788 FW_CAPS_CONFIG_HM_LE = 0x00000400, 5789 FW_CAPS_CONFIG_HM_MPS = 0x00000800, 5790 FW_CAPS_CONFIG_HM_XGMAC = 0x00001000, 5791 FW_CAPS_CONFIG_HM_CPLSWITCH = 0x00002000, 5792 FW_CAPS_CONFIG_HM_T4DBG = 0x00004000, 5793 FW_CAPS_CONFIG_HM_MI = 0x00008000, 5794 FW_CAPS_CONFIG_HM_I2CM = 0x00010000, 5795 FW_CAPS_CONFIG_HM_NCSI = 0x00020000, 5796 FW_CAPS_CONFIG_HM_SMB = 0x00040000, 5797 FW_CAPS_CONFIG_HM_MA = 0x00080000, 5798 FW_CAPS_CONFIG_HM_EDRAM = 0x00100000, 5799 FW_CAPS_CONFIG_HM_PMU = 0x00200000, 5800 FW_CAPS_CONFIG_HM_UART = 0x00400000, 5801 FW_CAPS_CONFIG_HM_SF = 0x00800000, 5802 }; 5803 5804 /* 5805 * The VF Register Map. 5806 * 5807 * The Scatter Gather Engine (SGE), Multiport Support module (MPS), PIO Local 5808 * bus module (PL) and CPU Interface Module (CIM) components are mapped via 5809 * the Slice to Module Map Table (see below) in the Physical Function Register 5810 * Map. The Mail Box Data (MBDATA) range is mapped via the PCI-E Mailbox Base 5811 * and Offset registers in the PF Register Map. The MBDATA base address is 5812 * quite constrained as it determines the Mailbox Data addresses for both PFs 5813 * and VFs, and therefore must fit in both the VF and PF Register Maps without 5814 * overlapping other registers. 5815 */ 5816 #define FW_T4VF_SGE_BASE_ADDR 0x0000 5817 #define FW_T4VF_MPS_BASE_ADDR 0x0100 5818 #define FW_T4VF_PL_BASE_ADDR 0x0200 5819 #define FW_T4VF_MBDATA_BASE_ADDR 0x0240 5820 #define FW_T6VF_MBDATA_BASE_ADDR 0x0280 /* aligned to mbox size 128B */ 5821 #define FW_T4VF_CIM_BASE_ADDR 0x0300 5822 5823 #define FW_T4VF_REGMAP_START 0x0000 5824 #define FW_T4VF_REGMAP_SIZE 0x0400 5825 5826 enum fw_caps_config_nbm { 5827 FW_CAPS_CONFIG_NBM_IPMI = 0x00000001, 5828 FW_CAPS_CONFIG_NBM_NCSI = 0x00000002, 5829 }; 5830 5831 enum fw_caps_config_link { 5832 FW_CAPS_CONFIG_LINK_PPP = 0x00000001, 5833 FW_CAPS_CONFIG_LINK_QFC = 0x00000002, 5834 FW_CAPS_CONFIG_LINK_DCBX = 0x00000004, 5835 }; 5836 5837 enum fw_caps_config_switch { 5838 FW_CAPS_CONFIG_SWITCH_INGRESS = 0x00000001, 5839 FW_CAPS_CONFIG_SWITCH_EGRESS = 0x00000002, 5840 }; 5841 5842 enum fw_caps_config_nic { 5843 FW_CAPS_CONFIG_NIC = 0x00000001, 5844 FW_CAPS_CONFIG_NIC_VM = 0x00000002, 5845 FW_CAPS_CONFIG_NIC_IDS = 0x00000004, 5846 FW_CAPS_CONFIG_NIC_UM = 0x00000008, 5847 FW_CAPS_CONFIG_NIC_UM_ISGL = 0x00000010, 5848 FW_CAPS_CONFIG_NIC_HASHFILTER = 0x00000020, 5849 FW_CAPS_CONFIG_NIC_ETHOFLD = 0x00000040, 5850 }; 5851 5852 enum fw_caps_config_toe { 5853 FW_CAPS_CONFIG_TOE = 0x00000001, 5854 FW_CAPS_CONFIG_TOE_SENDPATH = 0x00000002, 5855 }; 5856 5857 enum fw_caps_config_rdma { 5858 FW_CAPS_CONFIG_RDMA_RDDP = 0x00000001, 5859 FW_CAPS_CONFIG_RDMA_RDMAC = 0x00000002, 5860 FW_CAPS_CONFIG_RDMA_ROCEV2 = 0x00000004, 5861 }; 5862 5863 enum fw_caps_config_nvme { 5864 FW_CAPS_CONFIG_NVME_TCP = 0x00000001, 5865 }; 5866 5867 enum fw_caps_config_iscsi { 5868 FW_CAPS_CONFIG_ISCSI_INITIATOR_PDU = 0x00000001, 5869 FW_CAPS_CONFIG_ISCSI_TARGET_PDU = 0x00000002, 5870 FW_CAPS_CONFIG_ISCSI_INITIATOR_CNXOFLD = 0x00000004, 5871 FW_CAPS_CONFIG_ISCSI_TARGET_CNXOFLD = 0x00000008, 5872 FW_CAPS_CONFIG_ISCSI_INITIATOR_SSNOFLD = 0x00000010, 5873 FW_CAPS_CONFIG_ISCSI_TARGET_SSNOFLD = 0x00000020, 5874 FW_CAPS_CONFIG_ISCSI_T10DIF = 0x00000040, 5875 FW_CAPS_CONFIG_ISCSI_INITIATOR_CMDOFLD = 0x00000080, 5876 FW_CAPS_CONFIG_ISCSI_TARGET_CMDOFLD = 0x00000100, 5877 }; 5878 5879 enum fw_caps_config_crypto { 5880 FW_CAPS_CONFIG_CRYPTO_LOOKASIDE = 0x00000001, 5881 FW_CAPS_CONFIG_TLSKEYS = 0x00000002, 5882 FW_CAPS_CONFIG_IPSEC_INLINE = 0x00000004, /* NIC over ipsecofld */ 5883 FW_CAPS_CONFIG_TLS_HW = 0x00000008, 5884 FW_CAPS_CONFIG_OFLD_OVER_IPSEC_INLINE = 0x00000010,/* ofld over ipsecofld */ 5885 }; 5886 5887 enum fw_caps_config_fcoe { 5888 FW_CAPS_CONFIG_FCOE_INITIATOR = 0x00000001, 5889 FW_CAPS_CONFIG_FCOE_TARGET = 0x00000002, 5890 FW_CAPS_CONFIG_FCOE_CTRL_OFLD = 0x00000004, 5891 FW_CAPS_CONFIG_POFCOE_INITIATOR = 0x00000008, 5892 FW_CAPS_CONFIG_POFCOE_TARGET = 0x00000010, 5893 }; 5894 5895 enum fw_memtype_cf { 5896 FW_MEMTYPE_CF_EDC0 = FW_MEMTYPE_EDC0, 5897 FW_MEMTYPE_CF_EDC1 = FW_MEMTYPE_EDC1, 5898 FW_MEMTYPE_CF_EXTMEM = FW_MEMTYPE_EXTMEM, 5899 FW_MEMTYPE_CF_FLASH = FW_MEMTYPE_FLASH, 5900 FW_MEMTYPE_CF_INTERNAL = FW_MEMTYPE_INTERNAL, 5901 FW_MEMTYPE_CF_EXTMEM1 = FW_MEMTYPE_EXTMEM1, 5902 }; 5903 5904 struct fw_caps_config_cmd { 5905 __be32 op_to_write; 5906 __be32 cfvalid_to_len16; 5907 __be32 r2; 5908 __be32 hwmbitmap; 5909 __be16 nbmcaps; 5910 __be16 linkcaps; 5911 __be16 switchcaps; 5912 __be16 nvmecaps; 5913 __be16 niccaps; 5914 __be16 toecaps; 5915 __be16 rdmacaps; 5916 __be16 cryptocaps; 5917 __be16 iscsicaps; 5918 __be16 fcoecaps; 5919 __be32 cfcsum; 5920 __be32 finiver; 5921 __be32 finicsum; 5922 }; 5923 5924 #define S_FW_CAPS_CONFIG_CMD_CFVALID 27 5925 #define M_FW_CAPS_CONFIG_CMD_CFVALID 0x1 5926 #define V_FW_CAPS_CONFIG_CMD_CFVALID(x) ((x) << S_FW_CAPS_CONFIG_CMD_CFVALID) 5927 #define G_FW_CAPS_CONFIG_CMD_CFVALID(x) \ 5928 (((x) >> S_FW_CAPS_CONFIG_CMD_CFVALID) & M_FW_CAPS_CONFIG_CMD_CFVALID) 5929 #define F_FW_CAPS_CONFIG_CMD_CFVALID V_FW_CAPS_CONFIG_CMD_CFVALID(1U) 5930 5931 #define S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 24 5932 #define M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF 0x7 5933 #define V_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 5934 ((x) << S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 5935 #define G_FW_CAPS_CONFIG_CMD_MEMTYPE_CF(x) \ 5936 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) & \ 5937 M_FW_CAPS_CONFIG_CMD_MEMTYPE_CF) 5938 5939 #define S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 16 5940 #define M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF 0xff 5941 #define V_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 5942 ((x) << S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 5943 #define G_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF(x) \ 5944 (((x) >> S_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) & \ 5945 M_FW_CAPS_CONFIG_CMD_MEMADDR64K_CF) 5946 5947 /* 5948 * params command mnemonics 5949 */ 5950 enum fw_params_mnem { 5951 FW_PARAMS_MNEM_DEV = 1, /* device params */ 5952 FW_PARAMS_MNEM_PFVF = 2, /* function params */ 5953 FW_PARAMS_MNEM_REG = 3, /* limited register access */ 5954 FW_PARAMS_MNEM_DMAQ = 4, /* dma queue params */ 5955 FW_PARAMS_MNEM_CHNET = 5, /* chnet params */ 5956 FW_PARAMS_MNEM_LAST 5957 }; 5958 5959 /* 5960 * device parameters 5961 */ 5962 #define S_FW_PARAMS_PARAM_FILTER_MODE 16 5963 #define M_FW_PARAMS_PARAM_FILTER_MODE 0xffff 5964 #define V_FW_PARAMS_PARAM_FILTER_MODE(x) \ 5965 ((x) << S_FW_PARAMS_PARAM_FILTER_MODE) 5966 #define G_FW_PARAMS_PARAM_FILTER_MODE(x) \ 5967 (((x) >> S_FW_PARAMS_PARAM_FILTER_MODE) & \ 5968 M_FW_PARAMS_PARAM_FILTER_MODE) 5969 5970 #define S_FW_PARAMS_PARAM_FILTER_MASK 0 5971 #define M_FW_PARAMS_PARAM_FILTER_MASK 0xffff 5972 #define V_FW_PARAMS_PARAM_FILTER_MASK(x) \ 5973 ((x) << S_FW_PARAMS_PARAM_FILTER_MASK) 5974 #define G_FW_PARAMS_PARAM_FILTER_MASK(x) \ 5975 (((x) >> S_FW_PARAMS_PARAM_FILTER_MASK) & \ 5976 M_FW_PARAMS_PARAM_FILTER_MASK) 5977 5978 enum fw_params_param_dev { 5979 FW_PARAMS_PARAM_DEV_CCLK = 0x00, /* chip core clock in khz */ 5980 FW_PARAMS_PARAM_DEV_PORTVEC = 0x01, /* the port vector */ 5981 FW_PARAMS_PARAM_DEV_NTID = 0x02, /* reads the number of TIDs 5982 * allocated by the device's 5983 * Lookup Engine 5984 */ 5985 FW_PARAMS_PARAM_DEV_FLOWC_BUFFIFO_SZ = 0x03, 5986 FW_PARAMS_PARAM_DEV_INTFVER_NIC = 0x04, 5987 FW_PARAMS_PARAM_DEV_INTFVER_VNIC = 0x05, 5988 FW_PARAMS_PARAM_DEV_INTFVER_OFLD = 0x06, 5989 FW_PARAMS_PARAM_DEV_INTFVER_RI = 0x07, 5990 FW_PARAMS_PARAM_DEV_INTFVER_ISCSIPDU = 0x08, 5991 FW_PARAMS_PARAM_DEV_INTFVER_ISCSI = 0x09, 5992 FW_PARAMS_PARAM_DEV_INTFVER_FCOE = 0x0A, 5993 FW_PARAMS_PARAM_DEV_FWREV = 0x0B, 5994 FW_PARAMS_PARAM_DEV_TPREV = 0x0C, 5995 FW_PARAMS_PARAM_DEV_CF = 0x0D, 5996 FW_PARAMS_PARAM_DEV_BYPASS = 0x0E, 5997 FW_PARAMS_PARAM_DEV_PHYFW = 0x0F, 5998 FW_PARAMS_PARAM_DEV_LOAD = 0x10, 5999 FW_PARAMS_PARAM_DEV_DIAG = 0x11, 6000 FW_PARAMS_PARAM_DEV_UCLK = 0x12, /* uP clock in khz */ 6001 FW_PARAMS_PARAM_DEV_MAXORDIRD_QP = 0x13, /* max supported QP IRD/ORD 6002 */ 6003 FW_PARAMS_PARAM_DEV_MAXIRD_ADAPTER= 0x14,/* max supported ADAPTER IRD 6004 */ 6005 FW_PARAMS_PARAM_DEV_INTFVER_FCOEPDU = 0x15, 6006 FW_PARAMS_PARAM_DEV_MCINIT = 0x16, 6007 FW_PARAMS_PARAM_DEV_ULPTX_MEMWRITE_DSGL = 0x17, 6008 FW_PARAMS_PARAM_DEV_FWCACHE = 0x18, 6009 FW_PARAMS_PARAM_DEV_RSSINFO = 0x19, 6010 FW_PARAMS_PARAM_DEV_SCFGREV = 0x1A, 6011 FW_PARAMS_PARAM_DEV_VPDREV = 0x1B, 6012 FW_PARAMS_PARAM_DEV_RI_FR_NSMR_TPTE_WR = 0x1C, 6013 FW_PARAMS_PARAM_DEV_FILTER2_WR = 0x1D, 6014 6015 FW_PARAMS_PARAM_DEV_MPSBGMAP = 0x1E, 6016 FW_PARAMS_PARAM_DEV_TPCHMAP = 0x1F, 6017 FW_PARAMS_PARAM_DEV_HMA_SIZE = 0x20, 6018 FW_PARAMS_PARAM_DEV_RDMA_WRITE_WITH_IMM = 0x21, 6019 FW_PARAMS_PARAM_DEV_RING_BACKBONE = 0x22, 6020 FW_PARAMS_PARAM_DEV_PPOD_EDRAM = 0x23, 6021 FW_PARAMS_PARAM_DEV_RI_WRITE_CMPL_WR = 0x24, 6022 FW_PARAMS_PARAM_DEV_ADD_SMAC = 0x25, 6023 FW_PARAMS_PARAM_DEV_HPFILTER_REGION_SUPPORT = 0x26, 6024 FW_PARAMS_PARAM_DEV_OPAQUE_VIID_SMT_EXTN = 0x27, 6025 FW_PARAMS_PARAM_DEV_HASHFILTER_WITH_OFLD = 0x28, 6026 FW_PARAMS_PARAM_DEV_DBQ_TIMER = 0x29, 6027 FW_PARAMS_PARAM_DEV_DBQ_TIMERTICK = 0x2A, 6028 FW_PARAMS_PARAM_DEV_NUM_TM_CLASS = 0x2B, 6029 FW_PARAMS_PARAM_DEV_VF_TRVLAN = 0x2C, 6030 FW_PARAMS_PARAM_DEV_TCB_CACHE_FLUSH = 0x2D, 6031 FW_PARAMS_PARAM_DEV_FILTER = 0x2E, 6032 FW_PARAMS_PARAM_DEV_CLIP2_CMD = 0x2F, 6033 FW_PARAMS_PARAM_DEV_DEV_512SGL_MR = 0x30, 6034 FW_PARAMS_PARAM_DEV_KTLS_HW = 0x31, 6035 FW_PARAMS_PARAM_DEV_VI_ENABLE_INGRESS_AFTER_LINKUP = 0x32, 6036 FW_PARAMS_PARAM_DEV_TID_QID_SEL_MASK = 0x33, 6037 FW_PARAMS_PARAM_DEV_TX_TPCHMAP = 0x3A, 6038 }; 6039 6040 /* 6041 * dev bypass parameters; actions and modes 6042 */ 6043 enum fw_params_param_dev_bypass { 6044 6045 /* actions 6046 */ 6047 FW_PARAMS_PARAM_DEV_BYPASS_PFAIL = 0x00, 6048 FW_PARAMS_PARAM_DEV_BYPASS_CURRENT = 0x01, 6049 6050 /* modes 6051 */ 6052 FW_PARAMS_PARAM_DEV_BYPASS_NORMAL = 0x00, 6053 FW_PARAMS_PARAM_DEV_BYPASS_DROP = 0x1, 6054 FW_PARAMS_PARAM_DEV_BYPASS_BYPASS = 0x2, 6055 }; 6056 6057 enum fw_params_param_dev_phyfw { 6058 FW_PARAMS_PARAM_DEV_PHYFW_DOWNLOAD = 0x00, 6059 FW_PARAMS_PARAM_DEV_PHYFW_VERSION = 0x01, 6060 }; 6061 6062 enum fw_params_param_dev_diag { 6063 FW_PARAM_DEV_DIAG_TMP = 0x00, 6064 FW_PARAM_DEV_DIAG_VDD = 0x01, 6065 FW_PARAM_DEV_DIAG_MAXTMPTHRESH = 0x02, 6066 FW_PARAM_DEV_DIAG_RESET_TMP_SENSOR = 0x03, 6067 }; 6068 6069 enum fw_params_param_dev_filter{ 6070 FW_PARAM_DEV_FILTER_VNIC_MODE = 0x00, 6071 FW_PARAM_DEV_FILTER_MODE_MASK = 0x01, 6072 }; 6073 6074 enum fw_filter_vnic_mode { 6075 FW_VNIC_MODE_PF_VF = 0, 6076 FW_VNIC_MODE_OUTER_VLAN = 1, 6077 FW_VNIC_MODE_ENCAP_EN = 2, 6078 }; 6079 6080 enum fw_params_param_dev_ktls_hw { 6081 FW_PARAMS_PARAM_DEV_KTLS_HW_DISABLE = 0x00, 6082 FW_PARAMS_PARAM_DEV_KTLS_HW_ENABLE = 0x01, 6083 FW_PARAMS_PARAM_DEV_KTLS_HW_USER_DISABLE = 0x00, 6084 FW_PARAMS_PARAM_DEV_KTLS_HW_USER_ENABLE = 0x01, 6085 }; 6086 6087 enum fw_params_param_dev_fwcache { 6088 FW_PARAM_DEV_FWCACHE_FLUSH = 0x00, 6089 FW_PARAM_DEV_FWCACHE_FLUSHINV = 0x01, 6090 }; 6091 6092 /* 6093 * physical and virtual function parameters 6094 */ 6095 enum fw_params_param_pfvf { 6096 FW_PARAMS_PARAM_PFVF_RWXCAPS = 0x00, 6097 FW_PARAMS_PARAM_PFVF_ROUTE_START = 0x01, 6098 FW_PARAMS_PARAM_PFVF_ROUTE_END = 0x02, 6099 FW_PARAMS_PARAM_PFVF_CLIP_START = 0x03, 6100 FW_PARAMS_PARAM_PFVF_CLIP_END = 0x04, 6101 FW_PARAMS_PARAM_PFVF_FILTER_START = 0x05, 6102 FW_PARAMS_PARAM_PFVF_FILTER_END = 0x06, 6103 FW_PARAMS_PARAM_PFVF_SERVER_START = 0x07, 6104 FW_PARAMS_PARAM_PFVF_SERVER_END = 0x08, 6105 FW_PARAMS_PARAM_PFVF_TDDP_START = 0x09, 6106 FW_PARAMS_PARAM_PFVF_TDDP_END = 0x0A, 6107 FW_PARAMS_PARAM_PFVF_ISCSI_START = 0x0B, 6108 FW_PARAMS_PARAM_PFVF_ISCSI_END = 0x0C, 6109 /* no separate STAG/PBL START/END for nvmet. 6110 * use same rdma stag/pbl memory range */ 6111 FW_PARAMS_PARAM_PFVF_STAG_START = 0x0D, 6112 FW_PARAMS_PARAM_PFVF_STAG_END = 0x0E, 6113 FW_PARAMS_PARAM_PFVF_RQ_START = 0x1F, 6114 FW_PARAMS_PARAM_PFVF_RQ_END = 0x10, 6115 FW_PARAMS_PARAM_PFVF_PBL_START = 0x11, 6116 FW_PARAMS_PARAM_PFVF_PBL_END = 0x12, 6117 FW_PARAMS_PARAM_PFVF_L2T_START = 0x13, 6118 FW_PARAMS_PARAM_PFVF_L2T_END = 0x14, 6119 FW_PARAMS_PARAM_PFVF_SQRQ_START = 0x15, 6120 FW_PARAMS_PARAM_PFVF_SQRQ_END = 0x16, 6121 FW_PARAMS_PARAM_PFVF_CQ_START = 0x17, 6122 FW_PARAMS_PARAM_PFVF_CQ_END = 0x18, 6123 FW_PARAMS_PARAM_PFVF_SRQ_START = 0x19, 6124 FW_PARAMS_PARAM_PFVF_SRQ_END = 0x1A, 6125 FW_PARAMS_PARAM_PFVF_SCHEDCLASS_ETH = 0x20, 6126 FW_PARAMS_PARAM_PFVF_VIID = 0x24, 6127 FW_PARAMS_PARAM_PFVF_CPMASK = 0x25, 6128 FW_PARAMS_PARAM_PFVF_OCQ_START = 0x26, 6129 FW_PARAMS_PARAM_PFVF_OCQ_END = 0x27, 6130 FW_PARAMS_PARAM_PFVF_CONM_MAP = 0x28, 6131 FW_PARAMS_PARAM_PFVF_IQFLINT_START = 0x29, 6132 FW_PARAMS_PARAM_PFVF_IQFLINT_END = 0x2A, 6133 FW_PARAMS_PARAM_PFVF_EQ_START = 0x2B, 6134 FW_PARAMS_PARAM_PFVF_EQ_END = 0x2C, 6135 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_START = 0x2D, 6136 FW_PARAMS_PARAM_PFVF_ACTIVE_FILTER_END = 0x2E, 6137 FW_PARAMS_PARAM_PFVF_ETHOFLD_START = 0x2F, 6138 FW_PARAMS_PARAM_PFVF_ETHOFLD_END = 0x30, 6139 FW_PARAMS_PARAM_PFVF_CPLFW4MSG_ENCAP = 0x31, 6140 FW_PARAMS_PARAM_PFVF_HPFILTER_START = 0x32, 6141 FW_PARAMS_PARAM_PFVF_HPFILTER_END = 0x33, 6142 FW_PARAMS_PARAM_PFVF_TLS_START = 0x34, 6143 FW_PARAMS_PARAM_PFVF_TLS_END = 0x35, 6144 FW_PARAMS_PARAM_PFVF_RAWF_START = 0x36, 6145 FW_PARAMS_PARAM_PFVF_RAWF_END = 0x37, 6146 FW_PARAMS_PARAM_PFVF_RSSKEYINFO = 0x38, 6147 FW_PARAMS_PARAM_PFVF_NCRYPTO_LOOKASIDE = 0x39, 6148 FW_PARAMS_PARAM_PFVF_PORT_CAPS32 = 0x3A, 6149 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_START = 0x3B, 6150 FW_PARAMS_PARAM_PFVF_PPOD_EDRAM_END = 0x3C, 6151 FW_PARAMS_PARAM_PFVF_MAX_PKTS_PER_ETH_TX_PKTS_WR = 0x3D, 6152 FW_PARAMS_PARAM_PFVF_GET_SMT_START = 0x3E, 6153 FW_PARAMS_PARAM_PFVF_GET_SMT_SIZE = 0x3F, 6154 FW_PARAMS_PARAM_PFVF_LINK_STATE = 0x40, 6155 FW_PARAMS_PARAM_PFVF_RRQ_START = 0x41, 6156 FW_PARAMS_PARAM_PFVF_RRQ_END = 0x42, 6157 FW_PARAMS_PARAM_PFVF_PKTHDR_START = 0x43, 6158 FW_PARAMS_PARAM_PFVF_PKTHDR_END = 0x44, 6159 FW_PARAMS_PARAM_PFVF_NIPSEC_TUNNEL = 0x45, 6160 FW_PARAMS_PARAM_PFVF_NIPSEC_TRANSPORT = 0x46, 6161 FW_PARAMS_PARAM_PFVF_OFLD_NIPSEC_TUNNEL = 0x47, 6162 }; 6163 6164 /* 6165 * virtual link state as seen by the specified VF 6166 */ 6167 enum vf_link_states { 6168 VF_LINK_STATE_AUTO = 0x00, 6169 VF_LINK_STATE_ENABLE = 0x01, 6170 VF_LINK_STATE_DISABLE = 0x02, 6171 }; 6172 6173 /* 6174 * dma queue parameters 6175 */ 6176 enum fw_params_param_dmaq { 6177 FW_PARAMS_PARAM_DMAQ_IQ_DCAEN_DCACPU = 0x00, 6178 FW_PARAMS_PARAM_DMAQ_IQ_INTCNTTHRESH = 0x01, 6179 FW_PARAMS_PARAM_DMAQ_IQ_INTIDX = 0x02, 6180 FW_PARAMS_PARAM_DMAQ_IQ_DCA = 0x03, 6181 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_MNGT = 0x10, 6182 FW_PARAMS_PARAM_DMAQ_EQ_CMPLIQID_CTRL = 0x11, 6183 FW_PARAMS_PARAM_DMAQ_EQ_SCHEDCLASS_ETH = 0x12, 6184 FW_PARAMS_PARAM_DMAQ_EQ_DCBPRIO_ETH = 0x13, 6185 FW_PARAMS_PARAM_DMAQ_EQ_DCA = 0x14, 6186 FW_PARAMS_PARAM_DMAQ_EQ_TIMERIX = 0x15, 6187 FW_PARAMS_PARAM_DMAQ_CONM_CTXT = 0x20, 6188 FW_PARAMS_PARAM_DMAQ_FLM_DCA = 0x30 6189 }; 6190 6191 #define S_T7_DMAQ_CONM_CTXT_CNGTPMODE 0 6192 #define M_T7_DMAQ_CONM_CTXT_CNGTPMODE 0x3 6193 #define V_T7_DMAQ_CONM_CTXT_CNGTPMODE(x) ((x) << S_T7_DMAQ_CONM_CTXT_CNGTPMODE) 6194 #define G_T7_DMAQ_CONM_CTXT_CNGTPMODE(x) \ 6195 (((x) >> S_T7_DMAQ_CONM_CTXT_CNGTPMODE) & M_T7_DMAQ_CONM_CTXT_CNGTPMODE) 6196 6197 #define S_T7_DMAQ_CONM_CTXT_CH_VEC 2 6198 #define M_T7_DMAQ_CONM_CTXT_CH_VEC 0xf 6199 #define V_T7_DMAQ_CONM_CTXT_CH_VEC(x) ((x) << S_T7_DMAQ_CONM_CTXT_CH_VEC) 6200 #define G_T7_DMAQ_CONM_CTXT_CH_VEC(x) \ 6201 (((x) >> S_T7_DMAQ_CONM_CTXT_CH_VEC) & M_T7_DMAQ_CONM_CTXT_CH_VEC) 6202 6203 6204 /* 6205 * chnet parameters 6206 */ 6207 enum fw_params_param_chnet { 6208 FW_PARAMS_PARAM_CHNET_FLAGS = 0x00, 6209 }; 6210 6211 enum fw_params_param_chnet_flags { 6212 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6 = 0x1, 6213 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_DAD = 0x2, 6214 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_MLDV2= 0x4, 6215 FW_PARAMS_PARAM_CHNET_FLAGS_ENABLE_IPV6_SLAAC = 0x8, 6216 }; 6217 6218 #define S_FW_PARAMS_MNEM 24 6219 #define M_FW_PARAMS_MNEM 0xff 6220 #define V_FW_PARAMS_MNEM(x) ((x) << S_FW_PARAMS_MNEM) 6221 #define G_FW_PARAMS_MNEM(x) \ 6222 (((x) >> S_FW_PARAMS_MNEM) & M_FW_PARAMS_MNEM) 6223 6224 #define S_FW_PARAMS_PARAM_X 16 6225 #define M_FW_PARAMS_PARAM_X 0xff 6226 #define V_FW_PARAMS_PARAM_X(x) ((x) << S_FW_PARAMS_PARAM_X) 6227 #define G_FW_PARAMS_PARAM_X(x) \ 6228 (((x) >> S_FW_PARAMS_PARAM_X) & M_FW_PARAMS_PARAM_X) 6229 6230 #define S_FW_PARAMS_PARAM_Y 8 6231 #define M_FW_PARAMS_PARAM_Y 0xff 6232 #define V_FW_PARAMS_PARAM_Y(x) ((x) << S_FW_PARAMS_PARAM_Y) 6233 #define G_FW_PARAMS_PARAM_Y(x) \ 6234 (((x) >> S_FW_PARAMS_PARAM_Y) & M_FW_PARAMS_PARAM_Y) 6235 6236 #define S_FW_PARAMS_PARAM_Z 0 6237 #define M_FW_PARAMS_PARAM_Z 0xff 6238 #define V_FW_PARAMS_PARAM_Z(x) ((x) << S_FW_PARAMS_PARAM_Z) 6239 #define G_FW_PARAMS_PARAM_Z(x) \ 6240 (((x) >> S_FW_PARAMS_PARAM_Z) & M_FW_PARAMS_PARAM_Z) 6241 6242 #define S_FW_PARAMS_PARAM_XYZ 0 6243 #define M_FW_PARAMS_PARAM_XYZ 0xffffff 6244 #define V_FW_PARAMS_PARAM_XYZ(x) ((x) << S_FW_PARAMS_PARAM_XYZ) 6245 #define G_FW_PARAMS_PARAM_XYZ(x) \ 6246 (((x) >> S_FW_PARAMS_PARAM_XYZ) & M_FW_PARAMS_PARAM_XYZ) 6247 6248 #define S_FW_PARAMS_PARAM_YZ 0 6249 #define M_FW_PARAMS_PARAM_YZ 0xffff 6250 #define V_FW_PARAMS_PARAM_YZ(x) ((x) << S_FW_PARAMS_PARAM_YZ) 6251 #define G_FW_PARAMS_PARAM_YZ(x) \ 6252 (((x) >> S_FW_PARAMS_PARAM_YZ) & M_FW_PARAMS_PARAM_YZ) 6253 6254 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 31 6255 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN 0x1 6256 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 6257 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 6258 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN(x) \ 6259 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) & \ 6260 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINTEN) 6261 6262 #define S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 24 6263 #define M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT 0x3 6264 #define V_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 6265 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 6266 #define G_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT(x) \ 6267 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) & \ 6268 M_FW_PARAMS_PARAM_DMAQ_DCA_TPHINT) 6269 6270 #define S_FW_PARAMS_PARAM_DMAQ_DCA_ST 0 6271 #define M_FW_PARAMS_PARAM_DMAQ_DCA_ST 0x7ff 6272 #define V_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 6273 ((x) << S_FW_PARAMS_PARAM_DMAQ_DCA_ST) 6274 #define G_FW_PARAMS_PARAM_DMAQ_DCA_ST(x) \ 6275 (((x) >> S_FW_PARAMS_PARAM_DMAQ_DCA_ST) & M_FW_PARAMS_PARAM_DMAQ_DCA_ST) 6276 6277 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 29 6278 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE 0x7 6279 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 6280 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 6281 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE(x) \ 6282 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) & \ 6283 M_FW_PARAMS_PARAM_DMAQ_INTIDX_QTYPE) 6284 6285 #define S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0 6286 #define M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX 0x3ff 6287 #define V_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 6288 ((x) << S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 6289 #define G_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX(x) \ 6290 (((x) >> S_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) & \ 6291 M_FW_PARAMS_PARAM_DMAQ_INTIDX_INTIDX) 6292 6293 struct fw_params_cmd { 6294 __be32 op_to_vfn; 6295 __be32 retval_len16; 6296 struct fw_params_param { 6297 __be32 mnem; 6298 __be32 val; 6299 } param[7]; 6300 }; 6301 6302 #define S_FW_PARAMS_CMD_PFN 8 6303 #define M_FW_PARAMS_CMD_PFN 0x7 6304 #define V_FW_PARAMS_CMD_PFN(x) ((x) << S_FW_PARAMS_CMD_PFN) 6305 #define G_FW_PARAMS_CMD_PFN(x) \ 6306 (((x) >> S_FW_PARAMS_CMD_PFN) & M_FW_PARAMS_CMD_PFN) 6307 6308 #define S_FW_PARAMS_CMD_VFN 0 6309 #define M_FW_PARAMS_CMD_VFN 0xff 6310 #define V_FW_PARAMS_CMD_VFN(x) ((x) << S_FW_PARAMS_CMD_VFN) 6311 #define G_FW_PARAMS_CMD_VFN(x) \ 6312 (((x) >> S_FW_PARAMS_CMD_VFN) & M_FW_PARAMS_CMD_VFN) 6313 6314 struct fw_pfvf_cmd { 6315 __be32 op_to_vfn; 6316 __be32 retval_len16; 6317 __be32 niqflint_niq; 6318 __be32 type_to_neq; 6319 __be32 tc_to_nexactf; 6320 __be32 r_caps_to_nethctrl; 6321 __be16 nricq; 6322 __be16 nriqp; 6323 __be32 r4; 6324 }; 6325 6326 #define S_FW_PFVF_CMD_PFN 8 6327 #define M_FW_PFVF_CMD_PFN 0x7 6328 #define V_FW_PFVF_CMD_PFN(x) ((x) << S_FW_PFVF_CMD_PFN) 6329 #define G_FW_PFVF_CMD_PFN(x) \ 6330 (((x) >> S_FW_PFVF_CMD_PFN) & M_FW_PFVF_CMD_PFN) 6331 6332 #define S_FW_PFVF_CMD_VFN 0 6333 #define M_FW_PFVF_CMD_VFN 0xff 6334 #define V_FW_PFVF_CMD_VFN(x) ((x) << S_FW_PFVF_CMD_VFN) 6335 #define G_FW_PFVF_CMD_VFN(x) \ 6336 (((x) >> S_FW_PFVF_CMD_VFN) & M_FW_PFVF_CMD_VFN) 6337 6338 #define S_FW_PFVF_CMD_NIQFLINT 20 6339 #define M_FW_PFVF_CMD_NIQFLINT 0xfff 6340 #define V_FW_PFVF_CMD_NIQFLINT(x) ((x) << S_FW_PFVF_CMD_NIQFLINT) 6341 #define G_FW_PFVF_CMD_NIQFLINT(x) \ 6342 (((x) >> S_FW_PFVF_CMD_NIQFLINT) & M_FW_PFVF_CMD_NIQFLINT) 6343 6344 #define S_FW_PFVF_CMD_NIQ 0 6345 #define M_FW_PFVF_CMD_NIQ 0xfffff 6346 #define V_FW_PFVF_CMD_NIQ(x) ((x) << S_FW_PFVF_CMD_NIQ) 6347 #define G_FW_PFVF_CMD_NIQ(x) \ 6348 (((x) >> S_FW_PFVF_CMD_NIQ) & M_FW_PFVF_CMD_NIQ) 6349 6350 #define S_FW_PFVF_CMD_TYPE 31 6351 #define M_FW_PFVF_CMD_TYPE 0x1 6352 #define V_FW_PFVF_CMD_TYPE(x) ((x) << S_FW_PFVF_CMD_TYPE) 6353 #define G_FW_PFVF_CMD_TYPE(x) \ 6354 (((x) >> S_FW_PFVF_CMD_TYPE) & M_FW_PFVF_CMD_TYPE) 6355 #define F_FW_PFVF_CMD_TYPE V_FW_PFVF_CMD_TYPE(1U) 6356 6357 #define S_FW_PFVF_CMD_CMASK 24 6358 #define M_FW_PFVF_CMD_CMASK 0xf 6359 #define V_FW_PFVF_CMD_CMASK(x) ((x) << S_FW_PFVF_CMD_CMASK) 6360 #define G_FW_PFVF_CMD_CMASK(x) \ 6361 (((x) >> S_FW_PFVF_CMD_CMASK) & M_FW_PFVF_CMD_CMASK) 6362 6363 #define S_FW_PFVF_CMD_PMASK 20 6364 #define M_FW_PFVF_CMD_PMASK 0xf 6365 #define V_FW_PFVF_CMD_PMASK(x) ((x) << S_FW_PFVF_CMD_PMASK) 6366 #define G_FW_PFVF_CMD_PMASK(x) \ 6367 (((x) >> S_FW_PFVF_CMD_PMASK) & M_FW_PFVF_CMD_PMASK) 6368 6369 #define S_FW_PFVF_CMD_NEQ 0 6370 #define M_FW_PFVF_CMD_NEQ 0xfffff 6371 #define V_FW_PFVF_CMD_NEQ(x) ((x) << S_FW_PFVF_CMD_NEQ) 6372 #define G_FW_PFVF_CMD_NEQ(x) \ 6373 (((x) >> S_FW_PFVF_CMD_NEQ) & M_FW_PFVF_CMD_NEQ) 6374 6375 #define S_FW_PFVF_CMD_TC 24 6376 #define M_FW_PFVF_CMD_TC 0xff 6377 #define V_FW_PFVF_CMD_TC(x) ((x) << S_FW_PFVF_CMD_TC) 6378 #define G_FW_PFVF_CMD_TC(x) \ 6379 (((x) >> S_FW_PFVF_CMD_TC) & M_FW_PFVF_CMD_TC) 6380 6381 #define S_FW_PFVF_CMD_NVI 16 6382 #define M_FW_PFVF_CMD_NVI 0xff 6383 #define V_FW_PFVF_CMD_NVI(x) ((x) << S_FW_PFVF_CMD_NVI) 6384 #define G_FW_PFVF_CMD_NVI(x) \ 6385 (((x) >> S_FW_PFVF_CMD_NVI) & M_FW_PFVF_CMD_NVI) 6386 6387 #define S_FW_PFVF_CMD_NEXACTF 0 6388 #define M_FW_PFVF_CMD_NEXACTF 0xffff 6389 #define V_FW_PFVF_CMD_NEXACTF(x) ((x) << S_FW_PFVF_CMD_NEXACTF) 6390 #define G_FW_PFVF_CMD_NEXACTF(x) \ 6391 (((x) >> S_FW_PFVF_CMD_NEXACTF) & M_FW_PFVF_CMD_NEXACTF) 6392 6393 #define S_FW_PFVF_CMD_R_CAPS 24 6394 #define M_FW_PFVF_CMD_R_CAPS 0xff 6395 #define V_FW_PFVF_CMD_R_CAPS(x) ((x) << S_FW_PFVF_CMD_R_CAPS) 6396 #define G_FW_PFVF_CMD_R_CAPS(x) \ 6397 (((x) >> S_FW_PFVF_CMD_R_CAPS) & M_FW_PFVF_CMD_R_CAPS) 6398 6399 #define S_FW_PFVF_CMD_WX_CAPS 16 6400 #define M_FW_PFVF_CMD_WX_CAPS 0xff 6401 #define V_FW_PFVF_CMD_WX_CAPS(x) ((x) << S_FW_PFVF_CMD_WX_CAPS) 6402 #define G_FW_PFVF_CMD_WX_CAPS(x) \ 6403 (((x) >> S_FW_PFVF_CMD_WX_CAPS) & M_FW_PFVF_CMD_WX_CAPS) 6404 6405 #define S_FW_PFVF_CMD_NETHCTRL 0 6406 #define M_FW_PFVF_CMD_NETHCTRL 0xffff 6407 #define V_FW_PFVF_CMD_NETHCTRL(x) ((x) << S_FW_PFVF_CMD_NETHCTRL) 6408 #define G_FW_PFVF_CMD_NETHCTRL(x) \ 6409 (((x) >> S_FW_PFVF_CMD_NETHCTRL) & M_FW_PFVF_CMD_NETHCTRL) 6410 6411 /* 6412 * ingress queue type; the first 1K ingress queues can have associated 0, 6413 * 1 or 2 free lists and an interrupt, all other ingress queues lack these 6414 * capabilities 6415 */ 6416 enum fw_iq_type { 6417 FW_IQ_TYPE_FL_INT_CAP, 6418 FW_IQ_TYPE_NO_FL_INT_CAP, 6419 FW_IQ_TYPE_VF_CQ, 6420 FW_IQ_TYPE_CQ, 6421 }; 6422 6423 enum fw_iq_iqtype { 6424 FW_IQ_IQTYPE_OTHER, 6425 FW_IQ_IQTYPE_NIC, 6426 FW_IQ_IQTYPE_OFLD, 6427 }; 6428 6429 struct fw_iq_cmd { 6430 __be32 op_to_vfn; 6431 __be32 alloc_to_len16; 6432 __be16 physiqid; 6433 __be16 iqid; 6434 __be16 fl0id; 6435 __be16 fl1id; 6436 __be32 type_to_iqandstindex; 6437 __be16 iqdroprss_to_iqesize; 6438 __be16 iqsize; 6439 __be64 iqaddr; 6440 __be32 iqns_to_fl0congen; 6441 __be16 fl0dcaen_to_fl0cidxfthresh; 6442 __be16 fl0size; 6443 __be64 fl0addr; 6444 __be32 fl1cngchmap_to_fl1congen; 6445 __be16 fl1dcaen_to_fl1cidxfthresh; 6446 __be16 fl1size; 6447 __be64 fl1addr; 6448 }; 6449 6450 #define S_FW_IQ_CMD_PFN 8 6451 #define M_FW_IQ_CMD_PFN 0x7 6452 #define V_FW_IQ_CMD_PFN(x) ((x) << S_FW_IQ_CMD_PFN) 6453 #define G_FW_IQ_CMD_PFN(x) \ 6454 (((x) >> S_FW_IQ_CMD_PFN) & M_FW_IQ_CMD_PFN) 6455 6456 #define S_FW_IQ_CMD_VFN 0 6457 #define M_FW_IQ_CMD_VFN 0xff 6458 #define V_FW_IQ_CMD_VFN(x) ((x) << S_FW_IQ_CMD_VFN) 6459 #define G_FW_IQ_CMD_VFN(x) \ 6460 (((x) >> S_FW_IQ_CMD_VFN) & M_FW_IQ_CMD_VFN) 6461 6462 #define S_FW_IQ_CMD_ALLOC 31 6463 #define M_FW_IQ_CMD_ALLOC 0x1 6464 #define V_FW_IQ_CMD_ALLOC(x) ((x) << S_FW_IQ_CMD_ALLOC) 6465 #define G_FW_IQ_CMD_ALLOC(x) \ 6466 (((x) >> S_FW_IQ_CMD_ALLOC) & M_FW_IQ_CMD_ALLOC) 6467 #define F_FW_IQ_CMD_ALLOC V_FW_IQ_CMD_ALLOC(1U) 6468 6469 #define S_FW_IQ_CMD_FREE 30 6470 #define M_FW_IQ_CMD_FREE 0x1 6471 #define V_FW_IQ_CMD_FREE(x) ((x) << S_FW_IQ_CMD_FREE) 6472 #define G_FW_IQ_CMD_FREE(x) \ 6473 (((x) >> S_FW_IQ_CMD_FREE) & M_FW_IQ_CMD_FREE) 6474 #define F_FW_IQ_CMD_FREE V_FW_IQ_CMD_FREE(1U) 6475 6476 #define S_FW_IQ_CMD_MODIFY 29 6477 #define M_FW_IQ_CMD_MODIFY 0x1 6478 #define V_FW_IQ_CMD_MODIFY(x) ((x) << S_FW_IQ_CMD_MODIFY) 6479 #define G_FW_IQ_CMD_MODIFY(x) \ 6480 (((x) >> S_FW_IQ_CMD_MODIFY) & M_FW_IQ_CMD_MODIFY) 6481 #define F_FW_IQ_CMD_MODIFY V_FW_IQ_CMD_MODIFY(1U) 6482 6483 #define S_FW_IQ_CMD_IQSTART 28 6484 #define M_FW_IQ_CMD_IQSTART 0x1 6485 #define V_FW_IQ_CMD_IQSTART(x) ((x) << S_FW_IQ_CMD_IQSTART) 6486 #define G_FW_IQ_CMD_IQSTART(x) \ 6487 (((x) >> S_FW_IQ_CMD_IQSTART) & M_FW_IQ_CMD_IQSTART) 6488 #define F_FW_IQ_CMD_IQSTART V_FW_IQ_CMD_IQSTART(1U) 6489 6490 #define S_FW_IQ_CMD_IQSTOP 27 6491 #define M_FW_IQ_CMD_IQSTOP 0x1 6492 #define V_FW_IQ_CMD_IQSTOP(x) ((x) << S_FW_IQ_CMD_IQSTOP) 6493 #define G_FW_IQ_CMD_IQSTOP(x) \ 6494 (((x) >> S_FW_IQ_CMD_IQSTOP) & M_FW_IQ_CMD_IQSTOP) 6495 #define F_FW_IQ_CMD_IQSTOP V_FW_IQ_CMD_IQSTOP(1U) 6496 6497 #define S_FW_IQ_CMD_TYPE 29 6498 #define M_FW_IQ_CMD_TYPE 0x7 6499 #define V_FW_IQ_CMD_TYPE(x) ((x) << S_FW_IQ_CMD_TYPE) 6500 #define G_FW_IQ_CMD_TYPE(x) \ 6501 (((x) >> S_FW_IQ_CMD_TYPE) & M_FW_IQ_CMD_TYPE) 6502 6503 #define S_FW_IQ_CMD_IQASYNCH 28 6504 #define M_FW_IQ_CMD_IQASYNCH 0x1 6505 #define V_FW_IQ_CMD_IQASYNCH(x) ((x) << S_FW_IQ_CMD_IQASYNCH) 6506 #define G_FW_IQ_CMD_IQASYNCH(x) \ 6507 (((x) >> S_FW_IQ_CMD_IQASYNCH) & M_FW_IQ_CMD_IQASYNCH) 6508 #define F_FW_IQ_CMD_IQASYNCH V_FW_IQ_CMD_IQASYNCH(1U) 6509 6510 #define S_FW_IQ_CMD_VIID 16 6511 #define M_FW_IQ_CMD_VIID 0xfff 6512 #define V_FW_IQ_CMD_VIID(x) ((x) << S_FW_IQ_CMD_VIID) 6513 #define G_FW_IQ_CMD_VIID(x) \ 6514 (((x) >> S_FW_IQ_CMD_VIID) & M_FW_IQ_CMD_VIID) 6515 6516 #define S_FW_IQ_CMD_IQANDST 15 6517 #define M_FW_IQ_CMD_IQANDST 0x1 6518 #define V_FW_IQ_CMD_IQANDST(x) ((x) << S_FW_IQ_CMD_IQANDST) 6519 #define G_FW_IQ_CMD_IQANDST(x) \ 6520 (((x) >> S_FW_IQ_CMD_IQANDST) & M_FW_IQ_CMD_IQANDST) 6521 #define F_FW_IQ_CMD_IQANDST V_FW_IQ_CMD_IQANDST(1U) 6522 6523 #define S_FW_IQ_CMD_IQANUS 14 6524 #define M_FW_IQ_CMD_IQANUS 0x1 6525 #define V_FW_IQ_CMD_IQANUS(x) ((x) << S_FW_IQ_CMD_IQANUS) 6526 #define G_FW_IQ_CMD_IQANUS(x) \ 6527 (((x) >> S_FW_IQ_CMD_IQANUS) & M_FW_IQ_CMD_IQANUS) 6528 #define F_FW_IQ_CMD_IQANUS V_FW_IQ_CMD_IQANUS(1U) 6529 6530 #define S_FW_IQ_CMD_IQANUD 12 6531 #define M_FW_IQ_CMD_IQANUD 0x3 6532 #define V_FW_IQ_CMD_IQANUD(x) ((x) << S_FW_IQ_CMD_IQANUD) 6533 #define G_FW_IQ_CMD_IQANUD(x) \ 6534 (((x) >> S_FW_IQ_CMD_IQANUD) & M_FW_IQ_CMD_IQANUD) 6535 6536 #define S_FW_IQ_CMD_IQANDSTINDEX 0 6537 #define M_FW_IQ_CMD_IQANDSTINDEX 0xfff 6538 #define V_FW_IQ_CMD_IQANDSTINDEX(x) ((x) << S_FW_IQ_CMD_IQANDSTINDEX) 6539 #define G_FW_IQ_CMD_IQANDSTINDEX(x) \ 6540 (((x) >> S_FW_IQ_CMD_IQANDSTINDEX) & M_FW_IQ_CMD_IQANDSTINDEX) 6541 6542 #define S_FW_IQ_CMD_IQDROPRSS 15 6543 #define M_FW_IQ_CMD_IQDROPRSS 0x1 6544 #define V_FW_IQ_CMD_IQDROPRSS(x) ((x) << S_FW_IQ_CMD_IQDROPRSS) 6545 #define G_FW_IQ_CMD_IQDROPRSS(x) \ 6546 (((x) >> S_FW_IQ_CMD_IQDROPRSS) & M_FW_IQ_CMD_IQDROPRSS) 6547 #define F_FW_IQ_CMD_IQDROPRSS V_FW_IQ_CMD_IQDROPRSS(1U) 6548 6549 #define S_FW_IQ_CMD_IQGTSMODE 14 6550 #define M_FW_IQ_CMD_IQGTSMODE 0x1 6551 #define V_FW_IQ_CMD_IQGTSMODE(x) ((x) << S_FW_IQ_CMD_IQGTSMODE) 6552 #define G_FW_IQ_CMD_IQGTSMODE(x) \ 6553 (((x) >> S_FW_IQ_CMD_IQGTSMODE) & M_FW_IQ_CMD_IQGTSMODE) 6554 #define F_FW_IQ_CMD_IQGTSMODE V_FW_IQ_CMD_IQGTSMODE(1U) 6555 6556 #define S_FW_IQ_CMD_IQPCIECH 12 6557 #define M_FW_IQ_CMD_IQPCIECH 0x3 6558 #define V_FW_IQ_CMD_IQPCIECH(x) ((x) << S_FW_IQ_CMD_IQPCIECH) 6559 #define G_FW_IQ_CMD_IQPCIECH(x) \ 6560 (((x) >> S_FW_IQ_CMD_IQPCIECH) & M_FW_IQ_CMD_IQPCIECH) 6561 6562 #define S_FW_IQ_CMD_IQDCAEN 11 6563 #define M_FW_IQ_CMD_IQDCAEN 0x1 6564 #define V_FW_IQ_CMD_IQDCAEN(x) ((x) << S_FW_IQ_CMD_IQDCAEN) 6565 #define G_FW_IQ_CMD_IQDCAEN(x) \ 6566 (((x) >> S_FW_IQ_CMD_IQDCAEN) & M_FW_IQ_CMD_IQDCAEN) 6567 #define F_FW_IQ_CMD_IQDCAEN V_FW_IQ_CMD_IQDCAEN(1U) 6568 6569 #define S_FW_IQ_CMD_IQDCACPU 6 6570 #define M_FW_IQ_CMD_IQDCACPU 0x1f 6571 #define V_FW_IQ_CMD_IQDCACPU(x) ((x) << S_FW_IQ_CMD_IQDCACPU) 6572 #define G_FW_IQ_CMD_IQDCACPU(x) \ 6573 (((x) >> S_FW_IQ_CMD_IQDCACPU) & M_FW_IQ_CMD_IQDCACPU) 6574 6575 #define S_FW_IQ_CMD_IQINTCNTTHRESH 4 6576 #define M_FW_IQ_CMD_IQINTCNTTHRESH 0x3 6577 #define V_FW_IQ_CMD_IQINTCNTTHRESH(x) ((x) << S_FW_IQ_CMD_IQINTCNTTHRESH) 6578 #define G_FW_IQ_CMD_IQINTCNTTHRESH(x) \ 6579 (((x) >> S_FW_IQ_CMD_IQINTCNTTHRESH) & M_FW_IQ_CMD_IQINTCNTTHRESH) 6580 6581 #define S_FW_IQ_CMD_IQO 3 6582 #define M_FW_IQ_CMD_IQO 0x1 6583 #define V_FW_IQ_CMD_IQO(x) ((x) << S_FW_IQ_CMD_IQO) 6584 #define G_FW_IQ_CMD_IQO(x) \ 6585 (((x) >> S_FW_IQ_CMD_IQO) & M_FW_IQ_CMD_IQO) 6586 #define F_FW_IQ_CMD_IQO V_FW_IQ_CMD_IQO(1U) 6587 6588 #define S_FW_IQ_CMD_IQCPRIO 2 6589 #define M_FW_IQ_CMD_IQCPRIO 0x1 6590 #define V_FW_IQ_CMD_IQCPRIO(x) ((x) << S_FW_IQ_CMD_IQCPRIO) 6591 #define G_FW_IQ_CMD_IQCPRIO(x) \ 6592 (((x) >> S_FW_IQ_CMD_IQCPRIO) & M_FW_IQ_CMD_IQCPRIO) 6593 #define F_FW_IQ_CMD_IQCPRIO V_FW_IQ_CMD_IQCPRIO(1U) 6594 6595 #define S_FW_IQ_CMD_IQESIZE 0 6596 #define M_FW_IQ_CMD_IQESIZE 0x3 6597 #define V_FW_IQ_CMD_IQESIZE(x) ((x) << S_FW_IQ_CMD_IQESIZE) 6598 #define G_FW_IQ_CMD_IQESIZE(x) \ 6599 (((x) >> S_FW_IQ_CMD_IQESIZE) & M_FW_IQ_CMD_IQESIZE) 6600 6601 #define S_FW_IQ_CMD_IQNS 31 6602 #define M_FW_IQ_CMD_IQNS 0x1 6603 #define V_FW_IQ_CMD_IQNS(x) ((x) << S_FW_IQ_CMD_IQNS) 6604 #define G_FW_IQ_CMD_IQNS(x) \ 6605 (((x) >> S_FW_IQ_CMD_IQNS) & M_FW_IQ_CMD_IQNS) 6606 #define F_FW_IQ_CMD_IQNS V_FW_IQ_CMD_IQNS(1U) 6607 6608 #define S_FW_IQ_CMD_IQRO 30 6609 #define M_FW_IQ_CMD_IQRO 0x1 6610 #define V_FW_IQ_CMD_IQRO(x) ((x) << S_FW_IQ_CMD_IQRO) 6611 #define G_FW_IQ_CMD_IQRO(x) \ 6612 (((x) >> S_FW_IQ_CMD_IQRO) & M_FW_IQ_CMD_IQRO) 6613 #define F_FW_IQ_CMD_IQRO V_FW_IQ_CMD_IQRO(1U) 6614 6615 #define S_FW_IQ_CMD_IQFLINTIQHSEN 28 6616 #define M_FW_IQ_CMD_IQFLINTIQHSEN 0x3 6617 #define V_FW_IQ_CMD_IQFLINTIQHSEN(x) ((x) << S_FW_IQ_CMD_IQFLINTIQHSEN) 6618 #define G_FW_IQ_CMD_IQFLINTIQHSEN(x) \ 6619 (((x) >> S_FW_IQ_CMD_IQFLINTIQHSEN) & M_FW_IQ_CMD_IQFLINTIQHSEN) 6620 6621 #define S_FW_IQ_CMD_IQFLINTCONGEN 27 6622 #define M_FW_IQ_CMD_IQFLINTCONGEN 0x1 6623 #define V_FW_IQ_CMD_IQFLINTCONGEN(x) ((x) << S_FW_IQ_CMD_IQFLINTCONGEN) 6624 #define G_FW_IQ_CMD_IQFLINTCONGEN(x) \ 6625 (((x) >> S_FW_IQ_CMD_IQFLINTCONGEN) & M_FW_IQ_CMD_IQFLINTCONGEN) 6626 #define F_FW_IQ_CMD_IQFLINTCONGEN V_FW_IQ_CMD_IQFLINTCONGEN(1U) 6627 6628 #define S_FW_IQ_CMD_IQFLINTISCSIC 26 6629 #define M_FW_IQ_CMD_IQFLINTISCSIC 0x1 6630 #define V_FW_IQ_CMD_IQFLINTISCSIC(x) ((x) << S_FW_IQ_CMD_IQFLINTISCSIC) 6631 #define G_FW_IQ_CMD_IQFLINTISCSIC(x) \ 6632 (((x) >> S_FW_IQ_CMD_IQFLINTISCSIC) & M_FW_IQ_CMD_IQFLINTISCSIC) 6633 #define F_FW_IQ_CMD_IQFLINTISCSIC V_FW_IQ_CMD_IQFLINTISCSIC(1U) 6634 6635 #define S_FW_IQ_CMD_IQTYPE 24 6636 #define M_FW_IQ_CMD_IQTYPE 0x3 6637 #define V_FW_IQ_CMD_IQTYPE(x) ((x) << S_FW_IQ_CMD_IQTYPE) 6638 #define G_FW_IQ_CMD_IQTYPE(x) \ 6639 (((x) >> S_FW_IQ_CMD_IQTYPE) & M_FW_IQ_CMD_IQTYPE) 6640 6641 #define S_FW_IQ_CMD_FL0CNGCHMAP 20 6642 #define M_FW_IQ_CMD_FL0CNGCHMAP 0xf 6643 #define V_FW_IQ_CMD_FL0CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL0CNGCHMAP) 6644 #define G_FW_IQ_CMD_FL0CNGCHMAP(x) \ 6645 (((x) >> S_FW_IQ_CMD_FL0CNGCHMAP) & M_FW_IQ_CMD_FL0CNGCHMAP) 6646 6647 #define S_FW_IQ_CMD_FL0CONGDROP 16 6648 #define M_FW_IQ_CMD_FL0CONGDROP 0x1 6649 #define V_FW_IQ_CMD_FL0CONGDROP(x) ((x) << S_FW_IQ_CMD_FL0CONGDROP) 6650 #define G_FW_IQ_CMD_FL0CONGDROP(x) \ 6651 (((x) >> S_FW_IQ_CMD_FL0CONGDROP) & M_FW_IQ_CMD_FL0CONGDROP) 6652 #define F_FW_IQ_CMD_FL0CONGDROP V_FW_IQ_CMD_FL0CONGDROP(1U) 6653 6654 #define S_FW_IQ_CMD_FL0CACHELOCK 15 6655 #define M_FW_IQ_CMD_FL0CACHELOCK 0x1 6656 #define V_FW_IQ_CMD_FL0CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL0CACHELOCK) 6657 #define G_FW_IQ_CMD_FL0CACHELOCK(x) \ 6658 (((x) >> S_FW_IQ_CMD_FL0CACHELOCK) & M_FW_IQ_CMD_FL0CACHELOCK) 6659 #define F_FW_IQ_CMD_FL0CACHELOCK V_FW_IQ_CMD_FL0CACHELOCK(1U) 6660 6661 #define S_FW_IQ_CMD_FL0DBP 14 6662 #define M_FW_IQ_CMD_FL0DBP 0x1 6663 #define V_FW_IQ_CMD_FL0DBP(x) ((x) << S_FW_IQ_CMD_FL0DBP) 6664 #define G_FW_IQ_CMD_FL0DBP(x) \ 6665 (((x) >> S_FW_IQ_CMD_FL0DBP) & M_FW_IQ_CMD_FL0DBP) 6666 #define F_FW_IQ_CMD_FL0DBP V_FW_IQ_CMD_FL0DBP(1U) 6667 6668 #define S_FW_IQ_CMD_FL0DATANS 13 6669 #define M_FW_IQ_CMD_FL0DATANS 0x1 6670 #define V_FW_IQ_CMD_FL0DATANS(x) ((x) << S_FW_IQ_CMD_FL0DATANS) 6671 #define G_FW_IQ_CMD_FL0DATANS(x) \ 6672 (((x) >> S_FW_IQ_CMD_FL0DATANS) & M_FW_IQ_CMD_FL0DATANS) 6673 #define F_FW_IQ_CMD_FL0DATANS V_FW_IQ_CMD_FL0DATANS(1U) 6674 6675 #define S_FW_IQ_CMD_FL0DATARO 12 6676 #define M_FW_IQ_CMD_FL0DATARO 0x1 6677 #define V_FW_IQ_CMD_FL0DATARO(x) ((x) << S_FW_IQ_CMD_FL0DATARO) 6678 #define G_FW_IQ_CMD_FL0DATARO(x) \ 6679 (((x) >> S_FW_IQ_CMD_FL0DATARO) & M_FW_IQ_CMD_FL0DATARO) 6680 #define F_FW_IQ_CMD_FL0DATARO V_FW_IQ_CMD_FL0DATARO(1U) 6681 6682 #define S_FW_IQ_CMD_FL0CONGCIF 11 6683 #define M_FW_IQ_CMD_FL0CONGCIF 0x1 6684 #define V_FW_IQ_CMD_FL0CONGCIF(x) ((x) << S_FW_IQ_CMD_FL0CONGCIF) 6685 #define G_FW_IQ_CMD_FL0CONGCIF(x) \ 6686 (((x) >> S_FW_IQ_CMD_FL0CONGCIF) & M_FW_IQ_CMD_FL0CONGCIF) 6687 #define F_FW_IQ_CMD_FL0CONGCIF V_FW_IQ_CMD_FL0CONGCIF(1U) 6688 6689 #define S_FW_IQ_CMD_FL0ONCHIP 10 6690 #define M_FW_IQ_CMD_FL0ONCHIP 0x1 6691 #define V_FW_IQ_CMD_FL0ONCHIP(x) ((x) << S_FW_IQ_CMD_FL0ONCHIP) 6692 #define G_FW_IQ_CMD_FL0ONCHIP(x) \ 6693 (((x) >> S_FW_IQ_CMD_FL0ONCHIP) & M_FW_IQ_CMD_FL0ONCHIP) 6694 #define F_FW_IQ_CMD_FL0ONCHIP V_FW_IQ_CMD_FL0ONCHIP(1U) 6695 6696 #define S_FW_IQ_CMD_FL0STATUSPGNS 9 6697 #define M_FW_IQ_CMD_FL0STATUSPGNS 0x1 6698 #define V_FW_IQ_CMD_FL0STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGNS) 6699 #define G_FW_IQ_CMD_FL0STATUSPGNS(x) \ 6700 (((x) >> S_FW_IQ_CMD_FL0STATUSPGNS) & M_FW_IQ_CMD_FL0STATUSPGNS) 6701 #define F_FW_IQ_CMD_FL0STATUSPGNS V_FW_IQ_CMD_FL0STATUSPGNS(1U) 6702 6703 #define S_FW_IQ_CMD_FL0STATUSPGRO 8 6704 #define M_FW_IQ_CMD_FL0STATUSPGRO 0x1 6705 #define V_FW_IQ_CMD_FL0STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL0STATUSPGRO) 6706 #define G_FW_IQ_CMD_FL0STATUSPGRO(x) \ 6707 (((x) >> S_FW_IQ_CMD_FL0STATUSPGRO) & M_FW_IQ_CMD_FL0STATUSPGRO) 6708 #define F_FW_IQ_CMD_FL0STATUSPGRO V_FW_IQ_CMD_FL0STATUSPGRO(1U) 6709 6710 #define S_FW_IQ_CMD_FL0FETCHNS 7 6711 #define M_FW_IQ_CMD_FL0FETCHNS 0x1 6712 #define V_FW_IQ_CMD_FL0FETCHNS(x) ((x) << S_FW_IQ_CMD_FL0FETCHNS) 6713 #define G_FW_IQ_CMD_FL0FETCHNS(x) \ 6714 (((x) >> S_FW_IQ_CMD_FL0FETCHNS) & M_FW_IQ_CMD_FL0FETCHNS) 6715 #define F_FW_IQ_CMD_FL0FETCHNS V_FW_IQ_CMD_FL0FETCHNS(1U) 6716 6717 #define S_FW_IQ_CMD_FL0FETCHRO 6 6718 #define M_FW_IQ_CMD_FL0FETCHRO 0x1 6719 #define V_FW_IQ_CMD_FL0FETCHRO(x) ((x) << S_FW_IQ_CMD_FL0FETCHRO) 6720 #define G_FW_IQ_CMD_FL0FETCHRO(x) \ 6721 (((x) >> S_FW_IQ_CMD_FL0FETCHRO) & M_FW_IQ_CMD_FL0FETCHRO) 6722 #define F_FW_IQ_CMD_FL0FETCHRO V_FW_IQ_CMD_FL0FETCHRO(1U) 6723 6724 #define S_FW_IQ_CMD_FL0HOSTFCMODE 4 6725 #define M_FW_IQ_CMD_FL0HOSTFCMODE 0x3 6726 #define V_FW_IQ_CMD_FL0HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL0HOSTFCMODE) 6727 #define G_FW_IQ_CMD_FL0HOSTFCMODE(x) \ 6728 (((x) >> S_FW_IQ_CMD_FL0HOSTFCMODE) & M_FW_IQ_CMD_FL0HOSTFCMODE) 6729 6730 #define S_FW_IQ_CMD_FL0CPRIO 3 6731 #define M_FW_IQ_CMD_FL0CPRIO 0x1 6732 #define V_FW_IQ_CMD_FL0CPRIO(x) ((x) << S_FW_IQ_CMD_FL0CPRIO) 6733 #define G_FW_IQ_CMD_FL0CPRIO(x) \ 6734 (((x) >> S_FW_IQ_CMD_FL0CPRIO) & M_FW_IQ_CMD_FL0CPRIO) 6735 #define F_FW_IQ_CMD_FL0CPRIO V_FW_IQ_CMD_FL0CPRIO(1U) 6736 6737 #define S_FW_IQ_CMD_FL0PADEN 2 6738 #define M_FW_IQ_CMD_FL0PADEN 0x1 6739 #define V_FW_IQ_CMD_FL0PADEN(x) ((x) << S_FW_IQ_CMD_FL0PADEN) 6740 #define G_FW_IQ_CMD_FL0PADEN(x) \ 6741 (((x) >> S_FW_IQ_CMD_FL0PADEN) & M_FW_IQ_CMD_FL0PADEN) 6742 #define F_FW_IQ_CMD_FL0PADEN V_FW_IQ_CMD_FL0PADEN(1U) 6743 6744 #define S_FW_IQ_CMD_FL0PACKEN 1 6745 #define M_FW_IQ_CMD_FL0PACKEN 0x1 6746 #define V_FW_IQ_CMD_FL0PACKEN(x) ((x) << S_FW_IQ_CMD_FL0PACKEN) 6747 #define G_FW_IQ_CMD_FL0PACKEN(x) \ 6748 (((x) >> S_FW_IQ_CMD_FL0PACKEN) & M_FW_IQ_CMD_FL0PACKEN) 6749 #define F_FW_IQ_CMD_FL0PACKEN V_FW_IQ_CMD_FL0PACKEN(1U) 6750 6751 #define S_FW_IQ_CMD_FL0CONGEN 0 6752 #define M_FW_IQ_CMD_FL0CONGEN 0x1 6753 #define V_FW_IQ_CMD_FL0CONGEN(x) ((x) << S_FW_IQ_CMD_FL0CONGEN) 6754 #define G_FW_IQ_CMD_FL0CONGEN(x) \ 6755 (((x) >> S_FW_IQ_CMD_FL0CONGEN) & M_FW_IQ_CMD_FL0CONGEN) 6756 #define F_FW_IQ_CMD_FL0CONGEN V_FW_IQ_CMD_FL0CONGEN(1U) 6757 6758 #define S_FW_IQ_CMD_FL0DCAEN 15 6759 #define M_FW_IQ_CMD_FL0DCAEN 0x1 6760 #define V_FW_IQ_CMD_FL0DCAEN(x) ((x) << S_FW_IQ_CMD_FL0DCAEN) 6761 #define G_FW_IQ_CMD_FL0DCAEN(x) \ 6762 (((x) >> S_FW_IQ_CMD_FL0DCAEN) & M_FW_IQ_CMD_FL0DCAEN) 6763 #define F_FW_IQ_CMD_FL0DCAEN V_FW_IQ_CMD_FL0DCAEN(1U) 6764 6765 #define S_FW_IQ_CMD_FL0DCACPU 10 6766 #define M_FW_IQ_CMD_FL0DCACPU 0x1f 6767 #define V_FW_IQ_CMD_FL0DCACPU(x) ((x) << S_FW_IQ_CMD_FL0DCACPU) 6768 #define G_FW_IQ_CMD_FL0DCACPU(x) \ 6769 (((x) >> S_FW_IQ_CMD_FL0DCACPU) & M_FW_IQ_CMD_FL0DCACPU) 6770 6771 #define S_FW_IQ_CMD_FL0FBMIN 7 6772 #define M_FW_IQ_CMD_FL0FBMIN 0x7 6773 #define V_FW_IQ_CMD_FL0FBMIN(x) ((x) << S_FW_IQ_CMD_FL0FBMIN) 6774 #define G_FW_IQ_CMD_FL0FBMIN(x) \ 6775 (((x) >> S_FW_IQ_CMD_FL0FBMIN) & M_FW_IQ_CMD_FL0FBMIN) 6776 6777 #define S_FW_IQ_CMD_FL0FBMAX 4 6778 #define M_FW_IQ_CMD_FL0FBMAX 0x7 6779 #define V_FW_IQ_CMD_FL0FBMAX(x) ((x) << S_FW_IQ_CMD_FL0FBMAX) 6780 #define G_FW_IQ_CMD_FL0FBMAX(x) \ 6781 (((x) >> S_FW_IQ_CMD_FL0FBMAX) & M_FW_IQ_CMD_FL0FBMAX) 6782 6783 #define S_FW_IQ_CMD_FL0CIDXFTHRESHO 3 6784 #define M_FW_IQ_CMD_FL0CIDXFTHRESHO 0x1 6785 #define V_FW_IQ_CMD_FL0CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESHO) 6786 #define G_FW_IQ_CMD_FL0CIDXFTHRESHO(x) \ 6787 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESHO) & M_FW_IQ_CMD_FL0CIDXFTHRESHO) 6788 #define F_FW_IQ_CMD_FL0CIDXFTHRESHO V_FW_IQ_CMD_FL0CIDXFTHRESHO(1U) 6789 6790 #define S_FW_IQ_CMD_FL0CIDXFTHRESH 0 6791 #define M_FW_IQ_CMD_FL0CIDXFTHRESH 0x7 6792 #define V_FW_IQ_CMD_FL0CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL0CIDXFTHRESH) 6793 #define G_FW_IQ_CMD_FL0CIDXFTHRESH(x) \ 6794 (((x) >> S_FW_IQ_CMD_FL0CIDXFTHRESH) & M_FW_IQ_CMD_FL0CIDXFTHRESH) 6795 6796 #define S_FW_IQ_CMD_FL1CNGCHMAP 20 6797 #define M_FW_IQ_CMD_FL1CNGCHMAP 0xf 6798 #define V_FW_IQ_CMD_FL1CNGCHMAP(x) ((x) << S_FW_IQ_CMD_FL1CNGCHMAP) 6799 #define G_FW_IQ_CMD_FL1CNGCHMAP(x) \ 6800 (((x) >> S_FW_IQ_CMD_FL1CNGCHMAP) & M_FW_IQ_CMD_FL1CNGCHMAP) 6801 6802 #define S_FW_IQ_CMD_FL1CONGDROP 16 6803 #define M_FW_IQ_CMD_FL1CONGDROP 0x1 6804 #define V_FW_IQ_CMD_FL1CONGDROP(x) ((x) << S_FW_IQ_CMD_FL1CONGDROP) 6805 #define G_FW_IQ_CMD_FL1CONGDROP(x) \ 6806 (((x) >> S_FW_IQ_CMD_FL1CONGDROP) & M_FW_IQ_CMD_FL1CONGDROP) 6807 #define F_FW_IQ_CMD_FL1CONGDROP V_FW_IQ_CMD_FL1CONGDROP(1U) 6808 6809 #define S_FW_IQ_CMD_FL1CACHELOCK 15 6810 #define M_FW_IQ_CMD_FL1CACHELOCK 0x1 6811 #define V_FW_IQ_CMD_FL1CACHELOCK(x) ((x) << S_FW_IQ_CMD_FL1CACHELOCK) 6812 #define G_FW_IQ_CMD_FL1CACHELOCK(x) \ 6813 (((x) >> S_FW_IQ_CMD_FL1CACHELOCK) & M_FW_IQ_CMD_FL1CACHELOCK) 6814 #define F_FW_IQ_CMD_FL1CACHELOCK V_FW_IQ_CMD_FL1CACHELOCK(1U) 6815 6816 #define S_FW_IQ_CMD_FL1DBP 14 6817 #define M_FW_IQ_CMD_FL1DBP 0x1 6818 #define V_FW_IQ_CMD_FL1DBP(x) ((x) << S_FW_IQ_CMD_FL1DBP) 6819 #define G_FW_IQ_CMD_FL1DBP(x) \ 6820 (((x) >> S_FW_IQ_CMD_FL1DBP) & M_FW_IQ_CMD_FL1DBP) 6821 #define F_FW_IQ_CMD_FL1DBP V_FW_IQ_CMD_FL1DBP(1U) 6822 6823 #define S_FW_IQ_CMD_FL1DATANS 13 6824 #define M_FW_IQ_CMD_FL1DATANS 0x1 6825 #define V_FW_IQ_CMD_FL1DATANS(x) ((x) << S_FW_IQ_CMD_FL1DATANS) 6826 #define G_FW_IQ_CMD_FL1DATANS(x) \ 6827 (((x) >> S_FW_IQ_CMD_FL1DATANS) & M_FW_IQ_CMD_FL1DATANS) 6828 #define F_FW_IQ_CMD_FL1DATANS V_FW_IQ_CMD_FL1DATANS(1U) 6829 6830 #define S_FW_IQ_CMD_FL1DATARO 12 6831 #define M_FW_IQ_CMD_FL1DATARO 0x1 6832 #define V_FW_IQ_CMD_FL1DATARO(x) ((x) << S_FW_IQ_CMD_FL1DATARO) 6833 #define G_FW_IQ_CMD_FL1DATARO(x) \ 6834 (((x) >> S_FW_IQ_CMD_FL1DATARO) & M_FW_IQ_CMD_FL1DATARO) 6835 #define F_FW_IQ_CMD_FL1DATARO V_FW_IQ_CMD_FL1DATARO(1U) 6836 6837 #define S_FW_IQ_CMD_FL1CONGCIF 11 6838 #define M_FW_IQ_CMD_FL1CONGCIF 0x1 6839 #define V_FW_IQ_CMD_FL1CONGCIF(x) ((x) << S_FW_IQ_CMD_FL1CONGCIF) 6840 #define G_FW_IQ_CMD_FL1CONGCIF(x) \ 6841 (((x) >> S_FW_IQ_CMD_FL1CONGCIF) & M_FW_IQ_CMD_FL1CONGCIF) 6842 #define F_FW_IQ_CMD_FL1CONGCIF V_FW_IQ_CMD_FL1CONGCIF(1U) 6843 6844 #define S_FW_IQ_CMD_FL1ONCHIP 10 6845 #define M_FW_IQ_CMD_FL1ONCHIP 0x1 6846 #define V_FW_IQ_CMD_FL1ONCHIP(x) ((x) << S_FW_IQ_CMD_FL1ONCHIP) 6847 #define G_FW_IQ_CMD_FL1ONCHIP(x) \ 6848 (((x) >> S_FW_IQ_CMD_FL1ONCHIP) & M_FW_IQ_CMD_FL1ONCHIP) 6849 #define F_FW_IQ_CMD_FL1ONCHIP V_FW_IQ_CMD_FL1ONCHIP(1U) 6850 6851 #define S_FW_IQ_CMD_FL1STATUSPGNS 9 6852 #define M_FW_IQ_CMD_FL1STATUSPGNS 0x1 6853 #define V_FW_IQ_CMD_FL1STATUSPGNS(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGNS) 6854 #define G_FW_IQ_CMD_FL1STATUSPGNS(x) \ 6855 (((x) >> S_FW_IQ_CMD_FL1STATUSPGNS) & M_FW_IQ_CMD_FL1STATUSPGNS) 6856 #define F_FW_IQ_CMD_FL1STATUSPGNS V_FW_IQ_CMD_FL1STATUSPGNS(1U) 6857 6858 #define S_FW_IQ_CMD_FL1STATUSPGRO 8 6859 #define M_FW_IQ_CMD_FL1STATUSPGRO 0x1 6860 #define V_FW_IQ_CMD_FL1STATUSPGRO(x) ((x) << S_FW_IQ_CMD_FL1STATUSPGRO) 6861 #define G_FW_IQ_CMD_FL1STATUSPGRO(x) \ 6862 (((x) >> S_FW_IQ_CMD_FL1STATUSPGRO) & M_FW_IQ_CMD_FL1STATUSPGRO) 6863 #define F_FW_IQ_CMD_FL1STATUSPGRO V_FW_IQ_CMD_FL1STATUSPGRO(1U) 6864 6865 #define S_FW_IQ_CMD_FL1FETCHNS 7 6866 #define M_FW_IQ_CMD_FL1FETCHNS 0x1 6867 #define V_FW_IQ_CMD_FL1FETCHNS(x) ((x) << S_FW_IQ_CMD_FL1FETCHNS) 6868 #define G_FW_IQ_CMD_FL1FETCHNS(x) \ 6869 (((x) >> S_FW_IQ_CMD_FL1FETCHNS) & M_FW_IQ_CMD_FL1FETCHNS) 6870 #define F_FW_IQ_CMD_FL1FETCHNS V_FW_IQ_CMD_FL1FETCHNS(1U) 6871 6872 #define S_FW_IQ_CMD_FL1FETCHRO 6 6873 #define M_FW_IQ_CMD_FL1FETCHRO 0x1 6874 #define V_FW_IQ_CMD_FL1FETCHRO(x) ((x) << S_FW_IQ_CMD_FL1FETCHRO) 6875 #define G_FW_IQ_CMD_FL1FETCHRO(x) \ 6876 (((x) >> S_FW_IQ_CMD_FL1FETCHRO) & M_FW_IQ_CMD_FL1FETCHRO) 6877 #define F_FW_IQ_CMD_FL1FETCHRO V_FW_IQ_CMD_FL1FETCHRO(1U) 6878 6879 #define S_FW_IQ_CMD_FL1HOSTFCMODE 4 6880 #define M_FW_IQ_CMD_FL1HOSTFCMODE 0x3 6881 #define V_FW_IQ_CMD_FL1HOSTFCMODE(x) ((x) << S_FW_IQ_CMD_FL1HOSTFCMODE) 6882 #define G_FW_IQ_CMD_FL1HOSTFCMODE(x) \ 6883 (((x) >> S_FW_IQ_CMD_FL1HOSTFCMODE) & M_FW_IQ_CMD_FL1HOSTFCMODE) 6884 6885 #define S_FW_IQ_CMD_FL1CPRIO 3 6886 #define M_FW_IQ_CMD_FL1CPRIO 0x1 6887 #define V_FW_IQ_CMD_FL1CPRIO(x) ((x) << S_FW_IQ_CMD_FL1CPRIO) 6888 #define G_FW_IQ_CMD_FL1CPRIO(x) \ 6889 (((x) >> S_FW_IQ_CMD_FL1CPRIO) & M_FW_IQ_CMD_FL1CPRIO) 6890 #define F_FW_IQ_CMD_FL1CPRIO V_FW_IQ_CMD_FL1CPRIO(1U) 6891 6892 #define S_FW_IQ_CMD_FL1PADEN 2 6893 #define M_FW_IQ_CMD_FL1PADEN 0x1 6894 #define V_FW_IQ_CMD_FL1PADEN(x) ((x) << S_FW_IQ_CMD_FL1PADEN) 6895 #define G_FW_IQ_CMD_FL1PADEN(x) \ 6896 (((x) >> S_FW_IQ_CMD_FL1PADEN) & M_FW_IQ_CMD_FL1PADEN) 6897 #define F_FW_IQ_CMD_FL1PADEN V_FW_IQ_CMD_FL1PADEN(1U) 6898 6899 #define S_FW_IQ_CMD_FL1PACKEN 1 6900 #define M_FW_IQ_CMD_FL1PACKEN 0x1 6901 #define V_FW_IQ_CMD_FL1PACKEN(x) ((x) << S_FW_IQ_CMD_FL1PACKEN) 6902 #define G_FW_IQ_CMD_FL1PACKEN(x) \ 6903 (((x) >> S_FW_IQ_CMD_FL1PACKEN) & M_FW_IQ_CMD_FL1PACKEN) 6904 #define F_FW_IQ_CMD_FL1PACKEN V_FW_IQ_CMD_FL1PACKEN(1U) 6905 6906 #define S_FW_IQ_CMD_FL1CONGEN 0 6907 #define M_FW_IQ_CMD_FL1CONGEN 0x1 6908 #define V_FW_IQ_CMD_FL1CONGEN(x) ((x) << S_FW_IQ_CMD_FL1CONGEN) 6909 #define G_FW_IQ_CMD_FL1CONGEN(x) \ 6910 (((x) >> S_FW_IQ_CMD_FL1CONGEN) & M_FW_IQ_CMD_FL1CONGEN) 6911 #define F_FW_IQ_CMD_FL1CONGEN V_FW_IQ_CMD_FL1CONGEN(1U) 6912 6913 #define S_FW_IQ_CMD_FL1DCAEN 15 6914 #define M_FW_IQ_CMD_FL1DCAEN 0x1 6915 #define V_FW_IQ_CMD_FL1DCAEN(x) ((x) << S_FW_IQ_CMD_FL1DCAEN) 6916 #define G_FW_IQ_CMD_FL1DCAEN(x) \ 6917 (((x) >> S_FW_IQ_CMD_FL1DCAEN) & M_FW_IQ_CMD_FL1DCAEN) 6918 #define F_FW_IQ_CMD_FL1DCAEN V_FW_IQ_CMD_FL1DCAEN(1U) 6919 6920 #define S_FW_IQ_CMD_FL1DCACPU 10 6921 #define M_FW_IQ_CMD_FL1DCACPU 0x1f 6922 #define V_FW_IQ_CMD_FL1DCACPU(x) ((x) << S_FW_IQ_CMD_FL1DCACPU) 6923 #define G_FW_IQ_CMD_FL1DCACPU(x) \ 6924 (((x) >> S_FW_IQ_CMD_FL1DCACPU) & M_FW_IQ_CMD_FL1DCACPU) 6925 6926 #define S_FW_IQ_CMD_FL1FBMIN 7 6927 #define M_FW_IQ_CMD_FL1FBMIN 0x7 6928 #define V_FW_IQ_CMD_FL1FBMIN(x) ((x) << S_FW_IQ_CMD_FL1FBMIN) 6929 #define G_FW_IQ_CMD_FL1FBMIN(x) \ 6930 (((x) >> S_FW_IQ_CMD_FL1FBMIN) & M_FW_IQ_CMD_FL1FBMIN) 6931 6932 #define S_FW_IQ_CMD_FL1FBMAX 4 6933 #define M_FW_IQ_CMD_FL1FBMAX 0x7 6934 #define V_FW_IQ_CMD_FL1FBMAX(x) ((x) << S_FW_IQ_CMD_FL1FBMAX) 6935 #define G_FW_IQ_CMD_FL1FBMAX(x) \ 6936 (((x) >> S_FW_IQ_CMD_FL1FBMAX) & M_FW_IQ_CMD_FL1FBMAX) 6937 6938 #define S_FW_IQ_CMD_FL1CIDXFTHRESHO 3 6939 #define M_FW_IQ_CMD_FL1CIDXFTHRESHO 0x1 6940 #define V_FW_IQ_CMD_FL1CIDXFTHRESHO(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESHO) 6941 #define G_FW_IQ_CMD_FL1CIDXFTHRESHO(x) \ 6942 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESHO) & M_FW_IQ_CMD_FL1CIDXFTHRESHO) 6943 #define F_FW_IQ_CMD_FL1CIDXFTHRESHO V_FW_IQ_CMD_FL1CIDXFTHRESHO(1U) 6944 6945 #define S_FW_IQ_CMD_FL1CIDXFTHRESH 0 6946 #define M_FW_IQ_CMD_FL1CIDXFTHRESH 0x7 6947 #define V_FW_IQ_CMD_FL1CIDXFTHRESH(x) ((x) << S_FW_IQ_CMD_FL1CIDXFTHRESH) 6948 #define G_FW_IQ_CMD_FL1CIDXFTHRESH(x) \ 6949 (((x) >> S_FW_IQ_CMD_FL1CIDXFTHRESH) & M_FW_IQ_CMD_FL1CIDXFTHRESH) 6950 6951 struct fw_eq_mngt_cmd { 6952 __be32 op_to_vfn; 6953 __be32 alloc_to_len16; 6954 __be32 cmpliqid_eqid; 6955 __be32 physeqid_pkd; 6956 __be32 fetchszm_to_iqid; 6957 __be32 dcaen_to_eqsize; 6958 __be64 eqaddr; 6959 }; 6960 6961 #define S_FW_EQ_MNGT_CMD_PFN 8 6962 #define M_FW_EQ_MNGT_CMD_PFN 0x7 6963 #define V_FW_EQ_MNGT_CMD_PFN(x) ((x) << S_FW_EQ_MNGT_CMD_PFN) 6964 #define G_FW_EQ_MNGT_CMD_PFN(x) \ 6965 (((x) >> S_FW_EQ_MNGT_CMD_PFN) & M_FW_EQ_MNGT_CMD_PFN) 6966 6967 #define S_FW_EQ_MNGT_CMD_VFN 0 6968 #define M_FW_EQ_MNGT_CMD_VFN 0xff 6969 #define V_FW_EQ_MNGT_CMD_VFN(x) ((x) << S_FW_EQ_MNGT_CMD_VFN) 6970 #define G_FW_EQ_MNGT_CMD_VFN(x) \ 6971 (((x) >> S_FW_EQ_MNGT_CMD_VFN) & M_FW_EQ_MNGT_CMD_VFN) 6972 6973 #define S_FW_EQ_MNGT_CMD_ALLOC 31 6974 #define M_FW_EQ_MNGT_CMD_ALLOC 0x1 6975 #define V_FW_EQ_MNGT_CMD_ALLOC(x) ((x) << S_FW_EQ_MNGT_CMD_ALLOC) 6976 #define G_FW_EQ_MNGT_CMD_ALLOC(x) \ 6977 (((x) >> S_FW_EQ_MNGT_CMD_ALLOC) & M_FW_EQ_MNGT_CMD_ALLOC) 6978 #define F_FW_EQ_MNGT_CMD_ALLOC V_FW_EQ_MNGT_CMD_ALLOC(1U) 6979 6980 #define S_FW_EQ_MNGT_CMD_FREE 30 6981 #define M_FW_EQ_MNGT_CMD_FREE 0x1 6982 #define V_FW_EQ_MNGT_CMD_FREE(x) ((x) << S_FW_EQ_MNGT_CMD_FREE) 6983 #define G_FW_EQ_MNGT_CMD_FREE(x) \ 6984 (((x) >> S_FW_EQ_MNGT_CMD_FREE) & M_FW_EQ_MNGT_CMD_FREE) 6985 #define F_FW_EQ_MNGT_CMD_FREE V_FW_EQ_MNGT_CMD_FREE(1U) 6986 6987 #define S_FW_EQ_MNGT_CMD_MODIFY 29 6988 #define M_FW_EQ_MNGT_CMD_MODIFY 0x1 6989 #define V_FW_EQ_MNGT_CMD_MODIFY(x) ((x) << S_FW_EQ_MNGT_CMD_MODIFY) 6990 #define G_FW_EQ_MNGT_CMD_MODIFY(x) \ 6991 (((x) >> S_FW_EQ_MNGT_CMD_MODIFY) & M_FW_EQ_MNGT_CMD_MODIFY) 6992 #define F_FW_EQ_MNGT_CMD_MODIFY V_FW_EQ_MNGT_CMD_MODIFY(1U) 6993 6994 #define S_FW_EQ_MNGT_CMD_EQSTART 28 6995 #define M_FW_EQ_MNGT_CMD_EQSTART 0x1 6996 #define V_FW_EQ_MNGT_CMD_EQSTART(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTART) 6997 #define G_FW_EQ_MNGT_CMD_EQSTART(x) \ 6998 (((x) >> S_FW_EQ_MNGT_CMD_EQSTART) & M_FW_EQ_MNGT_CMD_EQSTART) 6999 #define F_FW_EQ_MNGT_CMD_EQSTART V_FW_EQ_MNGT_CMD_EQSTART(1U) 7000 7001 #define S_FW_EQ_MNGT_CMD_EQSTOP 27 7002 #define M_FW_EQ_MNGT_CMD_EQSTOP 0x1 7003 #define V_FW_EQ_MNGT_CMD_EQSTOP(x) ((x) << S_FW_EQ_MNGT_CMD_EQSTOP) 7004 #define G_FW_EQ_MNGT_CMD_EQSTOP(x) \ 7005 (((x) >> S_FW_EQ_MNGT_CMD_EQSTOP) & M_FW_EQ_MNGT_CMD_EQSTOP) 7006 #define F_FW_EQ_MNGT_CMD_EQSTOP V_FW_EQ_MNGT_CMD_EQSTOP(1U) 7007 7008 #define S_FW_EQ_MNGT_CMD_COREGROUP 16 7009 #define M_FW_EQ_MNGT_CMD_COREGROUP 0x3f 7010 #define V_FW_EQ_MNGT_CMD_COREGROUP(x) ((x) << S_FW_EQ_MNGT_CMD_COREGROUP) 7011 #define G_FW_EQ_MNGT_CMD_COREGROUP(x) \ 7012 (((x) >> S_FW_EQ_MNGT_CMD_COREGROUP) & M_FW_EQ_MNGT_CMD_COREGROUP) 7013 7014 #define S_FW_EQ_MNGT_CMD_CMPLIQID 20 7015 #define M_FW_EQ_MNGT_CMD_CMPLIQID 0xfff 7016 #define V_FW_EQ_MNGT_CMD_CMPLIQID(x) ((x) << S_FW_EQ_MNGT_CMD_CMPLIQID) 7017 #define G_FW_EQ_MNGT_CMD_CMPLIQID(x) \ 7018 (((x) >> S_FW_EQ_MNGT_CMD_CMPLIQID) & M_FW_EQ_MNGT_CMD_CMPLIQID) 7019 7020 #define S_FW_EQ_MNGT_CMD_EQID 0 7021 #define M_FW_EQ_MNGT_CMD_EQID 0xfffff 7022 #define V_FW_EQ_MNGT_CMD_EQID(x) ((x) << S_FW_EQ_MNGT_CMD_EQID) 7023 #define G_FW_EQ_MNGT_CMD_EQID(x) \ 7024 (((x) >> S_FW_EQ_MNGT_CMD_EQID) & M_FW_EQ_MNGT_CMD_EQID) 7025 7026 #define S_FW_EQ_MNGT_CMD_PHYSEQID 0 7027 #define M_FW_EQ_MNGT_CMD_PHYSEQID 0xfffff 7028 #define V_FW_EQ_MNGT_CMD_PHYSEQID(x) ((x) << S_FW_EQ_MNGT_CMD_PHYSEQID) 7029 #define G_FW_EQ_MNGT_CMD_PHYSEQID(x) \ 7030 (((x) >> S_FW_EQ_MNGT_CMD_PHYSEQID) & M_FW_EQ_MNGT_CMD_PHYSEQID) 7031 7032 #define S_FW_EQ_MNGT_CMD_FETCHSZM 26 7033 #define M_FW_EQ_MNGT_CMD_FETCHSZM 0x1 7034 #define V_FW_EQ_MNGT_CMD_FETCHSZM(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHSZM) 7035 #define G_FW_EQ_MNGT_CMD_FETCHSZM(x) \ 7036 (((x) >> S_FW_EQ_MNGT_CMD_FETCHSZM) & M_FW_EQ_MNGT_CMD_FETCHSZM) 7037 #define F_FW_EQ_MNGT_CMD_FETCHSZM V_FW_EQ_MNGT_CMD_FETCHSZM(1U) 7038 7039 #define S_FW_EQ_MNGT_CMD_STATUSPGNS 25 7040 #define M_FW_EQ_MNGT_CMD_STATUSPGNS 0x1 7041 #define V_FW_EQ_MNGT_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGNS) 7042 #define G_FW_EQ_MNGT_CMD_STATUSPGNS(x) \ 7043 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGNS) & M_FW_EQ_MNGT_CMD_STATUSPGNS) 7044 #define F_FW_EQ_MNGT_CMD_STATUSPGNS V_FW_EQ_MNGT_CMD_STATUSPGNS(1U) 7045 7046 #define S_FW_EQ_MNGT_CMD_STATUSPGRO 24 7047 #define M_FW_EQ_MNGT_CMD_STATUSPGRO 0x1 7048 #define V_FW_EQ_MNGT_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_MNGT_CMD_STATUSPGRO) 7049 #define G_FW_EQ_MNGT_CMD_STATUSPGRO(x) \ 7050 (((x) >> S_FW_EQ_MNGT_CMD_STATUSPGRO) & M_FW_EQ_MNGT_CMD_STATUSPGRO) 7051 #define F_FW_EQ_MNGT_CMD_STATUSPGRO V_FW_EQ_MNGT_CMD_STATUSPGRO(1U) 7052 7053 #define S_FW_EQ_MNGT_CMD_FETCHNS 23 7054 #define M_FW_EQ_MNGT_CMD_FETCHNS 0x1 7055 #define V_FW_EQ_MNGT_CMD_FETCHNS(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHNS) 7056 #define G_FW_EQ_MNGT_CMD_FETCHNS(x) \ 7057 (((x) >> S_FW_EQ_MNGT_CMD_FETCHNS) & M_FW_EQ_MNGT_CMD_FETCHNS) 7058 #define F_FW_EQ_MNGT_CMD_FETCHNS V_FW_EQ_MNGT_CMD_FETCHNS(1U) 7059 7060 #define S_FW_EQ_MNGT_CMD_FETCHRO 22 7061 #define M_FW_EQ_MNGT_CMD_FETCHRO 0x1 7062 #define V_FW_EQ_MNGT_CMD_FETCHRO(x) ((x) << S_FW_EQ_MNGT_CMD_FETCHRO) 7063 #define G_FW_EQ_MNGT_CMD_FETCHRO(x) \ 7064 (((x) >> S_FW_EQ_MNGT_CMD_FETCHRO) & M_FW_EQ_MNGT_CMD_FETCHRO) 7065 #define F_FW_EQ_MNGT_CMD_FETCHRO V_FW_EQ_MNGT_CMD_FETCHRO(1U) 7066 7067 #define S_FW_EQ_MNGT_CMD_HOSTFCMODE 20 7068 #define M_FW_EQ_MNGT_CMD_HOSTFCMODE 0x3 7069 #define V_FW_EQ_MNGT_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_MNGT_CMD_HOSTFCMODE) 7070 #define G_FW_EQ_MNGT_CMD_HOSTFCMODE(x) \ 7071 (((x) >> S_FW_EQ_MNGT_CMD_HOSTFCMODE) & M_FW_EQ_MNGT_CMD_HOSTFCMODE) 7072 7073 #define S_FW_EQ_MNGT_CMD_CPRIO 19 7074 #define M_FW_EQ_MNGT_CMD_CPRIO 0x1 7075 #define V_FW_EQ_MNGT_CMD_CPRIO(x) ((x) << S_FW_EQ_MNGT_CMD_CPRIO) 7076 #define G_FW_EQ_MNGT_CMD_CPRIO(x) \ 7077 (((x) >> S_FW_EQ_MNGT_CMD_CPRIO) & M_FW_EQ_MNGT_CMD_CPRIO) 7078 #define F_FW_EQ_MNGT_CMD_CPRIO V_FW_EQ_MNGT_CMD_CPRIO(1U) 7079 7080 #define S_FW_EQ_MNGT_CMD_ONCHIP 18 7081 #define M_FW_EQ_MNGT_CMD_ONCHIP 0x1 7082 #define V_FW_EQ_MNGT_CMD_ONCHIP(x) ((x) << S_FW_EQ_MNGT_CMD_ONCHIP) 7083 #define G_FW_EQ_MNGT_CMD_ONCHIP(x) \ 7084 (((x) >> S_FW_EQ_MNGT_CMD_ONCHIP) & M_FW_EQ_MNGT_CMD_ONCHIP) 7085 #define F_FW_EQ_MNGT_CMD_ONCHIP V_FW_EQ_MNGT_CMD_ONCHIP(1U) 7086 7087 #define S_FW_EQ_MNGT_CMD_PCIECHN 16 7088 #define M_FW_EQ_MNGT_CMD_PCIECHN 0x3 7089 #define V_FW_EQ_MNGT_CMD_PCIECHN(x) ((x) << S_FW_EQ_MNGT_CMD_PCIECHN) 7090 #define G_FW_EQ_MNGT_CMD_PCIECHN(x) \ 7091 (((x) >> S_FW_EQ_MNGT_CMD_PCIECHN) & M_FW_EQ_MNGT_CMD_PCIECHN) 7092 7093 #define S_FW_EQ_MNGT_CMD_IQID 0 7094 #define M_FW_EQ_MNGT_CMD_IQID 0xffff 7095 #define V_FW_EQ_MNGT_CMD_IQID(x) ((x) << S_FW_EQ_MNGT_CMD_IQID) 7096 #define G_FW_EQ_MNGT_CMD_IQID(x) \ 7097 (((x) >> S_FW_EQ_MNGT_CMD_IQID) & M_FW_EQ_MNGT_CMD_IQID) 7098 7099 #define S_FW_EQ_MNGT_CMD_DCAEN 31 7100 #define M_FW_EQ_MNGT_CMD_DCAEN 0x1 7101 #define V_FW_EQ_MNGT_CMD_DCAEN(x) ((x) << S_FW_EQ_MNGT_CMD_DCAEN) 7102 #define G_FW_EQ_MNGT_CMD_DCAEN(x) \ 7103 (((x) >> S_FW_EQ_MNGT_CMD_DCAEN) & M_FW_EQ_MNGT_CMD_DCAEN) 7104 #define F_FW_EQ_MNGT_CMD_DCAEN V_FW_EQ_MNGT_CMD_DCAEN(1U) 7105 7106 #define S_FW_EQ_MNGT_CMD_DCACPU 26 7107 #define M_FW_EQ_MNGT_CMD_DCACPU 0x1f 7108 #define V_FW_EQ_MNGT_CMD_DCACPU(x) ((x) << S_FW_EQ_MNGT_CMD_DCACPU) 7109 #define G_FW_EQ_MNGT_CMD_DCACPU(x) \ 7110 (((x) >> S_FW_EQ_MNGT_CMD_DCACPU) & M_FW_EQ_MNGT_CMD_DCACPU) 7111 7112 #define S_FW_EQ_MNGT_CMD_FBMIN 23 7113 #define M_FW_EQ_MNGT_CMD_FBMIN 0x7 7114 #define V_FW_EQ_MNGT_CMD_FBMIN(x) ((x) << S_FW_EQ_MNGT_CMD_FBMIN) 7115 #define G_FW_EQ_MNGT_CMD_FBMIN(x) \ 7116 (((x) >> S_FW_EQ_MNGT_CMD_FBMIN) & M_FW_EQ_MNGT_CMD_FBMIN) 7117 7118 #define S_FW_EQ_MNGT_CMD_FBMAX 20 7119 #define M_FW_EQ_MNGT_CMD_FBMAX 0x7 7120 #define V_FW_EQ_MNGT_CMD_FBMAX(x) ((x) << S_FW_EQ_MNGT_CMD_FBMAX) 7121 #define G_FW_EQ_MNGT_CMD_FBMAX(x) \ 7122 (((x) >> S_FW_EQ_MNGT_CMD_FBMAX) & M_FW_EQ_MNGT_CMD_FBMAX) 7123 7124 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESHO 19 7125 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESHO 0x1 7126 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 7127 ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 7128 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESHO(x) \ 7129 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESHO) & M_FW_EQ_MNGT_CMD_CIDXFTHRESHO) 7130 #define F_FW_EQ_MNGT_CMD_CIDXFTHRESHO V_FW_EQ_MNGT_CMD_CIDXFTHRESHO(1U) 7131 7132 #define S_FW_EQ_MNGT_CMD_CIDXFTHRESH 16 7133 #define M_FW_EQ_MNGT_CMD_CIDXFTHRESH 0x7 7134 #define V_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_MNGT_CMD_CIDXFTHRESH) 7135 #define G_FW_EQ_MNGT_CMD_CIDXFTHRESH(x) \ 7136 (((x) >> S_FW_EQ_MNGT_CMD_CIDXFTHRESH) & M_FW_EQ_MNGT_CMD_CIDXFTHRESH) 7137 7138 #define S_FW_EQ_MNGT_CMD_EQSIZE 0 7139 #define M_FW_EQ_MNGT_CMD_EQSIZE 0xffff 7140 #define V_FW_EQ_MNGT_CMD_EQSIZE(x) ((x) << S_FW_EQ_MNGT_CMD_EQSIZE) 7141 #define G_FW_EQ_MNGT_CMD_EQSIZE(x) \ 7142 (((x) >> S_FW_EQ_MNGT_CMD_EQSIZE) & M_FW_EQ_MNGT_CMD_EQSIZE) 7143 7144 struct fw_eq_eth_cmd { 7145 __be32 op_to_vfn; 7146 __be32 alloc_to_len16; 7147 __be32 eqid_pkd; 7148 __be32 physeqid_pkd; 7149 __be32 fetchszm_to_iqid; 7150 __be32 dcaen_to_eqsize; 7151 __be64 eqaddr; 7152 __be32 autoequiqe_to_viid; 7153 __be32 timeren_timerix; 7154 __be64 r9; 7155 }; 7156 7157 #define S_FW_EQ_ETH_CMD_PFN 8 7158 #define M_FW_EQ_ETH_CMD_PFN 0x7 7159 #define V_FW_EQ_ETH_CMD_PFN(x) ((x) << S_FW_EQ_ETH_CMD_PFN) 7160 #define G_FW_EQ_ETH_CMD_PFN(x) \ 7161 (((x) >> S_FW_EQ_ETH_CMD_PFN) & M_FW_EQ_ETH_CMD_PFN) 7162 7163 #define S_FW_EQ_ETH_CMD_VFN 0 7164 #define M_FW_EQ_ETH_CMD_VFN 0xff 7165 #define V_FW_EQ_ETH_CMD_VFN(x) ((x) << S_FW_EQ_ETH_CMD_VFN) 7166 #define G_FW_EQ_ETH_CMD_VFN(x) \ 7167 (((x) >> S_FW_EQ_ETH_CMD_VFN) & M_FW_EQ_ETH_CMD_VFN) 7168 7169 #define S_FW_EQ_ETH_CMD_ALLOC 31 7170 #define M_FW_EQ_ETH_CMD_ALLOC 0x1 7171 #define V_FW_EQ_ETH_CMD_ALLOC(x) ((x) << S_FW_EQ_ETH_CMD_ALLOC) 7172 #define G_FW_EQ_ETH_CMD_ALLOC(x) \ 7173 (((x) >> S_FW_EQ_ETH_CMD_ALLOC) & M_FW_EQ_ETH_CMD_ALLOC) 7174 #define F_FW_EQ_ETH_CMD_ALLOC V_FW_EQ_ETH_CMD_ALLOC(1U) 7175 7176 #define S_FW_EQ_ETH_CMD_FREE 30 7177 #define M_FW_EQ_ETH_CMD_FREE 0x1 7178 #define V_FW_EQ_ETH_CMD_FREE(x) ((x) << S_FW_EQ_ETH_CMD_FREE) 7179 #define G_FW_EQ_ETH_CMD_FREE(x) \ 7180 (((x) >> S_FW_EQ_ETH_CMD_FREE) & M_FW_EQ_ETH_CMD_FREE) 7181 #define F_FW_EQ_ETH_CMD_FREE V_FW_EQ_ETH_CMD_FREE(1U) 7182 7183 #define S_FW_EQ_ETH_CMD_MODIFY 29 7184 #define M_FW_EQ_ETH_CMD_MODIFY 0x1 7185 #define V_FW_EQ_ETH_CMD_MODIFY(x) ((x) << S_FW_EQ_ETH_CMD_MODIFY) 7186 #define G_FW_EQ_ETH_CMD_MODIFY(x) \ 7187 (((x) >> S_FW_EQ_ETH_CMD_MODIFY) & M_FW_EQ_ETH_CMD_MODIFY) 7188 #define F_FW_EQ_ETH_CMD_MODIFY V_FW_EQ_ETH_CMD_MODIFY(1U) 7189 7190 #define S_FW_EQ_ETH_CMD_EQSTART 28 7191 #define M_FW_EQ_ETH_CMD_EQSTART 0x1 7192 #define V_FW_EQ_ETH_CMD_EQSTART(x) ((x) << S_FW_EQ_ETH_CMD_EQSTART) 7193 #define G_FW_EQ_ETH_CMD_EQSTART(x) \ 7194 (((x) >> S_FW_EQ_ETH_CMD_EQSTART) & M_FW_EQ_ETH_CMD_EQSTART) 7195 #define F_FW_EQ_ETH_CMD_EQSTART V_FW_EQ_ETH_CMD_EQSTART(1U) 7196 7197 #define S_FW_EQ_ETH_CMD_EQSTOP 27 7198 #define M_FW_EQ_ETH_CMD_EQSTOP 0x1 7199 #define V_FW_EQ_ETH_CMD_EQSTOP(x) ((x) << S_FW_EQ_ETH_CMD_EQSTOP) 7200 #define G_FW_EQ_ETH_CMD_EQSTOP(x) \ 7201 (((x) >> S_FW_EQ_ETH_CMD_EQSTOP) & M_FW_EQ_ETH_CMD_EQSTOP) 7202 #define F_FW_EQ_ETH_CMD_EQSTOP V_FW_EQ_ETH_CMD_EQSTOP(1U) 7203 7204 #define S_FW_EQ_ETH_CMD_COREGROUP 16 7205 #define M_FW_EQ_ETH_CMD_COREGROUP 0x3f 7206 #define V_FW_EQ_ETH_CMD_COREGROUP(x) ((x) << S_FW_EQ_ETH_CMD_COREGROUP) 7207 #define G_FW_EQ_ETH_CMD_COREGROUP(x) \ 7208 (((x) >> S_FW_EQ_ETH_CMD_COREGROUP) & M_FW_EQ_ETH_CMD_COREGROUP) 7209 7210 #define S_FW_EQ_ETH_CMD_EQID 0 7211 #define M_FW_EQ_ETH_CMD_EQID 0xfffff 7212 #define V_FW_EQ_ETH_CMD_EQID(x) ((x) << S_FW_EQ_ETH_CMD_EQID) 7213 #define G_FW_EQ_ETH_CMD_EQID(x) \ 7214 (((x) >> S_FW_EQ_ETH_CMD_EQID) & M_FW_EQ_ETH_CMD_EQID) 7215 7216 #define S_FW_EQ_ETH_CMD_PHYSEQID 0 7217 #define M_FW_EQ_ETH_CMD_PHYSEQID 0xfffff 7218 #define V_FW_EQ_ETH_CMD_PHYSEQID(x) ((x) << S_FW_EQ_ETH_CMD_PHYSEQID) 7219 #define G_FW_EQ_ETH_CMD_PHYSEQID(x) \ 7220 (((x) >> S_FW_EQ_ETH_CMD_PHYSEQID) & M_FW_EQ_ETH_CMD_PHYSEQID) 7221 7222 #define S_FW_EQ_ETH_CMD_FETCHSZM 26 7223 #define M_FW_EQ_ETH_CMD_FETCHSZM 0x1 7224 #define V_FW_EQ_ETH_CMD_FETCHSZM(x) ((x) << S_FW_EQ_ETH_CMD_FETCHSZM) 7225 #define G_FW_EQ_ETH_CMD_FETCHSZM(x) \ 7226 (((x) >> S_FW_EQ_ETH_CMD_FETCHSZM) & M_FW_EQ_ETH_CMD_FETCHSZM) 7227 #define F_FW_EQ_ETH_CMD_FETCHSZM V_FW_EQ_ETH_CMD_FETCHSZM(1U) 7228 7229 #define S_FW_EQ_ETH_CMD_STATUSPGNS 25 7230 #define M_FW_EQ_ETH_CMD_STATUSPGNS 0x1 7231 #define V_FW_EQ_ETH_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGNS) 7232 #define G_FW_EQ_ETH_CMD_STATUSPGNS(x) \ 7233 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGNS) & M_FW_EQ_ETH_CMD_STATUSPGNS) 7234 #define F_FW_EQ_ETH_CMD_STATUSPGNS V_FW_EQ_ETH_CMD_STATUSPGNS(1U) 7235 7236 #define S_FW_EQ_ETH_CMD_STATUSPGRO 24 7237 #define M_FW_EQ_ETH_CMD_STATUSPGRO 0x1 7238 #define V_FW_EQ_ETH_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_ETH_CMD_STATUSPGRO) 7239 #define G_FW_EQ_ETH_CMD_STATUSPGRO(x) \ 7240 (((x) >> S_FW_EQ_ETH_CMD_STATUSPGRO) & M_FW_EQ_ETH_CMD_STATUSPGRO) 7241 #define F_FW_EQ_ETH_CMD_STATUSPGRO V_FW_EQ_ETH_CMD_STATUSPGRO(1U) 7242 7243 #define S_FW_EQ_ETH_CMD_FETCHNS 23 7244 #define M_FW_EQ_ETH_CMD_FETCHNS 0x1 7245 #define V_FW_EQ_ETH_CMD_FETCHNS(x) ((x) << S_FW_EQ_ETH_CMD_FETCHNS) 7246 #define G_FW_EQ_ETH_CMD_FETCHNS(x) \ 7247 (((x) >> S_FW_EQ_ETH_CMD_FETCHNS) & M_FW_EQ_ETH_CMD_FETCHNS) 7248 #define F_FW_EQ_ETH_CMD_FETCHNS V_FW_EQ_ETH_CMD_FETCHNS(1U) 7249 7250 #define S_FW_EQ_ETH_CMD_FETCHRO 22 7251 #define M_FW_EQ_ETH_CMD_FETCHRO 0x1 7252 #define V_FW_EQ_ETH_CMD_FETCHRO(x) ((x) << S_FW_EQ_ETH_CMD_FETCHRO) 7253 #define G_FW_EQ_ETH_CMD_FETCHRO(x) \ 7254 (((x) >> S_FW_EQ_ETH_CMD_FETCHRO) & M_FW_EQ_ETH_CMD_FETCHRO) 7255 #define F_FW_EQ_ETH_CMD_FETCHRO V_FW_EQ_ETH_CMD_FETCHRO(1U) 7256 7257 #define S_FW_EQ_ETH_CMD_HOSTFCMODE 20 7258 #define M_FW_EQ_ETH_CMD_HOSTFCMODE 0x3 7259 #define V_FW_EQ_ETH_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_ETH_CMD_HOSTFCMODE) 7260 #define G_FW_EQ_ETH_CMD_HOSTFCMODE(x) \ 7261 (((x) >> S_FW_EQ_ETH_CMD_HOSTFCMODE) & M_FW_EQ_ETH_CMD_HOSTFCMODE) 7262 7263 #define S_FW_EQ_ETH_CMD_CPRIO 19 7264 #define M_FW_EQ_ETH_CMD_CPRIO 0x1 7265 #define V_FW_EQ_ETH_CMD_CPRIO(x) ((x) << S_FW_EQ_ETH_CMD_CPRIO) 7266 #define G_FW_EQ_ETH_CMD_CPRIO(x) \ 7267 (((x) >> S_FW_EQ_ETH_CMD_CPRIO) & M_FW_EQ_ETH_CMD_CPRIO) 7268 #define F_FW_EQ_ETH_CMD_CPRIO V_FW_EQ_ETH_CMD_CPRIO(1U) 7269 7270 #define S_FW_EQ_ETH_CMD_ONCHIP 18 7271 #define M_FW_EQ_ETH_CMD_ONCHIP 0x1 7272 #define V_FW_EQ_ETH_CMD_ONCHIP(x) ((x) << S_FW_EQ_ETH_CMD_ONCHIP) 7273 #define G_FW_EQ_ETH_CMD_ONCHIP(x) \ 7274 (((x) >> S_FW_EQ_ETH_CMD_ONCHIP) & M_FW_EQ_ETH_CMD_ONCHIP) 7275 #define F_FW_EQ_ETH_CMD_ONCHIP V_FW_EQ_ETH_CMD_ONCHIP(1U) 7276 7277 #define S_FW_EQ_ETH_CMD_PCIECHN 16 7278 #define M_FW_EQ_ETH_CMD_PCIECHN 0x3 7279 #define V_FW_EQ_ETH_CMD_PCIECHN(x) ((x) << S_FW_EQ_ETH_CMD_PCIECHN) 7280 #define G_FW_EQ_ETH_CMD_PCIECHN(x) \ 7281 (((x) >> S_FW_EQ_ETH_CMD_PCIECHN) & M_FW_EQ_ETH_CMD_PCIECHN) 7282 7283 #define S_FW_EQ_ETH_CMD_IQID 0 7284 #define M_FW_EQ_ETH_CMD_IQID 0xffff 7285 #define V_FW_EQ_ETH_CMD_IQID(x) ((x) << S_FW_EQ_ETH_CMD_IQID) 7286 #define G_FW_EQ_ETH_CMD_IQID(x) \ 7287 (((x) >> S_FW_EQ_ETH_CMD_IQID) & M_FW_EQ_ETH_CMD_IQID) 7288 7289 #define S_FW_EQ_ETH_CMD_DCAEN 31 7290 #define M_FW_EQ_ETH_CMD_DCAEN 0x1 7291 #define V_FW_EQ_ETH_CMD_DCAEN(x) ((x) << S_FW_EQ_ETH_CMD_DCAEN) 7292 #define G_FW_EQ_ETH_CMD_DCAEN(x) \ 7293 (((x) >> S_FW_EQ_ETH_CMD_DCAEN) & M_FW_EQ_ETH_CMD_DCAEN) 7294 #define F_FW_EQ_ETH_CMD_DCAEN V_FW_EQ_ETH_CMD_DCAEN(1U) 7295 7296 #define S_FW_EQ_ETH_CMD_DCACPU 26 7297 #define M_FW_EQ_ETH_CMD_DCACPU 0x1f 7298 #define V_FW_EQ_ETH_CMD_DCACPU(x) ((x) << S_FW_EQ_ETH_CMD_DCACPU) 7299 #define G_FW_EQ_ETH_CMD_DCACPU(x) \ 7300 (((x) >> S_FW_EQ_ETH_CMD_DCACPU) & M_FW_EQ_ETH_CMD_DCACPU) 7301 7302 #define S_FW_EQ_ETH_CMD_FBMIN 23 7303 #define M_FW_EQ_ETH_CMD_FBMIN 0x7 7304 #define V_FW_EQ_ETH_CMD_FBMIN(x) ((x) << S_FW_EQ_ETH_CMD_FBMIN) 7305 #define G_FW_EQ_ETH_CMD_FBMIN(x) \ 7306 (((x) >> S_FW_EQ_ETH_CMD_FBMIN) & M_FW_EQ_ETH_CMD_FBMIN) 7307 7308 #define S_FW_EQ_ETH_CMD_FBMAX 20 7309 #define M_FW_EQ_ETH_CMD_FBMAX 0x7 7310 #define V_FW_EQ_ETH_CMD_FBMAX(x) ((x) << S_FW_EQ_ETH_CMD_FBMAX) 7311 #define G_FW_EQ_ETH_CMD_FBMAX(x) \ 7312 (((x) >> S_FW_EQ_ETH_CMD_FBMAX) & M_FW_EQ_ETH_CMD_FBMAX) 7313 7314 #define S_FW_EQ_ETH_CMD_CIDXFTHRESHO 19 7315 #define M_FW_EQ_ETH_CMD_CIDXFTHRESHO 0x1 7316 #define V_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESHO) 7317 #define G_FW_EQ_ETH_CMD_CIDXFTHRESHO(x) \ 7318 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESHO) & M_FW_EQ_ETH_CMD_CIDXFTHRESHO) 7319 #define F_FW_EQ_ETH_CMD_CIDXFTHRESHO V_FW_EQ_ETH_CMD_CIDXFTHRESHO(1U) 7320 7321 #define S_FW_EQ_ETH_CMD_CIDXFTHRESH 16 7322 #define M_FW_EQ_ETH_CMD_CIDXFTHRESH 0x7 7323 #define V_FW_EQ_ETH_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_ETH_CMD_CIDXFTHRESH) 7324 #define G_FW_EQ_ETH_CMD_CIDXFTHRESH(x) \ 7325 (((x) >> S_FW_EQ_ETH_CMD_CIDXFTHRESH) & M_FW_EQ_ETH_CMD_CIDXFTHRESH) 7326 7327 #define S_FW_EQ_ETH_CMD_EQSIZE 0 7328 #define M_FW_EQ_ETH_CMD_EQSIZE 0xffff 7329 #define V_FW_EQ_ETH_CMD_EQSIZE(x) ((x) << S_FW_EQ_ETH_CMD_EQSIZE) 7330 #define G_FW_EQ_ETH_CMD_EQSIZE(x) \ 7331 (((x) >> S_FW_EQ_ETH_CMD_EQSIZE) & M_FW_EQ_ETH_CMD_EQSIZE) 7332 7333 #define S_FW_EQ_ETH_CMD_AUTOEQUIQE 31 7334 #define M_FW_EQ_ETH_CMD_AUTOEQUIQE 0x1 7335 #define V_FW_EQ_ETH_CMD_AUTOEQUIQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUIQE) 7336 #define G_FW_EQ_ETH_CMD_AUTOEQUIQE(x) \ 7337 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUIQE) & M_FW_EQ_ETH_CMD_AUTOEQUIQE) 7338 #define F_FW_EQ_ETH_CMD_AUTOEQUIQE V_FW_EQ_ETH_CMD_AUTOEQUIQE(1U) 7339 7340 #define S_FW_EQ_ETH_CMD_AUTOEQUEQE 30 7341 #define M_FW_EQ_ETH_CMD_AUTOEQUEQE 0x1 7342 #define V_FW_EQ_ETH_CMD_AUTOEQUEQE(x) ((x) << S_FW_EQ_ETH_CMD_AUTOEQUEQE) 7343 #define G_FW_EQ_ETH_CMD_AUTOEQUEQE(x) \ 7344 (((x) >> S_FW_EQ_ETH_CMD_AUTOEQUEQE) & M_FW_EQ_ETH_CMD_AUTOEQUEQE) 7345 #define F_FW_EQ_ETH_CMD_AUTOEQUEQE V_FW_EQ_ETH_CMD_AUTOEQUEQE(1U) 7346 7347 #define S_FW_EQ_ETH_CMD_VIID 16 7348 #define M_FW_EQ_ETH_CMD_VIID 0xfff 7349 #define V_FW_EQ_ETH_CMD_VIID(x) ((x) << S_FW_EQ_ETH_CMD_VIID) 7350 #define G_FW_EQ_ETH_CMD_VIID(x) \ 7351 (((x) >> S_FW_EQ_ETH_CMD_VIID) & M_FW_EQ_ETH_CMD_VIID) 7352 7353 #define S_FW_EQ_ETH_CMD_TIMEREN 3 7354 #define M_FW_EQ_ETH_CMD_TIMEREN 0x1 7355 #define V_FW_EQ_ETH_CMD_TIMEREN(x) ((x) << S_FW_EQ_ETH_CMD_TIMEREN) 7356 #define G_FW_EQ_ETH_CMD_TIMEREN(x) \ 7357 (((x) >> S_FW_EQ_ETH_CMD_TIMEREN) & M_FW_EQ_ETH_CMD_TIMEREN) 7358 #define F_FW_EQ_ETH_CMD_TIMEREN V_FW_EQ_ETH_CMD_TIMEREN(1U) 7359 7360 #define S_FW_EQ_ETH_CMD_TIMERIX 0 7361 #define M_FW_EQ_ETH_CMD_TIMERIX 0x7 7362 #define V_FW_EQ_ETH_CMD_TIMERIX(x) ((x) << S_FW_EQ_ETH_CMD_TIMERIX) 7363 #define G_FW_EQ_ETH_CMD_TIMERIX(x) \ 7364 (((x) >> S_FW_EQ_ETH_CMD_TIMERIX) & M_FW_EQ_ETH_CMD_TIMERIX) 7365 7366 struct fw_eq_ctrl_cmd { 7367 __be32 op_to_vfn; 7368 __be32 alloc_to_len16; 7369 __be32 cmpliqid_eqid; 7370 __be32 physeqid_pkd; 7371 __be32 fetchszm_to_iqid; 7372 __be32 dcaen_to_eqsize; 7373 __be64 eqaddr; 7374 }; 7375 7376 #define S_FW_EQ_CTRL_CMD_PFN 8 7377 #define M_FW_EQ_CTRL_CMD_PFN 0x7 7378 #define V_FW_EQ_CTRL_CMD_PFN(x) ((x) << S_FW_EQ_CTRL_CMD_PFN) 7379 #define G_FW_EQ_CTRL_CMD_PFN(x) \ 7380 (((x) >> S_FW_EQ_CTRL_CMD_PFN) & M_FW_EQ_CTRL_CMD_PFN) 7381 7382 #define S_FW_EQ_CTRL_CMD_VFN 0 7383 #define M_FW_EQ_CTRL_CMD_VFN 0xff 7384 #define V_FW_EQ_CTRL_CMD_VFN(x) ((x) << S_FW_EQ_CTRL_CMD_VFN) 7385 #define G_FW_EQ_CTRL_CMD_VFN(x) \ 7386 (((x) >> S_FW_EQ_CTRL_CMD_VFN) & M_FW_EQ_CTRL_CMD_VFN) 7387 7388 #define S_FW_EQ_CTRL_CMD_ALLOC 31 7389 #define M_FW_EQ_CTRL_CMD_ALLOC 0x1 7390 #define V_FW_EQ_CTRL_CMD_ALLOC(x) ((x) << S_FW_EQ_CTRL_CMD_ALLOC) 7391 #define G_FW_EQ_CTRL_CMD_ALLOC(x) \ 7392 (((x) >> S_FW_EQ_CTRL_CMD_ALLOC) & M_FW_EQ_CTRL_CMD_ALLOC) 7393 #define F_FW_EQ_CTRL_CMD_ALLOC V_FW_EQ_CTRL_CMD_ALLOC(1U) 7394 7395 #define S_FW_EQ_CTRL_CMD_FREE 30 7396 #define M_FW_EQ_CTRL_CMD_FREE 0x1 7397 #define V_FW_EQ_CTRL_CMD_FREE(x) ((x) << S_FW_EQ_CTRL_CMD_FREE) 7398 #define G_FW_EQ_CTRL_CMD_FREE(x) \ 7399 (((x) >> S_FW_EQ_CTRL_CMD_FREE) & M_FW_EQ_CTRL_CMD_FREE) 7400 #define F_FW_EQ_CTRL_CMD_FREE V_FW_EQ_CTRL_CMD_FREE(1U) 7401 7402 #define S_FW_EQ_CTRL_CMD_MODIFY 29 7403 #define M_FW_EQ_CTRL_CMD_MODIFY 0x1 7404 #define V_FW_EQ_CTRL_CMD_MODIFY(x) ((x) << S_FW_EQ_CTRL_CMD_MODIFY) 7405 #define G_FW_EQ_CTRL_CMD_MODIFY(x) \ 7406 (((x) >> S_FW_EQ_CTRL_CMD_MODIFY) & M_FW_EQ_CTRL_CMD_MODIFY) 7407 #define F_FW_EQ_CTRL_CMD_MODIFY V_FW_EQ_CTRL_CMD_MODIFY(1U) 7408 7409 #define S_FW_EQ_CTRL_CMD_EQSTART 28 7410 #define M_FW_EQ_CTRL_CMD_EQSTART 0x1 7411 #define V_FW_EQ_CTRL_CMD_EQSTART(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTART) 7412 #define G_FW_EQ_CTRL_CMD_EQSTART(x) \ 7413 (((x) >> S_FW_EQ_CTRL_CMD_EQSTART) & M_FW_EQ_CTRL_CMD_EQSTART) 7414 #define F_FW_EQ_CTRL_CMD_EQSTART V_FW_EQ_CTRL_CMD_EQSTART(1U) 7415 7416 #define S_FW_EQ_CTRL_CMD_EQSTOP 27 7417 #define M_FW_EQ_CTRL_CMD_EQSTOP 0x1 7418 #define V_FW_EQ_CTRL_CMD_EQSTOP(x) ((x) << S_FW_EQ_CTRL_CMD_EQSTOP) 7419 #define G_FW_EQ_CTRL_CMD_EQSTOP(x) \ 7420 (((x) >> S_FW_EQ_CTRL_CMD_EQSTOP) & M_FW_EQ_CTRL_CMD_EQSTOP) 7421 #define F_FW_EQ_CTRL_CMD_EQSTOP V_FW_EQ_CTRL_CMD_EQSTOP(1U) 7422 7423 #define S_FW_EQ_CTRL_CMD_COREGROUP 16 7424 #define M_FW_EQ_CTRL_CMD_COREGROUP 0x3f 7425 #define V_FW_EQ_CTRL_CMD_COREGROUP(x) ((x) << S_FW_EQ_CTRL_CMD_COREGROUP) 7426 #define G_FW_EQ_CTRL_CMD_COREGROUP(x) \ 7427 (((x) >> S_FW_EQ_CTRL_CMD_COREGROUP) & M_FW_EQ_CTRL_CMD_COREGROUP) 7428 7429 #define S_FW_EQ_CTRL_CMD_CMPLIQID 20 7430 #define M_FW_EQ_CTRL_CMD_CMPLIQID 0xfff 7431 #define V_FW_EQ_CTRL_CMD_CMPLIQID(x) ((x) << S_FW_EQ_CTRL_CMD_CMPLIQID) 7432 #define G_FW_EQ_CTRL_CMD_CMPLIQID(x) \ 7433 (((x) >> S_FW_EQ_CTRL_CMD_CMPLIQID) & M_FW_EQ_CTRL_CMD_CMPLIQID) 7434 7435 #define S_FW_EQ_CTRL_CMD_EQID 0 7436 #define M_FW_EQ_CTRL_CMD_EQID 0xfffff 7437 #define V_FW_EQ_CTRL_CMD_EQID(x) ((x) << S_FW_EQ_CTRL_CMD_EQID) 7438 #define G_FW_EQ_CTRL_CMD_EQID(x) \ 7439 (((x) >> S_FW_EQ_CTRL_CMD_EQID) & M_FW_EQ_CTRL_CMD_EQID) 7440 7441 #define S_FW_EQ_CTRL_CMD_PHYSEQID 0 7442 #define M_FW_EQ_CTRL_CMD_PHYSEQID 0xfffff 7443 #define V_FW_EQ_CTRL_CMD_PHYSEQID(x) ((x) << S_FW_EQ_CTRL_CMD_PHYSEQID) 7444 #define G_FW_EQ_CTRL_CMD_PHYSEQID(x) \ 7445 (((x) >> S_FW_EQ_CTRL_CMD_PHYSEQID) & M_FW_EQ_CTRL_CMD_PHYSEQID) 7446 7447 #define S_FW_EQ_CTRL_CMD_FETCHSZM 26 7448 #define M_FW_EQ_CTRL_CMD_FETCHSZM 0x1 7449 #define V_FW_EQ_CTRL_CMD_FETCHSZM(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHSZM) 7450 #define G_FW_EQ_CTRL_CMD_FETCHSZM(x) \ 7451 (((x) >> S_FW_EQ_CTRL_CMD_FETCHSZM) & M_FW_EQ_CTRL_CMD_FETCHSZM) 7452 #define F_FW_EQ_CTRL_CMD_FETCHSZM V_FW_EQ_CTRL_CMD_FETCHSZM(1U) 7453 7454 #define S_FW_EQ_CTRL_CMD_STATUSPGNS 25 7455 #define M_FW_EQ_CTRL_CMD_STATUSPGNS 0x1 7456 #define V_FW_EQ_CTRL_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGNS) 7457 #define G_FW_EQ_CTRL_CMD_STATUSPGNS(x) \ 7458 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGNS) & M_FW_EQ_CTRL_CMD_STATUSPGNS) 7459 #define F_FW_EQ_CTRL_CMD_STATUSPGNS V_FW_EQ_CTRL_CMD_STATUSPGNS(1U) 7460 7461 #define S_FW_EQ_CTRL_CMD_STATUSPGRO 24 7462 #define M_FW_EQ_CTRL_CMD_STATUSPGRO 0x1 7463 #define V_FW_EQ_CTRL_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_CTRL_CMD_STATUSPGRO) 7464 #define G_FW_EQ_CTRL_CMD_STATUSPGRO(x) \ 7465 (((x) >> S_FW_EQ_CTRL_CMD_STATUSPGRO) & M_FW_EQ_CTRL_CMD_STATUSPGRO) 7466 #define F_FW_EQ_CTRL_CMD_STATUSPGRO V_FW_EQ_CTRL_CMD_STATUSPGRO(1U) 7467 7468 #define S_FW_EQ_CTRL_CMD_FETCHNS 23 7469 #define M_FW_EQ_CTRL_CMD_FETCHNS 0x1 7470 #define V_FW_EQ_CTRL_CMD_FETCHNS(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHNS) 7471 #define G_FW_EQ_CTRL_CMD_FETCHNS(x) \ 7472 (((x) >> S_FW_EQ_CTRL_CMD_FETCHNS) & M_FW_EQ_CTRL_CMD_FETCHNS) 7473 #define F_FW_EQ_CTRL_CMD_FETCHNS V_FW_EQ_CTRL_CMD_FETCHNS(1U) 7474 7475 #define S_FW_EQ_CTRL_CMD_FETCHRO 22 7476 #define M_FW_EQ_CTRL_CMD_FETCHRO 0x1 7477 #define V_FW_EQ_CTRL_CMD_FETCHRO(x) ((x) << S_FW_EQ_CTRL_CMD_FETCHRO) 7478 #define G_FW_EQ_CTRL_CMD_FETCHRO(x) \ 7479 (((x) >> S_FW_EQ_CTRL_CMD_FETCHRO) & M_FW_EQ_CTRL_CMD_FETCHRO) 7480 #define F_FW_EQ_CTRL_CMD_FETCHRO V_FW_EQ_CTRL_CMD_FETCHRO(1U) 7481 7482 #define S_FW_EQ_CTRL_CMD_HOSTFCMODE 20 7483 #define M_FW_EQ_CTRL_CMD_HOSTFCMODE 0x3 7484 #define V_FW_EQ_CTRL_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_CTRL_CMD_HOSTFCMODE) 7485 #define G_FW_EQ_CTRL_CMD_HOSTFCMODE(x) \ 7486 (((x) >> S_FW_EQ_CTRL_CMD_HOSTFCMODE) & M_FW_EQ_CTRL_CMD_HOSTFCMODE) 7487 7488 #define S_FW_EQ_CTRL_CMD_CPRIO 19 7489 #define M_FW_EQ_CTRL_CMD_CPRIO 0x1 7490 #define V_FW_EQ_CTRL_CMD_CPRIO(x) ((x) << S_FW_EQ_CTRL_CMD_CPRIO) 7491 #define G_FW_EQ_CTRL_CMD_CPRIO(x) \ 7492 (((x) >> S_FW_EQ_CTRL_CMD_CPRIO) & M_FW_EQ_CTRL_CMD_CPRIO) 7493 #define F_FW_EQ_CTRL_CMD_CPRIO V_FW_EQ_CTRL_CMD_CPRIO(1U) 7494 7495 #define S_FW_EQ_CTRL_CMD_ONCHIP 18 7496 #define M_FW_EQ_CTRL_CMD_ONCHIP 0x1 7497 #define V_FW_EQ_CTRL_CMD_ONCHIP(x) ((x) << S_FW_EQ_CTRL_CMD_ONCHIP) 7498 #define G_FW_EQ_CTRL_CMD_ONCHIP(x) \ 7499 (((x) >> S_FW_EQ_CTRL_CMD_ONCHIP) & M_FW_EQ_CTRL_CMD_ONCHIP) 7500 #define F_FW_EQ_CTRL_CMD_ONCHIP V_FW_EQ_CTRL_CMD_ONCHIP(1U) 7501 7502 #define S_FW_EQ_CTRL_CMD_PCIECHN 16 7503 #define M_FW_EQ_CTRL_CMD_PCIECHN 0x3 7504 #define V_FW_EQ_CTRL_CMD_PCIECHN(x) ((x) << S_FW_EQ_CTRL_CMD_PCIECHN) 7505 #define G_FW_EQ_CTRL_CMD_PCIECHN(x) \ 7506 (((x) >> S_FW_EQ_CTRL_CMD_PCIECHN) & M_FW_EQ_CTRL_CMD_PCIECHN) 7507 7508 #define S_FW_EQ_CTRL_CMD_IQID 0 7509 #define M_FW_EQ_CTRL_CMD_IQID 0xffff 7510 #define V_FW_EQ_CTRL_CMD_IQID(x) ((x) << S_FW_EQ_CTRL_CMD_IQID) 7511 #define G_FW_EQ_CTRL_CMD_IQID(x) \ 7512 (((x) >> S_FW_EQ_CTRL_CMD_IQID) & M_FW_EQ_CTRL_CMD_IQID) 7513 7514 #define S_FW_EQ_CTRL_CMD_DCAEN 31 7515 #define M_FW_EQ_CTRL_CMD_DCAEN 0x1 7516 #define V_FW_EQ_CTRL_CMD_DCAEN(x) ((x) << S_FW_EQ_CTRL_CMD_DCAEN) 7517 #define G_FW_EQ_CTRL_CMD_DCAEN(x) \ 7518 (((x) >> S_FW_EQ_CTRL_CMD_DCAEN) & M_FW_EQ_CTRL_CMD_DCAEN) 7519 #define F_FW_EQ_CTRL_CMD_DCAEN V_FW_EQ_CTRL_CMD_DCAEN(1U) 7520 7521 #define S_FW_EQ_CTRL_CMD_DCACPU 26 7522 #define M_FW_EQ_CTRL_CMD_DCACPU 0x1f 7523 #define V_FW_EQ_CTRL_CMD_DCACPU(x) ((x) << S_FW_EQ_CTRL_CMD_DCACPU) 7524 #define G_FW_EQ_CTRL_CMD_DCACPU(x) \ 7525 (((x) >> S_FW_EQ_CTRL_CMD_DCACPU) & M_FW_EQ_CTRL_CMD_DCACPU) 7526 7527 #define S_FW_EQ_CTRL_CMD_FBMIN 23 7528 #define M_FW_EQ_CTRL_CMD_FBMIN 0x7 7529 #define V_FW_EQ_CTRL_CMD_FBMIN(x) ((x) << S_FW_EQ_CTRL_CMD_FBMIN) 7530 #define G_FW_EQ_CTRL_CMD_FBMIN(x) \ 7531 (((x) >> S_FW_EQ_CTRL_CMD_FBMIN) & M_FW_EQ_CTRL_CMD_FBMIN) 7532 7533 #define S_FW_EQ_CTRL_CMD_FBMAX 20 7534 #define M_FW_EQ_CTRL_CMD_FBMAX 0x7 7535 #define V_FW_EQ_CTRL_CMD_FBMAX(x) ((x) << S_FW_EQ_CTRL_CMD_FBMAX) 7536 #define G_FW_EQ_CTRL_CMD_FBMAX(x) \ 7537 (((x) >> S_FW_EQ_CTRL_CMD_FBMAX) & M_FW_EQ_CTRL_CMD_FBMAX) 7538 7539 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESHO 19 7540 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESHO 0x1 7541 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 7542 ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 7543 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESHO(x) \ 7544 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESHO) & M_FW_EQ_CTRL_CMD_CIDXFTHRESHO) 7545 #define F_FW_EQ_CTRL_CMD_CIDXFTHRESHO V_FW_EQ_CTRL_CMD_CIDXFTHRESHO(1U) 7546 7547 #define S_FW_EQ_CTRL_CMD_CIDXFTHRESH 16 7548 #define M_FW_EQ_CTRL_CMD_CIDXFTHRESH 0x7 7549 #define V_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_CTRL_CMD_CIDXFTHRESH) 7550 #define G_FW_EQ_CTRL_CMD_CIDXFTHRESH(x) \ 7551 (((x) >> S_FW_EQ_CTRL_CMD_CIDXFTHRESH) & M_FW_EQ_CTRL_CMD_CIDXFTHRESH) 7552 7553 #define S_FW_EQ_CTRL_CMD_EQSIZE 0 7554 #define M_FW_EQ_CTRL_CMD_EQSIZE 0xffff 7555 #define V_FW_EQ_CTRL_CMD_EQSIZE(x) ((x) << S_FW_EQ_CTRL_CMD_EQSIZE) 7556 #define G_FW_EQ_CTRL_CMD_EQSIZE(x) \ 7557 (((x) >> S_FW_EQ_CTRL_CMD_EQSIZE) & M_FW_EQ_CTRL_CMD_EQSIZE) 7558 7559 struct fw_eq_ofld_cmd { 7560 __be32 op_to_vfn; 7561 __be32 alloc_to_len16; 7562 __be32 eqid_pkd; 7563 __be32 physeqid_pkd; 7564 __be32 fetchszm_to_iqid; 7565 __be32 dcaen_to_eqsize; 7566 __be64 eqaddr; 7567 }; 7568 7569 #define S_FW_EQ_OFLD_CMD_PFN 8 7570 #define M_FW_EQ_OFLD_CMD_PFN 0x7 7571 #define V_FW_EQ_OFLD_CMD_PFN(x) ((x) << S_FW_EQ_OFLD_CMD_PFN) 7572 #define G_FW_EQ_OFLD_CMD_PFN(x) \ 7573 (((x) >> S_FW_EQ_OFLD_CMD_PFN) & M_FW_EQ_OFLD_CMD_PFN) 7574 7575 #define S_FW_EQ_OFLD_CMD_VFN 0 7576 #define M_FW_EQ_OFLD_CMD_VFN 0xff 7577 #define V_FW_EQ_OFLD_CMD_VFN(x) ((x) << S_FW_EQ_OFLD_CMD_VFN) 7578 #define G_FW_EQ_OFLD_CMD_VFN(x) \ 7579 (((x) >> S_FW_EQ_OFLD_CMD_VFN) & M_FW_EQ_OFLD_CMD_VFN) 7580 7581 #define S_FW_EQ_OFLD_CMD_ALLOC 31 7582 #define M_FW_EQ_OFLD_CMD_ALLOC 0x1 7583 #define V_FW_EQ_OFLD_CMD_ALLOC(x) ((x) << S_FW_EQ_OFLD_CMD_ALLOC) 7584 #define G_FW_EQ_OFLD_CMD_ALLOC(x) \ 7585 (((x) >> S_FW_EQ_OFLD_CMD_ALLOC) & M_FW_EQ_OFLD_CMD_ALLOC) 7586 #define F_FW_EQ_OFLD_CMD_ALLOC V_FW_EQ_OFLD_CMD_ALLOC(1U) 7587 7588 #define S_FW_EQ_OFLD_CMD_FREE 30 7589 #define M_FW_EQ_OFLD_CMD_FREE 0x1 7590 #define V_FW_EQ_OFLD_CMD_FREE(x) ((x) << S_FW_EQ_OFLD_CMD_FREE) 7591 #define G_FW_EQ_OFLD_CMD_FREE(x) \ 7592 (((x) >> S_FW_EQ_OFLD_CMD_FREE) & M_FW_EQ_OFLD_CMD_FREE) 7593 #define F_FW_EQ_OFLD_CMD_FREE V_FW_EQ_OFLD_CMD_FREE(1U) 7594 7595 #define S_FW_EQ_OFLD_CMD_MODIFY 29 7596 #define M_FW_EQ_OFLD_CMD_MODIFY 0x1 7597 #define V_FW_EQ_OFLD_CMD_MODIFY(x) ((x) << S_FW_EQ_OFLD_CMD_MODIFY) 7598 #define G_FW_EQ_OFLD_CMD_MODIFY(x) \ 7599 (((x) >> S_FW_EQ_OFLD_CMD_MODIFY) & M_FW_EQ_OFLD_CMD_MODIFY) 7600 #define F_FW_EQ_OFLD_CMD_MODIFY V_FW_EQ_OFLD_CMD_MODIFY(1U) 7601 7602 #define S_FW_EQ_OFLD_CMD_EQSTART 28 7603 #define M_FW_EQ_OFLD_CMD_EQSTART 0x1 7604 #define V_FW_EQ_OFLD_CMD_EQSTART(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTART) 7605 #define G_FW_EQ_OFLD_CMD_EQSTART(x) \ 7606 (((x) >> S_FW_EQ_OFLD_CMD_EQSTART) & M_FW_EQ_OFLD_CMD_EQSTART) 7607 #define F_FW_EQ_OFLD_CMD_EQSTART V_FW_EQ_OFLD_CMD_EQSTART(1U) 7608 7609 #define S_FW_EQ_OFLD_CMD_EQSTOP 27 7610 #define M_FW_EQ_OFLD_CMD_EQSTOP 0x1 7611 #define V_FW_EQ_OFLD_CMD_EQSTOP(x) ((x) << S_FW_EQ_OFLD_CMD_EQSTOP) 7612 #define G_FW_EQ_OFLD_CMD_EQSTOP(x) \ 7613 (((x) >> S_FW_EQ_OFLD_CMD_EQSTOP) & M_FW_EQ_OFLD_CMD_EQSTOP) 7614 #define F_FW_EQ_OFLD_CMD_EQSTOP V_FW_EQ_OFLD_CMD_EQSTOP(1U) 7615 7616 #define S_FW_EQ_OFLD_CMD_COREGROUP 16 7617 #define M_FW_EQ_OFLD_CMD_COREGROUP 0x3f 7618 #define V_FW_EQ_OFLD_CMD_COREGROUP(x) ((x) << S_FW_EQ_OFLD_CMD_COREGROUP) 7619 #define G_FW_EQ_OFLD_CMD_COREGROUP(x) \ 7620 (((x) >> S_FW_EQ_OFLD_CMD_COREGROUP) & M_FW_EQ_OFLD_CMD_COREGROUP) 7621 7622 #define S_FW_EQ_OFLD_CMD_EQID 0 7623 #define M_FW_EQ_OFLD_CMD_EQID 0xfffff 7624 #define V_FW_EQ_OFLD_CMD_EQID(x) ((x) << S_FW_EQ_OFLD_CMD_EQID) 7625 #define G_FW_EQ_OFLD_CMD_EQID(x) \ 7626 (((x) >> S_FW_EQ_OFLD_CMD_EQID) & M_FW_EQ_OFLD_CMD_EQID) 7627 7628 #define S_FW_EQ_OFLD_CMD_PHYSEQID 0 7629 #define M_FW_EQ_OFLD_CMD_PHYSEQID 0xfffff 7630 #define V_FW_EQ_OFLD_CMD_PHYSEQID(x) ((x) << S_FW_EQ_OFLD_CMD_PHYSEQID) 7631 #define G_FW_EQ_OFLD_CMD_PHYSEQID(x) \ 7632 (((x) >> S_FW_EQ_OFLD_CMD_PHYSEQID) & M_FW_EQ_OFLD_CMD_PHYSEQID) 7633 7634 #define S_FW_EQ_OFLD_CMD_FETCHSZM 26 7635 #define M_FW_EQ_OFLD_CMD_FETCHSZM 0x1 7636 #define V_FW_EQ_OFLD_CMD_FETCHSZM(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHSZM) 7637 #define G_FW_EQ_OFLD_CMD_FETCHSZM(x) \ 7638 (((x) >> S_FW_EQ_OFLD_CMD_FETCHSZM) & M_FW_EQ_OFLD_CMD_FETCHSZM) 7639 #define F_FW_EQ_OFLD_CMD_FETCHSZM V_FW_EQ_OFLD_CMD_FETCHSZM(1U) 7640 7641 #define S_FW_EQ_OFLD_CMD_STATUSPGNS 25 7642 #define M_FW_EQ_OFLD_CMD_STATUSPGNS 0x1 7643 #define V_FW_EQ_OFLD_CMD_STATUSPGNS(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGNS) 7644 #define G_FW_EQ_OFLD_CMD_STATUSPGNS(x) \ 7645 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGNS) & M_FW_EQ_OFLD_CMD_STATUSPGNS) 7646 #define F_FW_EQ_OFLD_CMD_STATUSPGNS V_FW_EQ_OFLD_CMD_STATUSPGNS(1U) 7647 7648 #define S_FW_EQ_OFLD_CMD_STATUSPGRO 24 7649 #define M_FW_EQ_OFLD_CMD_STATUSPGRO 0x1 7650 #define V_FW_EQ_OFLD_CMD_STATUSPGRO(x) ((x) << S_FW_EQ_OFLD_CMD_STATUSPGRO) 7651 #define G_FW_EQ_OFLD_CMD_STATUSPGRO(x) \ 7652 (((x) >> S_FW_EQ_OFLD_CMD_STATUSPGRO) & M_FW_EQ_OFLD_CMD_STATUSPGRO) 7653 #define F_FW_EQ_OFLD_CMD_STATUSPGRO V_FW_EQ_OFLD_CMD_STATUSPGRO(1U) 7654 7655 #define S_FW_EQ_OFLD_CMD_FETCHNS 23 7656 #define M_FW_EQ_OFLD_CMD_FETCHNS 0x1 7657 #define V_FW_EQ_OFLD_CMD_FETCHNS(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHNS) 7658 #define G_FW_EQ_OFLD_CMD_FETCHNS(x) \ 7659 (((x) >> S_FW_EQ_OFLD_CMD_FETCHNS) & M_FW_EQ_OFLD_CMD_FETCHNS) 7660 #define F_FW_EQ_OFLD_CMD_FETCHNS V_FW_EQ_OFLD_CMD_FETCHNS(1U) 7661 7662 #define S_FW_EQ_OFLD_CMD_FETCHRO 22 7663 #define M_FW_EQ_OFLD_CMD_FETCHRO 0x1 7664 #define V_FW_EQ_OFLD_CMD_FETCHRO(x) ((x) << S_FW_EQ_OFLD_CMD_FETCHRO) 7665 #define G_FW_EQ_OFLD_CMD_FETCHRO(x) \ 7666 (((x) >> S_FW_EQ_OFLD_CMD_FETCHRO) & M_FW_EQ_OFLD_CMD_FETCHRO) 7667 #define F_FW_EQ_OFLD_CMD_FETCHRO V_FW_EQ_OFLD_CMD_FETCHRO(1U) 7668 7669 #define S_FW_EQ_OFLD_CMD_HOSTFCMODE 20 7670 #define M_FW_EQ_OFLD_CMD_HOSTFCMODE 0x3 7671 #define V_FW_EQ_OFLD_CMD_HOSTFCMODE(x) ((x) << S_FW_EQ_OFLD_CMD_HOSTFCMODE) 7672 #define G_FW_EQ_OFLD_CMD_HOSTFCMODE(x) \ 7673 (((x) >> S_FW_EQ_OFLD_CMD_HOSTFCMODE) & M_FW_EQ_OFLD_CMD_HOSTFCMODE) 7674 7675 #define S_FW_EQ_OFLD_CMD_CPRIO 19 7676 #define M_FW_EQ_OFLD_CMD_CPRIO 0x1 7677 #define V_FW_EQ_OFLD_CMD_CPRIO(x) ((x) << S_FW_EQ_OFLD_CMD_CPRIO) 7678 #define G_FW_EQ_OFLD_CMD_CPRIO(x) \ 7679 (((x) >> S_FW_EQ_OFLD_CMD_CPRIO) & M_FW_EQ_OFLD_CMD_CPRIO) 7680 #define F_FW_EQ_OFLD_CMD_CPRIO V_FW_EQ_OFLD_CMD_CPRIO(1U) 7681 7682 #define S_FW_EQ_OFLD_CMD_ONCHIP 18 7683 #define M_FW_EQ_OFLD_CMD_ONCHIP 0x1 7684 #define V_FW_EQ_OFLD_CMD_ONCHIP(x) ((x) << S_FW_EQ_OFLD_CMD_ONCHIP) 7685 #define G_FW_EQ_OFLD_CMD_ONCHIP(x) \ 7686 (((x) >> S_FW_EQ_OFLD_CMD_ONCHIP) & M_FW_EQ_OFLD_CMD_ONCHIP) 7687 #define F_FW_EQ_OFLD_CMD_ONCHIP V_FW_EQ_OFLD_CMD_ONCHIP(1U) 7688 7689 #define S_FW_EQ_OFLD_CMD_PCIECHN 16 7690 #define M_FW_EQ_OFLD_CMD_PCIECHN 0x3 7691 #define V_FW_EQ_OFLD_CMD_PCIECHN(x) ((x) << S_FW_EQ_OFLD_CMD_PCIECHN) 7692 #define G_FW_EQ_OFLD_CMD_PCIECHN(x) \ 7693 (((x) >> S_FW_EQ_OFLD_CMD_PCIECHN) & M_FW_EQ_OFLD_CMD_PCIECHN) 7694 7695 #define S_FW_EQ_OFLD_CMD_IQID 0 7696 #define M_FW_EQ_OFLD_CMD_IQID 0xffff 7697 #define V_FW_EQ_OFLD_CMD_IQID(x) ((x) << S_FW_EQ_OFLD_CMD_IQID) 7698 #define G_FW_EQ_OFLD_CMD_IQID(x) \ 7699 (((x) >> S_FW_EQ_OFLD_CMD_IQID) & M_FW_EQ_OFLD_CMD_IQID) 7700 7701 #define S_FW_EQ_OFLD_CMD_DCAEN 31 7702 #define M_FW_EQ_OFLD_CMD_DCAEN 0x1 7703 #define V_FW_EQ_OFLD_CMD_DCAEN(x) ((x) << S_FW_EQ_OFLD_CMD_DCAEN) 7704 #define G_FW_EQ_OFLD_CMD_DCAEN(x) \ 7705 (((x) >> S_FW_EQ_OFLD_CMD_DCAEN) & M_FW_EQ_OFLD_CMD_DCAEN) 7706 #define F_FW_EQ_OFLD_CMD_DCAEN V_FW_EQ_OFLD_CMD_DCAEN(1U) 7707 7708 #define S_FW_EQ_OFLD_CMD_DCACPU 26 7709 #define M_FW_EQ_OFLD_CMD_DCACPU 0x1f 7710 #define V_FW_EQ_OFLD_CMD_DCACPU(x) ((x) << S_FW_EQ_OFLD_CMD_DCACPU) 7711 #define G_FW_EQ_OFLD_CMD_DCACPU(x) \ 7712 (((x) >> S_FW_EQ_OFLD_CMD_DCACPU) & M_FW_EQ_OFLD_CMD_DCACPU) 7713 7714 #define S_FW_EQ_OFLD_CMD_FBMIN 23 7715 #define M_FW_EQ_OFLD_CMD_FBMIN 0x7 7716 #define V_FW_EQ_OFLD_CMD_FBMIN(x) ((x) << S_FW_EQ_OFLD_CMD_FBMIN) 7717 #define G_FW_EQ_OFLD_CMD_FBMIN(x) \ 7718 (((x) >> S_FW_EQ_OFLD_CMD_FBMIN) & M_FW_EQ_OFLD_CMD_FBMIN) 7719 7720 #define S_FW_EQ_OFLD_CMD_FBMAX 20 7721 #define M_FW_EQ_OFLD_CMD_FBMAX 0x7 7722 #define V_FW_EQ_OFLD_CMD_FBMAX(x) ((x) << S_FW_EQ_OFLD_CMD_FBMAX) 7723 #define G_FW_EQ_OFLD_CMD_FBMAX(x) \ 7724 (((x) >> S_FW_EQ_OFLD_CMD_FBMAX) & M_FW_EQ_OFLD_CMD_FBMAX) 7725 7726 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESHO 19 7727 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESHO 0x1 7728 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 7729 ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 7730 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESHO(x) \ 7731 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESHO) & M_FW_EQ_OFLD_CMD_CIDXFTHRESHO) 7732 #define F_FW_EQ_OFLD_CMD_CIDXFTHRESHO V_FW_EQ_OFLD_CMD_CIDXFTHRESHO(1U) 7733 7734 #define S_FW_EQ_OFLD_CMD_CIDXFTHRESH 16 7735 #define M_FW_EQ_OFLD_CMD_CIDXFTHRESH 0x7 7736 #define V_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) ((x) << S_FW_EQ_OFLD_CMD_CIDXFTHRESH) 7737 #define G_FW_EQ_OFLD_CMD_CIDXFTHRESH(x) \ 7738 (((x) >> S_FW_EQ_OFLD_CMD_CIDXFTHRESH) & M_FW_EQ_OFLD_CMD_CIDXFTHRESH) 7739 7740 #define S_FW_EQ_OFLD_CMD_EQSIZE 0 7741 #define M_FW_EQ_OFLD_CMD_EQSIZE 0xffff 7742 #define V_FW_EQ_OFLD_CMD_EQSIZE(x) ((x) << S_FW_EQ_OFLD_CMD_EQSIZE) 7743 #define G_FW_EQ_OFLD_CMD_EQSIZE(x) \ 7744 (((x) >> S_FW_EQ_OFLD_CMD_EQSIZE) & M_FW_EQ_OFLD_CMD_EQSIZE) 7745 7746 /* Following macros present here only to maintain backward 7747 * compatibiity. Driver must not use these anymore */ 7748 /* Macros for VIID parsing: 7749 VIID - [10:8] PFN, [7] VI Valid, [6:0] VI number */ 7750 #define S_FW_VIID_PFN 8 7751 #define M_FW_VIID_PFN 0x7 7752 #define V_FW_VIID_PFN(x) ((x) << S_FW_VIID_PFN) 7753 #define G_FW_VIID_PFN(x) (((x) >> S_FW_VIID_PFN) & M_FW_VIID_PFN) 7754 7755 #define S_FW_VIID_VIVLD 7 7756 #define M_FW_VIID_VIVLD 0x1 7757 #define V_FW_VIID_VIVLD(x) ((x) << S_FW_VIID_VIVLD) 7758 #define G_FW_VIID_VIVLD(x) (((x) >> S_FW_VIID_VIVLD) & M_FW_VIID_VIVLD) 7759 7760 #define S_FW_VIID_VIN 0 7761 #define M_FW_VIID_VIN 0x7F 7762 #define V_FW_VIID_VIN(x) ((x) << S_FW_VIID_VIN) 7763 #define G_FW_VIID_VIN(x) (((x) >> S_FW_VIID_VIN) & M_FW_VIID_VIN) 7764 7765 /* Macros for VIID parsing: 7766 VIID - [11:9] PFN, [8] VI Valid, [7:0] VI number */ 7767 #define S_FW_256VIID_PFN 9 7768 #define M_FW_256VIID_PFN 0x7 7769 #define V_FW_256VIID_PFN(x) ((x) << S_FW_256VIID_PFN) 7770 #define G_FW_256VIID_PFN(x) (((x) >> S_FW_256VIID_PFN) & M_FW_256VIID_PFN) 7771 7772 #define S_FW_256VIID_VIVLD 8 7773 #define M_FW_256VIID_VIVLD 0x1 7774 #define V_FW_256VIID_VIVLD(x) ((x) << S_FW_256VIID_VIVLD) 7775 #define G_FW_256VIID_VIVLD(x) (((x) >> S_FW_256VIID_VIVLD) & M_FW_256VIID_VIVLD) 7776 7777 #define S_FW_256VIID_VIN 0 7778 #define M_FW_256VIID_VIN 0xFF 7779 #define V_FW_256VIID_VIN(x) ((x) << S_FW_256VIID_VIN) 7780 #define G_FW_256VIID_VIN(x) (((x) >> S_FW_256VIID_VIN) & M_FW_256VIID_VIN) 7781 7782 enum fw_vi_func { 7783 FW_VI_FUNC_ETH, 7784 FW_VI_FUNC_OFLD, 7785 FW_VI_FUNC_IWARP, 7786 FW_VI_FUNC_OPENISCSI, 7787 FW_VI_FUNC_OPENFCOE, 7788 FW_VI_FUNC_FOISCSI, 7789 FW_VI_FUNC_FOFCOE, 7790 FW_VI_FUNC_FW, 7791 }; 7792 7793 struct fw_vi_cmd { 7794 __be32 op_to_vfn; 7795 __be32 alloc_to_len16; 7796 __be16 type_to_viid; 7797 __u8 mac[6]; 7798 __u8 portid_pkd; 7799 __u8 nmac; 7800 __u8 nmac0[6]; 7801 __be16 norss_rsssize; 7802 __u8 nmac1[6]; 7803 __be16 idsiiq_pkd; 7804 __u8 nmac2[6]; 7805 __be16 idseiq_pkd; 7806 __u8 nmac3[6]; 7807 __be64 r9; 7808 __be64 r10; 7809 }; 7810 7811 #define S_FW_VI_CMD_PFN 8 7812 #define M_FW_VI_CMD_PFN 0x7 7813 #define V_FW_VI_CMD_PFN(x) ((x) << S_FW_VI_CMD_PFN) 7814 #define G_FW_VI_CMD_PFN(x) \ 7815 (((x) >> S_FW_VI_CMD_PFN) & M_FW_VI_CMD_PFN) 7816 7817 #define S_FW_VI_CMD_VFN 0 7818 #define M_FW_VI_CMD_VFN 0xff 7819 #define V_FW_VI_CMD_VFN(x) ((x) << S_FW_VI_CMD_VFN) 7820 #define G_FW_VI_CMD_VFN(x) \ 7821 (((x) >> S_FW_VI_CMD_VFN) & M_FW_VI_CMD_VFN) 7822 7823 #define S_FW_VI_CMD_ALLOC 31 7824 #define M_FW_VI_CMD_ALLOC 0x1 7825 #define V_FW_VI_CMD_ALLOC(x) ((x) << S_FW_VI_CMD_ALLOC) 7826 #define G_FW_VI_CMD_ALLOC(x) \ 7827 (((x) >> S_FW_VI_CMD_ALLOC) & M_FW_VI_CMD_ALLOC) 7828 #define F_FW_VI_CMD_ALLOC V_FW_VI_CMD_ALLOC(1U) 7829 7830 #define S_FW_VI_CMD_FREE 30 7831 #define M_FW_VI_CMD_FREE 0x1 7832 #define V_FW_VI_CMD_FREE(x) ((x) << S_FW_VI_CMD_FREE) 7833 #define G_FW_VI_CMD_FREE(x) \ 7834 (((x) >> S_FW_VI_CMD_FREE) & M_FW_VI_CMD_FREE) 7835 #define F_FW_VI_CMD_FREE V_FW_VI_CMD_FREE(1U) 7836 7837 #define S_FW_VI_CMD_VFVLD 24 7838 #define M_FW_VI_CMD_VFVLD 0x1 7839 #define V_FW_VI_CMD_VFVLD(x) ((x) << S_FW_VI_CMD_VFVLD) 7840 #define G_FW_VI_CMD_VFVLD(x) \ 7841 (((x) >> S_FW_VI_CMD_VFVLD) & M_FW_VI_CMD_VFVLD) 7842 #define F_FW_VI_CMD_VFVLD V_FW_VI_CMD_VFVLD(1U) 7843 7844 #define S_FW_VI_CMD_VIN 16 7845 #define M_FW_VI_CMD_VIN 0xff 7846 #define V_FW_VI_CMD_VIN(x) ((x) << S_FW_VI_CMD_VIN) 7847 #define G_FW_VI_CMD_VIN(x) \ 7848 (((x) >> S_FW_VI_CMD_VIN) & M_FW_VI_CMD_VIN) 7849 7850 #define S_FW_VI_CMD_TYPE 15 7851 #define M_FW_VI_CMD_TYPE 0x1 7852 #define V_FW_VI_CMD_TYPE(x) ((x) << S_FW_VI_CMD_TYPE) 7853 #define G_FW_VI_CMD_TYPE(x) \ 7854 (((x) >> S_FW_VI_CMD_TYPE) & M_FW_VI_CMD_TYPE) 7855 #define F_FW_VI_CMD_TYPE V_FW_VI_CMD_TYPE(1U) 7856 7857 #define S_FW_VI_CMD_FUNC 12 7858 #define M_FW_VI_CMD_FUNC 0x7 7859 #define V_FW_VI_CMD_FUNC(x) ((x) << S_FW_VI_CMD_FUNC) 7860 #define G_FW_VI_CMD_FUNC(x) \ 7861 (((x) >> S_FW_VI_CMD_FUNC) & M_FW_VI_CMD_FUNC) 7862 7863 #define S_FW_VI_CMD_VIID 0 7864 #define M_FW_VI_CMD_VIID 0xfff 7865 #define V_FW_VI_CMD_VIID(x) ((x) << S_FW_VI_CMD_VIID) 7866 #define G_FW_VI_CMD_VIID(x) \ 7867 (((x) >> S_FW_VI_CMD_VIID) & M_FW_VI_CMD_VIID) 7868 7869 #define S_FW_VI_CMD_PORTID 4 7870 #define M_FW_VI_CMD_PORTID 0xf 7871 #define V_FW_VI_CMD_PORTID(x) ((x) << S_FW_VI_CMD_PORTID) 7872 #define G_FW_VI_CMD_PORTID(x) \ 7873 (((x) >> S_FW_VI_CMD_PORTID) & M_FW_VI_CMD_PORTID) 7874 7875 #define S_FW_VI_CMD_NORSS 11 7876 #define M_FW_VI_CMD_NORSS 0x1 7877 #define V_FW_VI_CMD_NORSS(x) ((x) << S_FW_VI_CMD_NORSS) 7878 #define G_FW_VI_CMD_NORSS(x) \ 7879 (((x) >> S_FW_VI_CMD_NORSS) & M_FW_VI_CMD_NORSS) 7880 #define F_FW_VI_CMD_NORSS V_FW_VI_CMD_NORSS(1U) 7881 7882 #define S_FW_VI_CMD_RSSSIZE 0 7883 #define M_FW_VI_CMD_RSSSIZE 0x7ff 7884 #define V_FW_VI_CMD_RSSSIZE(x) ((x) << S_FW_VI_CMD_RSSSIZE) 7885 #define G_FW_VI_CMD_RSSSIZE(x) \ 7886 (((x) >> S_FW_VI_CMD_RSSSIZE) & M_FW_VI_CMD_RSSSIZE) 7887 7888 #define S_FW_VI_CMD_IDSIIQ 0 7889 #define M_FW_VI_CMD_IDSIIQ 0x3ff 7890 #define V_FW_VI_CMD_IDSIIQ(x) ((x) << S_FW_VI_CMD_IDSIIQ) 7891 #define G_FW_VI_CMD_IDSIIQ(x) \ 7892 (((x) >> S_FW_VI_CMD_IDSIIQ) & M_FW_VI_CMD_IDSIIQ) 7893 7894 #define S_FW_VI_CMD_IDSEIQ 0 7895 #define M_FW_VI_CMD_IDSEIQ 0x3ff 7896 #define V_FW_VI_CMD_IDSEIQ(x) ((x) << S_FW_VI_CMD_IDSEIQ) 7897 #define G_FW_VI_CMD_IDSEIQ(x) \ 7898 (((x) >> S_FW_VI_CMD_IDSEIQ) & M_FW_VI_CMD_IDSEIQ) 7899 7900 /* Special VI_MAC command index ids */ 7901 #define FW_VI_MAC_ADD_MAC 0x3FF 7902 #define FW_VI_MAC_ADD_PERSIST_MAC 0x3FE 7903 #define FW_VI_MAC_MAC_BASED_FREE 0x3FD 7904 #define FW_VI_MAC_ID_BASED_FREE 0x3FC 7905 7906 enum fw_vi_mac_smac { 7907 FW_VI_MAC_MPS_TCAM_ENTRY, 7908 FW_VI_MAC_MPS_TCAM_ONLY, 7909 FW_VI_MAC_SMT_ONLY, 7910 FW_VI_MAC_SMT_AND_MPSTCAM 7911 }; 7912 7913 enum fw_vi_mac_result { 7914 FW_VI_MAC_R_SUCCESS, 7915 FW_VI_MAC_R_F_NONEXISTENT_NOMEM, 7916 FW_VI_MAC_R_SMAC_FAIL, 7917 FW_VI_MAC_R_F_ACL_CHECK 7918 }; 7919 7920 enum fw_vi_mac_entry_types { 7921 FW_VI_MAC_TYPE_EXACTMAC, 7922 FW_VI_MAC_TYPE_HASHVEC, 7923 FW_VI_MAC_TYPE_RAW, 7924 FW_VI_MAC_TYPE_EXACTMAC_VNI, 7925 }; 7926 7927 struct fw_vi_mac_cmd { 7928 __be32 op_to_viid; 7929 __be32 freemacs_to_len16; 7930 union fw_vi_mac { 7931 struct fw_vi_mac_exact { 7932 __be16 valid_to_idx; 7933 __u8 macaddr[6]; 7934 } exact[7]; 7935 struct fw_vi_mac_hash { 7936 __be64 hashvec; 7937 } hash; 7938 struct fw_vi_mac_raw { 7939 __be32 raw_idx_pkd; 7940 __be32 data0_pkd; 7941 __be32 data1[2]; 7942 __be64 data0m_pkd; 7943 __be32 data1m[2]; 7944 } raw; 7945 struct fw_vi_mac_vni { 7946 __be16 valid_to_idx; 7947 __u8 macaddr[6]; 7948 __be16 r7; 7949 __u8 macaddr_mask[6]; 7950 __be32 lookup_type_to_vni; 7951 __be32 vni_mask_pkd; 7952 } exact_vni[2]; 7953 } u; 7954 }; 7955 7956 #define S_FW_VI_MAC_CMD_SMTID 12 7957 #define M_FW_VI_MAC_CMD_SMTID 0xff 7958 #define V_FW_VI_MAC_CMD_SMTID(x) ((x) << S_FW_VI_MAC_CMD_SMTID) 7959 #define G_FW_VI_MAC_CMD_SMTID(x) \ 7960 (((x) >> S_FW_VI_MAC_CMD_SMTID) & M_FW_VI_MAC_CMD_SMTID) 7961 7962 #define S_FW_VI_MAC_CMD_VIID 0 7963 #define M_FW_VI_MAC_CMD_VIID 0xfff 7964 #define V_FW_VI_MAC_CMD_VIID(x) ((x) << S_FW_VI_MAC_CMD_VIID) 7965 #define G_FW_VI_MAC_CMD_VIID(x) \ 7966 (((x) >> S_FW_VI_MAC_CMD_VIID) & M_FW_VI_MAC_CMD_VIID) 7967 7968 #define S_FW_VI_MAC_CMD_FREEMACS 31 7969 #define M_FW_VI_MAC_CMD_FREEMACS 0x1 7970 #define V_FW_VI_MAC_CMD_FREEMACS(x) ((x) << S_FW_VI_MAC_CMD_FREEMACS) 7971 #define G_FW_VI_MAC_CMD_FREEMACS(x) \ 7972 (((x) >> S_FW_VI_MAC_CMD_FREEMACS) & M_FW_VI_MAC_CMD_FREEMACS) 7973 #define F_FW_VI_MAC_CMD_FREEMACS V_FW_VI_MAC_CMD_FREEMACS(1U) 7974 7975 #define S_FW_VI_MAC_CMD_IS_SMAC 30 7976 #define M_FW_VI_MAC_CMD_IS_SMAC 0x1 7977 #define V_FW_VI_MAC_CMD_IS_SMAC(x) ((x) << S_FW_VI_MAC_CMD_IS_SMAC) 7978 #define G_FW_VI_MAC_CMD_IS_SMAC(x) \ 7979 (((x) >> S_FW_VI_MAC_CMD_IS_SMAC) & M_FW_VI_MAC_CMD_IS_SMAC) 7980 #define F_FW_VI_MAC_CMD_IS_SMAC V_FW_VI_MAC_CMD_IS_SMAC(1U) 7981 7982 #define S_FW_VI_MAC_CMD_ENTRY_TYPE 23 7983 #define M_FW_VI_MAC_CMD_ENTRY_TYPE 0x7 7984 #define V_FW_VI_MAC_CMD_ENTRY_TYPE(x) ((x) << S_FW_VI_MAC_CMD_ENTRY_TYPE) 7985 #define G_FW_VI_MAC_CMD_ENTRY_TYPE(x) \ 7986 (((x) >> S_FW_VI_MAC_CMD_ENTRY_TYPE) & M_FW_VI_MAC_CMD_ENTRY_TYPE) 7987 7988 #define S_FW_VI_MAC_CMD_HASHUNIEN 22 7989 #define M_FW_VI_MAC_CMD_HASHUNIEN 0x1 7990 #define V_FW_VI_MAC_CMD_HASHUNIEN(x) ((x) << S_FW_VI_MAC_CMD_HASHUNIEN) 7991 #define G_FW_VI_MAC_CMD_HASHUNIEN(x) \ 7992 (((x) >> S_FW_VI_MAC_CMD_HASHUNIEN) & M_FW_VI_MAC_CMD_HASHUNIEN) 7993 #define F_FW_VI_MAC_CMD_HASHUNIEN V_FW_VI_MAC_CMD_HASHUNIEN(1U) 7994 7995 #define S_FW_VI_MAC_CMD_VALID 15 7996 #define M_FW_VI_MAC_CMD_VALID 0x1 7997 #define V_FW_VI_MAC_CMD_VALID(x) ((x) << S_FW_VI_MAC_CMD_VALID) 7998 #define G_FW_VI_MAC_CMD_VALID(x) \ 7999 (((x) >> S_FW_VI_MAC_CMD_VALID) & M_FW_VI_MAC_CMD_VALID) 8000 #define F_FW_VI_MAC_CMD_VALID V_FW_VI_MAC_CMD_VALID(1U) 8001 8002 #define S_FW_VI_MAC_CMD_PRIO 12 8003 #define M_FW_VI_MAC_CMD_PRIO 0x7 8004 #define V_FW_VI_MAC_CMD_PRIO(x) ((x) << S_FW_VI_MAC_CMD_PRIO) 8005 #define G_FW_VI_MAC_CMD_PRIO(x) \ 8006 (((x) >> S_FW_VI_MAC_CMD_PRIO) & M_FW_VI_MAC_CMD_PRIO) 8007 8008 #define S_FW_VI_MAC_CMD_SMAC_RESULT 10 8009 #define M_FW_VI_MAC_CMD_SMAC_RESULT 0x3 8010 #define V_FW_VI_MAC_CMD_SMAC_RESULT(x) ((x) << S_FW_VI_MAC_CMD_SMAC_RESULT) 8011 #define G_FW_VI_MAC_CMD_SMAC_RESULT(x) \ 8012 (((x) >> S_FW_VI_MAC_CMD_SMAC_RESULT) & M_FW_VI_MAC_CMD_SMAC_RESULT) 8013 8014 #define S_FW_VI_MAC_CMD_IDX 0 8015 #define M_FW_VI_MAC_CMD_IDX 0x3ff 8016 #define V_FW_VI_MAC_CMD_IDX(x) ((x) << S_FW_VI_MAC_CMD_IDX) 8017 #define G_FW_VI_MAC_CMD_IDX(x) \ 8018 (((x) >> S_FW_VI_MAC_CMD_IDX) & M_FW_VI_MAC_CMD_IDX) 8019 8020 #define S_FW_VI_MAC_CMD_RAW_IDX 16 8021 #define M_FW_VI_MAC_CMD_RAW_IDX 0xffff 8022 #define V_FW_VI_MAC_CMD_RAW_IDX(x) ((x) << S_FW_VI_MAC_CMD_RAW_IDX) 8023 #define G_FW_VI_MAC_CMD_RAW_IDX(x) \ 8024 (((x) >> S_FW_VI_MAC_CMD_RAW_IDX) & M_FW_VI_MAC_CMD_RAW_IDX) 8025 8026 #define S_FW_VI_MAC_CMD_DATA0 0 8027 #define M_FW_VI_MAC_CMD_DATA0 0xffff 8028 #define V_FW_VI_MAC_CMD_DATA0(x) ((x) << S_FW_VI_MAC_CMD_DATA0) 8029 #define G_FW_VI_MAC_CMD_DATA0(x) \ 8030 (((x) >> S_FW_VI_MAC_CMD_DATA0) & M_FW_VI_MAC_CMD_DATA0) 8031 8032 #define S_FW_VI_MAC_CMD_LOOKUP_TYPE 31 8033 #define M_FW_VI_MAC_CMD_LOOKUP_TYPE 0x1 8034 #define V_FW_VI_MAC_CMD_LOOKUP_TYPE(x) ((x) << S_FW_VI_MAC_CMD_LOOKUP_TYPE) 8035 #define G_FW_VI_MAC_CMD_LOOKUP_TYPE(x) \ 8036 (((x) >> S_FW_VI_MAC_CMD_LOOKUP_TYPE) & M_FW_VI_MAC_CMD_LOOKUP_TYPE) 8037 #define F_FW_VI_MAC_CMD_LOOKUP_TYPE V_FW_VI_MAC_CMD_LOOKUP_TYPE(1U) 8038 8039 #define S_FW_VI_MAC_CMD_DIP_HIT 30 8040 #define M_FW_VI_MAC_CMD_DIP_HIT 0x1 8041 #define V_FW_VI_MAC_CMD_DIP_HIT(x) ((x) << S_FW_VI_MAC_CMD_DIP_HIT) 8042 #define G_FW_VI_MAC_CMD_DIP_HIT(x) \ 8043 (((x) >> S_FW_VI_MAC_CMD_DIP_HIT) & M_FW_VI_MAC_CMD_DIP_HIT) 8044 #define F_FW_VI_MAC_CMD_DIP_HIT V_FW_VI_MAC_CMD_DIP_HIT(1U) 8045 8046 #define S_FW_VI_MAC_CMD_VNI 0 8047 #define M_FW_VI_MAC_CMD_VNI 0xffffff 8048 #define V_FW_VI_MAC_CMD_VNI(x) ((x) << S_FW_VI_MAC_CMD_VNI) 8049 #define G_FW_VI_MAC_CMD_VNI(x) \ 8050 (((x) >> S_FW_VI_MAC_CMD_VNI) & M_FW_VI_MAC_CMD_VNI) 8051 8052 /* Extracting loopback port number passed from driver. 8053 * as a part of fw_vi_mac_vni For non loopback entries 8054 * ignore the field and update port number from flowc. 8055 * Fw will ignore if physical port number received. 8056 * expected range (4-7). 8057 */ 8058 8059 #define S_FW_VI_MAC_CMD_PORT 24 8060 #define M_FW_VI_MAC_CMD_PORT 0x7 8061 #define V_FW_VI_MAC_CMD_PORT(x) ((x) << S_FW_VI_MAC_CMD_PORT) 8062 #define G_FW_VI_MAC_CMD_PORT(x) \ 8063 (((x) >> S_FW_VI_MAC_CMD_PORT) & M_FW_VI_MAC_CMD_PORT) 8064 8065 #define S_FW_VI_MAC_CMD_VNI_MASK 0 8066 #define M_FW_VI_MAC_CMD_VNI_MASK 0xffffff 8067 #define V_FW_VI_MAC_CMD_VNI_MASK(x) ((x) << S_FW_VI_MAC_CMD_VNI_MASK) 8068 #define G_FW_VI_MAC_CMD_VNI_MASK(x) \ 8069 (((x) >> S_FW_VI_MAC_CMD_VNI_MASK) & M_FW_VI_MAC_CMD_VNI_MASK) 8070 8071 /* T4 max MTU supported */ 8072 #define T4_MAX_MTU_SUPPORTED 9600 8073 #define FW_RXMODE_MTU_NO_CHG 65535 8074 8075 struct fw_vi_rxmode_cmd { 8076 __be32 op_to_viid; 8077 __be32 retval_len16; 8078 __be32 mtu_to_vlanexen; 8079 __be32 r4_lo; 8080 }; 8081 8082 #define S_FW_VI_RXMODE_CMD_VIID 0 8083 #define M_FW_VI_RXMODE_CMD_VIID 0xfff 8084 #define V_FW_VI_RXMODE_CMD_VIID(x) ((x) << S_FW_VI_RXMODE_CMD_VIID) 8085 #define G_FW_VI_RXMODE_CMD_VIID(x) \ 8086 (((x) >> S_FW_VI_RXMODE_CMD_VIID) & M_FW_VI_RXMODE_CMD_VIID) 8087 8088 #define S_FW_VI_RXMODE_CMD_MTU 16 8089 #define M_FW_VI_RXMODE_CMD_MTU 0xffff 8090 #define V_FW_VI_RXMODE_CMD_MTU(x) ((x) << S_FW_VI_RXMODE_CMD_MTU) 8091 #define G_FW_VI_RXMODE_CMD_MTU(x) \ 8092 (((x) >> S_FW_VI_RXMODE_CMD_MTU) & M_FW_VI_RXMODE_CMD_MTU) 8093 8094 #define S_FW_VI_RXMODE_CMD_PROMISCEN 14 8095 #define M_FW_VI_RXMODE_CMD_PROMISCEN 0x3 8096 #define V_FW_VI_RXMODE_CMD_PROMISCEN(x) ((x) << S_FW_VI_RXMODE_CMD_PROMISCEN) 8097 #define G_FW_VI_RXMODE_CMD_PROMISCEN(x) \ 8098 (((x) >> S_FW_VI_RXMODE_CMD_PROMISCEN) & M_FW_VI_RXMODE_CMD_PROMISCEN) 8099 8100 #define S_FW_VI_RXMODE_CMD_ALLMULTIEN 12 8101 #define M_FW_VI_RXMODE_CMD_ALLMULTIEN 0x3 8102 #define V_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 8103 ((x) << S_FW_VI_RXMODE_CMD_ALLMULTIEN) 8104 #define G_FW_VI_RXMODE_CMD_ALLMULTIEN(x) \ 8105 (((x) >> S_FW_VI_RXMODE_CMD_ALLMULTIEN) & M_FW_VI_RXMODE_CMD_ALLMULTIEN) 8106 8107 #define S_FW_VI_RXMODE_CMD_BROADCASTEN 10 8108 #define M_FW_VI_RXMODE_CMD_BROADCASTEN 0x3 8109 #define V_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 8110 ((x) << S_FW_VI_RXMODE_CMD_BROADCASTEN) 8111 #define G_FW_VI_RXMODE_CMD_BROADCASTEN(x) \ 8112 (((x) >> S_FW_VI_RXMODE_CMD_BROADCASTEN) & M_FW_VI_RXMODE_CMD_BROADCASTEN) 8113 8114 #define S_FW_VI_RXMODE_CMD_VLANEXEN 8 8115 #define M_FW_VI_RXMODE_CMD_VLANEXEN 0x3 8116 #define V_FW_VI_RXMODE_CMD_VLANEXEN(x) ((x) << S_FW_VI_RXMODE_CMD_VLANEXEN) 8117 #define G_FW_VI_RXMODE_CMD_VLANEXEN(x) \ 8118 (((x) >> S_FW_VI_RXMODE_CMD_VLANEXEN) & M_FW_VI_RXMODE_CMD_VLANEXEN) 8119 8120 struct fw_vi_enable_cmd { 8121 __be32 op_to_viid; 8122 __be32 ien_to_len16; 8123 __be16 blinkdur; 8124 __be16 r3; 8125 __be32 r4; 8126 }; 8127 8128 #define S_FW_VI_ENABLE_CMD_VIID 0 8129 #define M_FW_VI_ENABLE_CMD_VIID 0xfff 8130 #define V_FW_VI_ENABLE_CMD_VIID(x) ((x) << S_FW_VI_ENABLE_CMD_VIID) 8131 #define G_FW_VI_ENABLE_CMD_VIID(x) \ 8132 (((x) >> S_FW_VI_ENABLE_CMD_VIID) & M_FW_VI_ENABLE_CMD_VIID) 8133 8134 #define S_FW_VI_ENABLE_CMD_IEN 31 8135 #define M_FW_VI_ENABLE_CMD_IEN 0x1 8136 #define V_FW_VI_ENABLE_CMD_IEN(x) ((x) << S_FW_VI_ENABLE_CMD_IEN) 8137 #define G_FW_VI_ENABLE_CMD_IEN(x) \ 8138 (((x) >> S_FW_VI_ENABLE_CMD_IEN) & M_FW_VI_ENABLE_CMD_IEN) 8139 #define F_FW_VI_ENABLE_CMD_IEN V_FW_VI_ENABLE_CMD_IEN(1U) 8140 8141 #define S_FW_VI_ENABLE_CMD_EEN 30 8142 #define M_FW_VI_ENABLE_CMD_EEN 0x1 8143 #define V_FW_VI_ENABLE_CMD_EEN(x) ((x) << S_FW_VI_ENABLE_CMD_EEN) 8144 #define G_FW_VI_ENABLE_CMD_EEN(x) \ 8145 (((x) >> S_FW_VI_ENABLE_CMD_EEN) & M_FW_VI_ENABLE_CMD_EEN) 8146 #define F_FW_VI_ENABLE_CMD_EEN V_FW_VI_ENABLE_CMD_EEN(1U) 8147 8148 #define S_FW_VI_ENABLE_CMD_LED 29 8149 #define M_FW_VI_ENABLE_CMD_LED 0x1 8150 #define V_FW_VI_ENABLE_CMD_LED(x) ((x) << S_FW_VI_ENABLE_CMD_LED) 8151 #define G_FW_VI_ENABLE_CMD_LED(x) \ 8152 (((x) >> S_FW_VI_ENABLE_CMD_LED) & M_FW_VI_ENABLE_CMD_LED) 8153 #define F_FW_VI_ENABLE_CMD_LED V_FW_VI_ENABLE_CMD_LED(1U) 8154 8155 #define S_FW_VI_ENABLE_CMD_DCB_INFO 28 8156 #define M_FW_VI_ENABLE_CMD_DCB_INFO 0x1 8157 #define V_FW_VI_ENABLE_CMD_DCB_INFO(x) ((x) << S_FW_VI_ENABLE_CMD_DCB_INFO) 8158 #define G_FW_VI_ENABLE_CMD_DCB_INFO(x) \ 8159 (((x) >> S_FW_VI_ENABLE_CMD_DCB_INFO) & M_FW_VI_ENABLE_CMD_DCB_INFO) 8160 #define F_FW_VI_ENABLE_CMD_DCB_INFO V_FW_VI_ENABLE_CMD_DCB_INFO(1U) 8161 8162 /* VI VF stats offset definitions */ 8163 #define VI_VF_NUM_STATS 16 8164 enum fw_vi_stats_vf_index { 8165 FW_VI_VF_STAT_TX_BCAST_BYTES_IX, 8166 FW_VI_VF_STAT_TX_BCAST_FRAMES_IX, 8167 FW_VI_VF_STAT_TX_MCAST_BYTES_IX, 8168 FW_VI_VF_STAT_TX_MCAST_FRAMES_IX, 8169 FW_VI_VF_STAT_TX_UCAST_BYTES_IX, 8170 FW_VI_VF_STAT_TX_UCAST_FRAMES_IX, 8171 FW_VI_VF_STAT_TX_DROP_FRAMES_IX, 8172 FW_VI_VF_STAT_TX_OFLD_BYTES_IX, 8173 FW_VI_VF_STAT_TX_OFLD_FRAMES_IX, 8174 FW_VI_VF_STAT_RX_BCAST_BYTES_IX, 8175 FW_VI_VF_STAT_RX_BCAST_FRAMES_IX, 8176 FW_VI_VF_STAT_RX_MCAST_BYTES_IX, 8177 FW_VI_VF_STAT_RX_MCAST_FRAMES_IX, 8178 FW_VI_VF_STAT_RX_UCAST_BYTES_IX, 8179 FW_VI_VF_STAT_RX_UCAST_FRAMES_IX, 8180 FW_VI_VF_STAT_RX_ERR_FRAMES_IX 8181 }; 8182 8183 /* VI PF stats offset definitions */ 8184 #define VI_PF_NUM_STATS 17 8185 enum fw_vi_stats_pf_index { 8186 FW_VI_PF_STAT_TX_BCAST_BYTES_IX, 8187 FW_VI_PF_STAT_TX_BCAST_FRAMES_IX, 8188 FW_VI_PF_STAT_TX_MCAST_BYTES_IX, 8189 FW_VI_PF_STAT_TX_MCAST_FRAMES_IX, 8190 FW_VI_PF_STAT_TX_UCAST_BYTES_IX, 8191 FW_VI_PF_STAT_TX_UCAST_FRAMES_IX, 8192 FW_VI_PF_STAT_TX_OFLD_BYTES_IX, 8193 FW_VI_PF_STAT_TX_OFLD_FRAMES_IX, 8194 FW_VI_PF_STAT_RX_BYTES_IX, 8195 FW_VI_PF_STAT_RX_FRAMES_IX, 8196 FW_VI_PF_STAT_RX_BCAST_BYTES_IX, 8197 FW_VI_PF_STAT_RX_BCAST_FRAMES_IX, 8198 FW_VI_PF_STAT_RX_MCAST_BYTES_IX, 8199 FW_VI_PF_STAT_RX_MCAST_FRAMES_IX, 8200 FW_VI_PF_STAT_RX_UCAST_BYTES_IX, 8201 FW_VI_PF_STAT_RX_UCAST_FRAMES_IX, 8202 FW_VI_PF_STAT_RX_ERR_FRAMES_IX 8203 }; 8204 8205 struct fw_vi_stats_cmd { 8206 __be32 op_to_viid; 8207 __be32 retval_len16; 8208 union fw_vi_stats { 8209 struct fw_vi_stats_ctl { 8210 __be16 nstats_ix; 8211 __be16 r6; 8212 __be32 r7; 8213 __be64 stat0; 8214 __be64 stat1; 8215 __be64 stat2; 8216 __be64 stat3; 8217 __be64 stat4; 8218 __be64 stat5; 8219 } ctl; 8220 struct fw_vi_stats_pf { 8221 __be64 tx_bcast_bytes; 8222 __be64 tx_bcast_frames; 8223 __be64 tx_mcast_bytes; 8224 __be64 tx_mcast_frames; 8225 __be64 tx_ucast_bytes; 8226 __be64 tx_ucast_frames; 8227 __be64 tx_offload_bytes; 8228 __be64 tx_offload_frames; 8229 __be64 rx_pf_bytes; 8230 __be64 rx_pf_frames; 8231 __be64 rx_bcast_bytes; 8232 __be64 rx_bcast_frames; 8233 __be64 rx_mcast_bytes; 8234 __be64 rx_mcast_frames; 8235 __be64 rx_ucast_bytes; 8236 __be64 rx_ucast_frames; 8237 __be64 rx_err_frames; 8238 } pf; 8239 struct fw_vi_stats_vf { 8240 __be64 tx_bcast_bytes; 8241 __be64 tx_bcast_frames; 8242 __be64 tx_mcast_bytes; 8243 __be64 tx_mcast_frames; 8244 __be64 tx_ucast_bytes; 8245 __be64 tx_ucast_frames; 8246 __be64 tx_drop_frames; 8247 __be64 tx_offload_bytes; 8248 __be64 tx_offload_frames; 8249 __be64 rx_bcast_bytes; 8250 __be64 rx_bcast_frames; 8251 __be64 rx_mcast_bytes; 8252 __be64 rx_mcast_frames; 8253 __be64 rx_ucast_bytes; 8254 __be64 rx_ucast_frames; 8255 __be64 rx_err_frames; 8256 } vf; 8257 } u; 8258 }; 8259 8260 #define S_FW_VI_STATS_CMD_VIID 0 8261 #define M_FW_VI_STATS_CMD_VIID 0xfff 8262 #define V_FW_VI_STATS_CMD_VIID(x) ((x) << S_FW_VI_STATS_CMD_VIID) 8263 #define G_FW_VI_STATS_CMD_VIID(x) \ 8264 (((x) >> S_FW_VI_STATS_CMD_VIID) & M_FW_VI_STATS_CMD_VIID) 8265 8266 #define S_FW_VI_STATS_CMD_NSTATS 12 8267 #define M_FW_VI_STATS_CMD_NSTATS 0x7 8268 #define V_FW_VI_STATS_CMD_NSTATS(x) ((x) << S_FW_VI_STATS_CMD_NSTATS) 8269 #define G_FW_VI_STATS_CMD_NSTATS(x) \ 8270 (((x) >> S_FW_VI_STATS_CMD_NSTATS) & M_FW_VI_STATS_CMD_NSTATS) 8271 8272 #define S_FW_VI_STATS_CMD_IX 0 8273 #define M_FW_VI_STATS_CMD_IX 0x1f 8274 #define V_FW_VI_STATS_CMD_IX(x) ((x) << S_FW_VI_STATS_CMD_IX) 8275 #define G_FW_VI_STATS_CMD_IX(x) \ 8276 (((x) >> S_FW_VI_STATS_CMD_IX) & M_FW_VI_STATS_CMD_IX) 8277 8278 struct fw_acl_mac_cmd { 8279 __be32 op_to_vfn; 8280 __be32 en_to_len16; 8281 __u8 nmac; 8282 __u8 r3[7]; 8283 __be16 r4; 8284 __u8 macaddr0[6]; 8285 __be16 r5; 8286 __u8 macaddr1[6]; 8287 __be16 r6; 8288 __u8 macaddr2[6]; 8289 __be16 r7; 8290 __u8 macaddr3[6]; 8291 }; 8292 8293 #define S_FW_ACL_MAC_CMD_PFN 8 8294 #define M_FW_ACL_MAC_CMD_PFN 0x7 8295 #define V_FW_ACL_MAC_CMD_PFN(x) ((x) << S_FW_ACL_MAC_CMD_PFN) 8296 #define G_FW_ACL_MAC_CMD_PFN(x) \ 8297 (((x) >> S_FW_ACL_MAC_CMD_PFN) & M_FW_ACL_MAC_CMD_PFN) 8298 8299 #define S_FW_ACL_MAC_CMD_VFN 0 8300 #define M_FW_ACL_MAC_CMD_VFN 0xff 8301 #define V_FW_ACL_MAC_CMD_VFN(x) ((x) << S_FW_ACL_MAC_CMD_VFN) 8302 #define G_FW_ACL_MAC_CMD_VFN(x) \ 8303 (((x) >> S_FW_ACL_MAC_CMD_VFN) & M_FW_ACL_MAC_CMD_VFN) 8304 8305 #define S_FW_ACL_MAC_CMD_EN 31 8306 #define M_FW_ACL_MAC_CMD_EN 0x1 8307 #define V_FW_ACL_MAC_CMD_EN(x) ((x) << S_FW_ACL_MAC_CMD_EN) 8308 #define G_FW_ACL_MAC_CMD_EN(x) \ 8309 (((x) >> S_FW_ACL_MAC_CMD_EN) & M_FW_ACL_MAC_CMD_EN) 8310 #define F_FW_ACL_MAC_CMD_EN V_FW_ACL_MAC_CMD_EN(1U) 8311 8312 struct fw_acl_vlan_cmd { 8313 __be32 op_to_vfn; 8314 __be32 en_to_len16; 8315 __u8 nvlan; 8316 __u8 dropnovlan_fm; 8317 __u8 r3_lo[6]; 8318 __be16 vlanid[16]; 8319 }; 8320 8321 #define S_FW_ACL_VLAN_CMD_PFN 8 8322 #define M_FW_ACL_VLAN_CMD_PFN 0x7 8323 #define V_FW_ACL_VLAN_CMD_PFN(x) ((x) << S_FW_ACL_VLAN_CMD_PFN) 8324 #define G_FW_ACL_VLAN_CMD_PFN(x) \ 8325 (((x) >> S_FW_ACL_VLAN_CMD_PFN) & M_FW_ACL_VLAN_CMD_PFN) 8326 8327 #define S_FW_ACL_VLAN_CMD_VFN 0 8328 #define M_FW_ACL_VLAN_CMD_VFN 0xff 8329 #define V_FW_ACL_VLAN_CMD_VFN(x) ((x) << S_FW_ACL_VLAN_CMD_VFN) 8330 #define G_FW_ACL_VLAN_CMD_VFN(x) \ 8331 (((x) >> S_FW_ACL_VLAN_CMD_VFN) & M_FW_ACL_VLAN_CMD_VFN) 8332 8333 #define S_FW_ACL_VLAN_CMD_EN 31 8334 #define M_FW_ACL_VLAN_CMD_EN 0x1 8335 #define V_FW_ACL_VLAN_CMD_EN(x) ((x) << S_FW_ACL_VLAN_CMD_EN) 8336 #define G_FW_ACL_VLAN_CMD_EN(x) \ 8337 (((x) >> S_FW_ACL_VLAN_CMD_EN) & M_FW_ACL_VLAN_CMD_EN) 8338 #define F_FW_ACL_VLAN_CMD_EN V_FW_ACL_VLAN_CMD_EN(1U) 8339 8340 #define S_FW_ACL_VLAN_CMD_TRANSPARENT 30 8341 #define M_FW_ACL_VLAN_CMD_TRANSPARENT 0x1 8342 #define V_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 8343 ((x) << S_FW_ACL_VLAN_CMD_TRANSPARENT) 8344 #define G_FW_ACL_VLAN_CMD_TRANSPARENT(x) \ 8345 (((x) >> S_FW_ACL_VLAN_CMD_TRANSPARENT) & M_FW_ACL_VLAN_CMD_TRANSPARENT) 8346 #define F_FW_ACL_VLAN_CMD_TRANSPARENT V_FW_ACL_VLAN_CMD_TRANSPARENT(1U) 8347 8348 #define S_FW_ACL_VLAN_CMD_PMASK 16 8349 #define M_FW_ACL_VLAN_CMD_PMASK 0xf 8350 #define V_FW_ACL_VLAN_CMD_PMASK(x) ((x) << S_FW_ACL_VLAN_CMD_PMASK) 8351 #define G_FW_ACL_VLAN_CMD_PMASK(x) \ 8352 (((x) >> S_FW_ACL_VLAN_CMD_PMASK) & M_FW_ACL_VLAN_CMD_PMASK) 8353 8354 #define S_FW_ACL_VLAN_CMD_DROPNOVLAN 7 8355 #define M_FW_ACL_VLAN_CMD_DROPNOVLAN 0x1 8356 #define V_FW_ACL_VLAN_CMD_DROPNOVLAN(x) ((x) << S_FW_ACL_VLAN_CMD_DROPNOVLAN) 8357 #define G_FW_ACL_VLAN_CMD_DROPNOVLAN(x) \ 8358 (((x) >> S_FW_ACL_VLAN_CMD_DROPNOVLAN) & M_FW_ACL_VLAN_CMD_DROPNOVLAN) 8359 #define F_FW_ACL_VLAN_CMD_DROPNOVLAN V_FW_ACL_VLAN_CMD_DROPNOVLAN(1U) 8360 8361 #define S_FW_ACL_VLAN_CMD_FM 6 8362 #define M_FW_ACL_VLAN_CMD_FM 0x1 8363 #define V_FW_ACL_VLAN_CMD_FM(x) ((x) << S_FW_ACL_VLAN_CMD_FM) 8364 #define G_FW_ACL_VLAN_CMD_FM(x) \ 8365 (((x) >> S_FW_ACL_VLAN_CMD_FM) & M_FW_ACL_VLAN_CMD_FM) 8366 #define F_FW_ACL_VLAN_CMD_FM V_FW_ACL_VLAN_CMD_FM(1U) 8367 8368 /* old 16-bit port capabilities bitmap (fw_port_cap16_t) */ 8369 enum fw_port_cap { 8370 FW_PORT_CAP_SPEED_100M = 0x0001, 8371 FW_PORT_CAP_SPEED_1G = 0x0002, 8372 FW_PORT_CAP_SPEED_25G = 0x0004, 8373 FW_PORT_CAP_SPEED_10G = 0x0008, 8374 FW_PORT_CAP_SPEED_40G = 0x0010, 8375 FW_PORT_CAP_SPEED_100G = 0x0020, 8376 FW_PORT_CAP_FC_RX = 0x0040, 8377 FW_PORT_CAP_FC_TX = 0x0080, 8378 FW_PORT_CAP_ANEG = 0x0100, 8379 FW_PORT_CAP_MDIAUTO = 0x0200, 8380 FW_PORT_CAP_MDISTRAIGHT = 0x0400, 8381 FW_PORT_CAP_FEC_RS = 0x0800, 8382 FW_PORT_CAP_FEC_BASER_RS = 0x1000, 8383 FW_PORT_CAP_FORCE_PAUSE = 0x2000, 8384 FW_PORT_CAP_802_3_PAUSE = 0x4000, 8385 FW_PORT_CAP_802_3_ASM_DIR = 0x8000, 8386 }; 8387 8388 #define S_FW_PORT_CAP_SPEED 0 8389 #define M_FW_PORT_CAP_SPEED 0x3f 8390 #define V_FW_PORT_CAP_SPEED(x) ((x) << S_FW_PORT_CAP_SPEED) 8391 #define G_FW_PORT_CAP_SPEED(x) \ 8392 (((x) >> S_FW_PORT_CAP_SPEED) & M_FW_PORT_CAP_SPEED) 8393 8394 #define S_FW_PORT_CAP_FC 6 8395 #define M_FW_PORT_CAP_FC 0x3 8396 #define V_FW_PORT_CAP_FC(x) ((x) << S_FW_PORT_CAP_FC) 8397 #define G_FW_PORT_CAP_FC(x) \ 8398 (((x) >> S_FW_PORT_CAP_FC) & M_FW_PORT_CAP_FC) 8399 8400 #define S_FW_PORT_CAP_ANEG 8 8401 #define M_FW_PORT_CAP_ANEG 0x1 8402 #define V_FW_PORT_CAP_ANEG(x) ((x) << S_FW_PORT_CAP_ANEG) 8403 #define G_FW_PORT_CAP_ANEG(x) \ 8404 (((x) >> S_FW_PORT_CAP_ANEG) & M_FW_PORT_CAP_ANEG) 8405 8406 #define S_FW_PORT_CAP_FEC 11 8407 #define M_FW_PORT_CAP_FEC 0x3 8408 #define V_FW_PORT_CAP_FEC(x) ((x) << S_FW_PORT_CAP_FEC) 8409 #define G_FW_PORT_CAP_FEC(x) \ 8410 (((x) >> S_FW_PORT_CAP_FEC) & M_FW_PORT_CAP_FEC) 8411 8412 #define S_FW_PORT_CAP_FORCE_PAUSE 13 8413 #define M_FW_PORT_CAP_FORCE_PAUSE 0x1 8414 #define V_FW_PORT_CAP_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP_FORCE_PAUSE) 8415 #define G_FW_PORT_CAP_FORCE_PAUSE(x) \ 8416 (((x) >> S_FW_PORT_CAP_FORCE_PAUSE) & M_FW_PORT_CAP_FORCE_PAUSE) 8417 8418 #define S_FW_PORT_CAP_802_3 14 8419 #define M_FW_PORT_CAP_802_3 0x3 8420 #define V_FW_PORT_CAP_802_3(x) ((x) << S_FW_PORT_CAP_802_3) 8421 #define G_FW_PORT_CAP_802_3(x) \ 8422 (((x) >> S_FW_PORT_CAP_802_3) & M_FW_PORT_CAP_802_3) 8423 8424 enum fw_port_mdi { 8425 FW_PORT_CAP_MDI_UNCHANGED, 8426 FW_PORT_CAP_MDI_AUTO, 8427 FW_PORT_CAP_MDI_F_STRAIGHT, 8428 FW_PORT_CAP_MDI_F_CROSSOVER 8429 }; 8430 8431 #define S_FW_PORT_CAP_MDI 9 8432 #define M_FW_PORT_CAP_MDI 3 8433 #define V_FW_PORT_CAP_MDI(x) ((x) << S_FW_PORT_CAP_MDI) 8434 #define G_FW_PORT_CAP_MDI(x) (((x) >> S_FW_PORT_CAP_MDI) & M_FW_PORT_CAP_MDI) 8435 8436 /* new 32-bit port capabilities bitmap (fw_port_cap32_t) */ 8437 #define FW_PORT_CAP32_SPEED_100M 0x00000001UL 8438 #define FW_PORT_CAP32_SPEED_1G 0x00000002UL 8439 #define FW_PORT_CAP32_SPEED_10G 0x00000004UL 8440 #define FW_PORT_CAP32_SPEED_25G 0x00000008UL 8441 #define FW_PORT_CAP32_SPEED_40G 0x00000010UL 8442 #define FW_PORT_CAP32_SPEED_50G 0x00000020UL 8443 #define FW_PORT_CAP32_SPEED_100G 0x00000040UL 8444 #define FW_PORT_CAP32_SPEED_200G 0x00000080UL 8445 #define FW_PORT_CAP32_SPEED_400G 0x00000100UL 8446 #define FW_PORT_CAP32_SPEED_RESERVED1 0x00000200UL 8447 #define FW_PORT_CAP32_SPEED_RESERVED2 0x00000400UL 8448 #define FW_PORT_CAP32_SPEED_RESERVED3 0x00000800UL 8449 #define FW_PORT_CAP32_RESERVED1 0x0000f000UL 8450 #define FW_PORT_CAP32_FC_RX 0x00010000UL 8451 #define FW_PORT_CAP32_FC_TX 0x00020000UL 8452 #define FW_PORT_CAP32_802_3_PAUSE 0x00040000UL 8453 #define FW_PORT_CAP32_802_3_ASM_DIR 0x00080000UL 8454 #define FW_PORT_CAP32_ANEG 0x00100000UL 8455 #define FW_PORT_CAP32_MDIAUTO 0x00200000UL 8456 #define FW_PORT_CAP32_MDISTRAIGHT 0x00400000UL 8457 #define FW_PORT_CAP32_FEC_RS 0x00800000UL 8458 #define FW_PORT_CAP32_FEC_BASER_RS 0x01000000UL 8459 #define FW_PORT_CAP32_FEC_NO_FEC 0x02000000UL 8460 #define FW_PORT_CAP32_FEC_RESERVED2 0x04000000UL 8461 #define FW_PORT_CAP32_FEC_RESERVED3 0x08000000UL 8462 #define FW_PORT_CAP32_FORCE_PAUSE 0x10000000UL 8463 #define FW_PORT_CAP32_FORCE_FEC 0x20000000UL 8464 #define FW_PORT_CAP32_RESERVED2 0xc0000000UL 8465 8466 #define S_FW_PORT_CAP32_SPEED 0 8467 #define M_FW_PORT_CAP32_SPEED 0xfff 8468 #define V_FW_PORT_CAP32_SPEED(x) ((x) << S_FW_PORT_CAP32_SPEED) 8469 #define G_FW_PORT_CAP32_SPEED(x) \ 8470 (((x) >> S_FW_PORT_CAP32_SPEED) & M_FW_PORT_CAP32_SPEED) 8471 8472 #define S_FW_PORT_CAP32_FC 16 8473 #define M_FW_PORT_CAP32_FC 0x3 8474 #define V_FW_PORT_CAP32_FC(x) ((x) << S_FW_PORT_CAP32_FC) 8475 #define G_FW_PORT_CAP32_FC(x) \ 8476 (((x) >> S_FW_PORT_CAP32_FC) & M_FW_PORT_CAP32_FC) 8477 8478 #define S_FW_PORT_CAP32_802_3 18 8479 #define M_FW_PORT_CAP32_802_3 0x3 8480 #define V_FW_PORT_CAP32_802_3(x) ((x) << S_FW_PORT_CAP32_802_3) 8481 #define G_FW_PORT_CAP32_802_3(x) \ 8482 (((x) >> S_FW_PORT_CAP32_802_3) & M_FW_PORT_CAP32_802_3) 8483 8484 #define S_FW_PORT_CAP32_ANEG 20 8485 #define M_FW_PORT_CAP32_ANEG 0x1 8486 #define V_FW_PORT_CAP32_ANEG(x) ((x) << S_FW_PORT_CAP32_ANEG) 8487 #define G_FW_PORT_CAP32_ANEG(x) \ 8488 (((x) >> S_FW_PORT_CAP32_ANEG) & M_FW_PORT_CAP32_ANEG) 8489 8490 #define S_FW_PORT_CAP32_FORCE_PAUSE 28 8491 #define M_FW_PORT_CAP32_FORCE_PAUSE 0x1 8492 #define V_FW_PORT_CAP32_FORCE_PAUSE(x) ((x) << S_FW_PORT_CAP32_FORCE_PAUSE) 8493 #define G_FW_PORT_CAP32_FORCE_PAUSE(x) \ 8494 (((x) >> S_FW_PORT_CAP32_FORCE_PAUSE) & M_FW_PORT_CAP32_FORCE_PAUSE) 8495 8496 enum fw_port_mdi32 { 8497 FW_PORT_CAP32_MDI_UNCHANGED, 8498 FW_PORT_CAP32_MDI_AUTO, 8499 FW_PORT_CAP32_MDI_F_STRAIGHT, 8500 FW_PORT_CAP32_MDI_F_CROSSOVER 8501 }; 8502 8503 #define S_FW_PORT_CAP32_MDI 21 8504 #define M_FW_PORT_CAP32_MDI 3 8505 #define V_FW_PORT_CAP32_MDI(x) ((x) << S_FW_PORT_CAP32_MDI) 8506 #define G_FW_PORT_CAP32_MDI(x) \ 8507 (((x) >> S_FW_PORT_CAP32_MDI) & M_FW_PORT_CAP32_MDI) 8508 8509 #define S_FW_PORT_CAP32_FEC 23 8510 #define M_FW_PORT_CAP32_FEC 0x1f 8511 #define V_FW_PORT_CAP32_FEC(x) ((x) << S_FW_PORT_CAP32_FEC) 8512 #define G_FW_PORT_CAP32_FEC(x) \ 8513 (((x) >> S_FW_PORT_CAP32_FEC) & M_FW_PORT_CAP32_FEC) 8514 8515 /* macros to isolate various 32-bit Port Capabilities sub-fields */ 8516 #define CAP32_SPEED(__cap32) \ 8517 (V_FW_PORT_CAP32_SPEED(M_FW_PORT_CAP32_SPEED) & __cap32) 8518 8519 #define CAP32_FEC(__cap32) \ 8520 (V_FW_PORT_CAP32_FEC(M_FW_PORT_CAP32_FEC) & __cap32) 8521 8522 #define CAP32_FC(__cap32) \ 8523 (V_FW_PORT_CAP32_FC(M_FW_PORT_CAP32_FC) & __cap32) 8524 8525 static inline bool 8526 fec_supported(uint32_t caps) 8527 { 8528 8529 return ((caps & (FW_PORT_CAP32_SPEED_25G | FW_PORT_CAP32_SPEED_50G | 8530 FW_PORT_CAP32_SPEED_100G | FW_PORT_CAP32_SPEED_200G | 8531 FW_PORT_CAP32_SPEED_400G)) != 0); 8532 } 8533 8534 enum fw_port_action { 8535 FW_PORT_ACTION_L1_CFG = 0x0001, 8536 FW_PORT_ACTION_L2_CFG = 0x0002, 8537 FW_PORT_ACTION_GET_PORT_INFO = 0x0003, 8538 FW_PORT_ACTION_L2_PPP_CFG = 0x0004, 8539 FW_PORT_ACTION_L2_DCB_CFG = 0x0005, 8540 FW_PORT_ACTION_DCB_READ_TRANS = 0x0006, 8541 FW_PORT_ACTION_DCB_READ_RECV = 0x0007, 8542 FW_PORT_ACTION_DCB_READ_DET = 0x0008, 8543 FW_PORT_ACTION_L1_CFG32 = 0x0009, 8544 FW_PORT_ACTION_GET_PORT_INFO32 = 0x000a, 8545 FW_PORT_ACTION_LOW_PWR_TO_NORMAL = 0x0010, 8546 FW_PORT_ACTION_L1_LOW_PWR_EN = 0x0011, 8547 FW_PORT_ACTION_L2_WOL_MODE_EN = 0x0012, 8548 FW_PORT_ACTION_LPBK_TO_NORMAL = 0x0020, 8549 FW_PORT_ACTION_LPBK_SS_ASIC = 0x0022, 8550 FW_PORT_ACTION_LPBK_WS_ASIC = 0x0023, 8551 FW_PORT_ACTION_LPBK_WS_EXT_PHY = 0x0025, 8552 FW_PORT_ACTION_LPBK_SS_EXT = 0x0026, 8553 FW_PORT_ACTION_DIAGNOSTICS = 0x0027, 8554 FW_PORT_ACTION_LPBK_SS_EXT_PHY = 0x0028, 8555 FW_PORT_ACTION_PHY_RESET = 0x0040, 8556 FW_PORT_ACTION_PMA_RESET = 0x0041, 8557 FW_PORT_ACTION_PCS_RESET = 0x0042, 8558 FW_PORT_ACTION_PHYXS_RESET = 0x0043, 8559 FW_PORT_ACTION_DTEXS_REEST = 0x0044, 8560 FW_PORT_ACTION_AN_RESET = 0x0045, 8561 }; 8562 8563 enum fw_port_l2cfg_ctlbf { 8564 FW_PORT_L2_CTLBF_OVLAN0 = 0x01, 8565 FW_PORT_L2_CTLBF_OVLAN1 = 0x02, 8566 FW_PORT_L2_CTLBF_OVLAN2 = 0x04, 8567 FW_PORT_L2_CTLBF_OVLAN3 = 0x08, 8568 FW_PORT_L2_CTLBF_IVLAN = 0x10, 8569 FW_PORT_L2_CTLBF_TXIPG = 0x20, 8570 FW_PORT_L2_CTLBF_MTU = 0x40, 8571 FW_PORT_L2_CTLBF_OVLAN_FILT = 0x80, 8572 }; 8573 8574 enum fw_dcb_app_tlv_sf { 8575 FW_DCB_APP_SF_ETHERTYPE, 8576 FW_DCB_APP_SF_SOCKET_TCP, 8577 FW_DCB_APP_SF_SOCKET_UDP, 8578 FW_DCB_APP_SF_SOCKET_ALL, 8579 }; 8580 8581 enum fw_port_dcb_versions { 8582 FW_PORT_DCB_VER_UNKNOWN, 8583 FW_PORT_DCB_VER_CEE1D0, 8584 FW_PORT_DCB_VER_CEE1D01, 8585 FW_PORT_DCB_VER_IEEE, 8586 FW_PORT_DCB_VER_AUTO=7 8587 }; 8588 8589 enum fw_port_dcb_cfg { 8590 FW_PORT_DCB_CFG_PG = 0x01, 8591 FW_PORT_DCB_CFG_PFC = 0x02, 8592 FW_PORT_DCB_CFG_APPL = 0x04 8593 }; 8594 8595 enum fw_port_dcb_cfg_rc { 8596 FW_PORT_DCB_CFG_SUCCESS = 0x0, 8597 FW_PORT_DCB_CFG_ERROR = 0x1 8598 }; 8599 8600 enum fw_port_dcb_type { 8601 FW_PORT_DCB_TYPE_PGID = 0x00, 8602 FW_PORT_DCB_TYPE_PGRATE = 0x01, 8603 FW_PORT_DCB_TYPE_PRIORATE = 0x02, 8604 FW_PORT_DCB_TYPE_PFC = 0x03, 8605 FW_PORT_DCB_TYPE_APP_ID = 0x04, 8606 FW_PORT_DCB_TYPE_CONTROL = 0x05, 8607 }; 8608 8609 enum fw_port_dcb_feature_state { 8610 FW_PORT_DCB_FEATURE_STATE_PENDING = 0x0, 8611 FW_PORT_DCB_FEATURE_STATE_SUCCESS = 0x1, 8612 FW_PORT_DCB_FEATURE_STATE_ERROR = 0x2, 8613 FW_PORT_DCB_FEATURE_STATE_TIMEOUT = 0x3, 8614 }; 8615 8616 enum fw_port_diag_ops { 8617 FW_PORT_DIAGS_TEMP = 0x00, 8618 FW_PORT_DIAGS_TX_POWER = 0x01, 8619 FW_PORT_DIAGS_RX_POWER = 0x02, 8620 FW_PORT_DIAGS_TX_DIS = 0x03, 8621 }; 8622 8623 struct fw_port_cmd { 8624 __be32 op_to_portid; 8625 __be32 action_to_len16; 8626 union fw_port { 8627 struct fw_port_l1cfg { 8628 __be32 rcap; 8629 __be32 r; 8630 } l1cfg; 8631 struct fw_port_l2cfg { 8632 __u8 ctlbf; 8633 __u8 ovlan3_to_ivlan0; 8634 __be16 ivlantype; 8635 __be16 txipg_force_pinfo; 8636 __be16 mtu; 8637 __be16 ovlan0mask; 8638 __be16 ovlan0type; 8639 __be16 ovlan1mask; 8640 __be16 ovlan1type; 8641 __be16 ovlan2mask; 8642 __be16 ovlan2type; 8643 __be16 ovlan3mask; 8644 __be16 ovlan3type; 8645 } l2cfg; 8646 struct fw_port_info { 8647 __be32 lstatus_to_modtype; 8648 __be16 pcap; 8649 __be16 acap; 8650 __be16 mtu; 8651 __u8 cbllen; 8652 __u8 auxlinfo; 8653 __u8 dcbxdis_pkd; 8654 __u8 r8_lo; 8655 __be16 lpacap; 8656 __be64 r9; 8657 } info; 8658 struct fw_port_diags { 8659 __u8 diagop; 8660 __u8 r[3]; 8661 __be32 diagval; 8662 } diags; 8663 union fw_port_dcb { 8664 struct fw_port_dcb_pgid { 8665 __u8 type; 8666 __u8 apply_pkd; 8667 __u8 r10_lo[2]; 8668 __be32 pgid; 8669 __be64 r11; 8670 } pgid; 8671 struct fw_port_dcb_pgrate { 8672 __u8 type; 8673 __u8 apply_pkd; 8674 __u8 r10_lo[5]; 8675 __u8 num_tcs_supported; 8676 __u8 pgrate[8]; 8677 __u8 tsa[8]; 8678 } pgrate; 8679 struct fw_port_dcb_priorate { 8680 __u8 type; 8681 __u8 apply_pkd; 8682 __u8 r10_lo[6]; 8683 __u8 strict_priorate[8]; 8684 } priorate; 8685 struct fw_port_dcb_pfc { 8686 __u8 type; 8687 __u8 pfcen; 8688 __u8 apply_pkd; 8689 __u8 r10_lo[4]; 8690 __u8 max_pfc_tcs; 8691 __be64 r11; 8692 } pfc; 8693 struct fw_port_app_priority { 8694 __u8 type; 8695 __u8 apply_pkd; 8696 __u8 r10_lo; 8697 __u8 idx; 8698 __u8 user_prio_map; 8699 __u8 sel_field; 8700 __be16 protocolid; 8701 __be64 r12; 8702 } app_priority; 8703 struct fw_port_dcb_control { 8704 __u8 type; 8705 __u8 all_syncd_pkd; 8706 __be16 dcb_version_to_app_state; 8707 __be32 r11; 8708 __be64 r12; 8709 } control; 8710 } dcb; 8711 struct fw_port_l1cfg32 { 8712 __be32 rcap32; 8713 __be32 r; 8714 } l1cfg32; 8715 struct fw_port_info32 { 8716 __be32 lstatus32_to_cbllen32; 8717 __be32 auxlinfo32_mtu32; 8718 __be32 linkattr32; 8719 __be32 pcaps32; 8720 __be32 acaps32; 8721 __be32 lpacaps32; 8722 } info32; 8723 } u; 8724 }; 8725 8726 #define S_FW_PORT_CMD_READ 22 8727 #define M_FW_PORT_CMD_READ 0x1 8728 #define V_FW_PORT_CMD_READ(x) ((x) << S_FW_PORT_CMD_READ) 8729 #define G_FW_PORT_CMD_READ(x) \ 8730 (((x) >> S_FW_PORT_CMD_READ) & M_FW_PORT_CMD_READ) 8731 #define F_FW_PORT_CMD_READ V_FW_PORT_CMD_READ(1U) 8732 8733 #define S_FW_PORT_CMD_PORTID 0 8734 #define M_FW_PORT_CMD_PORTID 0xf 8735 #define V_FW_PORT_CMD_PORTID(x) ((x) << S_FW_PORT_CMD_PORTID) 8736 #define G_FW_PORT_CMD_PORTID(x) \ 8737 (((x) >> S_FW_PORT_CMD_PORTID) & M_FW_PORT_CMD_PORTID) 8738 8739 #define S_FW_PORT_CMD_ACTION 16 8740 #define M_FW_PORT_CMD_ACTION 0xffff 8741 #define V_FW_PORT_CMD_ACTION(x) ((x) << S_FW_PORT_CMD_ACTION) 8742 #define G_FW_PORT_CMD_ACTION(x) \ 8743 (((x) >> S_FW_PORT_CMD_ACTION) & M_FW_PORT_CMD_ACTION) 8744 8745 #define S_FW_PORT_CMD_OVLAN3 7 8746 #define M_FW_PORT_CMD_OVLAN3 0x1 8747 #define V_FW_PORT_CMD_OVLAN3(x) ((x) << S_FW_PORT_CMD_OVLAN3) 8748 #define G_FW_PORT_CMD_OVLAN3(x) \ 8749 (((x) >> S_FW_PORT_CMD_OVLAN3) & M_FW_PORT_CMD_OVLAN3) 8750 #define F_FW_PORT_CMD_OVLAN3 V_FW_PORT_CMD_OVLAN3(1U) 8751 8752 #define S_FW_PORT_CMD_OVLAN2 6 8753 #define M_FW_PORT_CMD_OVLAN2 0x1 8754 #define V_FW_PORT_CMD_OVLAN2(x) ((x) << S_FW_PORT_CMD_OVLAN2) 8755 #define G_FW_PORT_CMD_OVLAN2(x) \ 8756 (((x) >> S_FW_PORT_CMD_OVLAN2) & M_FW_PORT_CMD_OVLAN2) 8757 #define F_FW_PORT_CMD_OVLAN2 V_FW_PORT_CMD_OVLAN2(1U) 8758 8759 #define S_FW_PORT_CMD_OVLAN1 5 8760 #define M_FW_PORT_CMD_OVLAN1 0x1 8761 #define V_FW_PORT_CMD_OVLAN1(x) ((x) << S_FW_PORT_CMD_OVLAN1) 8762 #define G_FW_PORT_CMD_OVLAN1(x) \ 8763 (((x) >> S_FW_PORT_CMD_OVLAN1) & M_FW_PORT_CMD_OVLAN1) 8764 #define F_FW_PORT_CMD_OVLAN1 V_FW_PORT_CMD_OVLAN1(1U) 8765 8766 #define S_FW_PORT_CMD_OVLAN0 4 8767 #define M_FW_PORT_CMD_OVLAN0 0x1 8768 #define V_FW_PORT_CMD_OVLAN0(x) ((x) << S_FW_PORT_CMD_OVLAN0) 8769 #define G_FW_PORT_CMD_OVLAN0(x) \ 8770 (((x) >> S_FW_PORT_CMD_OVLAN0) & M_FW_PORT_CMD_OVLAN0) 8771 #define F_FW_PORT_CMD_OVLAN0 V_FW_PORT_CMD_OVLAN0(1U) 8772 8773 #define S_FW_PORT_CMD_IVLAN0 3 8774 #define M_FW_PORT_CMD_IVLAN0 0x1 8775 #define V_FW_PORT_CMD_IVLAN0(x) ((x) << S_FW_PORT_CMD_IVLAN0) 8776 #define G_FW_PORT_CMD_IVLAN0(x) \ 8777 (((x) >> S_FW_PORT_CMD_IVLAN0) & M_FW_PORT_CMD_IVLAN0) 8778 #define F_FW_PORT_CMD_IVLAN0 V_FW_PORT_CMD_IVLAN0(1U) 8779 8780 #define S_FW_PORT_CMD_OVLAN_FILT 2 8781 #define M_FW_PORT_CMD_OVLAN_FILT 0x1 8782 #define V_FW_PORT_CMD_OVLAN_FILT(x) ((x) << S_FW_PORT_CMD_OVLAN_FILT) 8783 #define G_FW_PORT_CMD_OVLAN_FILT(x) \ 8784 (((x) >> S_FW_PORT_CMD_OVLAN_FILT) & M_FW_PORT_CMD_OVLAN_FILT) 8785 #define F_FW_PORT_CMD_OVLAN_FILT V_FW_PORT_CMD_OVLAN_FILT(1U) 8786 8787 #define S_FW_PORT_CMD_TXIPG 3 8788 #define M_FW_PORT_CMD_TXIPG 0x1fff 8789 #define V_FW_PORT_CMD_TXIPG(x) ((x) << S_FW_PORT_CMD_TXIPG) 8790 #define G_FW_PORT_CMD_TXIPG(x) \ 8791 (((x) >> S_FW_PORT_CMD_TXIPG) & M_FW_PORT_CMD_TXIPG) 8792 8793 #define S_FW_PORT_CMD_FORCE_PINFO 0 8794 #define M_FW_PORT_CMD_FORCE_PINFO 0x1 8795 #define V_FW_PORT_CMD_FORCE_PINFO(x) ((x) << S_FW_PORT_CMD_FORCE_PINFO) 8796 #define G_FW_PORT_CMD_FORCE_PINFO(x) \ 8797 (((x) >> S_FW_PORT_CMD_FORCE_PINFO) & M_FW_PORT_CMD_FORCE_PINFO) 8798 #define F_FW_PORT_CMD_FORCE_PINFO V_FW_PORT_CMD_FORCE_PINFO(1U) 8799 8800 #define S_FW_PORT_CMD_LSTATUS 31 8801 #define M_FW_PORT_CMD_LSTATUS 0x1 8802 #define V_FW_PORT_CMD_LSTATUS(x) ((x) << S_FW_PORT_CMD_LSTATUS) 8803 #define G_FW_PORT_CMD_LSTATUS(x) \ 8804 (((x) >> S_FW_PORT_CMD_LSTATUS) & M_FW_PORT_CMD_LSTATUS) 8805 #define F_FW_PORT_CMD_LSTATUS V_FW_PORT_CMD_LSTATUS(1U) 8806 8807 #define S_FW_PORT_CMD_LSPEED 24 8808 #define M_FW_PORT_CMD_LSPEED 0x3f 8809 #define V_FW_PORT_CMD_LSPEED(x) ((x) << S_FW_PORT_CMD_LSPEED) 8810 #define G_FW_PORT_CMD_LSPEED(x) \ 8811 (((x) >> S_FW_PORT_CMD_LSPEED) & M_FW_PORT_CMD_LSPEED) 8812 8813 #define S_FW_PORT_CMD_TXPAUSE 23 8814 #define M_FW_PORT_CMD_TXPAUSE 0x1 8815 #define V_FW_PORT_CMD_TXPAUSE(x) ((x) << S_FW_PORT_CMD_TXPAUSE) 8816 #define G_FW_PORT_CMD_TXPAUSE(x) \ 8817 (((x) >> S_FW_PORT_CMD_TXPAUSE) & M_FW_PORT_CMD_TXPAUSE) 8818 #define F_FW_PORT_CMD_TXPAUSE V_FW_PORT_CMD_TXPAUSE(1U) 8819 8820 #define S_FW_PORT_CMD_RXPAUSE 22 8821 #define M_FW_PORT_CMD_RXPAUSE 0x1 8822 #define V_FW_PORT_CMD_RXPAUSE(x) ((x) << S_FW_PORT_CMD_RXPAUSE) 8823 #define G_FW_PORT_CMD_RXPAUSE(x) \ 8824 (((x) >> S_FW_PORT_CMD_RXPAUSE) & M_FW_PORT_CMD_RXPAUSE) 8825 #define F_FW_PORT_CMD_RXPAUSE V_FW_PORT_CMD_RXPAUSE(1U) 8826 8827 #define S_FW_PORT_CMD_MDIOCAP 21 8828 #define M_FW_PORT_CMD_MDIOCAP 0x1 8829 #define V_FW_PORT_CMD_MDIOCAP(x) ((x) << S_FW_PORT_CMD_MDIOCAP) 8830 #define G_FW_PORT_CMD_MDIOCAP(x) \ 8831 (((x) >> S_FW_PORT_CMD_MDIOCAP) & M_FW_PORT_CMD_MDIOCAP) 8832 #define F_FW_PORT_CMD_MDIOCAP V_FW_PORT_CMD_MDIOCAP(1U) 8833 8834 #define S_FW_PORT_CMD_MDIOADDR 16 8835 #define M_FW_PORT_CMD_MDIOADDR 0x1f 8836 #define V_FW_PORT_CMD_MDIOADDR(x) ((x) << S_FW_PORT_CMD_MDIOADDR) 8837 #define G_FW_PORT_CMD_MDIOADDR(x) \ 8838 (((x) >> S_FW_PORT_CMD_MDIOADDR) & M_FW_PORT_CMD_MDIOADDR) 8839 8840 #define S_FW_PORT_CMD_LPTXPAUSE 15 8841 #define M_FW_PORT_CMD_LPTXPAUSE 0x1 8842 #define V_FW_PORT_CMD_LPTXPAUSE(x) ((x) << S_FW_PORT_CMD_LPTXPAUSE) 8843 #define G_FW_PORT_CMD_LPTXPAUSE(x) \ 8844 (((x) >> S_FW_PORT_CMD_LPTXPAUSE) & M_FW_PORT_CMD_LPTXPAUSE) 8845 #define F_FW_PORT_CMD_LPTXPAUSE V_FW_PORT_CMD_LPTXPAUSE(1U) 8846 8847 #define S_FW_PORT_CMD_LPRXPAUSE 14 8848 #define M_FW_PORT_CMD_LPRXPAUSE 0x1 8849 #define V_FW_PORT_CMD_LPRXPAUSE(x) ((x) << S_FW_PORT_CMD_LPRXPAUSE) 8850 #define G_FW_PORT_CMD_LPRXPAUSE(x) \ 8851 (((x) >> S_FW_PORT_CMD_LPRXPAUSE) & M_FW_PORT_CMD_LPRXPAUSE) 8852 #define F_FW_PORT_CMD_LPRXPAUSE V_FW_PORT_CMD_LPRXPAUSE(1U) 8853 8854 #define S_FW_PORT_CMD_PTYPE 8 8855 #define M_FW_PORT_CMD_PTYPE 0x1f 8856 #define V_FW_PORT_CMD_PTYPE(x) ((x) << S_FW_PORT_CMD_PTYPE) 8857 #define G_FW_PORT_CMD_PTYPE(x) \ 8858 (((x) >> S_FW_PORT_CMD_PTYPE) & M_FW_PORT_CMD_PTYPE) 8859 8860 #define S_FW_PORT_CMD_LINKDNRC 5 8861 #define M_FW_PORT_CMD_LINKDNRC 0x7 8862 #define V_FW_PORT_CMD_LINKDNRC(x) ((x) << S_FW_PORT_CMD_LINKDNRC) 8863 #define G_FW_PORT_CMD_LINKDNRC(x) \ 8864 (((x) >> S_FW_PORT_CMD_LINKDNRC) & M_FW_PORT_CMD_LINKDNRC) 8865 8866 #define S_FW_PORT_CMD_MODTYPE 0 8867 #define M_FW_PORT_CMD_MODTYPE 0x1f 8868 #define V_FW_PORT_CMD_MODTYPE(x) ((x) << S_FW_PORT_CMD_MODTYPE) 8869 #define G_FW_PORT_CMD_MODTYPE(x) \ 8870 (((x) >> S_FW_PORT_CMD_MODTYPE) & M_FW_PORT_CMD_MODTYPE) 8871 8872 #define S_FW_PORT_AUXLINFO_KX4 2 8873 #define M_FW_PORT_AUXLINFO_KX4 0x1 8874 #define V_FW_PORT_AUXLINFO_KX4(x) \ 8875 ((x) << S_FW_PORT_AUXLINFO_KX4) 8876 #define G_FW_PORT_AUXLINFO_KX4(x) \ 8877 (((x) >> S_FW_PORT_AUXLINFO_KX4) & M_FW_PORT_AUXLINFO_KX4) 8878 #define F_FW_PORT_AUXLINFO_KX4 V_FW_PORT_AUXLINFO_KX4(1U) 8879 8880 #define S_FW_PORT_AUXLINFO_KR 1 8881 #define M_FW_PORT_AUXLINFO_KR 0x1 8882 #define V_FW_PORT_AUXLINFO_KR(x) \ 8883 ((x) << S_FW_PORT_AUXLINFO_KR) 8884 #define G_FW_PORT_AUXLINFO_KR(x) \ 8885 (((x) >> S_FW_PORT_AUXLINFO_KR) & M_FW_PORT_AUXLINFO_KR) 8886 #define F_FW_PORT_AUXLINFO_KR V_FW_PORT_AUXLINFO_KR(1U) 8887 8888 #define S_FW_PORT_CMD_DCBXDIS 7 8889 #define M_FW_PORT_CMD_DCBXDIS 0x1 8890 #define V_FW_PORT_CMD_DCBXDIS(x) ((x) << S_FW_PORT_CMD_DCBXDIS) 8891 #define G_FW_PORT_CMD_DCBXDIS(x) \ 8892 (((x) >> S_FW_PORT_CMD_DCBXDIS) & M_FW_PORT_CMD_DCBXDIS) 8893 #define F_FW_PORT_CMD_DCBXDIS V_FW_PORT_CMD_DCBXDIS(1U) 8894 8895 #define S_FW_PORT_CMD_APPLY 7 8896 #define M_FW_PORT_CMD_APPLY 0x1 8897 #define V_FW_PORT_CMD_APPLY(x) ((x) << S_FW_PORT_CMD_APPLY) 8898 #define G_FW_PORT_CMD_APPLY(x) \ 8899 (((x) >> S_FW_PORT_CMD_APPLY) & M_FW_PORT_CMD_APPLY) 8900 #define F_FW_PORT_CMD_APPLY V_FW_PORT_CMD_APPLY(1U) 8901 8902 #define S_FW_PORT_CMD_ALL_SYNCD 7 8903 #define M_FW_PORT_CMD_ALL_SYNCD 0x1 8904 #define V_FW_PORT_CMD_ALL_SYNCD(x) ((x) << S_FW_PORT_CMD_ALL_SYNCD) 8905 #define G_FW_PORT_CMD_ALL_SYNCD(x) \ 8906 (((x) >> S_FW_PORT_CMD_ALL_SYNCD) & M_FW_PORT_CMD_ALL_SYNCD) 8907 #define F_FW_PORT_CMD_ALL_SYNCD V_FW_PORT_CMD_ALL_SYNCD(1U) 8908 8909 #define S_FW_PORT_CMD_DCB_VERSION 12 8910 #define M_FW_PORT_CMD_DCB_VERSION 0x7 8911 #define V_FW_PORT_CMD_DCB_VERSION(x) ((x) << S_FW_PORT_CMD_DCB_VERSION) 8912 #define G_FW_PORT_CMD_DCB_VERSION(x) \ 8913 (((x) >> S_FW_PORT_CMD_DCB_VERSION) & M_FW_PORT_CMD_DCB_VERSION) 8914 8915 #define S_FW_PORT_CMD_PFC_STATE 8 8916 #define M_FW_PORT_CMD_PFC_STATE 0xf 8917 #define V_FW_PORT_CMD_PFC_STATE(x) ((x) << S_FW_PORT_CMD_PFC_STATE) 8918 #define G_FW_PORT_CMD_PFC_STATE(x) \ 8919 (((x) >> S_FW_PORT_CMD_PFC_STATE) & M_FW_PORT_CMD_PFC_STATE) 8920 8921 #define S_FW_PORT_CMD_ETS_STATE 4 8922 #define M_FW_PORT_CMD_ETS_STATE 0xf 8923 #define V_FW_PORT_CMD_ETS_STATE(x) ((x) << S_FW_PORT_CMD_ETS_STATE) 8924 #define G_FW_PORT_CMD_ETS_STATE(x) \ 8925 (((x) >> S_FW_PORT_CMD_ETS_STATE) & M_FW_PORT_CMD_ETS_STATE) 8926 8927 #define S_FW_PORT_CMD_APP_STATE 0 8928 #define M_FW_PORT_CMD_APP_STATE 0xf 8929 #define V_FW_PORT_CMD_APP_STATE(x) ((x) << S_FW_PORT_CMD_APP_STATE) 8930 #define G_FW_PORT_CMD_APP_STATE(x) \ 8931 (((x) >> S_FW_PORT_CMD_APP_STATE) & M_FW_PORT_CMD_APP_STATE) 8932 8933 #define S_FW_PORT_CMD_LSTATUS32 31 8934 #define M_FW_PORT_CMD_LSTATUS32 0x1 8935 #define V_FW_PORT_CMD_LSTATUS32(x) ((x) << S_FW_PORT_CMD_LSTATUS32) 8936 #define G_FW_PORT_CMD_LSTATUS32(x) \ 8937 (((x) >> S_FW_PORT_CMD_LSTATUS32) & M_FW_PORT_CMD_LSTATUS32) 8938 #define F_FW_PORT_CMD_LSTATUS32 V_FW_PORT_CMD_LSTATUS32(1U) 8939 8940 #define S_FW_PORT_CMD_LINKDNRC32 28 8941 #define M_FW_PORT_CMD_LINKDNRC32 0x7 8942 #define V_FW_PORT_CMD_LINKDNRC32(x) ((x) << S_FW_PORT_CMD_LINKDNRC32) 8943 #define G_FW_PORT_CMD_LINKDNRC32(x) \ 8944 (((x) >> S_FW_PORT_CMD_LINKDNRC32) & M_FW_PORT_CMD_LINKDNRC32) 8945 8946 #define S_FW_PORT_CMD_DCBXDIS32 27 8947 #define M_FW_PORT_CMD_DCBXDIS32 0x1 8948 #define V_FW_PORT_CMD_DCBXDIS32(x) ((x) << S_FW_PORT_CMD_DCBXDIS32) 8949 #define G_FW_PORT_CMD_DCBXDIS32(x) \ 8950 (((x) >> S_FW_PORT_CMD_DCBXDIS32) & M_FW_PORT_CMD_DCBXDIS32) 8951 #define F_FW_PORT_CMD_DCBXDIS32 V_FW_PORT_CMD_DCBXDIS32(1U) 8952 8953 #define S_FW_PORT_CMD_MDIOCAP32 26 8954 #define M_FW_PORT_CMD_MDIOCAP32 0x1 8955 #define V_FW_PORT_CMD_MDIOCAP32(x) ((x) << S_FW_PORT_CMD_MDIOCAP32) 8956 #define G_FW_PORT_CMD_MDIOCAP32(x) \ 8957 (((x) >> S_FW_PORT_CMD_MDIOCAP32) & M_FW_PORT_CMD_MDIOCAP32) 8958 #define F_FW_PORT_CMD_MDIOCAP32 V_FW_PORT_CMD_MDIOCAP32(1U) 8959 8960 #define S_FW_PORT_CMD_MDIOADDR32 21 8961 #define M_FW_PORT_CMD_MDIOADDR32 0x1f 8962 #define V_FW_PORT_CMD_MDIOADDR32(x) ((x) << S_FW_PORT_CMD_MDIOADDR32) 8963 #define G_FW_PORT_CMD_MDIOADDR32(x) \ 8964 (((x) >> S_FW_PORT_CMD_MDIOADDR32) & M_FW_PORT_CMD_MDIOADDR32) 8965 8966 #define S_FW_PORT_CMD_PORTTYPE32 13 8967 #define M_FW_PORT_CMD_PORTTYPE32 0xff 8968 #define V_FW_PORT_CMD_PORTTYPE32(x) ((x) << S_FW_PORT_CMD_PORTTYPE32) 8969 #define G_FW_PORT_CMD_PORTTYPE32(x) \ 8970 (((x) >> S_FW_PORT_CMD_PORTTYPE32) & M_FW_PORT_CMD_PORTTYPE32) 8971 8972 #define S_FW_PORT_CMD_MODTYPE32 8 8973 #define M_FW_PORT_CMD_MODTYPE32 0x1f 8974 #define V_FW_PORT_CMD_MODTYPE32(x) ((x) << S_FW_PORT_CMD_MODTYPE32) 8975 #define G_FW_PORT_CMD_MODTYPE32(x) \ 8976 (((x) >> S_FW_PORT_CMD_MODTYPE32) & M_FW_PORT_CMD_MODTYPE32) 8977 8978 #define S_FW_PORT_CMD_CBLLEN32 0 8979 #define M_FW_PORT_CMD_CBLLEN32 0xff 8980 #define V_FW_PORT_CMD_CBLLEN32(x) ((x) << S_FW_PORT_CMD_CBLLEN32) 8981 #define G_FW_PORT_CMD_CBLLEN32(x) \ 8982 (((x) >> S_FW_PORT_CMD_CBLLEN32) & M_FW_PORT_CMD_CBLLEN32) 8983 8984 #define S_FW_PORT_CMD_AUXLINFO32 24 8985 #define M_FW_PORT_CMD_AUXLINFO32 0xff 8986 #define V_FW_PORT_CMD_AUXLINFO32(x) ((x) << S_FW_PORT_CMD_AUXLINFO32) 8987 #define G_FW_PORT_CMD_AUXLINFO32(x) \ 8988 (((x) >> S_FW_PORT_CMD_AUXLINFO32) & M_FW_PORT_CMD_AUXLINFO32) 8989 8990 #define S_FW_PORT_AUXLINFO32_KX4 2 8991 #define M_FW_PORT_AUXLINFO32_KX4 0x1 8992 #define V_FW_PORT_AUXLINFO32_KX4(x) \ 8993 ((x) << S_FW_PORT_AUXLINFO32_KX4) 8994 #define G_FW_PORT_AUXLINFO32_KX4(x) \ 8995 (((x) >> S_FW_PORT_AUXLINFO32_KX4) & M_FW_PORT_AUXLINFO32_KX4) 8996 #define F_FW_PORT_AUXLINFO32_KX4 V_FW_PORT_AUXLINFO32_KX4(1U) 8997 8998 #define S_FW_PORT_AUXLINFO32_KR 1 8999 #define M_FW_PORT_AUXLINFO32_KR 0x1 9000 #define V_FW_PORT_AUXLINFO32_KR(x) \ 9001 ((x) << S_FW_PORT_AUXLINFO32_KR) 9002 #define G_FW_PORT_AUXLINFO32_KR(x) \ 9003 (((x) >> S_FW_PORT_AUXLINFO32_KR) & M_FW_PORT_AUXLINFO32_KR) 9004 #define F_FW_PORT_AUXLINFO32_KR V_FW_PORT_AUXLINFO32_KR(1U) 9005 9006 #define S_FW_PORT_CMD_MTU32 0 9007 #define M_FW_PORT_CMD_MTU32 0xffff 9008 #define V_FW_PORT_CMD_MTU32(x) ((x) << S_FW_PORT_CMD_MTU32) 9009 #define G_FW_PORT_CMD_MTU32(x) \ 9010 (((x) >> S_FW_PORT_CMD_MTU32) & M_FW_PORT_CMD_MTU32) 9011 9012 /* 9013 * These are configured into the VPD and hence tools that generate 9014 * VPD may use this enumeration. 9015 * extPHY #lanes T4_I2C extI2C BP_Eq BP_ANEG Speed 9016 * 9017 * REMEMBER: 9018 * Update the Common Code t4_hw.c:t4_get_port_type_description() 9019 * with any new Firmware Port Technology Types! 9020 */ 9021 enum fw_port_type { 9022 FW_PORT_TYPE_FIBER_XFI = 0, /* Y, 1, N, Y, N, N, 10G */ 9023 FW_PORT_TYPE_FIBER_XAUI = 1, /* Y, 4, N, Y, N, N, 10G */ 9024 FW_PORT_TYPE_BT_SGMII = 2, /* Y, 1, No, No, No, No, 1G/100M */ 9025 FW_PORT_TYPE_BT_XFI = 3, /* Y, 1, No, No, No, No, 10G/1G/100M */ 9026 FW_PORT_TYPE_BT_XAUI = 4, /* Y, 4, No, No, No, No, 10G/1G/100M */ 9027 FW_PORT_TYPE_KX4 = 5, /* No, 4, No, No, Yes, Yes, 10G */ 9028 FW_PORT_TYPE_CX4 = 6, /* No, 4, No, No, No, No, 10G */ 9029 FW_PORT_TYPE_KX = 7, /* No, 1, No, No, Yes, No, 1G */ 9030 FW_PORT_TYPE_KR = 8, /* No, 1, No, No, Yes, Yes, 10G BP AN */ 9031 FW_PORT_TYPE_SFP = 9, /* No, 1, Yes, No, No, No, 10G */ 9032 FW_PORT_TYPE_BP_AP = 10, /* No, 1, No, No, Yes, Yes, 10G, BP AN */ 9033 FW_PORT_TYPE_BP4_AP = 11, /* No, 4, No, No, Yes, Yes, 10G, BP AN */ 9034 FW_PORT_TYPE_QSFP_10G = 12, /* No, 1, Yes, No, No, No, 10G */ 9035 FW_PORT_TYPE_QSA = 13, /* No, 1, Yes, No, No, No, 10G */ 9036 FW_PORT_TYPE_QSFP = 14, /* No, 4, Yes, No, No, No, 40G */ 9037 FW_PORT_TYPE_BP40_BA = 15, /* No, 4, No, No, Yes, Yes, 40G/10G/1G, BP AN */ 9038 FW_PORT_TYPE_KR4_100G = 16, /* No, 4, 100G/40G/50G/25G/10G/1G, BP AN */ 9039 FW_PORT_TYPE_CR4_QSFP = 17, /* No, 4, 100G/40G/25G */ 9040 FW_PORT_TYPE_CR_QSFP = 18, /* No, 1, 25G, Spider cable */ 9041 FW_PORT_TYPE_CR2_QSFP = 19, /* No, 2, 50G, Spider cable */ 9042 FW_PORT_TYPE_SFP28 = 20, /* No, 1, 25G/10G/1G */ 9043 FW_PORT_TYPE_KR_SFP28 = 21, /* No, 1, 25G/10G/1G using Backplane */ 9044 FW_PORT_TYPE_KR_XLAUI = 22, /* No, 4, 40G/10G/1G, No AN*/ 9045 FW_PORT_TYPE_BARE_LINK_50G = 23, /* No, 1, 50G */ 9046 FW_PORT_TYPE_BARE_LINK_100G = 24, /* No, 2, 100G/50G */ 9047 FW_PORT_TYPE_BARE_LINK_200G = 25, /* No, 4, 200G/100G/50G */ 9048 FW_PORT_TYPE_SFP56 = 26, /* No, 1, 50G/25G */ 9049 FW_PORT_TYPE_QSFP56 = 27, /* No, 4, 200G/100G/50G/25G */ 9050 FW_PORT_TYPE_QSFP56_4_50G = 28, /* No, 1, 50G, Spider cable */ 9051 FW_PORT_TYPE_KR_50G = 29, /* No, 1, 50G/25G/10G/1G, BP AN */ 9052 FW_PORT_TYPE_KR2_100G = 30, /* No, 2, 100G/50G/25G/10G/1G, BP AN */ 9053 FW_PORT_TYPE_KR4_200G = 31, /* No, 4, 200G/100G/40G/50G/25G/10G/1G, BP AN */ 9054 FW_PORT_TYPE_QSFP56_2_50G = 32, /* No, 1, 50G, Spider cable */ 9055 FW_PORT_TYPE_OSFP = 33, /* No, 8, 400G/200G/100G/50G */ 9056 FW_PORT_TYPE_QSFPDD = 34, /* No, 8, 400G/200G/100G/50G */ 9057 FW_PORT_TYPE_OSFP_2_200G = 35, /* No, 4, 200G, Spider cable */ 9058 FW_PORT_TYPE_QSFPDD_2_200G = 36,/* No, 4, 200G, Spider cable */ 9059 FW_PORT_TYPE_KR8_400G = 37, /* No, 8, 400G/200G/100G/50G/40G/25G/10G/1G, BP AN */ 9060 FW_PORT_TYPE_QSFP56_2_100G = 38,/* No, 2, 100G, Spider cable */ 9061 FW_PORT_TYPE_QSFPDD_4_100G = 39,/* No, 2, 100G, Spider cable */ 9062 FW_PORT_TYPE_KR2_50G = 40, /* No, 1, 50G/25G/10G/1G, BP AN */ 9063 FW_PORT_TYPE_MAX, 9064 FW_PORT_TYPE_NONE = M_FW_PORT_CMD_PORTTYPE32 9065 }; 9066 9067 static inline bool 9068 is_bt(enum fw_port_type port_type) 9069 { 9070 return (port_type == FW_PORT_TYPE_BT_SGMII || 9071 port_type == FW_PORT_TYPE_BT_XFI || 9072 port_type == FW_PORT_TYPE_BT_XAUI); 9073 } 9074 9075 /* These are read from module's EEPROM and determined once the 9076 module is inserted. */ 9077 enum fw_port_module_type { 9078 FW_PORT_MOD_TYPE_NA = 0x0, 9079 FW_PORT_MOD_TYPE_LR = 0x1, 9080 FW_PORT_MOD_TYPE_SR = 0x2, 9081 FW_PORT_MOD_TYPE_ER = 0x3, 9082 FW_PORT_MOD_TYPE_TWINAX_PASSIVE = 0x4, 9083 FW_PORT_MOD_TYPE_TWINAX_ACTIVE = 0x5, 9084 FW_PORT_MOD_TYPE_LRM = 0x6, 9085 FW_PORT_MOD_TYPE_LR_SIMPLEX = 0x7, 9086 FW_PORT_MOD_TYPE_DR = 0x8, 9087 FW_PORT_MOD_TYPE_ERROR = M_FW_PORT_CMD_MODTYPE - 3, 9088 FW_PORT_MOD_TYPE_UNKNOWN = M_FW_PORT_CMD_MODTYPE - 2, 9089 FW_PORT_MOD_TYPE_NOTSUPPORTED = M_FW_PORT_CMD_MODTYPE - 1, 9090 FW_PORT_MOD_TYPE_NONE = M_FW_PORT_CMD_MODTYPE 9091 }; 9092 9093 /* used by FW and tools may use this to generate VPD */ 9094 enum fw_port_mod_sub_type { 9095 FW_PORT_MOD_SUB_TYPE_NA, 9096 FW_PORT_MOD_SUB_TYPE_MV88E114X=0x1, 9097 FW_PORT_MOD_SUB_TYPE_TN8022=0x2, 9098 FW_PORT_MOD_SUB_TYPE_AQ1202=0x3, 9099 FW_PORT_MOD_SUB_TYPE_88x3120=0x4, 9100 FW_PORT_MOD_SUB_TYPE_BCM84834=0x5, 9101 FW_PORT_MOD_SUB_TYPE_BCM5482=0x6, 9102 FW_PORT_MOD_SUB_TYPE_BCM84856=0x7, 9103 FW_PORT_MOD_SUB_TYPE_BT_VSC8634=0x8, 9104 9105 /* 9106 * The following will never been in the VPD. They are TWINAX cable 9107 * lengths decoded from SFP+ module i2c PROMs. These should almost 9108 * certainly go somewhere else ... 9109 */ 9110 FW_PORT_MOD_SUB_TYPE_TWINAX_1=0x9, 9111 FW_PORT_MOD_SUB_TYPE_TWINAX_3=0xA, 9112 FW_PORT_MOD_SUB_TYPE_TWINAX_5=0xB, 9113 FW_PORT_MOD_SUB_TYPE_TWINAX_7=0xC, 9114 }; 9115 9116 /* link down reason codes (3b) */ 9117 enum fw_port_link_dn_rc { 9118 FW_PORT_LINK_DN_RC_NONE, 9119 FW_PORT_LINK_DN_RC_REMFLT, /* Remote fault detected */ 9120 FW_PORT_LINK_DN_ANEG_F, /* Auto-negotiation fault */ 9121 FW_PORT_LINK_DN_RESERVED3, 9122 FW_PORT_LINK_DN_OVERHEAT, /* Port overheated */ 9123 FW_PORT_LINK_DN_UNKNOWN, /* Unable to determine reason */ 9124 FW_PORT_LINK_DN_RX_LOS, /* No RX signal detected */ 9125 FW_PORT_LINK_DN_RESERVED7 9126 }; 9127 enum fw_port_stats_tx_index { 9128 FW_STAT_TX_PORT_BYTES_IX = 0, 9129 FW_STAT_TX_PORT_FRAMES_IX, 9130 FW_STAT_TX_PORT_BCAST_IX, 9131 FW_STAT_TX_PORT_MCAST_IX, 9132 FW_STAT_TX_PORT_UCAST_IX, 9133 FW_STAT_TX_PORT_ERROR_IX, 9134 FW_STAT_TX_PORT_64B_IX, 9135 FW_STAT_TX_PORT_65B_127B_IX, 9136 FW_STAT_TX_PORT_128B_255B_IX, 9137 FW_STAT_TX_PORT_256B_511B_IX, 9138 FW_STAT_TX_PORT_512B_1023B_IX, 9139 FW_STAT_TX_PORT_1024B_1518B_IX, 9140 FW_STAT_TX_PORT_1519B_MAX_IX, 9141 FW_STAT_TX_PORT_DROP_IX, 9142 FW_STAT_TX_PORT_PAUSE_IX, 9143 FW_STAT_TX_PORT_PPP0_IX, 9144 FW_STAT_TX_PORT_PPP1_IX, 9145 FW_STAT_TX_PORT_PPP2_IX, 9146 FW_STAT_TX_PORT_PPP3_IX, 9147 FW_STAT_TX_PORT_PPP4_IX, 9148 FW_STAT_TX_PORT_PPP5_IX, 9149 FW_STAT_TX_PORT_PPP6_IX, 9150 FW_STAT_TX_PORT_PPP7_IX, 9151 FW_NUM_PORT_TX_STATS 9152 }; 9153 9154 enum fw_port_stat_rx_index { 9155 FW_STAT_RX_PORT_BYTES_IX = 0, 9156 FW_STAT_RX_PORT_FRAMES_IX, 9157 FW_STAT_RX_PORT_BCAST_IX, 9158 FW_STAT_RX_PORT_MCAST_IX, 9159 FW_STAT_RX_PORT_UCAST_IX, 9160 FW_STAT_RX_PORT_MTU_ERROR_IX, 9161 FW_STAT_RX_PORT_MTU_CRC_ERROR_IX, 9162 FW_STAT_RX_PORT_CRC_ERROR_IX, 9163 FW_STAT_RX_PORT_LEN_ERROR_IX, 9164 FW_STAT_RX_PORT_SYM_ERROR_IX, 9165 FW_STAT_RX_PORT_64B_IX, 9166 FW_STAT_RX_PORT_65B_127B_IX, 9167 FW_STAT_RX_PORT_128B_255B_IX, 9168 FW_STAT_RX_PORT_256B_511B_IX, 9169 FW_STAT_RX_PORT_512B_1023B_IX, 9170 FW_STAT_RX_PORT_1024B_1518B_IX, 9171 FW_STAT_RX_PORT_1519B_MAX_IX, 9172 FW_STAT_RX_PORT_PAUSE_IX, 9173 FW_STAT_RX_PORT_PPP0_IX, 9174 FW_STAT_RX_PORT_PPP1_IX, 9175 FW_STAT_RX_PORT_PPP2_IX, 9176 FW_STAT_RX_PORT_PPP3_IX, 9177 FW_STAT_RX_PORT_PPP4_IX, 9178 FW_STAT_RX_PORT_PPP5_IX, 9179 FW_STAT_RX_PORT_PPP6_IX, 9180 FW_STAT_RX_PORT_PPP7_IX, 9181 FW_STAT_RX_PORT_LESS_64B_IX, 9182 FW_STAT_RX_PORT_MAC_ERROR_IX, 9183 FW_NUM_PORT_RX_STATS 9184 }; 9185 /* port stats */ 9186 #define FW_NUM_PORT_STATS (FW_NUM_PORT_TX_STATS + \ 9187 FW_NUM_PORT_RX_STATS) 9188 9189 9190 struct fw_port_stats_cmd { 9191 __be32 op_to_portid; 9192 __be32 retval_len16; 9193 union fw_port_stats { 9194 struct fw_port_stats_ctl { 9195 __u8 nstats_bg_bm; 9196 __u8 tx_ix; 9197 __be16 r6; 9198 __be32 r7; 9199 __be64 stat0; 9200 __be64 stat1; 9201 __be64 stat2; 9202 __be64 stat3; 9203 __be64 stat4; 9204 __be64 stat5; 9205 } ctl; 9206 struct fw_port_stats_all { 9207 __be64 tx_bytes; 9208 __be64 tx_frames; 9209 __be64 tx_bcast; 9210 __be64 tx_mcast; 9211 __be64 tx_ucast; 9212 __be64 tx_error; 9213 __be64 tx_64b; 9214 __be64 tx_65b_127b; 9215 __be64 tx_128b_255b; 9216 __be64 tx_256b_511b; 9217 __be64 tx_512b_1023b; 9218 __be64 tx_1024b_1518b; 9219 __be64 tx_1519b_max; 9220 __be64 tx_drop; 9221 __be64 tx_pause; 9222 __be64 tx_ppp0; 9223 __be64 tx_ppp1; 9224 __be64 tx_ppp2; 9225 __be64 tx_ppp3; 9226 __be64 tx_ppp4; 9227 __be64 tx_ppp5; 9228 __be64 tx_ppp6; 9229 __be64 tx_ppp7; 9230 __be64 rx_bytes; 9231 __be64 rx_frames; 9232 __be64 rx_bcast; 9233 __be64 rx_mcast; 9234 __be64 rx_ucast; 9235 __be64 rx_mtu_error; 9236 __be64 rx_mtu_crc_error; 9237 __be64 rx_crc_error; 9238 __be64 rx_len_error; 9239 __be64 rx_sym_error; 9240 __be64 rx_64b; 9241 __be64 rx_65b_127b; 9242 __be64 rx_128b_255b; 9243 __be64 rx_256b_511b; 9244 __be64 rx_512b_1023b; 9245 __be64 rx_1024b_1518b; 9246 __be64 rx_1519b_max; 9247 __be64 rx_pause; 9248 __be64 rx_ppp0; 9249 __be64 rx_ppp1; 9250 __be64 rx_ppp2; 9251 __be64 rx_ppp3; 9252 __be64 rx_ppp4; 9253 __be64 rx_ppp5; 9254 __be64 rx_ppp6; 9255 __be64 rx_ppp7; 9256 __be64 rx_less_64b; 9257 __be64 rx_bg_drop; 9258 __be64 rx_bg_trunc; 9259 } all; 9260 } u; 9261 }; 9262 9263 #define S_FW_PORT_STATS_CMD_NSTATS 4 9264 #define M_FW_PORT_STATS_CMD_NSTATS 0x7 9265 #define V_FW_PORT_STATS_CMD_NSTATS(x) ((x) << S_FW_PORT_STATS_CMD_NSTATS) 9266 #define G_FW_PORT_STATS_CMD_NSTATS(x) \ 9267 (((x) >> S_FW_PORT_STATS_CMD_NSTATS) & M_FW_PORT_STATS_CMD_NSTATS) 9268 9269 #define S_FW_PORT_STATS_CMD_BG_BM 0 9270 #define M_FW_PORT_STATS_CMD_BG_BM 0x3 9271 #define V_FW_PORT_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_STATS_CMD_BG_BM) 9272 #define G_FW_PORT_STATS_CMD_BG_BM(x) \ 9273 (((x) >> S_FW_PORT_STATS_CMD_BG_BM) & M_FW_PORT_STATS_CMD_BG_BM) 9274 9275 #define S_FW_PORT_STATS_CMD_TX 7 9276 #define M_FW_PORT_STATS_CMD_TX 0x1 9277 #define V_FW_PORT_STATS_CMD_TX(x) ((x) << S_FW_PORT_STATS_CMD_TX) 9278 #define G_FW_PORT_STATS_CMD_TX(x) \ 9279 (((x) >> S_FW_PORT_STATS_CMD_TX) & M_FW_PORT_STATS_CMD_TX) 9280 #define F_FW_PORT_STATS_CMD_TX V_FW_PORT_STATS_CMD_TX(1U) 9281 9282 #define S_FW_PORT_STATS_CMD_IX 0 9283 #define M_FW_PORT_STATS_CMD_IX 0x3f 9284 #define V_FW_PORT_STATS_CMD_IX(x) ((x) << S_FW_PORT_STATS_CMD_IX) 9285 #define G_FW_PORT_STATS_CMD_IX(x) \ 9286 (((x) >> S_FW_PORT_STATS_CMD_IX) & M_FW_PORT_STATS_CMD_IX) 9287 9288 /* port loopback stats */ 9289 #define FW_NUM_LB_STATS 14 9290 enum fw_port_lb_stats_index { 9291 FW_STAT_LB_PORT_BYTES_IX, 9292 FW_STAT_LB_PORT_FRAMES_IX, 9293 FW_STAT_LB_PORT_BCAST_IX, 9294 FW_STAT_LB_PORT_MCAST_IX, 9295 FW_STAT_LB_PORT_UCAST_IX, 9296 FW_STAT_LB_PORT_ERROR_IX, 9297 FW_STAT_LB_PORT_64B_IX, 9298 FW_STAT_LB_PORT_65B_127B_IX, 9299 FW_STAT_LB_PORT_128B_255B_IX, 9300 FW_STAT_LB_PORT_256B_511B_IX, 9301 FW_STAT_LB_PORT_512B_1023B_IX, 9302 FW_STAT_LB_PORT_1024B_1518B_IX, 9303 FW_STAT_LB_PORT_1519B_MAX_IX, 9304 FW_STAT_LB_PORT_DROP_FRAMES_IX 9305 }; 9306 9307 struct fw_port_lb_stats_cmd { 9308 __be32 op_to_lbport; 9309 __be32 retval_len16; 9310 union fw_port_lb_stats { 9311 struct fw_port_lb_stats_ctl { 9312 __u8 nstats_bg_bm; 9313 __u8 ix_pkd; 9314 __be16 r6; 9315 __be32 r7; 9316 __be64 stat0; 9317 __be64 stat1; 9318 __be64 stat2; 9319 __be64 stat3; 9320 __be64 stat4; 9321 __be64 stat5; 9322 } ctl; 9323 struct fw_port_lb_stats_all { 9324 __be64 tx_bytes; 9325 __be64 tx_frames; 9326 __be64 tx_bcast; 9327 __be64 tx_mcast; 9328 __be64 tx_ucast; 9329 __be64 tx_error; 9330 __be64 tx_64b; 9331 __be64 tx_65b_127b; 9332 __be64 tx_128b_255b; 9333 __be64 tx_256b_511b; 9334 __be64 tx_512b_1023b; 9335 __be64 tx_1024b_1518b; 9336 __be64 tx_1519b_max; 9337 __be64 rx_lb_drop; 9338 __be64 rx_lb_trunc; 9339 } all; 9340 } u; 9341 }; 9342 9343 #define S_FW_PORT_LB_STATS_CMD_LBPORT 0 9344 #define M_FW_PORT_LB_STATS_CMD_LBPORT 0xf 9345 #define V_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 9346 ((x) << S_FW_PORT_LB_STATS_CMD_LBPORT) 9347 #define G_FW_PORT_LB_STATS_CMD_LBPORT(x) \ 9348 (((x) >> S_FW_PORT_LB_STATS_CMD_LBPORT) & M_FW_PORT_LB_STATS_CMD_LBPORT) 9349 9350 #define S_FW_PORT_LB_STATS_CMD_NSTATS 4 9351 #define M_FW_PORT_LB_STATS_CMD_NSTATS 0x7 9352 #define V_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 9353 ((x) << S_FW_PORT_LB_STATS_CMD_NSTATS) 9354 #define G_FW_PORT_LB_STATS_CMD_NSTATS(x) \ 9355 (((x) >> S_FW_PORT_LB_STATS_CMD_NSTATS) & M_FW_PORT_LB_STATS_CMD_NSTATS) 9356 9357 #define S_FW_PORT_LB_STATS_CMD_BG_BM 0 9358 #define M_FW_PORT_LB_STATS_CMD_BG_BM 0x3 9359 #define V_FW_PORT_LB_STATS_CMD_BG_BM(x) ((x) << S_FW_PORT_LB_STATS_CMD_BG_BM) 9360 #define G_FW_PORT_LB_STATS_CMD_BG_BM(x) \ 9361 (((x) >> S_FW_PORT_LB_STATS_CMD_BG_BM) & M_FW_PORT_LB_STATS_CMD_BG_BM) 9362 9363 #define S_FW_PORT_LB_STATS_CMD_IX 0 9364 #define M_FW_PORT_LB_STATS_CMD_IX 0xf 9365 #define V_FW_PORT_LB_STATS_CMD_IX(x) ((x) << S_FW_PORT_LB_STATS_CMD_IX) 9366 #define G_FW_PORT_LB_STATS_CMD_IX(x) \ 9367 (((x) >> S_FW_PORT_LB_STATS_CMD_IX) & M_FW_PORT_LB_STATS_CMD_IX) 9368 9369 /* Trace related defines */ 9370 #define FW_TRACE_CAPTURE_MAX_SINGLE_FLT_MODE 10240 9371 #define FW_TRACE_CAPTURE_MAX_MULTI_FLT_MODE 2560 9372 9373 struct fw_port_trace_cmd { 9374 __be32 op_to_portid; 9375 __be32 retval_len16; 9376 __be16 traceen_to_pciech; 9377 __be16 qnum; 9378 __be32 r5; 9379 }; 9380 9381 #define S_FW_PORT_TRACE_CMD_PORTID 0 9382 #define M_FW_PORT_TRACE_CMD_PORTID 0xf 9383 #define V_FW_PORT_TRACE_CMD_PORTID(x) ((x) << S_FW_PORT_TRACE_CMD_PORTID) 9384 #define G_FW_PORT_TRACE_CMD_PORTID(x) \ 9385 (((x) >> S_FW_PORT_TRACE_CMD_PORTID) & M_FW_PORT_TRACE_CMD_PORTID) 9386 9387 #define S_FW_PORT_TRACE_CMD_TRACEEN 15 9388 #define M_FW_PORT_TRACE_CMD_TRACEEN 0x1 9389 #define V_FW_PORT_TRACE_CMD_TRACEEN(x) ((x) << S_FW_PORT_TRACE_CMD_TRACEEN) 9390 #define G_FW_PORT_TRACE_CMD_TRACEEN(x) \ 9391 (((x) >> S_FW_PORT_TRACE_CMD_TRACEEN) & M_FW_PORT_TRACE_CMD_TRACEEN) 9392 #define F_FW_PORT_TRACE_CMD_TRACEEN V_FW_PORT_TRACE_CMD_TRACEEN(1U) 9393 9394 #define S_FW_PORT_TRACE_CMD_FLTMODE 14 9395 #define M_FW_PORT_TRACE_CMD_FLTMODE 0x1 9396 #define V_FW_PORT_TRACE_CMD_FLTMODE(x) ((x) << S_FW_PORT_TRACE_CMD_FLTMODE) 9397 #define G_FW_PORT_TRACE_CMD_FLTMODE(x) \ 9398 (((x) >> S_FW_PORT_TRACE_CMD_FLTMODE) & M_FW_PORT_TRACE_CMD_FLTMODE) 9399 #define F_FW_PORT_TRACE_CMD_FLTMODE V_FW_PORT_TRACE_CMD_FLTMODE(1U) 9400 9401 #define S_FW_PORT_TRACE_CMD_DUPLEN 13 9402 #define M_FW_PORT_TRACE_CMD_DUPLEN 0x1 9403 #define V_FW_PORT_TRACE_CMD_DUPLEN(x) ((x) << S_FW_PORT_TRACE_CMD_DUPLEN) 9404 #define G_FW_PORT_TRACE_CMD_DUPLEN(x) \ 9405 (((x) >> S_FW_PORT_TRACE_CMD_DUPLEN) & M_FW_PORT_TRACE_CMD_DUPLEN) 9406 #define F_FW_PORT_TRACE_CMD_DUPLEN V_FW_PORT_TRACE_CMD_DUPLEN(1U) 9407 9408 #define S_FW_PORT_TRACE_CMD_RUNTFLTSIZE 8 9409 #define M_FW_PORT_TRACE_CMD_RUNTFLTSIZE 0x1f 9410 #define V_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 9411 ((x) << S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 9412 #define G_FW_PORT_TRACE_CMD_RUNTFLTSIZE(x) \ 9413 (((x) >> S_FW_PORT_TRACE_CMD_RUNTFLTSIZE) & \ 9414 M_FW_PORT_TRACE_CMD_RUNTFLTSIZE) 9415 9416 #define S_FW_PORT_TRACE_CMD_PCIECH 6 9417 #define M_FW_PORT_TRACE_CMD_PCIECH 0x3 9418 #define V_FW_PORT_TRACE_CMD_PCIECH(x) ((x) << S_FW_PORT_TRACE_CMD_PCIECH) 9419 #define G_FW_PORT_TRACE_CMD_PCIECH(x) \ 9420 (((x) >> S_FW_PORT_TRACE_CMD_PCIECH) & M_FW_PORT_TRACE_CMD_PCIECH) 9421 9422 struct fw_port_trace_mmap_cmd { 9423 __be32 op_to_portid; 9424 __be32 retval_len16; 9425 __be32 fid_to_skipoffset; 9426 __be32 minpktsize_capturemax; 9427 __u8 map[224]; 9428 }; 9429 9430 #define S_FW_PORT_TRACE_MMAP_CMD_PORTID 0 9431 #define M_FW_PORT_TRACE_MMAP_CMD_PORTID 0xf 9432 #define V_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 9433 ((x) << S_FW_PORT_TRACE_MMAP_CMD_PORTID) 9434 #define G_FW_PORT_TRACE_MMAP_CMD_PORTID(x) \ 9435 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_PORTID) & \ 9436 M_FW_PORT_TRACE_MMAP_CMD_PORTID) 9437 9438 #define S_FW_PORT_TRACE_MMAP_CMD_FID 30 9439 #define M_FW_PORT_TRACE_MMAP_CMD_FID 0x3 9440 #define V_FW_PORT_TRACE_MMAP_CMD_FID(x) ((x) << S_FW_PORT_TRACE_MMAP_CMD_FID) 9441 #define G_FW_PORT_TRACE_MMAP_CMD_FID(x) \ 9442 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_FID) & M_FW_PORT_TRACE_MMAP_CMD_FID) 9443 9444 #define S_FW_PORT_TRACE_MMAP_CMD_MMAPEN 29 9445 #define M_FW_PORT_TRACE_MMAP_CMD_MMAPEN 0x1 9446 #define V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 9447 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 9448 #define G_FW_PORT_TRACE_MMAP_CMD_MMAPEN(x) \ 9449 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MMAPEN) & \ 9450 M_FW_PORT_TRACE_MMAP_CMD_MMAPEN) 9451 #define F_FW_PORT_TRACE_MMAP_CMD_MMAPEN V_FW_PORT_TRACE_MMAP_CMD_MMAPEN(1U) 9452 9453 #define S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 28 9454 #define M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN 0x1 9455 #define V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 9456 ((x) << S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 9457 #define G_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(x) \ 9458 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) & \ 9459 M_FW_PORT_TRACE_MMAP_CMD_DCMAPEN) 9460 #define F_FW_PORT_TRACE_MMAP_CMD_DCMAPEN V_FW_PORT_TRACE_MMAP_CMD_DCMAPEN(1U) 9461 9462 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 8 9463 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH 0x1f 9464 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 9465 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 9466 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH(x) \ 9467 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) & \ 9468 M_FW_PORT_TRACE_MMAP_CMD_SKIPLENGTH) 9469 9470 #define S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0 9471 #define M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET 0x1f 9472 #define V_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 9473 ((x) << S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 9474 #define G_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET(x) \ 9475 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) & \ 9476 M_FW_PORT_TRACE_MMAP_CMD_SKIPOFFSET) 9477 9478 #define S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 18 9479 #define M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE 0x3fff 9480 #define V_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 9481 ((x) << S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 9482 #define G_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE(x) \ 9483 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) & \ 9484 M_FW_PORT_TRACE_MMAP_CMD_MINPKTSIZE) 9485 9486 #define S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0 9487 #define M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX 0x3fff 9488 #define V_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 9489 ((x) << S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 9490 #define G_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX(x) \ 9491 (((x) >> S_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) & \ 9492 M_FW_PORT_TRACE_MMAP_CMD_CAPTUREMAX) 9493 9494 enum fw_ptp_subop { 9495 9496 /* none */ 9497 FW_PTP_SC_INIT_TIMER = 0x00, 9498 FW_PTP_SC_TX_TYPE = 0x01, 9499 9500 /* init */ 9501 FW_PTP_SC_RXTIME_STAMP = 0x08, 9502 FW_PTP_SC_RDRX_TYPE = 0x09, 9503 9504 /* ts */ 9505 FW_PTP_SC_ADJ_FREQ = 0x10, 9506 FW_PTP_SC_ADJ_TIME = 0x11, 9507 FW_PTP_SC_ADJ_FTIME = 0x12, 9508 FW_PTP_SC_WALL_CLOCK = 0x13, 9509 FW_PTP_SC_GET_TIME = 0x14, 9510 FW_PTP_SC_SET_TIME = 0x15, 9511 }; 9512 9513 struct fw_ptp_cmd { 9514 __be32 op_to_portid; 9515 __be32 retval_len16; 9516 union fw_ptp { 9517 struct fw_ptp_sc { 9518 __u8 sc; 9519 __u8 r3[7]; 9520 } scmd; 9521 struct fw_ptp_init { 9522 __u8 sc; 9523 __u8 txchan; 9524 __be16 absid; 9525 __be16 mode; 9526 __be16 ptp_rx_ctrl_pkd; 9527 } init; 9528 struct fw_ptp_ts { 9529 __u8 sc; 9530 __u8 sign; 9531 __be16 r3; 9532 __be32 ppb; 9533 __be64 tm; 9534 } ts; 9535 } u; 9536 __be64 r3; 9537 }; 9538 9539 #define S_FW_PTP_CMD_PORTID 0 9540 #define M_FW_PTP_CMD_PORTID 0xf 9541 #define V_FW_PTP_CMD_PORTID(x) ((x) << S_FW_PTP_CMD_PORTID) 9542 #define G_FW_PTP_CMD_PORTID(x) \ 9543 (((x) >> S_FW_PTP_CMD_PORTID) & M_FW_PTP_CMD_PORTID) 9544 9545 #define S_FW_PTP_CMD_PTP_RX_CTRL 15 9546 #define M_FW_PTP_CMD_PTP_RX_CTRL 0x1 9547 #define V_FW_PTP_CMD_PTP_RX_CTRL(x) ((x) << S_FW_PTP_CMD_PTP_RX_CTRL) 9548 #define G_FW_PTP_CMD_PTP_RX_CTRL(x) \ 9549 (((x) >> S_FW_PTP_CMD_PTP_RX_CTRL) & M_FW_PTP_CMD_PTP_RX_CTRL) 9550 #define F_FW_PTP_CMD_PTP_RX_CTRL V_FW_PTP_CMD_PTP_RX_CTRL(1U) 9551 9552 9553 struct fw_rss_ind_tbl_cmd { 9554 __be32 op_to_viid; 9555 __be32 retval_len16; 9556 __be16 niqid; 9557 __be16 startidx; 9558 __be32 r3; 9559 __be32 iq0_to_iq2; 9560 __be32 iq3_to_iq5; 9561 __be32 iq6_to_iq8; 9562 __be32 iq9_to_iq11; 9563 __be32 iq12_to_iq14; 9564 __be32 iq15_to_iq17; 9565 __be32 iq18_to_iq20; 9566 __be32 iq21_to_iq23; 9567 __be32 iq24_to_iq26; 9568 __be32 iq27_to_iq29; 9569 __be32 iq30_iq31; 9570 __be32 r15_lo; 9571 }; 9572 9573 #define S_FW_RSS_IND_TBL_CMD_VIID 0 9574 #define M_FW_RSS_IND_TBL_CMD_VIID 0xfff 9575 #define V_FW_RSS_IND_TBL_CMD_VIID(x) ((x) << S_FW_RSS_IND_TBL_CMD_VIID) 9576 #define G_FW_RSS_IND_TBL_CMD_VIID(x) \ 9577 (((x) >> S_FW_RSS_IND_TBL_CMD_VIID) & M_FW_RSS_IND_TBL_CMD_VIID) 9578 9579 #define S_FW_RSS_IND_TBL_CMD_IQ0 20 9580 #define M_FW_RSS_IND_TBL_CMD_IQ0 0x3ff 9581 #define V_FW_RSS_IND_TBL_CMD_IQ0(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ0) 9582 #define G_FW_RSS_IND_TBL_CMD_IQ0(x) \ 9583 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ0) & M_FW_RSS_IND_TBL_CMD_IQ0) 9584 9585 #define S_FW_RSS_IND_TBL_CMD_IQ1 10 9586 #define M_FW_RSS_IND_TBL_CMD_IQ1 0x3ff 9587 #define V_FW_RSS_IND_TBL_CMD_IQ1(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ1) 9588 #define G_FW_RSS_IND_TBL_CMD_IQ1(x) \ 9589 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ1) & M_FW_RSS_IND_TBL_CMD_IQ1) 9590 9591 #define S_FW_RSS_IND_TBL_CMD_IQ2 0 9592 #define M_FW_RSS_IND_TBL_CMD_IQ2 0x3ff 9593 #define V_FW_RSS_IND_TBL_CMD_IQ2(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ2) 9594 #define G_FW_RSS_IND_TBL_CMD_IQ2(x) \ 9595 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ2) & M_FW_RSS_IND_TBL_CMD_IQ2) 9596 9597 #define S_FW_RSS_IND_TBL_CMD_IQ3 20 9598 #define M_FW_RSS_IND_TBL_CMD_IQ3 0x3ff 9599 #define V_FW_RSS_IND_TBL_CMD_IQ3(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ3) 9600 #define G_FW_RSS_IND_TBL_CMD_IQ3(x) \ 9601 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ3) & M_FW_RSS_IND_TBL_CMD_IQ3) 9602 9603 #define S_FW_RSS_IND_TBL_CMD_IQ4 10 9604 #define M_FW_RSS_IND_TBL_CMD_IQ4 0x3ff 9605 #define V_FW_RSS_IND_TBL_CMD_IQ4(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ4) 9606 #define G_FW_RSS_IND_TBL_CMD_IQ4(x) \ 9607 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ4) & M_FW_RSS_IND_TBL_CMD_IQ4) 9608 9609 #define S_FW_RSS_IND_TBL_CMD_IQ5 0 9610 #define M_FW_RSS_IND_TBL_CMD_IQ5 0x3ff 9611 #define V_FW_RSS_IND_TBL_CMD_IQ5(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ5) 9612 #define G_FW_RSS_IND_TBL_CMD_IQ5(x) \ 9613 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ5) & M_FW_RSS_IND_TBL_CMD_IQ5) 9614 9615 #define S_FW_RSS_IND_TBL_CMD_IQ6 20 9616 #define M_FW_RSS_IND_TBL_CMD_IQ6 0x3ff 9617 #define V_FW_RSS_IND_TBL_CMD_IQ6(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ6) 9618 #define G_FW_RSS_IND_TBL_CMD_IQ6(x) \ 9619 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ6) & M_FW_RSS_IND_TBL_CMD_IQ6) 9620 9621 #define S_FW_RSS_IND_TBL_CMD_IQ7 10 9622 #define M_FW_RSS_IND_TBL_CMD_IQ7 0x3ff 9623 #define V_FW_RSS_IND_TBL_CMD_IQ7(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ7) 9624 #define G_FW_RSS_IND_TBL_CMD_IQ7(x) \ 9625 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ7) & M_FW_RSS_IND_TBL_CMD_IQ7) 9626 9627 #define S_FW_RSS_IND_TBL_CMD_IQ8 0 9628 #define M_FW_RSS_IND_TBL_CMD_IQ8 0x3ff 9629 #define V_FW_RSS_IND_TBL_CMD_IQ8(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ8) 9630 #define G_FW_RSS_IND_TBL_CMD_IQ8(x) \ 9631 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ8) & M_FW_RSS_IND_TBL_CMD_IQ8) 9632 9633 #define S_FW_RSS_IND_TBL_CMD_IQ9 20 9634 #define M_FW_RSS_IND_TBL_CMD_IQ9 0x3ff 9635 #define V_FW_RSS_IND_TBL_CMD_IQ9(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ9) 9636 #define G_FW_RSS_IND_TBL_CMD_IQ9(x) \ 9637 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ9) & M_FW_RSS_IND_TBL_CMD_IQ9) 9638 9639 #define S_FW_RSS_IND_TBL_CMD_IQ10 10 9640 #define M_FW_RSS_IND_TBL_CMD_IQ10 0x3ff 9641 #define V_FW_RSS_IND_TBL_CMD_IQ10(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ10) 9642 #define G_FW_RSS_IND_TBL_CMD_IQ10(x) \ 9643 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ10) & M_FW_RSS_IND_TBL_CMD_IQ10) 9644 9645 #define S_FW_RSS_IND_TBL_CMD_IQ11 0 9646 #define M_FW_RSS_IND_TBL_CMD_IQ11 0x3ff 9647 #define V_FW_RSS_IND_TBL_CMD_IQ11(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ11) 9648 #define G_FW_RSS_IND_TBL_CMD_IQ11(x) \ 9649 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ11) & M_FW_RSS_IND_TBL_CMD_IQ11) 9650 9651 #define S_FW_RSS_IND_TBL_CMD_IQ12 20 9652 #define M_FW_RSS_IND_TBL_CMD_IQ12 0x3ff 9653 #define V_FW_RSS_IND_TBL_CMD_IQ12(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ12) 9654 #define G_FW_RSS_IND_TBL_CMD_IQ12(x) \ 9655 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ12) & M_FW_RSS_IND_TBL_CMD_IQ12) 9656 9657 #define S_FW_RSS_IND_TBL_CMD_IQ13 10 9658 #define M_FW_RSS_IND_TBL_CMD_IQ13 0x3ff 9659 #define V_FW_RSS_IND_TBL_CMD_IQ13(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ13) 9660 #define G_FW_RSS_IND_TBL_CMD_IQ13(x) \ 9661 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ13) & M_FW_RSS_IND_TBL_CMD_IQ13) 9662 9663 #define S_FW_RSS_IND_TBL_CMD_IQ14 0 9664 #define M_FW_RSS_IND_TBL_CMD_IQ14 0x3ff 9665 #define V_FW_RSS_IND_TBL_CMD_IQ14(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ14) 9666 #define G_FW_RSS_IND_TBL_CMD_IQ14(x) \ 9667 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ14) & M_FW_RSS_IND_TBL_CMD_IQ14) 9668 9669 #define S_FW_RSS_IND_TBL_CMD_IQ15 20 9670 #define M_FW_RSS_IND_TBL_CMD_IQ15 0x3ff 9671 #define V_FW_RSS_IND_TBL_CMD_IQ15(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ15) 9672 #define G_FW_RSS_IND_TBL_CMD_IQ15(x) \ 9673 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ15) & M_FW_RSS_IND_TBL_CMD_IQ15) 9674 9675 #define S_FW_RSS_IND_TBL_CMD_IQ16 10 9676 #define M_FW_RSS_IND_TBL_CMD_IQ16 0x3ff 9677 #define V_FW_RSS_IND_TBL_CMD_IQ16(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ16) 9678 #define G_FW_RSS_IND_TBL_CMD_IQ16(x) \ 9679 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ16) & M_FW_RSS_IND_TBL_CMD_IQ16) 9680 9681 #define S_FW_RSS_IND_TBL_CMD_IQ17 0 9682 #define M_FW_RSS_IND_TBL_CMD_IQ17 0x3ff 9683 #define V_FW_RSS_IND_TBL_CMD_IQ17(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ17) 9684 #define G_FW_RSS_IND_TBL_CMD_IQ17(x) \ 9685 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ17) & M_FW_RSS_IND_TBL_CMD_IQ17) 9686 9687 #define S_FW_RSS_IND_TBL_CMD_IQ18 20 9688 #define M_FW_RSS_IND_TBL_CMD_IQ18 0x3ff 9689 #define V_FW_RSS_IND_TBL_CMD_IQ18(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ18) 9690 #define G_FW_RSS_IND_TBL_CMD_IQ18(x) \ 9691 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ18) & M_FW_RSS_IND_TBL_CMD_IQ18) 9692 9693 #define S_FW_RSS_IND_TBL_CMD_IQ19 10 9694 #define M_FW_RSS_IND_TBL_CMD_IQ19 0x3ff 9695 #define V_FW_RSS_IND_TBL_CMD_IQ19(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ19) 9696 #define G_FW_RSS_IND_TBL_CMD_IQ19(x) \ 9697 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ19) & M_FW_RSS_IND_TBL_CMD_IQ19) 9698 9699 #define S_FW_RSS_IND_TBL_CMD_IQ20 0 9700 #define M_FW_RSS_IND_TBL_CMD_IQ20 0x3ff 9701 #define V_FW_RSS_IND_TBL_CMD_IQ20(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ20) 9702 #define G_FW_RSS_IND_TBL_CMD_IQ20(x) \ 9703 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ20) & M_FW_RSS_IND_TBL_CMD_IQ20) 9704 9705 #define S_FW_RSS_IND_TBL_CMD_IQ21 20 9706 #define M_FW_RSS_IND_TBL_CMD_IQ21 0x3ff 9707 #define V_FW_RSS_IND_TBL_CMD_IQ21(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ21) 9708 #define G_FW_RSS_IND_TBL_CMD_IQ21(x) \ 9709 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ21) & M_FW_RSS_IND_TBL_CMD_IQ21) 9710 9711 #define S_FW_RSS_IND_TBL_CMD_IQ22 10 9712 #define M_FW_RSS_IND_TBL_CMD_IQ22 0x3ff 9713 #define V_FW_RSS_IND_TBL_CMD_IQ22(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ22) 9714 #define G_FW_RSS_IND_TBL_CMD_IQ22(x) \ 9715 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ22) & M_FW_RSS_IND_TBL_CMD_IQ22) 9716 9717 #define S_FW_RSS_IND_TBL_CMD_IQ23 0 9718 #define M_FW_RSS_IND_TBL_CMD_IQ23 0x3ff 9719 #define V_FW_RSS_IND_TBL_CMD_IQ23(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ23) 9720 #define G_FW_RSS_IND_TBL_CMD_IQ23(x) \ 9721 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ23) & M_FW_RSS_IND_TBL_CMD_IQ23) 9722 9723 #define S_FW_RSS_IND_TBL_CMD_IQ24 20 9724 #define M_FW_RSS_IND_TBL_CMD_IQ24 0x3ff 9725 #define V_FW_RSS_IND_TBL_CMD_IQ24(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ24) 9726 #define G_FW_RSS_IND_TBL_CMD_IQ24(x) \ 9727 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ24) & M_FW_RSS_IND_TBL_CMD_IQ24) 9728 9729 #define S_FW_RSS_IND_TBL_CMD_IQ25 10 9730 #define M_FW_RSS_IND_TBL_CMD_IQ25 0x3ff 9731 #define V_FW_RSS_IND_TBL_CMD_IQ25(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ25) 9732 #define G_FW_RSS_IND_TBL_CMD_IQ25(x) \ 9733 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ25) & M_FW_RSS_IND_TBL_CMD_IQ25) 9734 9735 #define S_FW_RSS_IND_TBL_CMD_IQ26 0 9736 #define M_FW_RSS_IND_TBL_CMD_IQ26 0x3ff 9737 #define V_FW_RSS_IND_TBL_CMD_IQ26(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ26) 9738 #define G_FW_RSS_IND_TBL_CMD_IQ26(x) \ 9739 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ26) & M_FW_RSS_IND_TBL_CMD_IQ26) 9740 9741 #define S_FW_RSS_IND_TBL_CMD_IQ27 20 9742 #define M_FW_RSS_IND_TBL_CMD_IQ27 0x3ff 9743 #define V_FW_RSS_IND_TBL_CMD_IQ27(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ27) 9744 #define G_FW_RSS_IND_TBL_CMD_IQ27(x) \ 9745 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ27) & M_FW_RSS_IND_TBL_CMD_IQ27) 9746 9747 #define S_FW_RSS_IND_TBL_CMD_IQ28 10 9748 #define M_FW_RSS_IND_TBL_CMD_IQ28 0x3ff 9749 #define V_FW_RSS_IND_TBL_CMD_IQ28(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ28) 9750 #define G_FW_RSS_IND_TBL_CMD_IQ28(x) \ 9751 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ28) & M_FW_RSS_IND_TBL_CMD_IQ28) 9752 9753 #define S_FW_RSS_IND_TBL_CMD_IQ29 0 9754 #define M_FW_RSS_IND_TBL_CMD_IQ29 0x3ff 9755 #define V_FW_RSS_IND_TBL_CMD_IQ29(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ29) 9756 #define G_FW_RSS_IND_TBL_CMD_IQ29(x) \ 9757 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ29) & M_FW_RSS_IND_TBL_CMD_IQ29) 9758 9759 #define S_FW_RSS_IND_TBL_CMD_IQ30 20 9760 #define M_FW_RSS_IND_TBL_CMD_IQ30 0x3ff 9761 #define V_FW_RSS_IND_TBL_CMD_IQ30(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ30) 9762 #define G_FW_RSS_IND_TBL_CMD_IQ30(x) \ 9763 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ30) & M_FW_RSS_IND_TBL_CMD_IQ30) 9764 9765 #define S_FW_RSS_IND_TBL_CMD_IQ31 10 9766 #define M_FW_RSS_IND_TBL_CMD_IQ31 0x3ff 9767 #define V_FW_RSS_IND_TBL_CMD_IQ31(x) ((x) << S_FW_RSS_IND_TBL_CMD_IQ31) 9768 #define G_FW_RSS_IND_TBL_CMD_IQ31(x) \ 9769 (((x) >> S_FW_RSS_IND_TBL_CMD_IQ31) & M_FW_RSS_IND_TBL_CMD_IQ31) 9770 9771 struct fw_rss_glb_config_cmd { 9772 __be32 op_to_write; 9773 __be32 retval_len16; 9774 union fw_rss_glb_config { 9775 struct fw_rss_glb_config_manual { 9776 __be32 mode_pkd; 9777 __be32 r3; 9778 __be64 r4; 9779 __be64 r5; 9780 } manual; 9781 struct fw_rss_glb_config_basicvirtual { 9782 __be32 mode_keymode; 9783 __be32 synmapen_to_hashtoeplitz; 9784 __be64 r8; 9785 __be64 r9; 9786 } basicvirtual; 9787 } u; 9788 }; 9789 9790 #define S_FW_RSS_GLB_CONFIG_CMD_MODE 28 9791 #define M_FW_RSS_GLB_CONFIG_CMD_MODE 0xf 9792 #define V_FW_RSS_GLB_CONFIG_CMD_MODE(x) ((x) << S_FW_RSS_GLB_CONFIG_CMD_MODE) 9793 #define G_FW_RSS_GLB_CONFIG_CMD_MODE(x) \ 9794 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_MODE) & M_FW_RSS_GLB_CONFIG_CMD_MODE) 9795 9796 #define FW_RSS_GLB_CONFIG_CMD_MODE_MANUAL 0 9797 #define FW_RSS_GLB_CONFIG_CMD_MODE_BASICVIRTUAL 1 9798 #define FW_RSS_GLB_CONFIG_CMD_MODE_MAX 1 9799 9800 #define S_FW_RSS_GLB_CONFIG_CMD_KEYMODE 26 9801 #define M_FW_RSS_GLB_CONFIG_CMD_KEYMODE 0x3 9802 #define V_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 9803 ((x) << S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 9804 #define G_FW_RSS_GLB_CONFIG_CMD_KEYMODE(x) \ 9805 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_KEYMODE) & \ 9806 M_FW_RSS_GLB_CONFIG_CMD_KEYMODE) 9807 9808 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBKEY 0 9809 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_GLBVF_KEY 1 9810 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_PFVF_KEY 2 9811 #define FW_RSS_GLB_CONFIG_CMD_KEYMODE_IDXVF_KEY 3 9812 9813 #define S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 8 9814 #define M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN 0x1 9815 #define V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 9816 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 9817 #define G_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(x) \ 9818 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) & \ 9819 M_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN) 9820 #define F_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN V_FW_RSS_GLB_CONFIG_CMD_SYNMAPEN(1U) 9821 9822 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 7 9823 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 0x1 9824 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 9825 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 9826 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(x) \ 9827 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) & \ 9828 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6) 9829 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6 \ 9830 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV6(1U) 9831 9832 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 6 9833 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 0x1 9834 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 9835 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 9836 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(x) \ 9837 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) & \ 9838 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6) 9839 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6 \ 9840 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV6(1U) 9841 9842 #define S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 5 9843 #define M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 0x1 9844 #define V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 9845 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 9846 #define G_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(x) \ 9847 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) & \ 9848 M_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4) 9849 #define F_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4 \ 9850 V_FW_RSS_GLB_CONFIG_CMD_SYN4TUPENIPV4(1U) 9851 9852 #define S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 4 9853 #define M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 0x1 9854 #define V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 9855 ((x) << S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 9856 #define G_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(x) \ 9857 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) & \ 9858 M_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4) 9859 #define F_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4 \ 9860 V_FW_RSS_GLB_CONFIG_CMD_SYN2TUPENIPV4(1U) 9861 9862 #define S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 3 9863 #define M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN 0x1 9864 #define V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 9865 ((x) << S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 9866 #define G_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(x) \ 9867 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) & \ 9868 M_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN) 9869 #define F_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN V_FW_RSS_GLB_CONFIG_CMD_OFDMAPEN(1U) 9870 9871 #define S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 2 9872 #define M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN 0x1 9873 #define V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 9874 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 9875 #define G_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(x) \ 9876 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) & \ 9877 M_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN) 9878 #define F_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN V_FW_RSS_GLB_CONFIG_CMD_TNLMAPEN(1U) 9879 9880 #define S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 1 9881 #define M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP 0x1 9882 #define V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 9883 ((x) << S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 9884 #define G_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(x) \ 9885 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) & \ 9886 M_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP) 9887 #define F_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP \ 9888 V_FW_RSS_GLB_CONFIG_CMD_TNLALLLKP(1U) 9889 9890 #define S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0 9891 #define M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ 0x1 9892 #define V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 9893 ((x) << S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 9894 #define G_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(x) \ 9895 (((x) >> S_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) & \ 9896 M_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ) 9897 #define F_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ \ 9898 V_FW_RSS_GLB_CONFIG_CMD_HASHTOEPLITZ(1U) 9899 9900 struct fw_rss_vi_config_cmd { 9901 __be32 op_to_viid; 9902 __be32 retval_len16; 9903 union fw_rss_vi_config { 9904 struct fw_rss_vi_config_manual { 9905 __be64 r3; 9906 __be64 r4; 9907 __be64 r5; 9908 } manual; 9909 struct fw_rss_vi_config_basicvirtual { 9910 __be32 r6; 9911 __be32 defaultq_to_udpen; 9912 __be32 secretkeyidx_pkd; 9913 __be32 secretkeyxor; 9914 __be64 r10; 9915 } basicvirtual; 9916 } u; 9917 }; 9918 9919 #define S_FW_RSS_VI_CONFIG_CMD_VIID 0 9920 #define M_FW_RSS_VI_CONFIG_CMD_VIID 0xfff 9921 #define V_FW_RSS_VI_CONFIG_CMD_VIID(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_VIID) 9922 #define G_FW_RSS_VI_CONFIG_CMD_VIID(x) \ 9923 (((x) >> S_FW_RSS_VI_CONFIG_CMD_VIID) & M_FW_RSS_VI_CONFIG_CMD_VIID) 9924 9925 #define S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 16 9926 #define M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ 0x3ff 9927 #define V_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 9928 ((x) << S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 9929 #define G_FW_RSS_VI_CONFIG_CMD_DEFAULTQ(x) \ 9930 (((x) >> S_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) & \ 9931 M_FW_RSS_VI_CONFIG_CMD_DEFAULTQ) 9932 9933 #define S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 4 9934 #define M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN 0x1 9935 #define V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 9936 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 9937 #define G_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(x) \ 9938 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) & \ 9939 M_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN) 9940 #define F_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN \ 9941 V_FW_RSS_VI_CONFIG_CMD_IP6FOURTUPEN(1U) 9942 9943 #define S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 3 9944 #define M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN 0x1 9945 #define V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 9946 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 9947 #define G_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(x) \ 9948 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) & \ 9949 M_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN) 9950 #define F_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN \ 9951 V_FW_RSS_VI_CONFIG_CMD_IP6TWOTUPEN(1U) 9952 9953 #define S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 2 9954 #define M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN 0x1 9955 #define V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 9956 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 9957 #define G_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(x) \ 9958 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) & \ 9959 M_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN) 9960 #define F_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN \ 9961 V_FW_RSS_VI_CONFIG_CMD_IP4FOURTUPEN(1U) 9962 9963 #define S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 1 9964 #define M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN 0x1 9965 #define V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 9966 ((x) << S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 9967 #define G_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(x) \ 9968 (((x) >> S_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) & \ 9969 M_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN) 9970 #define F_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN \ 9971 V_FW_RSS_VI_CONFIG_CMD_IP4TWOTUPEN(1U) 9972 9973 #define S_FW_RSS_VI_CONFIG_CMD_UDPEN 0 9974 #define M_FW_RSS_VI_CONFIG_CMD_UDPEN 0x1 9975 #define V_FW_RSS_VI_CONFIG_CMD_UDPEN(x) ((x) << S_FW_RSS_VI_CONFIG_CMD_UDPEN) 9976 #define G_FW_RSS_VI_CONFIG_CMD_UDPEN(x) \ 9977 (((x) >> S_FW_RSS_VI_CONFIG_CMD_UDPEN) & M_FW_RSS_VI_CONFIG_CMD_UDPEN) 9978 #define F_FW_RSS_VI_CONFIG_CMD_UDPEN V_FW_RSS_VI_CONFIG_CMD_UDPEN(1U) 9979 9980 #define S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0 9981 #define M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX 0xf 9982 #define V_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 9983 ((x) << S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 9984 #define G_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX(x) \ 9985 (((x) >> S_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) & \ 9986 M_FW_RSS_VI_CONFIG_CMD_SECRETKEYIDX) 9987 9988 enum fw_sched_sc { 9989 FW_SCHED_SC_CONFIG = 0, 9990 FW_SCHED_SC_PARAMS = 1, 9991 }; 9992 9993 enum fw_sched_type { 9994 FW_SCHED_TYPE_PKTSCHED = 0, 9995 FW_SCHED_TYPE_STREAMSCHED = 1, 9996 }; 9997 9998 enum fw_sched_params_level { 9999 FW_SCHED_PARAMS_LEVEL_CL_RL = 0, 10000 FW_SCHED_PARAMS_LEVEL_CL_WRR = 1, 10001 FW_SCHED_PARAMS_LEVEL_CH_RL = 2, 10002 }; 10003 10004 enum fw_sched_params_mode { 10005 FW_SCHED_PARAMS_MODE_CLASS = 0, 10006 FW_SCHED_PARAMS_MODE_FLOW = 1, 10007 }; 10008 10009 enum fw_sched_params_unit { 10010 FW_SCHED_PARAMS_UNIT_BITRATE = 0, 10011 FW_SCHED_PARAMS_UNIT_PKTRATE = 1, 10012 }; 10013 10014 enum fw_sched_params_rate { 10015 FW_SCHED_PARAMS_RATE_REL = 0, 10016 FW_SCHED_PARAMS_RATE_ABS = 1, 10017 }; 10018 10019 struct fw_sched_cmd { 10020 __be32 op_to_write; 10021 __be32 retval_len16; 10022 union fw_sched { 10023 struct fw_sched_config { 10024 __u8 sc; 10025 __u8 type; 10026 __u8 minmaxen; 10027 __u8 r3[5]; 10028 __u8 nclasses[4]; 10029 __be32 r4; 10030 } config; 10031 struct fw_sched_params { 10032 __u8 sc; 10033 __u8 type; 10034 __u8 level; 10035 __u8 mode; 10036 __u8 unit; 10037 __u8 rate; 10038 __u8 ch; 10039 __u8 cl; 10040 __be32 min; 10041 __be32 max; 10042 __be16 weight; 10043 __be16 pktsize; 10044 __be16 burstsize; 10045 __be16 r4; 10046 } params; 10047 } u; 10048 }; 10049 10050 /* 10051 * length of the formatting string 10052 */ 10053 #define FW_DEVLOG_FMT_LEN 192 10054 10055 /* 10056 * maximum number of the formatting string parameters 10057 */ 10058 #define FW_DEVLOG_FMT_PARAMS_NUM 8 10059 10060 /* 10061 * priority levels 10062 */ 10063 enum fw_devlog_level { 10064 FW_DEVLOG_LEVEL_EMERG = 0x0, 10065 FW_DEVLOG_LEVEL_CRIT = 0x1, 10066 FW_DEVLOG_LEVEL_ERR = 0x2, 10067 FW_DEVLOG_LEVEL_NOTICE = 0x3, 10068 FW_DEVLOG_LEVEL_INFO = 0x4, 10069 FW_DEVLOG_LEVEL_DEBUG = 0x5, 10070 FW_DEVLOG_LEVEL_MAX = 0x5, 10071 }; 10072 10073 /* 10074 * facilities that may send a log message 10075 */ 10076 enum fw_devlog_facility { 10077 FW_DEVLOG_FACILITY_CORE = 0x00, 10078 FW_DEVLOG_FACILITY_CF = 0x01, 10079 FW_DEVLOG_FACILITY_SCHED = 0x02, 10080 FW_DEVLOG_FACILITY_TIMER = 0x04, 10081 FW_DEVLOG_FACILITY_RES = 0x06, 10082 FW_DEVLOG_FACILITY_HW = 0x08, 10083 FW_DEVLOG_FACILITY_FLR = 0x10, 10084 FW_DEVLOG_FACILITY_DMAQ = 0x12, 10085 FW_DEVLOG_FACILITY_PHY = 0x14, 10086 FW_DEVLOG_FACILITY_MAC = 0x16, 10087 FW_DEVLOG_FACILITY_PORT = 0x18, 10088 FW_DEVLOG_FACILITY_VI = 0x1A, 10089 FW_DEVLOG_FACILITY_FILTER = 0x1C, 10090 FW_DEVLOG_FACILITY_ACL = 0x1E, 10091 FW_DEVLOG_FACILITY_TM = 0x20, 10092 FW_DEVLOG_FACILITY_QFC = 0x22, 10093 FW_DEVLOG_FACILITY_DCB = 0x24, 10094 FW_DEVLOG_FACILITY_ETH = 0x26, 10095 FW_DEVLOG_FACILITY_OFLD = 0x28, 10096 FW_DEVLOG_FACILITY_RI = 0x2A, 10097 FW_DEVLOG_FACILITY_ISCSI = 0x2C, 10098 FW_DEVLOG_FACILITY_FCOE = 0x2E, 10099 FW_DEVLOG_FACILITY_FOISCSI = 0x30, 10100 FW_DEVLOG_FACILITY_FOFCOE = 0x32, 10101 FW_DEVLOG_FACILITY_CHNET = 0x34, 10102 FW_DEVLOG_FACILITY_COISCSI = 0x36, 10103 FW_DEVLOG_FACILITY_MAX = 0x38, 10104 }; 10105 10106 /* 10107 * log message format 10108 */ 10109 struct fw_devlog_e { 10110 __be64 timestamp; 10111 __be32 seqno; 10112 __be16 reserved1; 10113 __u8 level; 10114 __u8 facility; 10115 __u8 fmt[FW_DEVLOG_FMT_LEN]; 10116 __be32 params[FW_DEVLOG_FMT_PARAMS_NUM]; 10117 __be32 reserved3[4]; 10118 }; 10119 10120 struct fw_devlog_cmd { 10121 __be32 op_to_write; 10122 __be32 retval_len16; 10123 __u8 level; 10124 __u8 r2[7]; 10125 __be32 memtype_devlog_memaddr16_devlog; 10126 __be32 memsize_devlog; 10127 __u8 num_devlog; 10128 __u8 r3[3]; 10129 __be32 r4; 10130 }; 10131 10132 #define S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 28 10133 #define M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG 0xf 10134 #define V_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 10135 ((x) << S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 10136 #define G_FW_DEVLOG_CMD_MEMTYPE_DEVLOG(x) \ 10137 (((x) >> S_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) & M_FW_DEVLOG_CMD_MEMTYPE_DEVLOG) 10138 10139 #define S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0 10140 #define M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG 0xfffffff 10141 #define V_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 10142 ((x) << S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 10143 #define G_FW_DEVLOG_CMD_MEMADDR16_DEVLOG(x) \ 10144 (((x) >> S_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) & \ 10145 M_FW_DEVLOG_CMD_MEMADDR16_DEVLOG) 10146 10147 enum fw_watchdog_actions { 10148 FW_WATCHDOG_ACTION_SHUTDOWN = 0, 10149 FW_WATCHDOG_ACTION_FLR = 1, 10150 FW_WATCHDOG_ACTION_BYPASS = 2, 10151 FW_WATCHDOG_ACTION_TMPCHK = 3, 10152 FW_WATCHDOG_ACTION_PAUSEOFF = 4, 10153 10154 FW_WATCHDOG_ACTION_MAX = 5, 10155 }; 10156 10157 #define FW_WATCHDOG_MAX_TIMEOUT_SECS 60 10158 10159 struct fw_watchdog_cmd { 10160 __be32 op_to_vfn; 10161 __be32 retval_len16; 10162 __be32 timeout; 10163 __be32 action; 10164 }; 10165 10166 #define S_FW_WATCHDOG_CMD_PFN 8 10167 #define M_FW_WATCHDOG_CMD_PFN 0x7 10168 #define V_FW_WATCHDOG_CMD_PFN(x) ((x) << S_FW_WATCHDOG_CMD_PFN) 10169 #define G_FW_WATCHDOG_CMD_PFN(x) \ 10170 (((x) >> S_FW_WATCHDOG_CMD_PFN) & M_FW_WATCHDOG_CMD_PFN) 10171 10172 #define S_FW_WATCHDOG_CMD_VFN 0 10173 #define M_FW_WATCHDOG_CMD_VFN 0xff 10174 #define V_FW_WATCHDOG_CMD_VFN(x) ((x) << S_FW_WATCHDOG_CMD_VFN) 10175 #define G_FW_WATCHDOG_CMD_VFN(x) \ 10176 (((x) >> S_FW_WATCHDOG_CMD_VFN) & M_FW_WATCHDOG_CMD_VFN) 10177 10178 struct fw_clip_cmd { 10179 __be32 op_to_write; 10180 __be32 alloc_to_len16; 10181 __be64 ip_hi; 10182 __be64 ip_lo; 10183 __be32 r4[2]; 10184 }; 10185 10186 #define S_FW_CLIP_CMD_ALLOC 31 10187 #define M_FW_CLIP_CMD_ALLOC 0x1 10188 #define V_FW_CLIP_CMD_ALLOC(x) ((x) << S_FW_CLIP_CMD_ALLOC) 10189 #define G_FW_CLIP_CMD_ALLOC(x) \ 10190 (((x) >> S_FW_CLIP_CMD_ALLOC) & M_FW_CLIP_CMD_ALLOC) 10191 #define F_FW_CLIP_CMD_ALLOC V_FW_CLIP_CMD_ALLOC(1U) 10192 10193 #define S_FW_CLIP_CMD_FREE 30 10194 #define M_FW_CLIP_CMD_FREE 0x1 10195 #define V_FW_CLIP_CMD_FREE(x) ((x) << S_FW_CLIP_CMD_FREE) 10196 #define G_FW_CLIP_CMD_FREE(x) \ 10197 (((x) >> S_FW_CLIP_CMD_FREE) & M_FW_CLIP_CMD_FREE) 10198 #define F_FW_CLIP_CMD_FREE V_FW_CLIP_CMD_FREE(1U) 10199 10200 #define S_FW_CLIP_CMD_INDEX 16 10201 #define M_FW_CLIP_CMD_INDEX 0x1fff 10202 #define V_FW_CLIP_CMD_INDEX(x) ((x) << S_FW_CLIP_CMD_INDEX) 10203 #define G_FW_CLIP_CMD_INDEX(x) \ 10204 (((x) >> S_FW_CLIP_CMD_INDEX) & M_FW_CLIP_CMD_INDEX) 10205 10206 struct fw_clip2_cmd { 10207 __be32 op_to_write; 10208 __be32 alloc_to_len16; 10209 __be64 ip_hi; 10210 __be64 ip_lo; 10211 __be64 ipm_hi; 10212 __be64 ipm_lo; 10213 __be32 r4[2]; 10214 }; 10215 10216 /****************************************************************************** 10217 * F O i S C S I C O M M A N D s 10218 **************************************/ 10219 10220 #define FW_CHNET_IFACE_ADDR_MAX 3 10221 10222 enum fw_chnet_iface_cmd_subop { 10223 FW_CHNET_IFACE_CMD_SUBOP_NOOP = 0, 10224 10225 FW_CHNET_IFACE_CMD_SUBOP_LINK_UP, 10226 FW_CHNET_IFACE_CMD_SUBOP_LINK_DOWN, 10227 10228 FW_CHNET_IFACE_CMD_SUBOP_MTU_SET, 10229 FW_CHNET_IFACE_CMD_SUBOP_MTU_GET, 10230 10231 FW_CHNET_IFACE_CMD_SUBOP_MAX, 10232 }; 10233 10234 struct fw_chnet_iface_cmd { 10235 __be32 op_to_portid; 10236 __be32 retval_len16; 10237 __u8 subop; 10238 __u8 r2[2]; 10239 __u8 flags; 10240 __be32 ifid_ifstate; 10241 __be16 mtu; 10242 __be16 vlanid; 10243 __be32 r3; 10244 __be16 r4; 10245 __u8 mac[6]; 10246 }; 10247 10248 #define S_FW_CHNET_IFACE_CMD_PORTID 0 10249 #define M_FW_CHNET_IFACE_CMD_PORTID 0xf 10250 #define V_FW_CHNET_IFACE_CMD_PORTID(x) ((x) << S_FW_CHNET_IFACE_CMD_PORTID) 10251 #define G_FW_CHNET_IFACE_CMD_PORTID(x) \ 10252 (((x) >> S_FW_CHNET_IFACE_CMD_PORTID) & M_FW_CHNET_IFACE_CMD_PORTID) 10253 10254 #define S_FW_CHNET_IFACE_CMD_RSS_IQID 16 10255 #define M_FW_CHNET_IFACE_CMD_RSS_IQID 0xffff 10256 #define V_FW_CHNET_IFACE_CMD_RSS_IQID(x) \ 10257 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID) 10258 #define G_FW_CHNET_IFACE_CMD_RSS_IQID(x) \ 10259 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID) & M_FW_CHNET_IFACE_CMD_RSS_IQID) 10260 10261 #define S_FW_CHNET_IFACE_CMD_RSS_IQID_F 0 10262 #define M_FW_CHNET_IFACE_CMD_RSS_IQID_F 0x1 10263 #define V_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \ 10264 ((x) << S_FW_CHNET_IFACE_CMD_RSS_IQID_F) 10265 #define G_FW_CHNET_IFACE_CMD_RSS_IQID_F(x) \ 10266 (((x) >> S_FW_CHNET_IFACE_CMD_RSS_IQID_F) & \ 10267 M_FW_CHNET_IFACE_CMD_RSS_IQID_F) 10268 #define F_FW_CHNET_IFACE_CMD_RSS_IQID_F V_FW_CHNET_IFACE_CMD_RSS_IQID_F(1U) 10269 10270 #define S_FW_CHNET_IFACE_CMD_IFID 8 10271 #define M_FW_CHNET_IFACE_CMD_IFID 0xffffff 10272 #define V_FW_CHNET_IFACE_CMD_IFID(x) ((x) << S_FW_CHNET_IFACE_CMD_IFID) 10273 #define G_FW_CHNET_IFACE_CMD_IFID(x) \ 10274 (((x) >> S_FW_CHNET_IFACE_CMD_IFID) & M_FW_CHNET_IFACE_CMD_IFID) 10275 10276 #define S_FW_CHNET_IFACE_CMD_IFSTATE 0 10277 #define M_FW_CHNET_IFACE_CMD_IFSTATE 0xff 10278 #define V_FW_CHNET_IFACE_CMD_IFSTATE(x) ((x) << S_FW_CHNET_IFACE_CMD_IFSTATE) 10279 #define G_FW_CHNET_IFACE_CMD_IFSTATE(x) \ 10280 (((x) >> S_FW_CHNET_IFACE_CMD_IFSTATE) & M_FW_CHNET_IFACE_CMD_IFSTATE) 10281 10282 struct fw_fcoe_res_info_cmd { 10283 __be32 op_to_read; 10284 __be32 retval_len16; 10285 __be16 e_d_tov; 10286 __be16 r_a_tov_seq; 10287 __be16 r_a_tov_els; 10288 __be16 r_r_tov; 10289 __be32 max_xchgs; 10290 __be32 max_ssns; 10291 __be32 used_xchgs; 10292 __be32 used_ssns; 10293 __be32 max_fcfs; 10294 __be32 max_vnps; 10295 __be32 used_fcfs; 10296 __be32 used_vnps; 10297 }; 10298 10299 struct fw_fcoe_link_cmd { 10300 __be32 op_to_portid; 10301 __be32 retval_len16; 10302 __be32 sub_opcode_fcfi; 10303 __u8 r3; 10304 __u8 lstatus; 10305 __be16 flags; 10306 __u8 r4; 10307 __u8 set_vlan; 10308 __be16 vlan_id; 10309 __be32 vnpi_pkd; 10310 __be16 r6; 10311 __u8 phy_mac[6]; 10312 __u8 vnport_wwnn[8]; 10313 __u8 vnport_wwpn[8]; 10314 }; 10315 10316 #define S_FW_FCOE_LINK_CMD_PORTID 0 10317 #define M_FW_FCOE_LINK_CMD_PORTID 0xf 10318 #define V_FW_FCOE_LINK_CMD_PORTID(x) ((x) << S_FW_FCOE_LINK_CMD_PORTID) 10319 #define G_FW_FCOE_LINK_CMD_PORTID(x) \ 10320 (((x) >> S_FW_FCOE_LINK_CMD_PORTID) & M_FW_FCOE_LINK_CMD_PORTID) 10321 10322 #define S_FW_FCOE_LINK_CMD_SUB_OPCODE 24 10323 #define M_FW_FCOE_LINK_CMD_SUB_OPCODE 0xff 10324 #define V_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 10325 ((x) << S_FW_FCOE_LINK_CMD_SUB_OPCODE) 10326 #define G_FW_FCOE_LINK_CMD_SUB_OPCODE(x) \ 10327 (((x) >> S_FW_FCOE_LINK_CMD_SUB_OPCODE) & M_FW_FCOE_LINK_CMD_SUB_OPCODE) 10328 10329 #define S_FW_FCOE_LINK_CMD_FCFI 0 10330 #define M_FW_FCOE_LINK_CMD_FCFI 0xffffff 10331 #define V_FW_FCOE_LINK_CMD_FCFI(x) ((x) << S_FW_FCOE_LINK_CMD_FCFI) 10332 #define G_FW_FCOE_LINK_CMD_FCFI(x) \ 10333 (((x) >> S_FW_FCOE_LINK_CMD_FCFI) & M_FW_FCOE_LINK_CMD_FCFI) 10334 10335 #define S_FW_FCOE_LINK_CMD_VNPI 0 10336 #define M_FW_FCOE_LINK_CMD_VNPI 0xfffff 10337 #define V_FW_FCOE_LINK_CMD_VNPI(x) ((x) << S_FW_FCOE_LINK_CMD_VNPI) 10338 #define G_FW_FCOE_LINK_CMD_VNPI(x) \ 10339 (((x) >> S_FW_FCOE_LINK_CMD_VNPI) & M_FW_FCOE_LINK_CMD_VNPI) 10340 10341 struct fw_fcoe_vnp_cmd { 10342 __be32 op_to_fcfi; 10343 __be32 alloc_to_len16; 10344 __be32 gen_wwn_to_vnpi; 10345 __be32 vf_id; 10346 __be16 iqid; 10347 __u8 vnport_mac[6]; 10348 __u8 vnport_wwnn[8]; 10349 __u8 vnport_wwpn[8]; 10350 __u8 cmn_srv_parms[16]; 10351 __u8 clsp_word_0_1[8]; 10352 }; 10353 10354 #define S_FW_FCOE_VNP_CMD_FCFI 0 10355 #define M_FW_FCOE_VNP_CMD_FCFI 0xfffff 10356 #define V_FW_FCOE_VNP_CMD_FCFI(x) ((x) << S_FW_FCOE_VNP_CMD_FCFI) 10357 #define G_FW_FCOE_VNP_CMD_FCFI(x) \ 10358 (((x) >> S_FW_FCOE_VNP_CMD_FCFI) & M_FW_FCOE_VNP_CMD_FCFI) 10359 10360 #define S_FW_FCOE_VNP_CMD_ALLOC 31 10361 #define M_FW_FCOE_VNP_CMD_ALLOC 0x1 10362 #define V_FW_FCOE_VNP_CMD_ALLOC(x) ((x) << S_FW_FCOE_VNP_CMD_ALLOC) 10363 #define G_FW_FCOE_VNP_CMD_ALLOC(x) \ 10364 (((x) >> S_FW_FCOE_VNP_CMD_ALLOC) & M_FW_FCOE_VNP_CMD_ALLOC) 10365 #define F_FW_FCOE_VNP_CMD_ALLOC V_FW_FCOE_VNP_CMD_ALLOC(1U) 10366 10367 #define S_FW_FCOE_VNP_CMD_FREE 30 10368 #define M_FW_FCOE_VNP_CMD_FREE 0x1 10369 #define V_FW_FCOE_VNP_CMD_FREE(x) ((x) << S_FW_FCOE_VNP_CMD_FREE) 10370 #define G_FW_FCOE_VNP_CMD_FREE(x) \ 10371 (((x) >> S_FW_FCOE_VNP_CMD_FREE) & M_FW_FCOE_VNP_CMD_FREE) 10372 #define F_FW_FCOE_VNP_CMD_FREE V_FW_FCOE_VNP_CMD_FREE(1U) 10373 10374 #define S_FW_FCOE_VNP_CMD_MODIFY 29 10375 #define M_FW_FCOE_VNP_CMD_MODIFY 0x1 10376 #define V_FW_FCOE_VNP_CMD_MODIFY(x) ((x) << S_FW_FCOE_VNP_CMD_MODIFY) 10377 #define G_FW_FCOE_VNP_CMD_MODIFY(x) \ 10378 (((x) >> S_FW_FCOE_VNP_CMD_MODIFY) & M_FW_FCOE_VNP_CMD_MODIFY) 10379 #define F_FW_FCOE_VNP_CMD_MODIFY V_FW_FCOE_VNP_CMD_MODIFY(1U) 10380 10381 #define S_FW_FCOE_VNP_CMD_GEN_WWN 22 10382 #define M_FW_FCOE_VNP_CMD_GEN_WWN 0x1 10383 #define V_FW_FCOE_VNP_CMD_GEN_WWN(x) ((x) << S_FW_FCOE_VNP_CMD_GEN_WWN) 10384 #define G_FW_FCOE_VNP_CMD_GEN_WWN(x) \ 10385 (((x) >> S_FW_FCOE_VNP_CMD_GEN_WWN) & M_FW_FCOE_VNP_CMD_GEN_WWN) 10386 #define F_FW_FCOE_VNP_CMD_GEN_WWN V_FW_FCOE_VNP_CMD_GEN_WWN(1U) 10387 10388 #define S_FW_FCOE_VNP_CMD_PERSIST 21 10389 #define M_FW_FCOE_VNP_CMD_PERSIST 0x1 10390 #define V_FW_FCOE_VNP_CMD_PERSIST(x) ((x) << S_FW_FCOE_VNP_CMD_PERSIST) 10391 #define G_FW_FCOE_VNP_CMD_PERSIST(x) \ 10392 (((x) >> S_FW_FCOE_VNP_CMD_PERSIST) & M_FW_FCOE_VNP_CMD_PERSIST) 10393 #define F_FW_FCOE_VNP_CMD_PERSIST V_FW_FCOE_VNP_CMD_PERSIST(1U) 10394 10395 #define S_FW_FCOE_VNP_CMD_VFID_EN 20 10396 #define M_FW_FCOE_VNP_CMD_VFID_EN 0x1 10397 #define V_FW_FCOE_VNP_CMD_VFID_EN(x) ((x) << S_FW_FCOE_VNP_CMD_VFID_EN) 10398 #define G_FW_FCOE_VNP_CMD_VFID_EN(x) \ 10399 (((x) >> S_FW_FCOE_VNP_CMD_VFID_EN) & M_FW_FCOE_VNP_CMD_VFID_EN) 10400 #define F_FW_FCOE_VNP_CMD_VFID_EN V_FW_FCOE_VNP_CMD_VFID_EN(1U) 10401 10402 #define S_FW_FCOE_VNP_CMD_VNPI 0 10403 #define M_FW_FCOE_VNP_CMD_VNPI 0xfffff 10404 #define V_FW_FCOE_VNP_CMD_VNPI(x) ((x) << S_FW_FCOE_VNP_CMD_VNPI) 10405 #define G_FW_FCOE_VNP_CMD_VNPI(x) \ 10406 (((x) >> S_FW_FCOE_VNP_CMD_VNPI) & M_FW_FCOE_VNP_CMD_VNPI) 10407 10408 struct fw_fcoe_sparams_cmd { 10409 __be32 op_to_portid; 10410 __be32 retval_len16; 10411 __u8 r3[7]; 10412 __u8 cos; 10413 __u8 lport_wwnn[8]; 10414 __u8 lport_wwpn[8]; 10415 __u8 cmn_srv_parms[16]; 10416 __u8 cls_srv_parms[16]; 10417 }; 10418 10419 #define S_FW_FCOE_SPARAMS_CMD_PORTID 0 10420 #define M_FW_FCOE_SPARAMS_CMD_PORTID 0xf 10421 #define V_FW_FCOE_SPARAMS_CMD_PORTID(x) ((x) << S_FW_FCOE_SPARAMS_CMD_PORTID) 10422 #define G_FW_FCOE_SPARAMS_CMD_PORTID(x) \ 10423 (((x) >> S_FW_FCOE_SPARAMS_CMD_PORTID) & M_FW_FCOE_SPARAMS_CMD_PORTID) 10424 10425 struct fw_fcoe_stats_cmd { 10426 __be32 op_to_flowid; 10427 __be32 free_to_len16; 10428 union fw_fcoe_stats { 10429 struct fw_fcoe_stats_ctl { 10430 __u8 nstats_port; 10431 __u8 port_valid_ix; 10432 __be16 r6; 10433 __be32 r7; 10434 __be64 stat0; 10435 __be64 stat1; 10436 __be64 stat2; 10437 __be64 stat3; 10438 __be64 stat4; 10439 __be64 stat5; 10440 } ctl; 10441 struct fw_fcoe_port_stats { 10442 __be64 tx_bcast_bytes; 10443 __be64 tx_bcast_frames; 10444 __be64 tx_mcast_bytes; 10445 __be64 tx_mcast_frames; 10446 __be64 tx_ucast_bytes; 10447 __be64 tx_ucast_frames; 10448 __be64 tx_drop_frames; 10449 __be64 tx_offload_bytes; 10450 __be64 tx_offload_frames; 10451 __be64 rx_bcast_bytes; 10452 __be64 rx_bcast_frames; 10453 __be64 rx_mcast_bytes; 10454 __be64 rx_mcast_frames; 10455 __be64 rx_ucast_bytes; 10456 __be64 rx_ucast_frames; 10457 __be64 rx_err_frames; 10458 } port_stats; 10459 struct fw_fcoe_fcf_stats { 10460 __be32 fip_tx_bytes; 10461 __be32 fip_tx_fr; 10462 __be64 fcf_ka; 10463 __be64 mcast_adv_rcvd; 10464 __be16 ucast_adv_rcvd; 10465 __be16 sol_sent; 10466 __be16 vlan_req; 10467 __be16 vlan_rpl; 10468 __be16 clr_vlink; 10469 __be16 link_down; 10470 __be16 link_up; 10471 __be16 logo; 10472 __be16 flogi_req; 10473 __be16 flogi_rpl; 10474 __be16 fdisc_req; 10475 __be16 fdisc_rpl; 10476 __be16 fka_prd_chg; 10477 __be16 fc_map_chg; 10478 __be16 vfid_chg; 10479 __u8 no_fka_req; 10480 __u8 no_vnp; 10481 } fcf_stats; 10482 struct fw_fcoe_pcb_stats { 10483 __be64 tx_bytes; 10484 __be64 tx_frames; 10485 __be64 rx_bytes; 10486 __be64 rx_frames; 10487 __be32 vnp_ka; 10488 __be32 unsol_els_rcvd; 10489 __be64 unsol_cmd_rcvd; 10490 __be16 implicit_logo; 10491 __be16 flogi_inv_sparm; 10492 __be16 fdisc_inv_sparm; 10493 __be16 flogi_rjt; 10494 __be16 fdisc_rjt; 10495 __be16 no_ssn; 10496 __be16 mac_flt_fail; 10497 __be16 inv_fr_rcvd; 10498 } pcb_stats; 10499 struct fw_fcoe_scb_stats { 10500 __be64 tx_bytes; 10501 __be64 tx_frames; 10502 __be64 rx_bytes; 10503 __be64 rx_frames; 10504 __be32 host_abrt_req; 10505 __be32 adap_auto_abrt; 10506 __be32 adap_abrt_rsp; 10507 __be32 host_ios_req; 10508 __be16 ssn_offl_ios; 10509 __be16 ssn_not_rdy_ios; 10510 __u8 rx_data_ddp_err; 10511 __u8 ddp_flt_set_err; 10512 __be16 rx_data_fr_err; 10513 __u8 bad_st_abrt_req; 10514 __u8 no_io_abrt_req; 10515 __u8 abort_tmo; 10516 __u8 abort_tmo_2; 10517 __be32 abort_req; 10518 __u8 no_ppod_res_tmo; 10519 __u8 bp_tmo; 10520 __u8 adap_auto_cls; 10521 __u8 no_io_cls_req; 10522 __be32 host_cls_req; 10523 __be64 unsol_cmd_rcvd; 10524 __be32 plogi_req_rcvd; 10525 __be32 prli_req_rcvd; 10526 __be16 logo_req_rcvd; 10527 __be16 prlo_req_rcvd; 10528 __be16 plogi_rjt_rcvd; 10529 __be16 prli_rjt_rcvd; 10530 __be32 adisc_req_rcvd; 10531 __be32 rscn_rcvd; 10532 __be32 rrq_req_rcvd; 10533 __be32 unsol_els_rcvd; 10534 __u8 adisc_rjt_rcvd; 10535 __u8 scr_rjt; 10536 __u8 ct_rjt; 10537 __u8 inval_bls_rcvd; 10538 __be32 ba_rjt_rcvd; 10539 } scb_stats; 10540 } u; 10541 }; 10542 10543 #define S_FW_FCOE_STATS_CMD_FLOWID 0 10544 #define M_FW_FCOE_STATS_CMD_FLOWID 0xfffff 10545 #define V_FW_FCOE_STATS_CMD_FLOWID(x) ((x) << S_FW_FCOE_STATS_CMD_FLOWID) 10546 #define G_FW_FCOE_STATS_CMD_FLOWID(x) \ 10547 (((x) >> S_FW_FCOE_STATS_CMD_FLOWID) & M_FW_FCOE_STATS_CMD_FLOWID) 10548 10549 #define S_FW_FCOE_STATS_CMD_FREE 30 10550 #define M_FW_FCOE_STATS_CMD_FREE 0x1 10551 #define V_FW_FCOE_STATS_CMD_FREE(x) ((x) << S_FW_FCOE_STATS_CMD_FREE) 10552 #define G_FW_FCOE_STATS_CMD_FREE(x) \ 10553 (((x) >> S_FW_FCOE_STATS_CMD_FREE) & M_FW_FCOE_STATS_CMD_FREE) 10554 #define F_FW_FCOE_STATS_CMD_FREE V_FW_FCOE_STATS_CMD_FREE(1U) 10555 10556 #define S_FW_FCOE_STATS_CMD_NSTATS 4 10557 #define M_FW_FCOE_STATS_CMD_NSTATS 0x7 10558 #define V_FW_FCOE_STATS_CMD_NSTATS(x) ((x) << S_FW_FCOE_STATS_CMD_NSTATS) 10559 #define G_FW_FCOE_STATS_CMD_NSTATS(x) \ 10560 (((x) >> S_FW_FCOE_STATS_CMD_NSTATS) & M_FW_FCOE_STATS_CMD_NSTATS) 10561 10562 #define S_FW_FCOE_STATS_CMD_PORT 0 10563 #define M_FW_FCOE_STATS_CMD_PORT 0x3 10564 #define V_FW_FCOE_STATS_CMD_PORT(x) ((x) << S_FW_FCOE_STATS_CMD_PORT) 10565 #define G_FW_FCOE_STATS_CMD_PORT(x) \ 10566 (((x) >> S_FW_FCOE_STATS_CMD_PORT) & M_FW_FCOE_STATS_CMD_PORT) 10567 10568 #define S_FW_FCOE_STATS_CMD_PORT_VALID 7 10569 #define M_FW_FCOE_STATS_CMD_PORT_VALID 0x1 10570 #define V_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 10571 ((x) << S_FW_FCOE_STATS_CMD_PORT_VALID) 10572 #define G_FW_FCOE_STATS_CMD_PORT_VALID(x) \ 10573 (((x) >> S_FW_FCOE_STATS_CMD_PORT_VALID) & M_FW_FCOE_STATS_CMD_PORT_VALID) 10574 #define F_FW_FCOE_STATS_CMD_PORT_VALID V_FW_FCOE_STATS_CMD_PORT_VALID(1U) 10575 10576 #define S_FW_FCOE_STATS_CMD_IX 0 10577 #define M_FW_FCOE_STATS_CMD_IX 0x3f 10578 #define V_FW_FCOE_STATS_CMD_IX(x) ((x) << S_FW_FCOE_STATS_CMD_IX) 10579 #define G_FW_FCOE_STATS_CMD_IX(x) \ 10580 (((x) >> S_FW_FCOE_STATS_CMD_IX) & M_FW_FCOE_STATS_CMD_IX) 10581 10582 struct fw_fcoe_fcf_cmd { 10583 __be32 op_to_fcfi; 10584 __be32 retval_len16; 10585 __be16 priority_pkd; 10586 __u8 mac[6]; 10587 __u8 name_id[8]; 10588 __u8 fabric[8]; 10589 __be16 vf_id; 10590 __be16 max_fcoe_size; 10591 __u8 vlan_id; 10592 __u8 fc_map[3]; 10593 __be32 fka_adv; 10594 __be32 r6; 10595 __u8 r7_hi; 10596 __u8 fpma_to_portid; 10597 __u8 spma_mac[6]; 10598 __be64 r8; 10599 }; 10600 10601 #define S_FW_FCOE_FCF_CMD_FCFI 0 10602 #define M_FW_FCOE_FCF_CMD_FCFI 0xfffff 10603 #define V_FW_FCOE_FCF_CMD_FCFI(x) ((x) << S_FW_FCOE_FCF_CMD_FCFI) 10604 #define G_FW_FCOE_FCF_CMD_FCFI(x) \ 10605 (((x) >> S_FW_FCOE_FCF_CMD_FCFI) & M_FW_FCOE_FCF_CMD_FCFI) 10606 10607 #define S_FW_FCOE_FCF_CMD_PRIORITY 0 10608 #define M_FW_FCOE_FCF_CMD_PRIORITY 0xff 10609 #define V_FW_FCOE_FCF_CMD_PRIORITY(x) ((x) << S_FW_FCOE_FCF_CMD_PRIORITY) 10610 #define G_FW_FCOE_FCF_CMD_PRIORITY(x) \ 10611 (((x) >> S_FW_FCOE_FCF_CMD_PRIORITY) & M_FW_FCOE_FCF_CMD_PRIORITY) 10612 10613 #define S_FW_FCOE_FCF_CMD_FPMA 6 10614 #define M_FW_FCOE_FCF_CMD_FPMA 0x1 10615 #define V_FW_FCOE_FCF_CMD_FPMA(x) ((x) << S_FW_FCOE_FCF_CMD_FPMA) 10616 #define G_FW_FCOE_FCF_CMD_FPMA(x) \ 10617 (((x) >> S_FW_FCOE_FCF_CMD_FPMA) & M_FW_FCOE_FCF_CMD_FPMA) 10618 #define F_FW_FCOE_FCF_CMD_FPMA V_FW_FCOE_FCF_CMD_FPMA(1U) 10619 10620 #define S_FW_FCOE_FCF_CMD_SPMA 5 10621 #define M_FW_FCOE_FCF_CMD_SPMA 0x1 10622 #define V_FW_FCOE_FCF_CMD_SPMA(x) ((x) << S_FW_FCOE_FCF_CMD_SPMA) 10623 #define G_FW_FCOE_FCF_CMD_SPMA(x) \ 10624 (((x) >> S_FW_FCOE_FCF_CMD_SPMA) & M_FW_FCOE_FCF_CMD_SPMA) 10625 #define F_FW_FCOE_FCF_CMD_SPMA V_FW_FCOE_FCF_CMD_SPMA(1U) 10626 10627 #define S_FW_FCOE_FCF_CMD_LOGIN 4 10628 #define M_FW_FCOE_FCF_CMD_LOGIN 0x1 10629 #define V_FW_FCOE_FCF_CMD_LOGIN(x) ((x) << S_FW_FCOE_FCF_CMD_LOGIN) 10630 #define G_FW_FCOE_FCF_CMD_LOGIN(x) \ 10631 (((x) >> S_FW_FCOE_FCF_CMD_LOGIN) & M_FW_FCOE_FCF_CMD_LOGIN) 10632 #define F_FW_FCOE_FCF_CMD_LOGIN V_FW_FCOE_FCF_CMD_LOGIN(1U) 10633 10634 #define S_FW_FCOE_FCF_CMD_PORTID 0 10635 #define M_FW_FCOE_FCF_CMD_PORTID 0xf 10636 #define V_FW_FCOE_FCF_CMD_PORTID(x) ((x) << S_FW_FCOE_FCF_CMD_PORTID) 10637 #define G_FW_FCOE_FCF_CMD_PORTID(x) \ 10638 (((x) >> S_FW_FCOE_FCF_CMD_PORTID) & M_FW_FCOE_FCF_CMD_PORTID) 10639 10640 /****************************************************************************** 10641 * E R R O R a n d D E B U G C O M M A N D s 10642 ******************************************************/ 10643 10644 enum fw_error_type { 10645 FW_ERROR_TYPE_EXCEPTION = 0x0, 10646 FW_ERROR_TYPE_HWMODULE = 0x1, 10647 FW_ERROR_TYPE_WR = 0x2, 10648 FW_ERROR_TYPE_ACL = 0x3, 10649 }; 10650 10651 enum fw_dcb_ieee_locations { 10652 FW_IEEE_LOC_LOCAL, 10653 FW_IEEE_LOC_PEER, 10654 FW_IEEE_LOC_OPERATIONAL, 10655 }; 10656 10657 struct fw_dcb_ieee_cmd { 10658 __be32 op_to_location; 10659 __be32 changed_to_len16; 10660 union fw_dcbx_stats { 10661 struct fw_dcbx_pfc_stats_ieee { 10662 __be32 pfc_mbc_pkd; 10663 __be32 pfc_willing_to_pfc_en; 10664 } dcbx_pfc_stats; 10665 struct fw_dcbx_ets_stats_ieee { 10666 __be32 cbs_to_ets_max_tc; 10667 __be32 pg_table; 10668 __u8 pg_percent[8]; 10669 __u8 tsa[8]; 10670 } dcbx_ets_stats; 10671 struct fw_dcbx_app_stats_ieee { 10672 __be32 num_apps_pkd; 10673 __be32 r6; 10674 __be32 app[4]; 10675 } dcbx_app_stats; 10676 struct fw_dcbx_control { 10677 __be32 multi_peer_invalidated; 10678 __u8 version; 10679 __u8 r6[3]; 10680 } dcbx_control; 10681 } u; 10682 }; 10683 10684 #define S_FW_DCB_IEEE_CMD_PORT 8 10685 #define M_FW_DCB_IEEE_CMD_PORT 0x7 10686 #define V_FW_DCB_IEEE_CMD_PORT(x) ((x) << S_FW_DCB_IEEE_CMD_PORT) 10687 #define G_FW_DCB_IEEE_CMD_PORT(x) \ 10688 (((x) >> S_FW_DCB_IEEE_CMD_PORT) & M_FW_DCB_IEEE_CMD_PORT) 10689 10690 #define S_FW_DCB_IEEE_CMD_FEATURE 2 10691 #define M_FW_DCB_IEEE_CMD_FEATURE 0x7 10692 #define V_FW_DCB_IEEE_CMD_FEATURE(x) ((x) << S_FW_DCB_IEEE_CMD_FEATURE) 10693 #define G_FW_DCB_IEEE_CMD_FEATURE(x) \ 10694 (((x) >> S_FW_DCB_IEEE_CMD_FEATURE) & M_FW_DCB_IEEE_CMD_FEATURE) 10695 10696 #define S_FW_DCB_IEEE_CMD_LOCATION 0 10697 #define M_FW_DCB_IEEE_CMD_LOCATION 0x3 10698 #define V_FW_DCB_IEEE_CMD_LOCATION(x) ((x) << S_FW_DCB_IEEE_CMD_LOCATION) 10699 #define G_FW_DCB_IEEE_CMD_LOCATION(x) \ 10700 (((x) >> S_FW_DCB_IEEE_CMD_LOCATION) & M_FW_DCB_IEEE_CMD_LOCATION) 10701 10702 #define S_FW_DCB_IEEE_CMD_CHANGED 20 10703 #define M_FW_DCB_IEEE_CMD_CHANGED 0x1 10704 #define V_FW_DCB_IEEE_CMD_CHANGED(x) ((x) << S_FW_DCB_IEEE_CMD_CHANGED) 10705 #define G_FW_DCB_IEEE_CMD_CHANGED(x) \ 10706 (((x) >> S_FW_DCB_IEEE_CMD_CHANGED) & M_FW_DCB_IEEE_CMD_CHANGED) 10707 #define F_FW_DCB_IEEE_CMD_CHANGED V_FW_DCB_IEEE_CMD_CHANGED(1U) 10708 10709 #define S_FW_DCB_IEEE_CMD_RECEIVED 19 10710 #define M_FW_DCB_IEEE_CMD_RECEIVED 0x1 10711 #define V_FW_DCB_IEEE_CMD_RECEIVED(x) ((x) << S_FW_DCB_IEEE_CMD_RECEIVED) 10712 #define G_FW_DCB_IEEE_CMD_RECEIVED(x) \ 10713 (((x) >> S_FW_DCB_IEEE_CMD_RECEIVED) & M_FW_DCB_IEEE_CMD_RECEIVED) 10714 #define F_FW_DCB_IEEE_CMD_RECEIVED V_FW_DCB_IEEE_CMD_RECEIVED(1U) 10715 10716 #define S_FW_DCB_IEEE_CMD_APPLY 18 10717 #define M_FW_DCB_IEEE_CMD_APPLY 0x1 10718 #define V_FW_DCB_IEEE_CMD_APPLY(x) ((x) << S_FW_DCB_IEEE_CMD_APPLY) 10719 #define G_FW_DCB_IEEE_CMD_APPLY(x) \ 10720 (((x) >> S_FW_DCB_IEEE_CMD_APPLY) & M_FW_DCB_IEEE_CMD_APPLY) 10721 #define F_FW_DCB_IEEE_CMD_APPLY V_FW_DCB_IEEE_CMD_APPLY(1U) 10722 10723 #define S_FW_DCB_IEEE_CMD_DISABLED 17 10724 #define M_FW_DCB_IEEE_CMD_DISABLED 0x1 10725 #define V_FW_DCB_IEEE_CMD_DISABLED(x) ((x) << S_FW_DCB_IEEE_CMD_DISABLED) 10726 #define G_FW_DCB_IEEE_CMD_DISABLED(x) \ 10727 (((x) >> S_FW_DCB_IEEE_CMD_DISABLED) & M_FW_DCB_IEEE_CMD_DISABLED) 10728 #define F_FW_DCB_IEEE_CMD_DISABLED V_FW_DCB_IEEE_CMD_DISABLED(1U) 10729 10730 #define S_FW_DCB_IEEE_CMD_MORE 16 10731 #define M_FW_DCB_IEEE_CMD_MORE 0x1 10732 #define V_FW_DCB_IEEE_CMD_MORE(x) ((x) << S_FW_DCB_IEEE_CMD_MORE) 10733 #define G_FW_DCB_IEEE_CMD_MORE(x) \ 10734 (((x) >> S_FW_DCB_IEEE_CMD_MORE) & M_FW_DCB_IEEE_CMD_MORE) 10735 #define F_FW_DCB_IEEE_CMD_MORE V_FW_DCB_IEEE_CMD_MORE(1U) 10736 10737 #define S_FW_DCB_IEEE_CMD_PFC_MBC 0 10738 #define M_FW_DCB_IEEE_CMD_PFC_MBC 0x1 10739 #define V_FW_DCB_IEEE_CMD_PFC_MBC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MBC) 10740 #define G_FW_DCB_IEEE_CMD_PFC_MBC(x) \ 10741 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MBC) & M_FW_DCB_IEEE_CMD_PFC_MBC) 10742 #define F_FW_DCB_IEEE_CMD_PFC_MBC V_FW_DCB_IEEE_CMD_PFC_MBC(1U) 10743 10744 #define S_FW_DCB_IEEE_CMD_PFC_WILLING 16 10745 #define M_FW_DCB_IEEE_CMD_PFC_WILLING 0x1 10746 #define V_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 10747 ((x) << S_FW_DCB_IEEE_CMD_PFC_WILLING) 10748 #define G_FW_DCB_IEEE_CMD_PFC_WILLING(x) \ 10749 (((x) >> S_FW_DCB_IEEE_CMD_PFC_WILLING) & M_FW_DCB_IEEE_CMD_PFC_WILLING) 10750 #define F_FW_DCB_IEEE_CMD_PFC_WILLING V_FW_DCB_IEEE_CMD_PFC_WILLING(1U) 10751 10752 #define S_FW_DCB_IEEE_CMD_PFC_MAX_TC 8 10753 #define M_FW_DCB_IEEE_CMD_PFC_MAX_TC 0xff 10754 #define V_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_MAX_TC) 10755 #define G_FW_DCB_IEEE_CMD_PFC_MAX_TC(x) \ 10756 (((x) >> S_FW_DCB_IEEE_CMD_PFC_MAX_TC) & M_FW_DCB_IEEE_CMD_PFC_MAX_TC) 10757 10758 #define S_FW_DCB_IEEE_CMD_PFC_EN 0 10759 #define M_FW_DCB_IEEE_CMD_PFC_EN 0xff 10760 #define V_FW_DCB_IEEE_CMD_PFC_EN(x) ((x) << S_FW_DCB_IEEE_CMD_PFC_EN) 10761 #define G_FW_DCB_IEEE_CMD_PFC_EN(x) \ 10762 (((x) >> S_FW_DCB_IEEE_CMD_PFC_EN) & M_FW_DCB_IEEE_CMD_PFC_EN) 10763 10764 #define S_FW_DCB_IEEE_CMD_CBS 16 10765 #define M_FW_DCB_IEEE_CMD_CBS 0x1 10766 #define V_FW_DCB_IEEE_CMD_CBS(x) ((x) << S_FW_DCB_IEEE_CMD_CBS) 10767 #define G_FW_DCB_IEEE_CMD_CBS(x) \ 10768 (((x) >> S_FW_DCB_IEEE_CMD_CBS) & M_FW_DCB_IEEE_CMD_CBS) 10769 #define F_FW_DCB_IEEE_CMD_CBS V_FW_DCB_IEEE_CMD_CBS(1U) 10770 10771 #define S_FW_DCB_IEEE_CMD_ETS_WILLING 8 10772 #define M_FW_DCB_IEEE_CMD_ETS_WILLING 0x1 10773 #define V_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 10774 ((x) << S_FW_DCB_IEEE_CMD_ETS_WILLING) 10775 #define G_FW_DCB_IEEE_CMD_ETS_WILLING(x) \ 10776 (((x) >> S_FW_DCB_IEEE_CMD_ETS_WILLING) & M_FW_DCB_IEEE_CMD_ETS_WILLING) 10777 #define F_FW_DCB_IEEE_CMD_ETS_WILLING V_FW_DCB_IEEE_CMD_ETS_WILLING(1U) 10778 10779 #define S_FW_DCB_IEEE_CMD_ETS_MAX_TC 0 10780 #define M_FW_DCB_IEEE_CMD_ETS_MAX_TC 0xff 10781 #define V_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) ((x) << S_FW_DCB_IEEE_CMD_ETS_MAX_TC) 10782 #define G_FW_DCB_IEEE_CMD_ETS_MAX_TC(x) \ 10783 (((x) >> S_FW_DCB_IEEE_CMD_ETS_MAX_TC) & M_FW_DCB_IEEE_CMD_ETS_MAX_TC) 10784 10785 #define S_FW_DCB_IEEE_CMD_NUM_APPS 0 10786 #define M_FW_DCB_IEEE_CMD_NUM_APPS 0x7 10787 #define V_FW_DCB_IEEE_CMD_NUM_APPS(x) ((x) << S_FW_DCB_IEEE_CMD_NUM_APPS) 10788 #define G_FW_DCB_IEEE_CMD_NUM_APPS(x) \ 10789 (((x) >> S_FW_DCB_IEEE_CMD_NUM_APPS) & M_FW_DCB_IEEE_CMD_NUM_APPS) 10790 10791 #define S_FW_DCB_IEEE_CMD_MULTI_PEER 31 10792 #define M_FW_DCB_IEEE_CMD_MULTI_PEER 0x1 10793 #define V_FW_DCB_IEEE_CMD_MULTI_PEER(x) ((x) << S_FW_DCB_IEEE_CMD_MULTI_PEER) 10794 #define G_FW_DCB_IEEE_CMD_MULTI_PEER(x) \ 10795 (((x) >> S_FW_DCB_IEEE_CMD_MULTI_PEER) & M_FW_DCB_IEEE_CMD_MULTI_PEER) 10796 #define F_FW_DCB_IEEE_CMD_MULTI_PEER V_FW_DCB_IEEE_CMD_MULTI_PEER(1U) 10797 10798 #define S_FW_DCB_IEEE_CMD_INVALIDATED 30 10799 #define M_FW_DCB_IEEE_CMD_INVALIDATED 0x1 10800 #define V_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 10801 ((x) << S_FW_DCB_IEEE_CMD_INVALIDATED) 10802 #define G_FW_DCB_IEEE_CMD_INVALIDATED(x) \ 10803 (((x) >> S_FW_DCB_IEEE_CMD_INVALIDATED) & M_FW_DCB_IEEE_CMD_INVALIDATED) 10804 #define F_FW_DCB_IEEE_CMD_INVALIDATED V_FW_DCB_IEEE_CMD_INVALIDATED(1U) 10805 10806 /* Hand-written */ 10807 #define S_FW_DCB_IEEE_CMD_APP_PROTOCOL 16 10808 #define M_FW_DCB_IEEE_CMD_APP_PROTOCOL 0xffff 10809 #define V_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PROTOCOL) 10810 #define G_FW_DCB_IEEE_CMD_APP_PROTOCOL(x) \ 10811 (((x) >> S_FW_DCB_IEEE_CMD_APP_PROTOCOL) & M_FW_DCB_IEEE_CMD_APP_PROTOCOL) 10812 10813 #define S_FW_DCB_IEEE_CMD_APP_SELECT 3 10814 #define M_FW_DCB_IEEE_CMD_APP_SELECT 0x7 10815 #define V_FW_DCB_IEEE_CMD_APP_SELECT(x) ((x) << S_FW_DCB_IEEE_CMD_APP_SELECT) 10816 #define G_FW_DCB_IEEE_CMD_APP_SELECT(x) \ 10817 (((x) >> S_FW_DCB_IEEE_CMD_APP_SELECT) & M_FW_DCB_IEEE_CMD_APP_SELECT) 10818 10819 #define S_FW_DCB_IEEE_CMD_APP_PRIORITY 0 10820 #define M_FW_DCB_IEEE_CMD_APP_PRIORITY 0x7 10821 #define V_FW_DCB_IEEE_CMD_APP_PRIORITY(x) ((x) << S_FW_DCB_IEEE_CMD_APP_PRIORITY) 10822 #define G_FW_DCB_IEEE_CMD_APP_PRIORITY(x) \ 10823 (((x) >> S_FW_DCB_IEEE_CMD_APP_PRIORITY) & M_FW_DCB_IEEE_CMD_APP_PRIORITY) 10824 10825 10826 struct fw_error_cmd { 10827 __be32 op_to_type; 10828 __be32 len16_pkd; 10829 union fw_error { 10830 struct fw_error_exception { 10831 __be32 info[6]; 10832 } exception; 10833 struct fw_error_hwmodule { 10834 __be32 regaddr; 10835 __be32 regval; 10836 } hwmodule; 10837 struct fw_error_wr { 10838 __be16 cidx; 10839 __be16 pfn_vfn; 10840 __be32 eqid; 10841 __u8 wrhdr[16]; 10842 } wr; 10843 struct fw_error_acl { 10844 __be16 cidx; 10845 __be16 pfn_vfn; 10846 __be32 eqid; 10847 __be16 mv_pkd; 10848 __u8 val[6]; 10849 __be64 r4; 10850 } acl; 10851 } u; 10852 }; 10853 10854 #define S_FW_ERROR_CMD_FATAL 4 10855 #define M_FW_ERROR_CMD_FATAL 0x1 10856 #define V_FW_ERROR_CMD_FATAL(x) ((x) << S_FW_ERROR_CMD_FATAL) 10857 #define G_FW_ERROR_CMD_FATAL(x) \ 10858 (((x) >> S_FW_ERROR_CMD_FATAL) & M_FW_ERROR_CMD_FATAL) 10859 #define F_FW_ERROR_CMD_FATAL V_FW_ERROR_CMD_FATAL(1U) 10860 10861 #define S_FW_ERROR_CMD_TYPE 0 10862 #define M_FW_ERROR_CMD_TYPE 0xf 10863 #define V_FW_ERROR_CMD_TYPE(x) ((x) << S_FW_ERROR_CMD_TYPE) 10864 #define G_FW_ERROR_CMD_TYPE(x) \ 10865 (((x) >> S_FW_ERROR_CMD_TYPE) & M_FW_ERROR_CMD_TYPE) 10866 10867 #define S_FW_ERROR_CMD_PFN 8 10868 #define M_FW_ERROR_CMD_PFN 0x7 10869 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 10870 #define G_FW_ERROR_CMD_PFN(x) \ 10871 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 10872 10873 #define S_FW_ERROR_CMD_VFN 0 10874 #define M_FW_ERROR_CMD_VFN 0xff 10875 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 10876 #define G_FW_ERROR_CMD_VFN(x) \ 10877 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 10878 10879 #define S_FW_ERROR_CMD_PFN 8 10880 #define M_FW_ERROR_CMD_PFN 0x7 10881 #define V_FW_ERROR_CMD_PFN(x) ((x) << S_FW_ERROR_CMD_PFN) 10882 #define G_FW_ERROR_CMD_PFN(x) \ 10883 (((x) >> S_FW_ERROR_CMD_PFN) & M_FW_ERROR_CMD_PFN) 10884 10885 #define S_FW_ERROR_CMD_VFN 0 10886 #define M_FW_ERROR_CMD_VFN 0xff 10887 #define V_FW_ERROR_CMD_VFN(x) ((x) << S_FW_ERROR_CMD_VFN) 10888 #define G_FW_ERROR_CMD_VFN(x) \ 10889 (((x) >> S_FW_ERROR_CMD_VFN) & M_FW_ERROR_CMD_VFN) 10890 10891 #define S_FW_ERROR_CMD_MV 15 10892 #define M_FW_ERROR_CMD_MV 0x1 10893 #define V_FW_ERROR_CMD_MV(x) ((x) << S_FW_ERROR_CMD_MV) 10894 #define G_FW_ERROR_CMD_MV(x) \ 10895 (((x) >> S_FW_ERROR_CMD_MV) & M_FW_ERROR_CMD_MV) 10896 #define F_FW_ERROR_CMD_MV V_FW_ERROR_CMD_MV(1U) 10897 10898 struct fw_debug_cmd { 10899 __be32 op_type; 10900 __be32 len16_pkd; 10901 union fw_debug { 10902 struct fw_debug_assert { 10903 __be32 fcid; 10904 __be32 line; 10905 __be32 x; 10906 __be32 y; 10907 __u8 filename_0_7[8]; 10908 __u8 filename_8_15[8]; 10909 __be64 r3; 10910 } assert; 10911 struct fw_debug_prt { 10912 __be16 dprtstridx; 10913 __be16 r3[3]; 10914 __be32 dprtstrparam0; 10915 __be32 dprtstrparam1; 10916 __be32 dprtstrparam2; 10917 __be32 dprtstrparam3; 10918 } prt; 10919 } u; 10920 }; 10921 10922 #define S_FW_DEBUG_CMD_TYPE 0 10923 #define M_FW_DEBUG_CMD_TYPE 0xff 10924 #define V_FW_DEBUG_CMD_TYPE(x) ((x) << S_FW_DEBUG_CMD_TYPE) 10925 #define G_FW_DEBUG_CMD_TYPE(x) \ 10926 (((x) >> S_FW_DEBUG_CMD_TYPE) & M_FW_DEBUG_CMD_TYPE) 10927 10928 enum fw_diag_cmd_type { 10929 FW_DIAG_CMD_TYPE_OFLDIAG = 0, 10930 FW_DIAG_CMD_TYPE_MEM_TEST_DIAG, 10931 }; 10932 10933 enum fw_diag_cmd_ofldiag_op { 10934 FW_DIAG_CMD_OFLDIAG_TEST_NONE = 0, 10935 FW_DIAG_CMD_OFLDIAG_TEST_START, 10936 FW_DIAG_CMD_OFLDIAG_TEST_STOP, 10937 FW_DIAG_CMD_OFLDIAG_TEST_STATUS, 10938 }; 10939 10940 enum fw_diag_cmd_ofldiag_status { 10941 FW_DIAG_CMD_OFLDIAG_STATUS_IDLE = 0, 10942 FW_DIAG_CMD_OFLDIAG_STATUS_RUNNING, 10943 FW_DIAG_CMD_OFLDIAG_STATUS_FAILED, 10944 FW_DIAG_CMD_OFLDIAG_STATUS_PASSED, 10945 }; 10946 10947 enum fw_diag_cmd_memdiag_op { 10948 FW_DIAG_CMD_MEMDIAG_TEST_START=1, 10949 FW_DIAG_CMD_MEMDIAG_TEST_STOP, 10950 FW_DIAG_CMD_MEMDIAG_TEST_STATUS, 10951 FW_DIAG_CMD_MEMDIAG_TEST_INIT, 10952 }; 10953 10954 10955 enum fw_diag_cmd_memdiag_status { 10956 FW_DIAG_CMD_MEMDIAG_STATUS_NONE, 10957 FW_DIAG_CMD_MEMDIAG_STATUS_RUNNING, 10958 FW_DIAG_CMD_MEMDIAG_STATUS_FAILED, 10959 FW_DIAG_CMD_MEMDIAG_STATUS_PASSED 10960 }; 10961 10962 10963 struct fw_diag_cmd { 10964 __be32 op_type; 10965 __be32 len16_pkd; 10966 union fw_diag_test { 10967 struct fw_diag_test_ofldiag { 10968 __u8 test_op; 10969 __u8 r3; 10970 __be16 test_status; 10971 __be32 duration; 10972 } ofldiag; 10973 struct fw_diag_test_memtest_diag { 10974 __u8 test_op; 10975 __u8 test_status; 10976 __be16 size; /* in KB */ 10977 __be32 duration; /* in seconds */ 10978 } memdiag; 10979 } u; 10980 }; 10981 10982 #define S_FW_DIAG_CMD_OPCODE 24 10983 #define M_FW_DIAG_CMD_OPCODE 0xff 10984 #define V_FW_DIAG_CMD_OPCODE(x) ((x) << S_FW_DIAG_CMD_OPCODE) 10985 #define G_FW_DIAG_CMD_OPCODE(x) \ 10986 (((x) >> S_FW_DIAG_CMD_OPCODE) & M_FW_DIAG_CMD_OPCODE) 10987 10988 #define S_FW_DIAG_CMD_TYPE 0 10989 #define M_FW_DIAG_CMD_TYPE 0xff 10990 #define V_FW_DIAG_CMD_TYPE(x) ((x) << S_FW_DIAG_CMD_TYPE) 10991 #define G_FW_DIAG_CMD_TYPE(x) \ 10992 (((x) >> S_FW_DIAG_CMD_TYPE) & M_FW_DIAG_CMD_TYPE) 10993 10994 #define S_FW_DIAG_CMD_LEN16 0 10995 #define M_FW_DIAG_CMD_LEN16 0xff 10996 #define V_FW_DIAG_CMD_LEN16(x) ((x) << S_FW_DIAG_CMD_LEN16) 10997 #define G_FW_DIAG_CMD_LEN16(x) \ 10998 (((x) >> S_FW_DIAG_CMD_LEN16) & M_FW_DIAG_CMD_LEN16) 10999 11000 struct fw_hma_cmd { 11001 __be32 op_pkd; 11002 __be32 retval_len16; 11003 __be32 mode_to_pcie_params; 11004 __be32 naddr_size; 11005 __be32 addr_size_pkd; 11006 __be32 r6; 11007 __be64 phy_address[5]; 11008 }; 11009 11010 #define S_FW_HMA_CMD_MODE 31 11011 #define M_FW_HMA_CMD_MODE 0x1 11012 #define V_FW_HMA_CMD_MODE(x) ((x) << S_FW_HMA_CMD_MODE) 11013 #define G_FW_HMA_CMD_MODE(x) \ 11014 (((x) >> S_FW_HMA_CMD_MODE) & M_FW_HMA_CMD_MODE) 11015 #define F_FW_HMA_CMD_MODE V_FW_HMA_CMD_MODE(1U) 11016 11017 #define S_FW_HMA_CMD_SOC 30 11018 #define M_FW_HMA_CMD_SOC 0x1 11019 #define V_FW_HMA_CMD_SOC(x) ((x) << S_FW_HMA_CMD_SOC) 11020 #define G_FW_HMA_CMD_SOC(x) (((x) >> S_FW_HMA_CMD_SOC) & M_FW_HMA_CMD_SOC) 11021 #define F_FW_HMA_CMD_SOC V_FW_HMA_CMD_SOC(1U) 11022 11023 #define S_FW_HMA_CMD_EOC 29 11024 #define M_FW_HMA_CMD_EOC 0x1 11025 #define V_FW_HMA_CMD_EOC(x) ((x) << S_FW_HMA_CMD_EOC) 11026 #define G_FW_HMA_CMD_EOC(x) (((x) >> S_FW_HMA_CMD_EOC) & M_FW_HMA_CMD_EOC) 11027 #define F_FW_HMA_CMD_EOC V_FW_HMA_CMD_EOC(1U) 11028 11029 #define S_FW_HMA_CMD_PCIE_PARAMS 0 11030 #define M_FW_HMA_CMD_PCIE_PARAMS 0x7ffffff 11031 #define V_FW_HMA_CMD_PCIE_PARAMS(x) ((x) << S_FW_HMA_CMD_PCIE_PARAMS) 11032 #define G_FW_HMA_CMD_PCIE_PARAMS(x) \ 11033 (((x) >> S_FW_HMA_CMD_PCIE_PARAMS) & M_FW_HMA_CMD_PCIE_PARAMS) 11034 11035 #define S_FW_HMA_CMD_NADDR 12 11036 #define M_FW_HMA_CMD_NADDR 0x3f 11037 #define V_FW_HMA_CMD_NADDR(x) ((x) << S_FW_HMA_CMD_NADDR) 11038 #define G_FW_HMA_CMD_NADDR(x) \ 11039 (((x) >> S_FW_HMA_CMD_NADDR) & M_FW_HMA_CMD_NADDR) 11040 11041 #define S_FW_HMA_CMD_SIZE 0 11042 #define M_FW_HMA_CMD_SIZE 0xfff 11043 #define V_FW_HMA_CMD_SIZE(x) ((x) << S_FW_HMA_CMD_SIZE) 11044 #define G_FW_HMA_CMD_SIZE(x) \ 11045 (((x) >> S_FW_HMA_CMD_SIZE) & M_FW_HMA_CMD_SIZE) 11046 11047 #define S_FW_HMA_CMD_ADDR_SIZE 11 11048 #define M_FW_HMA_CMD_ADDR_SIZE 0x1fffff 11049 #define V_FW_HMA_CMD_ADDR_SIZE(x) ((x) << S_FW_HMA_CMD_ADDR_SIZE) 11050 #define G_FW_HMA_CMD_ADDR_SIZE(x) \ 11051 (((x) >> S_FW_HMA_CMD_ADDR_SIZE) & M_FW_HMA_CMD_ADDR_SIZE) 11052 11053 struct fw_jbof_win_reg_cmd { 11054 __be32 op_pkd; 11055 __be32 alloc_to_len16; 11056 __be32 window_num_pcie_params; 11057 __be32 window_size; 11058 __be64 bus_addr; 11059 __be64 phy_address; 11060 }; 11061 11062 #define S_FW_JBOF_WIN_REG_CMD_ALLOC 31 11063 #define M_FW_JBOF_WIN_REG_CMD_ALLOC 0x1 11064 #define V_FW_JBOF_WIN_REG_CMD_ALLOC(x) ((x) << S_FW_JBOF_WIN_REG_CMD_ALLOC) 11065 #define G_FW_JBOF_WIN_REG_CMD_ALLOC(x) \ 11066 (((x) >> S_FW_JBOF_WIN_REG_CMD_ALLOC) & M_FW_JBOF_WIN_REG_CMD_ALLOC) 11067 #define F_FW_JBOF_WIN_REG_CMD_ALLOC V_FW_JBOF_WIN_REG_CMD_ALLOC(1U) 11068 11069 #define S_FW_JBOF_WIN_REG_CMD_FREE 30 11070 #define M_FW_JBOF_WIN_REG_CMD_FREE 0x1 11071 #define V_FW_JBOF_WIN_REG_CMD_FREE(x) ((x) << S_FW_JBOF_WIN_REG_CMD_FREE) 11072 #define G_FW_JBOF_WIN_REG_CMD_FREE(x) \ 11073 (((x) >> S_FW_JBOF_WIN_REG_CMD_FREE) & M_FW_JBOF_WIN_REG_CMD_FREE) 11074 #define F_FW_JBOF_WIN_REG_CMD_FREE V_FW_JBOF_WIN_REG_CMD_FREE(1U) 11075 11076 #define S_FW_JBOF_WIN_REG_CMD_WINDOW_NUM 7 11077 #define M_FW_JBOF_WIN_REG_CMD_WINDOW_NUM 0xf 11078 #define V_FW_JBOF_WIN_REG_CMD_WINDOW_NUM(x) \ 11079 ((x) << S_FW_JBOF_WIN_REG_CMD_WINDOW_NUM) 11080 #define G_FW_JBOF_WIN_REG_CMD_WINDOW_NUM(x) \ 11081 (((x) >> S_FW_JBOF_WIN_REG_CMD_WINDOW_NUM) & \ 11082 M_FW_JBOF_WIN_REG_CMD_WINDOW_NUM) 11083 11084 #define S_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS 0 11085 #define M_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS 0x7f 11086 #define V_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS(x) \ 11087 ((x) << S_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS) 11088 #define G_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS(x) \ 11089 (((x) >> S_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS) & \ 11090 M_FW_JBOF_WIN_REG_CMD_PCIE_PARAMS) 11091 11092 /****************************************************************************** 11093 * P C I E F W R E G I S T E R 11094 **************************************/ 11095 11096 enum pcie_fw_eval { 11097 PCIE_FW_EVAL_CRASH = 0, 11098 PCIE_FW_EVAL_PREP = 1, 11099 PCIE_FW_EVAL_CONF = 2, 11100 PCIE_FW_EVAL_INIT = 3, 11101 PCIE_FW_EVAL_UNEXPECTEDEVENT = 4, 11102 PCIE_FW_EVAL_OVERHEAT = 5, 11103 PCIE_FW_EVAL_DEVICESHUTDOWN = 6, 11104 }; 11105 11106 /** 11107 * Register definitions for the PCIE_FW register which the firmware uses 11108 * to retain status across RESETs. This register should be considered 11109 * as a READ-ONLY register for Host Software and only to be used to 11110 * track firmware initialization/error state, etc. 11111 */ 11112 #define S_PCIE_FW_ERR 31 11113 #define M_PCIE_FW_ERR 0x1 11114 #define V_PCIE_FW_ERR(x) ((x) << S_PCIE_FW_ERR) 11115 #define G_PCIE_FW_ERR(x) (((x) >> S_PCIE_FW_ERR) & M_PCIE_FW_ERR) 11116 #define F_PCIE_FW_ERR V_PCIE_FW_ERR(1U) 11117 11118 #define S_PCIE_FW_INIT 30 11119 #define M_PCIE_FW_INIT 0x1 11120 #define V_PCIE_FW_INIT(x) ((x) << S_PCIE_FW_INIT) 11121 #define G_PCIE_FW_INIT(x) (((x) >> S_PCIE_FW_INIT) & M_PCIE_FW_INIT) 11122 #define F_PCIE_FW_INIT V_PCIE_FW_INIT(1U) 11123 11124 #define S_PCIE_FW_HALT 29 11125 #define M_PCIE_FW_HALT 0x1 11126 #define V_PCIE_FW_HALT(x) ((x) << S_PCIE_FW_HALT) 11127 #define G_PCIE_FW_HALT(x) (((x) >> S_PCIE_FW_HALT) & M_PCIE_FW_HALT) 11128 #define F_PCIE_FW_HALT V_PCIE_FW_HALT(1U) 11129 11130 #define S_PCIE_FW_EVAL 24 11131 #define M_PCIE_FW_EVAL 0x7 11132 #define V_PCIE_FW_EVAL(x) ((x) << S_PCIE_FW_EVAL) 11133 #define G_PCIE_FW_EVAL(x) (((x) >> S_PCIE_FW_EVAL) & M_PCIE_FW_EVAL) 11134 11135 #define S_PCIE_FW_STAGE 21 11136 #define M_PCIE_FW_STAGE 0x7 11137 #define V_PCIE_FW_STAGE(x) ((x) << S_PCIE_FW_STAGE) 11138 #define G_PCIE_FW_STAGE(x) (((x) >> S_PCIE_FW_STAGE) & M_PCIE_FW_STAGE) 11139 11140 #define S_PCIE_FW_ASYNCNOT_VLD 20 11141 #define M_PCIE_FW_ASYNCNOT_VLD 0x1 11142 #define V_PCIE_FW_ASYNCNOT_VLD(x) \ 11143 ((x) << S_PCIE_FW_ASYNCNOT_VLD) 11144 #define G_PCIE_FW_ASYNCNOT_VLD(x) \ 11145 (((x) >> S_PCIE_FW_ASYNCNOT_VLD) & M_PCIE_FW_ASYNCNOT_VLD) 11146 #define F_PCIE_FW_ASYNCNOT_VLD V_PCIE_FW_ASYNCNOT_VLD(1U) 11147 11148 #define S_PCIE_FW_ASYNCNOTINT 19 11149 #define M_PCIE_FW_ASYNCNOTINT 0x1 11150 #define V_PCIE_FW_ASYNCNOTINT(x) \ 11151 ((x) << S_PCIE_FW_ASYNCNOTINT) 11152 #define G_PCIE_FW_ASYNCNOTINT(x) \ 11153 (((x) >> S_PCIE_FW_ASYNCNOTINT) & M_PCIE_FW_ASYNCNOTINT) 11154 #define F_PCIE_FW_ASYNCNOTINT V_PCIE_FW_ASYNCNOTINT(1U) 11155 11156 #define S_PCIE_FW_ASYNCNOT 16 11157 #define M_PCIE_FW_ASYNCNOT 0x7 11158 #define V_PCIE_FW_ASYNCNOT(x) ((x) << S_PCIE_FW_ASYNCNOT) 11159 #define G_PCIE_FW_ASYNCNOT(x) \ 11160 (((x) >> S_PCIE_FW_ASYNCNOT) & M_PCIE_FW_ASYNCNOT) 11161 11162 #define S_PCIE_FW_MASTER_VLD 15 11163 #define M_PCIE_FW_MASTER_VLD 0x1 11164 #define V_PCIE_FW_MASTER_VLD(x) ((x) << S_PCIE_FW_MASTER_VLD) 11165 #define G_PCIE_FW_MASTER_VLD(x) \ 11166 (((x) >> S_PCIE_FW_MASTER_VLD) & M_PCIE_FW_MASTER_VLD) 11167 #define F_PCIE_FW_MASTER_VLD V_PCIE_FW_MASTER_VLD(1U) 11168 11169 #define S_PCIE_FW_MASTER 12 11170 #define M_PCIE_FW_MASTER 0x7 11171 #define V_PCIE_FW_MASTER(x) ((x) << S_PCIE_FW_MASTER) 11172 #define G_PCIE_FW_MASTER(x) (((x) >> S_PCIE_FW_MASTER) & M_PCIE_FW_MASTER) 11173 11174 #define S_PCIE_FW_RESET_VLD 11 11175 #define M_PCIE_FW_RESET_VLD 0x1 11176 #define V_PCIE_FW_RESET_VLD(x) ((x) << S_PCIE_FW_RESET_VLD) 11177 #define G_PCIE_FW_RESET_VLD(x) \ 11178 (((x) >> S_PCIE_FW_RESET_VLD) & M_PCIE_FW_RESET_VLD) 11179 #define F_PCIE_FW_RESET_VLD V_PCIE_FW_RESET_VLD(1U) 11180 11181 #define S_PCIE_FW_RESET 8 11182 #define M_PCIE_FW_RESET 0x7 11183 #define V_PCIE_FW_RESET(x) ((x) << S_PCIE_FW_RESET) 11184 #define G_PCIE_FW_RESET(x) \ 11185 (((x) >> S_PCIE_FW_RESET) & M_PCIE_FW_RESET) 11186 11187 #define S_PCIE_FW_REGISTERED 0 11188 #define M_PCIE_FW_REGISTERED 0xff 11189 #define V_PCIE_FW_REGISTERED(x) ((x) << S_PCIE_FW_REGISTERED) 11190 #define G_PCIE_FW_REGISTERED(x) \ 11191 (((x) >> S_PCIE_FW_REGISTERED) & M_PCIE_FW_REGISTERED) 11192 11193 11194 /****************************************************************************** 11195 * P C I E F W P F 0 R E G I S T E R 11196 **********************************************/ 11197 11198 /* 11199 * this register is available as 32-bit of persistent storage (across 11200 * PL_RST based chip-reset) for boot drivers (i.e. firmware and driver 11201 * will not write it) 11202 */ 11203 11204 11205 /****************************************************************************** 11206 * P C I E F W P F 7 R E G I S T E R 11207 **********************************************/ 11208 11209 /* 11210 * PF7 stores the Firmware Device Log parameters which allows Host Drivers to 11211 * access the "devlog" which needing to contact firmware. The encoding is 11212 * mostly the same as that returned by the DEVLOG command except for the size 11213 * which is encoded as the number of entries in multiples-1 of 128 here rather 11214 * than the memory size as is done in the DEVLOG command. Thus, 0 means 128 11215 * and 15 means 2048. This of course in turn constrains the allowed values 11216 * for the devlog size ... 11217 */ 11218 #define PCIE_FW_PF_DEVLOG 7 11219 11220 #define S_PCIE_FW_PF_DEVLOG_COUNT_MSB 31 11221 #define M_PCIE_FW_PF_DEVLOG_COUNT_MSB 0x1 11222 #define V_PCIE_FW_PF_DEVLOG_COUNT_MSB(x) \ 11223 ((x) << S_PCIE_FW_PF_DEVLOG_COUNT_MSB) 11224 #define G_PCIE_FW_PF_DEVLOG_COUNT_MSB(x) \ 11225 (((x) >> S_PCIE_FW_PF_DEVLOG_COUNT_MSB) & M_PCIE_FW_PF_DEVLOG_COUNT_MSB) 11226 11227 #define S_PCIE_FW_PF_DEVLOG_NENTRIES128 28 11228 #define M_PCIE_FW_PF_DEVLOG_NENTRIES128 0x7 11229 #define V_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 11230 ((x) << S_PCIE_FW_PF_DEVLOG_NENTRIES128) 11231 #define G_PCIE_FW_PF_DEVLOG_NENTRIES128(x) \ 11232 (((x) >> S_PCIE_FW_PF_DEVLOG_NENTRIES128) & \ 11233 M_PCIE_FW_PF_DEVLOG_NENTRIES128) 11234 11235 #define S_PCIE_FW_PF_DEVLOG_ADDR16 4 11236 #define M_PCIE_FW_PF_DEVLOG_ADDR16 0xffffff 11237 #define V_PCIE_FW_PF_DEVLOG_ADDR16(x) ((x) << S_PCIE_FW_PF_DEVLOG_ADDR16) 11238 #define G_PCIE_FW_PF_DEVLOG_ADDR16(x) \ 11239 (((x) >> S_PCIE_FW_PF_DEVLOG_ADDR16) & M_PCIE_FW_PF_DEVLOG_ADDR16) 11240 11241 #define S_PCIE_FW_PF_DEVLOG_COUNT_LSB 3 11242 #define M_PCIE_FW_PF_DEVLOG_COUNT_LSB 0x1 11243 #define V_PCIE_FW_PF_DEVLOG_COUNT_LSB(x) \ 11244 ((x) << S_PCIE_FW_PF_DEVLOG_COUNT_LSB) 11245 #define G_PCIE_FW_PF_DEVLOG_COUNT_LSB(x) \ 11246 (((x) >> S_PCIE_FW_PF_DEVLOG_COUNT_LSB) & M_PCIE_FW_PF_DEVLOG_COUNT_LSB) 11247 11248 #define S_PCIE_FW_PF_DEVLOG_MEMTYPE 0 11249 #define M_PCIE_FW_PF_DEVLOG_MEMTYPE 0x7 11250 #define V_PCIE_FW_PF_DEVLOG_MEMTYPE(x) ((x) << S_PCIE_FW_PF_DEVLOG_MEMTYPE) 11251 #define G_PCIE_FW_PF_DEVLOG_MEMTYPE(x) \ 11252 (((x) >> S_PCIE_FW_PF_DEVLOG_MEMTYPE) & M_PCIE_FW_PF_DEVLOG_MEMTYPE) 11253 11254 11255 /****************************************************************************** 11256 * B I N A R Y H E A D E R F O R M A T 11257 **********************************************/ 11258 11259 /* 11260 * firmware binary header format 11261 */ 11262 struct fw_hdr { 11263 __u8 ver; 11264 __u8 chip; /* terminator chip family */ 11265 __be16 len512; /* bin length in units of 512-bytes */ 11266 __be32 fw_ver; /* firmware version */ 11267 __be32 tp_microcode_ver; /* tcp processor microcode version */ 11268 __u8 intfver_nic; 11269 __u8 intfver_vnic; 11270 __u8 intfver_ofld; 11271 __u8 intfver_ri; 11272 __u8 intfver_iscsipdu; 11273 __u8 intfver_iscsi; 11274 __u8 intfver_fcoepdu; 11275 __u8 intfver_fcoe; 11276 __u32 reserved2; 11277 __u32 reserved3; 11278 __be32 magic; /* runtime or bootstrap fw */ 11279 __be32 flags; 11280 __be32 reserved6[4]; 11281 __u8 reserved7[3]; 11282 __u8 dsign_len; 11283 __u8 dsign[72]; /* fw binary digital signature */ 11284 }; 11285 11286 enum fw_hdr_chip { 11287 FW_HDR_CHIP_T4, 11288 FW_HDR_CHIP_T5, 11289 FW_HDR_CHIP_T6, 11290 FW_HDR_CHIP_T7 11291 }; 11292 11293 #define S_FW_HDR_FW_VER_MAJOR 24 11294 #define M_FW_HDR_FW_VER_MAJOR 0xff 11295 #define V_FW_HDR_FW_VER_MAJOR(x) \ 11296 ((x) << S_FW_HDR_FW_VER_MAJOR) 11297 #define G_FW_HDR_FW_VER_MAJOR(x) \ 11298 (((x) >> S_FW_HDR_FW_VER_MAJOR) & M_FW_HDR_FW_VER_MAJOR) 11299 11300 #define S_FW_HDR_FW_VER_MINOR 16 11301 #define M_FW_HDR_FW_VER_MINOR 0xff 11302 #define V_FW_HDR_FW_VER_MINOR(x) \ 11303 ((x) << S_FW_HDR_FW_VER_MINOR) 11304 #define G_FW_HDR_FW_VER_MINOR(x) \ 11305 (((x) >> S_FW_HDR_FW_VER_MINOR) & M_FW_HDR_FW_VER_MINOR) 11306 11307 #define S_FW_HDR_FW_VER_MICRO 8 11308 #define M_FW_HDR_FW_VER_MICRO 0xff 11309 #define V_FW_HDR_FW_VER_MICRO(x) \ 11310 ((x) << S_FW_HDR_FW_VER_MICRO) 11311 #define G_FW_HDR_FW_VER_MICRO(x) \ 11312 (((x) >> S_FW_HDR_FW_VER_MICRO) & M_FW_HDR_FW_VER_MICRO) 11313 11314 #define S_FW_HDR_FW_VER_BUILD 0 11315 #define M_FW_HDR_FW_VER_BUILD 0xff 11316 #define V_FW_HDR_FW_VER_BUILD(x) \ 11317 ((x) << S_FW_HDR_FW_VER_BUILD) 11318 #define G_FW_HDR_FW_VER_BUILD(x) \ 11319 (((x) >> S_FW_HDR_FW_VER_BUILD) & M_FW_HDR_FW_VER_BUILD) 11320 11321 enum { 11322 T4FW_VERSION_MAJOR = 1, 11323 T4FW_VERSION_MINOR = 27, 11324 T4FW_VERSION_MICRO = 5, 11325 T4FW_VERSION_BUILD = 0, 11326 11327 T5FW_VERSION_MAJOR = 1, 11328 T5FW_VERSION_MINOR = 27, 11329 T5FW_VERSION_MICRO = 5, 11330 T5FW_VERSION_BUILD = 0, 11331 11332 T6FW_VERSION_MAJOR = 1, 11333 T6FW_VERSION_MINOR = 27, 11334 T6FW_VERSION_MICRO = 5, 11335 T6FW_VERSION_BUILD = 0, 11336 11337 T7FW_VERSION_MAJOR = 2, 11338 T7FW_VERSION_MINOR = 0, 11339 T7FW_VERSION_MICRO = 0, 11340 T7FW_VERSION_BUILD = 0, 11341 }; 11342 11343 enum { 11344 /* T4 11345 */ 11346 T4FW_HDR_INTFVER_NIC = 0x00, 11347 T4FW_HDR_INTFVER_VNIC = 0x00, 11348 T4FW_HDR_INTFVER_OFLD = 0x00, 11349 T4FW_HDR_INTFVER_RI = 0x00, 11350 T4FW_HDR_INTFVER_ISCSIPDU= 0x00, 11351 T4FW_HDR_INTFVER_ISCSI = 0x00, 11352 T4FW_HDR_INTFVER_FCOEPDU = 0x00, 11353 T4FW_HDR_INTFVER_FCOE = 0x00, 11354 11355 /* T5 11356 */ 11357 T5FW_HDR_INTFVER_NIC = 0x00, 11358 T5FW_HDR_INTFVER_VNIC = 0x00, 11359 T5FW_HDR_INTFVER_OFLD = 0x00, 11360 T5FW_HDR_INTFVER_RI = 0x00, 11361 T5FW_HDR_INTFVER_ISCSIPDU= 0x00, 11362 T5FW_HDR_INTFVER_ISCSI = 0x00, 11363 T5FW_HDR_INTFVER_FCOEPDU= 0x00, 11364 T5FW_HDR_INTFVER_FCOE = 0x00, 11365 11366 /* T6 11367 */ 11368 T6FW_HDR_INTFVER_NIC = 0x00, 11369 T6FW_HDR_INTFVER_VNIC = 0x00, 11370 T6FW_HDR_INTFVER_OFLD = 0x00, 11371 T6FW_HDR_INTFVER_RI = 0x00, 11372 T6FW_HDR_INTFVER_ISCSIPDU= 0x00, 11373 T6FW_HDR_INTFVER_ISCSI = 0x00, 11374 T6FW_HDR_INTFVER_FCOEPDU= 0x00, 11375 T6FW_HDR_INTFVER_FCOE = 0x00, 11376 11377 /* T7 11378 */ 11379 T7FW_HDR_INTFVER_NIC = 0x00, 11380 T7FW_HDR_INTFVER_VNIC = 0x00, 11381 T7FW_HDR_INTFVER_OFLD = 0x00, 11382 T7FW_HDR_INTFVER_RI = 0x00, 11383 T7FW_HDR_INTFVER_ISCSIPDU= 0x00, 11384 T7FW_HDR_INTFVER_ISCSI = 0x00, 11385 T7FW_HDR_INTFVER_FCOEPDU= 0x00, 11386 T7FW_HDR_INTFVER_FCOE = 0x00, 11387 }; 11388 11389 #define FW_VERSION32(MAJOR, MINOR, MICRO, BUILD) ( \ 11390 V_FW_HDR_FW_VER_MAJOR(MAJOR) | V_FW_HDR_FW_VER_MINOR(MINOR) | \ 11391 V_FW_HDR_FW_VER_MICRO(MICRO) | V_FW_HDR_FW_VER_BUILD(BUILD)) 11392 11393 enum { 11394 FW_HDR_MAGIC_RUNTIME = 0x00000000, 11395 FW_HDR_MAGIC_BOOTSTRAP = 0x626f6f74, 11396 }; 11397 11398 enum fw_hdr_flags { 11399 FW_HDR_FLAGS_RESET_HALT = 0x00000001, 11400 FW_HDR_FLAGS_SIGNED_FW = 0x00000002, 11401 }; 11402 11403 /* 11404 * External PHY firmware binary header format 11405 */ 11406 struct fw_ephy_hdr { 11407 __u8 ver; 11408 __u8 reserved; 11409 __be16 len512; /* bin length in units of 512-bytes */ 11410 __be32 magic; 11411 11412 __be16 vendor_id; 11413 __be16 device_id; 11414 __be32 version; 11415 11416 __be32 reserved1[4]; 11417 }; 11418 11419 enum { 11420 FW_EPHY_HDR_MAGIC = 0x65706879, 11421 }; 11422 11423 struct fw_ifconf_dhcp_info { 11424 __be32 addr; 11425 __be32 mask; 11426 __be16 vlanid; 11427 __be16 mtu; 11428 __be32 gw; 11429 __u8 op; 11430 __u8 len; 11431 __u8 data[270]; 11432 }; 11433 11434 struct fw_ifconf_ping_info { 11435 __be16 ping_pldsize; 11436 }; 11437 11438 #endif /* _T4FW_INTERFACE_H_ */ 11439