1 /************************************************************************** 2 3 Copyright (c) 2007, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Chelsio Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32 $FreeBSD$ 33 34 ***************************************************************************/ 35 #ifndef __CHELSIO_COMMON_H 36 #define __CHELSIO_COMMON_H 37 38 #include <dev/cxgb/cxgb_osdep.h> 39 40 enum { 41 MAX_NPORTS = 2, /* max # of ports */ 42 MAX_FRAME_SIZE = 10240, /* max MAC frame size, including header + FCS */ 43 EEPROMSIZE = 8192, /* Serial EEPROM size */ 44 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ 45 TCB_SIZE = 128, /* TCB size */ 46 NMTUS = 16, /* size of MTU table */ 47 NCCTRL_WIN = 32, /* # of congestion control windows */ 48 NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 49 }; 50 51 #define MAX_RX_COALESCING_LEN 16224U 52 53 enum { 54 PAUSE_RX = 1 << 0, 55 PAUSE_TX = 1 << 1, 56 PAUSE_AUTONEG = 1 << 2 57 }; 58 59 enum { 60 SUPPORTED_OFFLOAD = 1 << 24, 61 SUPPORTED_IRQ = 1 << 25 62 }; 63 64 enum { /* adapter interrupt-maintained statistics */ 65 STAT_ULP_CH0_PBL_OOB, 66 STAT_ULP_CH1_PBL_OOB, 67 STAT_PCI_CORR_ECC, 68 69 IRQ_NUM_STATS /* keep last */ 70 }; 71 72 enum { 73 FW_VERSION_MAJOR = 3, 74 FW_VERSION_MINOR = 2, 75 FW_VERSION_MICRO = 0 76 }; 77 78 enum { 79 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 80 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 81 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 82 }; 83 84 enum sge_context_type { /* SGE egress context types */ 85 SGE_CNTXT_RDMA = 0, 86 SGE_CNTXT_ETH = 2, 87 SGE_CNTXT_OFLD = 4, 88 SGE_CNTXT_CTRL = 5 89 }; 90 91 enum { 92 AN_PKT_SIZE = 32, /* async notification packet size */ 93 IMMED_PKT_SIZE = 48 /* packet size for immediate data */ 94 }; 95 96 struct sg_ent { /* SGE scatter/gather entry */ 97 u32 len[2]; 98 u64 addr[2]; 99 }; 100 101 #ifndef SGE_NUM_GENBITS 102 /* Must be 1 or 2 */ 103 # define SGE_NUM_GENBITS 2 104 #endif 105 106 #define TX_DESC_FLITS 16U 107 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) 108 109 struct cphy; 110 111 struct mdio_ops { 112 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr, 113 int reg_addr, unsigned int *val); 114 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr, 115 int reg_addr, unsigned int val); 116 }; 117 118 struct adapter_info { 119 unsigned char nports; /* # of ports */ 120 unsigned char phy_base_addr; /* MDIO PHY base address */ 121 unsigned char mdien; 122 unsigned char mdiinv; 123 unsigned int gpio_out; /* GPIO output settings */ 124 unsigned int gpio_intr; /* GPIO IRQ enable mask */ 125 unsigned long caps; /* adapter capabilities */ 126 const struct mdio_ops *mdio_ops; /* MDIO operations */ 127 const char *desc; /* product description */ 128 }; 129 130 struct port_type_info { 131 void (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr, 132 const struct mdio_ops *ops); 133 unsigned int caps; 134 const char *desc; 135 }; 136 137 struct mc5_stats { 138 unsigned long parity_err; 139 unsigned long active_rgn_full; 140 unsigned long nfa_srch_err; 141 unsigned long unknown_cmd; 142 unsigned long reqq_parity_err; 143 unsigned long dispq_parity_err; 144 unsigned long del_act_empty; 145 }; 146 147 struct mc7_stats { 148 unsigned long corr_err; 149 unsigned long uncorr_err; 150 unsigned long parity_err; 151 unsigned long addr_err; 152 }; 153 154 struct mac_stats { 155 u64 tx_octets; /* total # of octets in good frames */ 156 u64 tx_octets_bad; /* total # of octets in error frames */ 157 u64 tx_frames; /* all good frames */ 158 u64 tx_mcast_frames; /* good multicast frames */ 159 u64 tx_bcast_frames; /* good broadcast frames */ 160 u64 tx_pause; /* # of transmitted pause frames */ 161 u64 tx_deferred; /* frames with deferred transmissions */ 162 u64 tx_late_collisions; /* # of late collisions */ 163 u64 tx_total_collisions; /* # of total collisions */ 164 u64 tx_excess_collisions; /* frame errors from excessive collissions */ 165 u64 tx_underrun; /* # of Tx FIFO underruns */ 166 u64 tx_len_errs; /* # of Tx length errors */ 167 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ 168 u64 tx_excess_deferral; /* # of frames with excessive deferral */ 169 u64 tx_fcs_errs; /* # of frames with bad FCS */ 170 171 u64 tx_frames_64; /* # of Tx frames in a particular range */ 172 u64 tx_frames_65_127; 173 u64 tx_frames_128_255; 174 u64 tx_frames_256_511; 175 u64 tx_frames_512_1023; 176 u64 tx_frames_1024_1518; 177 u64 tx_frames_1519_max; 178 179 u64 rx_octets; /* total # of octets in good frames */ 180 u64 rx_octets_bad; /* total # of octets in error frames */ 181 u64 rx_frames; /* all good frames */ 182 u64 rx_mcast_frames; /* good multicast frames */ 183 u64 rx_bcast_frames; /* good broadcast frames */ 184 u64 rx_pause; /* # of received pause frames */ 185 u64 rx_fcs_errs; /* # of received frames with bad FCS */ 186 u64 rx_align_errs; /* alignment errors */ 187 u64 rx_symbol_errs; /* symbol errors */ 188 u64 rx_data_errs; /* data errors */ 189 u64 rx_sequence_errs; /* sequence errors */ 190 u64 rx_runt; /* # of runt frames */ 191 u64 rx_jabber; /* # of jabber frames */ 192 u64 rx_short; /* # of short frames */ 193 u64 rx_too_long; /* # of oversized frames */ 194 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ 195 196 u64 rx_frames_64; /* # of Rx frames in a particular range */ 197 u64 rx_frames_65_127; 198 u64 rx_frames_128_255; 199 u64 rx_frames_256_511; 200 u64 rx_frames_512_1023; 201 u64 rx_frames_1024_1518; 202 u64 rx_frames_1519_max; 203 204 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ 205 206 unsigned long tx_fifo_parity_err; 207 unsigned long rx_fifo_parity_err; 208 unsigned long tx_fifo_urun; 209 unsigned long rx_fifo_ovfl; 210 unsigned long serdes_signal_loss; 211 unsigned long xaui_pcs_ctc_err; 212 unsigned long xaui_pcs_align_change; 213 214 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ 215 unsigned long num_resets; /* # times reset due to stuck TX */ 216 }; 217 218 struct tp_mib_stats { 219 u32 ipInReceive_hi; 220 u32 ipInReceive_lo; 221 u32 ipInHdrErrors_hi; 222 u32 ipInHdrErrors_lo; 223 u32 ipInAddrErrors_hi; 224 u32 ipInAddrErrors_lo; 225 u32 ipInUnknownProtos_hi; 226 u32 ipInUnknownProtos_lo; 227 u32 ipInDiscards_hi; 228 u32 ipInDiscards_lo; 229 u32 ipInDelivers_hi; 230 u32 ipInDelivers_lo; 231 u32 ipOutRequests_hi; 232 u32 ipOutRequests_lo; 233 u32 ipOutDiscards_hi; 234 u32 ipOutDiscards_lo; 235 u32 ipOutNoRoutes_hi; 236 u32 ipOutNoRoutes_lo; 237 u32 ipReasmTimeout; 238 u32 ipReasmReqds; 239 u32 ipReasmOKs; 240 u32 ipReasmFails; 241 242 u32 reserved[8]; 243 244 u32 tcpActiveOpens; 245 u32 tcpPassiveOpens; 246 u32 tcpAttemptFails; 247 u32 tcpEstabResets; 248 u32 tcpOutRsts; 249 u32 tcpCurrEstab; 250 u32 tcpInSegs_hi; 251 u32 tcpInSegs_lo; 252 u32 tcpOutSegs_hi; 253 u32 tcpOutSegs_lo; 254 u32 tcpRetransSeg_hi; 255 u32 tcpRetransSeg_lo; 256 u32 tcpInErrs_hi; 257 u32 tcpInErrs_lo; 258 u32 tcpRtoMin; 259 u32 tcpRtoMax; 260 }; 261 262 struct tp_params { 263 unsigned int nchan; /* # of channels */ 264 unsigned int pmrx_size; /* total PMRX capacity */ 265 unsigned int pmtx_size; /* total PMTX capacity */ 266 unsigned int cm_size; /* total CM capacity */ 267 unsigned int chan_rx_size; /* per channel Rx size */ 268 unsigned int chan_tx_size; /* per channel Tx size */ 269 unsigned int rx_pg_size; /* Rx page size */ 270 unsigned int tx_pg_size; /* Tx page size */ 271 unsigned int rx_num_pgs; /* # of Rx pages */ 272 unsigned int tx_num_pgs; /* # of Tx pages */ 273 unsigned int ntimer_qs; /* # of timer queues */ 274 unsigned int dack_re; /* DACK timer resolution */ 275 }; 276 277 struct qset_params { /* SGE queue set parameters */ 278 unsigned int polling; /* polling/interrupt service for rspq */ 279 unsigned int coalesce_nsecs; /* irq coalescing timer */ 280 unsigned int rspq_size; /* # of entries in response queue */ 281 unsigned int fl_size; /* # of entries in regular free list */ 282 unsigned int jumbo_size; /* # of entries in jumbo free list */ 283 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ 284 unsigned int cong_thres; /* FL congestion threshold */ 285 unsigned int vector; /* Interrupt (line or vector) number */ 286 }; 287 288 struct sge_params { 289 unsigned int max_pkt_size; /* max offload pkt size */ 290 struct qset_params qset[SGE_QSETS]; 291 }; 292 293 struct mc5_params { 294 unsigned int mode; /* selects MC5 width */ 295 unsigned int nservers; /* size of server region */ 296 unsigned int nfilters; /* size of filter region */ 297 unsigned int nroutes; /* size of routing region */ 298 }; 299 300 /* Default MC5 region sizes */ 301 enum { 302 DEFAULT_NSERVERS = 512, 303 DEFAULT_NFILTERS = 128 304 }; 305 306 /* MC5 modes, these must be non-0 */ 307 enum { 308 MC5_MODE_144_BIT = 1, 309 MC5_MODE_72_BIT = 2 310 }; 311 312 struct vpd_params { 313 unsigned int cclk; 314 unsigned int mclk; 315 unsigned int uclk; 316 unsigned int mdc; 317 unsigned int mem_timing; 318 u8 eth_base[6]; 319 u8 port_type[MAX_NPORTS]; 320 unsigned short xauicfg[2]; 321 }; 322 323 struct pci_params { 324 unsigned int vpd_cap_addr; 325 unsigned int pcie_cap_addr; 326 unsigned short speed; 327 unsigned char width; 328 unsigned char variant; 329 }; 330 331 enum { 332 PCI_VARIANT_PCI, 333 PCI_VARIANT_PCIX_MODE1_PARITY, 334 PCI_VARIANT_PCIX_MODE1_ECC, 335 PCI_VARIANT_PCIX_266_MODE2, 336 PCI_VARIANT_PCIE 337 }; 338 339 struct adapter_params { 340 struct sge_params sge; 341 struct mc5_params mc5; 342 struct tp_params tp; 343 struct vpd_params vpd; 344 struct pci_params pci; 345 346 const struct adapter_info *info; 347 348 #ifdef CONFIG_CHELSIO_T3_CORE 349 unsigned short mtus[NMTUS]; 350 unsigned short a_wnd[NCCTRL_WIN]; 351 unsigned short b_wnd[NCCTRL_WIN]; 352 #endif 353 unsigned int nports; /* # of ethernet ports */ 354 unsigned int stats_update_period; /* MAC stats accumulation period */ 355 unsigned int linkpoll_period; /* link poll period in 0.1s */ 356 unsigned int rev; /* chip revision */ 357 }; 358 359 enum { /* chip revisions */ 360 T3_REV_A = 0, 361 T3_REV_B = 2, 362 T3_REV_B2 = 3, 363 }; 364 365 struct trace_params { 366 u32 sip; 367 u32 sip_mask; 368 u32 dip; 369 u32 dip_mask; 370 u16 sport; 371 u16 sport_mask; 372 u16 dport; 373 u16 dport_mask; 374 u32 vlan:12; 375 u32 vlan_mask:12; 376 u32 intf:4; 377 u32 intf_mask:4; 378 u8 proto; 379 u8 proto_mask; 380 }; 381 382 struct link_config { 383 unsigned int supported; /* link capabilities */ 384 unsigned int advertising; /* advertised capabilities */ 385 unsigned short requested_speed; /* speed user has requested */ 386 unsigned short speed; /* actual link speed */ 387 unsigned char requested_duplex; /* duplex user has requested */ 388 unsigned char duplex; /* actual link duplex */ 389 unsigned char requested_fc; /* flow control user has requested */ 390 unsigned char fc; /* actual link flow control */ 391 unsigned char autoneg; /* autonegotiating? */ 392 unsigned int link_ok; /* link up? */ 393 }; 394 395 #define SPEED_INVALID 0xffff 396 #define DUPLEX_INVALID 0xff 397 398 struct mc5 { 399 adapter_t *adapter; 400 unsigned int tcam_size; 401 unsigned char part_type; 402 unsigned char parity_enabled; 403 unsigned char mode; 404 struct mc5_stats stats; 405 }; 406 407 static inline unsigned int t3_mc5_size(const struct mc5 *p) 408 { 409 return p->tcam_size; 410 } 411 412 struct mc7 { 413 adapter_t *adapter; /* backpointer to adapter */ 414 unsigned int size; /* memory size in bytes */ 415 unsigned int width; /* MC7 interface width */ 416 unsigned int offset; /* register address offset for MC7 instance */ 417 const char *name; /* name of MC7 instance */ 418 struct mc7_stats stats; /* MC7 statistics */ 419 }; 420 421 static inline unsigned int t3_mc7_size(const struct mc7 *p) 422 { 423 return p->size; 424 } 425 426 struct cmac { 427 adapter_t *adapter; 428 unsigned int offset; 429 unsigned int nucast; /* # of address filters for unicast MACs */ 430 unsigned int tcnt; 431 unsigned int xcnt; 432 unsigned int toggle_cnt; 433 unsigned int txen; 434 struct mac_stats stats; 435 }; 436 437 enum { 438 MAC_DIRECTION_RX = 1, 439 MAC_DIRECTION_TX = 2, 440 MAC_RXFIFO_SIZE = 32768 441 }; 442 443 /* IEEE 802.3ae specified MDIO devices */ 444 enum { 445 MDIO_DEV_PMA_PMD = 1, 446 MDIO_DEV_WIS = 2, 447 MDIO_DEV_PCS = 3, 448 MDIO_DEV_XGXS = 4 449 }; 450 451 /* PHY loopback direction */ 452 enum { 453 PHY_LOOPBACK_TX = 1, 454 PHY_LOOPBACK_RX = 2 455 }; 456 457 /* PHY interrupt types */ 458 enum { 459 cphy_cause_link_change = 1, 460 cphy_cause_fifo_error = 2 461 }; 462 463 /* PHY operations */ 464 struct cphy_ops { 465 void (*destroy)(struct cphy *phy); 466 int (*reset)(struct cphy *phy, int wait); 467 468 int (*intr_enable)(struct cphy *phy); 469 int (*intr_disable)(struct cphy *phy); 470 int (*intr_clear)(struct cphy *phy); 471 int (*intr_handler)(struct cphy *phy); 472 473 int (*autoneg_enable)(struct cphy *phy); 474 int (*autoneg_restart)(struct cphy *phy); 475 476 int (*advertise)(struct cphy *phy, unsigned int advertise_map); 477 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); 478 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 479 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, 480 int *duplex, int *fc); 481 int (*power_down)(struct cphy *phy, int enable); 482 }; 483 484 /* A PHY instance */ 485 struct cphy { 486 int addr; /* PHY address */ 487 adapter_t *adapter; /* associated adapter */ 488 unsigned long fifo_errors; /* FIFO over/under-flows */ 489 const struct cphy_ops *ops; /* PHY operations */ 490 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, 491 int reg_addr, unsigned int *val); 492 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr, 493 int reg_addr, unsigned int val); 494 }; 495 496 /* Convenience MDIO read/write wrappers */ 497 static inline int mdio_read(struct cphy *phy, int mmd, int reg, 498 unsigned int *valp) 499 { 500 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp); 501 } 502 503 static inline int mdio_write(struct cphy *phy, int mmd, int reg, 504 unsigned int val) 505 { 506 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val); 507 } 508 509 /* Convenience initializer */ 510 static inline void cphy_init(struct cphy *phy, adapter_t *adapter, 511 int phy_addr, struct cphy_ops *phy_ops, 512 const struct mdio_ops *mdio_ops) 513 { 514 phy->adapter = adapter; 515 phy->addr = phy_addr; 516 phy->ops = phy_ops; 517 if (mdio_ops) { 518 phy->mdio_read = mdio_ops->read; 519 phy->mdio_write = mdio_ops->write; 520 } 521 } 522 523 /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ 524 #define MAC_STATS_ACCUM_SECS 180 525 526 #define XGM_REG(reg_addr, idx) \ 527 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) 528 529 struct addr_val_pair { 530 unsigned int reg_addr; 531 unsigned int val; 532 }; 533 534 #include <dev/cxgb/cxgb_adapter.h> 535 536 #ifndef PCI_VENDOR_ID_CHELSIO 537 # define PCI_VENDOR_ID_CHELSIO 0x1425 538 #endif 539 540 #define for_each_port(adapter, iter) \ 541 for (iter = 0; iter < (adapter)->params.nports; ++iter) 542 543 #define adapter_info(adap) ((adap)->params.info) 544 545 static inline int uses_xaui(const adapter_t *adap) 546 { 547 return adapter_info(adap)->caps & SUPPORTED_AUI; 548 } 549 550 static inline int is_10G(const adapter_t *adap) 551 { 552 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; 553 } 554 555 static inline int is_offload(const adapter_t *adap) 556 { 557 #ifdef CONFIG_CHELSIO_T3_CORE 558 return adapter_info(adap)->caps & SUPPORTED_OFFLOAD; 559 #else 560 return 0; 561 #endif 562 } 563 564 static inline unsigned int core_ticks_per_usec(const adapter_t *adap) 565 { 566 return adap->params.vpd.cclk / 1000; 567 } 568 569 static inline unsigned int dack_ticks_to_usec(const adapter_t *adap, 570 unsigned int ticks) 571 { 572 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 573 } 574 575 static inline unsigned int is_pcie(const adapter_t *adap) 576 { 577 return adap->params.pci.variant == PCI_VARIANT_PCIE; 578 } 579 580 void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val); 581 void t3_read_indirect(adapter_t *adap, unsigned int addr_reg, 582 unsigned int data_reg, u32 *vals, unsigned int nregs, 583 unsigned int start_idx); 584 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, 585 unsigned int offset); 586 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, 587 int attempts, int delay, u32 *valp); 588 589 static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask, 590 int polarity, int attempts, int delay) 591 { 592 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, 593 delay, NULL); 594 } 595 596 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, 597 unsigned int set); 598 int t3_phy_reset(struct cphy *phy, int mmd, int wait); 599 int t3_phy_advertise(struct cphy *phy, unsigned int advert); 600 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); 601 602 void t3_intr_enable(adapter_t *adapter); 603 void t3_intr_disable(adapter_t *adapter); 604 void t3_intr_clear(adapter_t *adapter); 605 void t3_port_intr_enable(adapter_t *adapter, int idx); 606 void t3_port_intr_disable(adapter_t *adapter, int idx); 607 void t3_port_intr_clear(adapter_t *adapter, int idx); 608 int t3_slow_intr_handler(adapter_t *adapter); 609 int t3_phy_intr_handler(adapter_t *adapter); 610 611 void t3_link_changed(adapter_t *adapter, int port_id); 612 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 613 const struct adapter_info *t3_get_adapter_info(unsigned int board_id); 614 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data); 615 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data); 616 int t3_seeprom_wp(adapter_t *adapter, int enable); 617 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, 618 u32 *data, int byte_oriented); 619 int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size); 620 int t3_get_fw_version(adapter_t *adapter, u32 *vers); 621 int t3_check_fw_version(adapter_t *adapter); 622 int t3_init_hw(adapter_t *adapter, u32 fw_params); 623 void mac_prep(struct cmac *mac, adapter_t *adapter, int index); 624 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai); 625 int t3_reset_adapter(adapter_t *adapter); 626 int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset); 627 void t3_led_ready(adapter_t *adapter); 628 void t3_fatal_err(adapter_t *adapter); 629 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on); 630 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, 631 const u16 *rspq); 632 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map); 633 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask); 634 void t3_port_failover(adapter_t *adapter, int port); 635 void t3_failover_done(adapter_t *adapter, int port); 636 void t3_failover_clear(adapter_t *adapter); 637 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n, 638 unsigned int *valp); 639 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, 640 u64 *buf); 641 642 int t3_mac_reset(struct cmac *mac); 643 void t3b_pcs_reset(struct cmac *mac); 644 int t3_mac_enable(struct cmac *mac, int which); 645 int t3_mac_disable(struct cmac *mac, int which); 646 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); 647 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); 648 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); 649 int t3_mac_set_num_ucast(struct cmac *mac, int n); 650 const struct mac_stats *t3_mac_update_stats(struct cmac *mac); 651 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, 652 int fc); 653 int t3b2_mac_watchdog_task(struct cmac *mac); 654 655 void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode); 656 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 657 unsigned int nroutes); 658 void t3_mc5_intr_handler(struct mc5 *mc5); 659 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, 660 u32 *buf); 661 662 #ifdef CONFIG_CHELSIO_T3_CORE 663 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh); 664 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size); 665 void t3_tp_set_offload_mode(adapter_t *adap, int enable); 666 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps); 667 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS], 668 unsigned short alpha[NCCTRL_WIN], 669 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); 670 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]); 671 void t3_get_cong_cntl_tab(adapter_t *adap, 672 unsigned short incr[NMTUS][NCCTRL_WIN]); 673 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, 674 int filter_index, int invert, int enable); 675 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched); 676 int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg); 677 void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps, 678 unsigned int *ipg); 679 void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]); 680 void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals, 681 unsigned int start, unsigned int n); 682 #endif 683 684 void t3_sge_prep(adapter_t *adap, struct sge_params *p); 685 void t3_sge_init(adapter_t *adap, struct sge_params *p); 686 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, 687 enum sge_context_type type, int respq, u64 base_addr, 688 unsigned int size, unsigned int token, int gen, 689 unsigned int cidx); 690 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, 691 u64 base_addr, unsigned int size, unsigned int esize, 692 unsigned int cong_thres, int gen, unsigned int cidx); 693 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, 694 u64 base_addr, unsigned int size, 695 unsigned int fl_thres, int gen, unsigned int cidx); 696 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, 697 unsigned int size, int rspq, int ovfl_mode, 698 unsigned int credits, unsigned int credit_thres); 699 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable); 700 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id); 701 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id); 702 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id); 703 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]); 704 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]); 705 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]); 706 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]); 707 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, 708 unsigned int credits); 709 710 void t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 711 const struct mdio_ops *mdio_ops); 712 void t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 713 const struct mdio_ops *mdio_ops); 714 void t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 715 const struct mdio_ops *mdio_ops); 716 void t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 717 const struct mdio_ops *mdio_ops); 718 void t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 719 const struct mdio_ops *mdio_ops); 720 void t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr, 721 const struct mdio_ops *mdio_ops); 722 #endif /* __CHELSIO_COMMON_H */ 723