1 /************************************************************************** 2 SPDX-License-Identifier: BSD-2-Clause 3 4 Copyright (c) 2007-2009, Chelsio Inc. 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Neither the name of the Chelsio Corporation nor the names of its 14 contributors may be used to endorse or promote products derived from 15 this software without specific prior written permission. 16 17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 POSSIBILITY OF SUCH DAMAGE. 28 29 $FreeBSD$ 30 31 ***************************************************************************/ 32 #ifndef __CHELSIO_COMMON_H 33 #define __CHELSIO_COMMON_H 34 35 #include <cxgb_osdep.h> 36 37 enum { 38 MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */ 39 EEPROMSIZE = 8192, /* Serial EEPROM size */ 40 SERNUM_LEN = 16, /* Serial # length */ 41 ECNUM_LEN = 16, /* EC # length */ 42 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ 43 TCB_SIZE = 128, /* TCB size */ 44 NMTUS = 16, /* size of MTU table */ 45 NCCTRL_WIN = 32, /* # of congestion control windows */ 46 NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 47 PROTO_SRAM_LINES = 128, /* size of protocol sram */ 48 EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */ 49 }; 50 51 #define MAX_RX_COALESCING_LEN 12288U 52 53 enum { 54 PAUSE_RX = 1 << 0, 55 PAUSE_TX = 1 << 1, 56 PAUSE_AUTONEG = 1 << 2 57 }; 58 59 enum { 60 SUPPORTED_LINK_IRQ = 1 << 24, 61 /* skip 25 */ 62 SUPPORTED_MISC_IRQ = 1 << 26, 63 SUPPORTED_IRQ = (SUPPORTED_LINK_IRQ | SUPPORTED_MISC_IRQ), 64 }; 65 66 enum { /* adapter interrupt-maintained statistics */ 67 STAT_ULP_CH0_PBL_OOB, 68 STAT_ULP_CH1_PBL_OOB, 69 STAT_PCI_CORR_ECC, 70 71 IRQ_NUM_STATS /* keep last */ 72 }; 73 74 enum { 75 TP_VERSION_MAJOR = 1, 76 TP_VERSION_MINOR = 1, 77 TP_VERSION_MICRO = 0 78 }; 79 80 #define S_TP_VERSION_MAJOR 16 81 #define M_TP_VERSION_MAJOR 0xFF 82 #define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) 83 #define G_TP_VERSION_MAJOR(x) \ 84 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR) 85 86 #define S_TP_VERSION_MINOR 8 87 #define M_TP_VERSION_MINOR 0xFF 88 #define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) 89 #define G_TP_VERSION_MINOR(x) \ 90 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR) 91 92 #define S_TP_VERSION_MICRO 0 93 #define M_TP_VERSION_MICRO 0xFF 94 #define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) 95 #define G_TP_VERSION_MICRO(x) \ 96 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) 97 98 enum { 99 FW_VERSION_MAJOR = 7, 100 FW_VERSION_MINOR = 11, 101 FW_VERSION_MICRO = 0 102 }; 103 104 enum { 105 LA_CTRL = 0x80, 106 LA_DATA = 0x84, 107 LA_ENTRIES = 512 108 }; 109 110 enum { 111 IOQ_ENTRIES = 7 112 }; 113 114 enum { 115 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 116 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 117 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 118 }; 119 120 enum sge_context_type { /* SGE egress context types */ 121 SGE_CNTXT_RDMA = 0, 122 SGE_CNTXT_ETH = 2, 123 SGE_CNTXT_OFLD = 4, 124 SGE_CNTXT_CTRL = 5 125 }; 126 127 enum { 128 AN_PKT_SIZE = 32, /* async notification packet size */ 129 IMMED_PKT_SIZE = 48 /* packet size for immediate data */ 130 }; 131 132 struct sg_ent { /* SGE scatter/gather entry */ 133 __be32 len[2]; 134 __be64 addr[2]; 135 }; 136 137 #ifndef SGE_NUM_GENBITS 138 /* Must be 1 or 2 */ 139 # define SGE_NUM_GENBITS 2 140 #endif 141 142 #define TX_DESC_FLITS 16U 143 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) 144 145 #define MAX_PHYINTRS 4 146 147 struct cphy; 148 149 struct mdio_ops { 150 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr, 151 int reg_addr, unsigned int *val); 152 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr, 153 int reg_addr, unsigned int val); 154 }; 155 156 struct adapter_info { 157 unsigned char nports0; /* # of ports on channel 0 */ 158 unsigned char nports1; /* # of ports on channel 1 */ 159 unsigned char phy_base_addr; /* MDIO PHY base address */ 160 unsigned int gpio_out; /* GPIO output settings */ 161 unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */ 162 unsigned long caps; /* adapter capabilities */ 163 const struct mdio_ops *mdio_ops; /* MDIO operations */ 164 const char *desc; /* product description */ 165 }; 166 167 struct mc5_stats { 168 unsigned long parity_err; 169 unsigned long active_rgn_full; 170 unsigned long nfa_srch_err; 171 unsigned long unknown_cmd; 172 unsigned long reqq_parity_err; 173 unsigned long dispq_parity_err; 174 unsigned long del_act_empty; 175 }; 176 177 struct mc7_stats { 178 unsigned long corr_err; 179 unsigned long uncorr_err; 180 unsigned long parity_err; 181 unsigned long addr_err; 182 }; 183 184 struct mac_stats { 185 u64 tx_octets; /* total # of octets in good frames */ 186 u64 tx_octets_bad; /* total # of octets in error frames */ 187 u64 tx_frames; /* all good frames */ 188 u64 tx_mcast_frames; /* good multicast frames */ 189 u64 tx_bcast_frames; /* good broadcast frames */ 190 u64 tx_pause; /* # of transmitted pause frames */ 191 u64 tx_deferred; /* frames with deferred transmissions */ 192 u64 tx_late_collisions; /* # of late collisions */ 193 u64 tx_total_collisions; /* # of total collisions */ 194 u64 tx_excess_collisions; /* frame errors from excessive collisions */ 195 u64 tx_underrun; /* # of Tx FIFO underruns */ 196 u64 tx_len_errs; /* # of Tx length errors */ 197 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ 198 u64 tx_excess_deferral; /* # of frames with excessive deferral */ 199 u64 tx_fcs_errs; /* # of frames with bad FCS */ 200 201 u64 tx_frames_64; /* # of Tx frames in a particular range */ 202 u64 tx_frames_65_127; 203 u64 tx_frames_128_255; 204 u64 tx_frames_256_511; 205 u64 tx_frames_512_1023; 206 u64 tx_frames_1024_1518; 207 u64 tx_frames_1519_max; 208 209 u64 rx_octets; /* total # of octets in good frames */ 210 u64 rx_octets_bad; /* total # of octets in error frames */ 211 u64 rx_frames; /* all good frames */ 212 u64 rx_mcast_frames; /* good multicast frames */ 213 u64 rx_bcast_frames; /* good broadcast frames */ 214 u64 rx_pause; /* # of received pause frames */ 215 u64 rx_fcs_errs; /* # of received frames with bad FCS */ 216 u64 rx_align_errs; /* alignment errors */ 217 u64 rx_symbol_errs; /* symbol errors */ 218 u64 rx_data_errs; /* data errors */ 219 u64 rx_sequence_errs; /* sequence errors */ 220 u64 rx_runt; /* # of runt frames */ 221 u64 rx_jabber; /* # of jabber frames */ 222 u64 rx_short; /* # of short frames */ 223 u64 rx_too_long; /* # of oversized frames */ 224 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ 225 226 u64 rx_frames_64; /* # of Rx frames in a particular range */ 227 u64 rx_frames_65_127; 228 u64 rx_frames_128_255; 229 u64 rx_frames_256_511; 230 u64 rx_frames_512_1023; 231 u64 rx_frames_1024_1518; 232 u64 rx_frames_1519_max; 233 234 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ 235 236 unsigned long tx_fifo_parity_err; 237 unsigned long rx_fifo_parity_err; 238 unsigned long tx_fifo_urun; 239 unsigned long rx_fifo_ovfl; 240 unsigned long serdes_signal_loss; 241 unsigned long xaui_pcs_ctc_err; 242 unsigned long xaui_pcs_align_change; 243 244 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ 245 unsigned long num_resets; /* # times reset due to stuck TX */ 246 247 unsigned long link_faults; /* # detected link faults */ 248 }; 249 250 struct tp_mib_stats { 251 u32 ipInReceive_hi; 252 u32 ipInReceive_lo; 253 u32 ipInHdrErrors_hi; 254 u32 ipInHdrErrors_lo; 255 u32 ipInAddrErrors_hi; 256 u32 ipInAddrErrors_lo; 257 u32 ipInUnknownProtos_hi; 258 u32 ipInUnknownProtos_lo; 259 u32 ipInDiscards_hi; 260 u32 ipInDiscards_lo; 261 u32 ipInDelivers_hi; 262 u32 ipInDelivers_lo; 263 u32 ipOutRequests_hi; 264 u32 ipOutRequests_lo; 265 u32 ipOutDiscards_hi; 266 u32 ipOutDiscards_lo; 267 u32 ipOutNoRoutes_hi; 268 u32 ipOutNoRoutes_lo; 269 u32 ipReasmTimeout; 270 u32 ipReasmReqds; 271 u32 ipReasmOKs; 272 u32 ipReasmFails; 273 274 u32 reserved[8]; 275 276 u32 tcpActiveOpens; 277 u32 tcpPassiveOpens; 278 u32 tcpAttemptFails; 279 u32 tcpEstabResets; 280 u32 tcpOutRsts; 281 u32 tcpCurrEstab; 282 u32 tcpInSegs_hi; 283 u32 tcpInSegs_lo; 284 u32 tcpOutSegs_hi; 285 u32 tcpOutSegs_lo; 286 u32 tcpRetransSeg_hi; 287 u32 tcpRetransSeg_lo; 288 u32 tcpInErrs_hi; 289 u32 tcpInErrs_lo; 290 u32 tcpRtoMin; 291 u32 tcpRtoMax; 292 }; 293 294 struct tp_params { 295 unsigned int nchan; /* # of channels */ 296 unsigned int pmrx_size; /* total PMRX capacity */ 297 unsigned int pmtx_size; /* total PMTX capacity */ 298 unsigned int cm_size; /* total CM capacity */ 299 unsigned int chan_rx_size; /* per channel Rx size */ 300 unsigned int chan_tx_size; /* per channel Tx size */ 301 unsigned int rx_pg_size; /* Rx page size */ 302 unsigned int tx_pg_size; /* Tx page size */ 303 unsigned int rx_num_pgs; /* # of Rx pages */ 304 unsigned int tx_num_pgs; /* # of Tx pages */ 305 unsigned int ntimer_qs; /* # of timer queues */ 306 unsigned int tre; /* log2 of core clocks per TP tick */ 307 unsigned int dack_re; /* DACK timer resolution */ 308 }; 309 310 struct qset_params { /* SGE queue set parameters */ 311 unsigned int polling; /* polling/interrupt service for rspq */ 312 unsigned int lro; /* large receive offload */ 313 unsigned int coalesce_usecs; /* irq coalescing timer */ 314 unsigned int rspq_size; /* # of entries in response queue */ 315 unsigned int fl_size; /* # of entries in regular free list */ 316 unsigned int jumbo_size; /* # of entries in jumbo free list */ 317 unsigned int jumbo_buf_size; /* buffer size of jumbo entry */ 318 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ 319 unsigned int cong_thres; /* FL congestion threshold */ 320 unsigned int vector; /* Interrupt (line or vector) number */ 321 }; 322 323 struct sge_params { 324 unsigned int max_pkt_size; /* max offload pkt size */ 325 struct qset_params qset[SGE_QSETS]; 326 }; 327 328 struct mc5_params { 329 unsigned int mode; /* selects MC5 width */ 330 unsigned int nservers; /* size of server region */ 331 unsigned int nfilters; /* size of filter region */ 332 unsigned int nroutes; /* size of routing region */ 333 }; 334 335 /* Default MC5 region sizes */ 336 enum { 337 DEFAULT_NSERVERS = 512, 338 DEFAULT_NFILTERS = 128 339 }; 340 341 /* MC5 modes, these must be non-0 */ 342 enum { 343 MC5_MODE_144_BIT = 1, 344 MC5_MODE_72_BIT = 2 345 }; 346 347 /* MC5 min active region size */ 348 enum { MC5_MIN_TIDS = 16 }; 349 350 struct vpd_params { 351 unsigned int cclk; 352 unsigned int mclk; 353 unsigned int uclk; 354 unsigned int mdc; 355 unsigned int mem_timing; 356 u8 sn[SERNUM_LEN + 1]; 357 u8 ec[ECNUM_LEN + 1]; 358 u8 eth_base[6]; 359 u8 port_type[MAX_NPORTS]; 360 unsigned short xauicfg[2]; 361 }; 362 363 struct generic_vpd { 364 u32 offset; 365 u32 len; 366 u8 *data; 367 }; 368 369 enum { MAX_VPD_BYTES = 32000 }; 370 371 struct pci_params { 372 unsigned int vpd_cap_addr; 373 unsigned int pcie_cap_addr; 374 unsigned short speed; 375 unsigned char width; 376 unsigned char variant; 377 }; 378 379 enum { 380 PCI_VARIANT_PCI, 381 PCI_VARIANT_PCIX_MODE1_PARITY, 382 PCI_VARIANT_PCIX_MODE1_ECC, 383 PCI_VARIANT_PCIX_266_MODE2, 384 PCI_VARIANT_PCIE 385 }; 386 387 struct adapter_params { 388 struct sge_params sge; 389 struct mc5_params mc5; 390 struct tp_params tp; 391 struct vpd_params vpd; 392 struct pci_params pci; 393 394 const struct adapter_info *info; 395 396 unsigned short mtus[NMTUS]; 397 unsigned short a_wnd[NCCTRL_WIN]; 398 unsigned short b_wnd[NCCTRL_WIN]; 399 unsigned int nports; /* # of ethernet ports */ 400 unsigned int chan_map; /* bitmap of in-use Tx channels */ 401 unsigned int stats_update_period; /* MAC stats accumulation period */ 402 unsigned int linkpoll_period; /* link poll period in 0.1s */ 403 unsigned int rev; /* chip revision */ 404 unsigned int offload; 405 }; 406 407 enum { /* chip revisions */ 408 T3_REV_A = 0, 409 T3_REV_B = 2, 410 T3_REV_B2 = 3, 411 T3_REV_C = 4, 412 }; 413 414 struct trace_params { 415 u32 sip; 416 u32 sip_mask; 417 u32 dip; 418 u32 dip_mask; 419 u16 sport; 420 u16 sport_mask; 421 u16 dport; 422 u16 dport_mask; 423 u32 vlan:12; 424 u32 vlan_mask:12; 425 u32 intf:4; 426 u32 intf_mask:4; 427 u8 proto; 428 u8 proto_mask; 429 }; 430 431 struct link_config { 432 unsigned int supported; /* link capabilities */ 433 unsigned int advertising; /* advertised capabilities */ 434 unsigned short requested_speed; /* speed user has requested */ 435 unsigned short speed; /* actual link speed */ 436 unsigned char requested_duplex; /* duplex user has requested */ 437 unsigned char duplex; /* actual link duplex */ 438 unsigned char requested_fc; /* flow control user has requested */ 439 unsigned char fc; /* actual link flow control */ 440 unsigned char autoneg; /* autonegotiating? */ 441 unsigned int link_ok; /* link up? */ 442 }; 443 444 #define SPEED_INVALID 0xffff 445 #define DUPLEX_INVALID 0xff 446 447 struct mc5 { 448 adapter_t *adapter; 449 unsigned int tcam_size; 450 unsigned char part_type; 451 unsigned char parity_enabled; 452 unsigned char mode; 453 struct mc5_stats stats; 454 }; 455 456 static inline unsigned int t3_mc5_size(const struct mc5 *p) 457 { 458 return p->tcam_size; 459 } 460 461 struct mc7 { 462 adapter_t *adapter; /* backpointer to adapter */ 463 unsigned int size; /* memory size in bytes */ 464 unsigned int width; /* MC7 interface width */ 465 unsigned int offset; /* register address offset for MC7 instance */ 466 const char *name; /* name of MC7 instance */ 467 struct mc7_stats stats; /* MC7 statistics */ 468 }; 469 470 static inline unsigned int t3_mc7_size(const struct mc7 *p) 471 { 472 return p->size; 473 } 474 475 struct cmac { 476 adapter_t *adapter; 477 unsigned int offset; 478 unsigned char nucast; /* # of address filters for unicast MACs */ 479 unsigned char multiport; /* multiple ports connected to this MAC */ 480 unsigned char ext_port; /* external MAC port */ 481 unsigned char promisc_map; /* which external ports are promiscuous */ 482 unsigned int tx_tcnt; 483 unsigned int tx_xcnt; 484 u64 tx_mcnt; 485 unsigned int rx_xcnt; 486 unsigned int rx_ocnt; 487 u64 rx_mcnt; 488 unsigned int toggle_cnt; 489 unsigned int txen; 490 unsigned int was_reset; 491 u64 rx_pause; 492 struct mac_stats stats; 493 }; 494 495 enum { 496 MAC_DIRECTION_RX = 1, 497 MAC_DIRECTION_TX = 2, 498 MAC_RXFIFO_SIZE = 32768 499 }; 500 501 /* IEEE 802.3 specified MDIO devices */ 502 enum { 503 MDIO_DEV_PMA_PMD = 1, 504 MDIO_DEV_WIS = 2, 505 MDIO_DEV_PCS = 3, 506 MDIO_DEV_XGXS = 4, 507 MDIO_DEV_ANEG = 7, 508 MDIO_DEV_VEND1 = 30, 509 MDIO_DEV_VEND2 = 31 510 }; 511 512 /* LASI control and status registers */ 513 enum { 514 RX_ALARM_CTRL = 0x9000, 515 TX_ALARM_CTRL = 0x9001, 516 LASI_CTRL = 0x9002, 517 RX_ALARM_STAT = 0x9003, 518 TX_ALARM_STAT = 0x9004, 519 LASI_STAT = 0x9005 520 }; 521 522 /* PHY loopback direction */ 523 enum { 524 PHY_LOOPBACK_TX = 1, 525 PHY_LOOPBACK_RX = 2 526 }; 527 528 /* PHY interrupt types */ 529 enum { 530 cphy_cause_link_change = 1, 531 cphy_cause_fifo_error = 2, 532 cphy_cause_module_change = 4, 533 cphy_cause_alarm = 8, 534 }; 535 536 /* PHY module types */ 537 enum { 538 phy_modtype_none, 539 phy_modtype_sr, 540 phy_modtype_lr, 541 phy_modtype_lrm, 542 phy_modtype_twinax, 543 phy_modtype_twinax_long, 544 phy_modtype_unknown 545 }; 546 547 enum { 548 PHY_LINK_DOWN = 0, 549 PHY_LINK_UP, 550 PHY_LINK_PARTIAL 551 }; 552 553 /* PHY operations */ 554 struct cphy_ops { 555 int (*reset)(struct cphy *phy, int wait); 556 557 int (*intr_enable)(struct cphy *phy); 558 int (*intr_disable)(struct cphy *phy); 559 int (*intr_clear)(struct cphy *phy); 560 int (*intr_handler)(struct cphy *phy); 561 562 int (*autoneg_enable)(struct cphy *phy); 563 int (*autoneg_restart)(struct cphy *phy); 564 565 int (*advertise)(struct cphy *phy, unsigned int advertise_map); 566 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); 567 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 568 int (*get_link_status)(struct cphy *phy, int *link_state, int *speed, 569 int *duplex, int *fc); 570 int (*power_down)(struct cphy *phy, int enable); 571 }; 572 573 /* A PHY instance */ 574 struct cphy { 575 u8 addr; /* PHY address */ 576 u8 modtype; /* PHY module type */ 577 u8 rst; 578 unsigned int priv; /* scratch pad */ 579 unsigned int caps; /* PHY capabilities */ 580 adapter_t *adapter; /* associated adapter */ 581 pinfo_t *pinfo; /* associated port */ 582 const char *desc; /* PHY description */ 583 unsigned long fifo_errors; /* FIFO over/under-flows */ 584 const struct cphy_ops *ops; /* PHY operations */ 585 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, 586 int reg_addr, unsigned int *val); 587 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr, 588 int reg_addr, unsigned int val); 589 }; 590 591 /* Convenience MDIO read/write wrappers */ 592 static inline int mdio_read(struct cphy *phy, int mmd, int reg, 593 unsigned int *valp) 594 { 595 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp); 596 } 597 598 static inline int mdio_write(struct cphy *phy, int mmd, int reg, 599 unsigned int val) 600 { 601 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val); 602 } 603 604 /* Convenience initializer */ 605 static inline void cphy_init(struct cphy *phy, adapter_t *adapter, pinfo_t *pinfo, 606 int phy_addr, struct cphy_ops *phy_ops, 607 const struct mdio_ops *mdio_ops, unsigned int caps, 608 const char *desc) 609 { 610 phy->addr = (u8)phy_addr; 611 phy->caps = caps; 612 phy->adapter = adapter; 613 phy->pinfo = pinfo; 614 phy->desc = desc; 615 phy->ops = phy_ops; 616 if (mdio_ops) { 617 phy->mdio_read = mdio_ops->read; 618 phy->mdio_write = mdio_ops->write; 619 } 620 } 621 622 /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ 623 #define MAC_STATS_ACCUM_SECS 180 624 625 /* The external MAC needs accumulation every 30 seconds */ 626 #define VSC_STATS_ACCUM_SECS 30 627 628 #define XGM_REG(reg_addr, idx) \ 629 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) 630 631 struct addr_val_pair { 632 unsigned int reg_addr; 633 unsigned int val; 634 }; 635 636 #include <cxgb_adapter.h> 637 638 #ifndef PCI_VENDOR_ID_CHELSIO 639 # define PCI_VENDOR_ID_CHELSIO 0x1425 640 #endif 641 642 #define for_each_port(adapter, iter) \ 643 for (iter = 0; iter < (adapter)->params.nports; ++iter) 644 645 #define adapter_info(adap) ((adap)->params.info) 646 647 static inline int uses_xaui(const adapter_t *adap) 648 { 649 return adapter_info(adap)->caps & SUPPORTED_AUI; 650 } 651 652 static inline int is_10G(const adapter_t *adap) 653 { 654 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; 655 } 656 657 static inline int is_offload(const adapter_t *adap) 658 { 659 return adap->params.offload; 660 } 661 662 static inline unsigned int core_ticks_per_usec(const adapter_t *adap) 663 { 664 return adap->params.vpd.cclk / 1000; 665 } 666 667 static inline unsigned int dack_ticks_to_usec(const adapter_t *adap, 668 unsigned int ticks) 669 { 670 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 671 } 672 673 static inline unsigned int is_pcie(const adapter_t *adap) 674 { 675 return adap->params.pci.variant == PCI_VARIANT_PCIE; 676 } 677 678 void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val); 679 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, 680 unsigned int offset); 681 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, 682 int attempts, int delay, u32 *valp); 683 684 static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask, 685 int polarity, int attempts, int delay) 686 { 687 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, 688 delay, NULL); 689 } 690 691 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, 692 unsigned int set); 693 int t3_phy_reset(struct cphy *phy, int mmd, int wait); 694 int t3_phy_advertise(struct cphy *phy, unsigned int advert); 695 int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert); 696 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); 697 int t3_phy_lasi_intr_enable(struct cphy *phy); 698 int t3_phy_lasi_intr_disable(struct cphy *phy); 699 int t3_phy_lasi_intr_clear(struct cphy *phy); 700 int t3_phy_lasi_intr_handler(struct cphy *phy); 701 702 void t3_intr_enable(adapter_t *adapter); 703 void t3_intr_disable(adapter_t *adapter); 704 void t3_intr_clear(adapter_t *adapter); 705 void t3_xgm_intr_enable(adapter_t *adapter, int idx); 706 void t3_xgm_intr_disable(adapter_t *adapter, int idx); 707 void t3_port_intr_enable(adapter_t *adapter, int idx); 708 void t3_port_intr_disable(adapter_t *adapter, int idx); 709 void t3_port_intr_clear(adapter_t *adapter, int idx); 710 int t3_slow_intr_handler(adapter_t *adapter); 711 712 void t3_link_changed(adapter_t *adapter, int port_id); 713 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 714 const struct adapter_info *t3_get_adapter_info(unsigned int board_id); 715 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data); 716 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data); 717 int t3_seeprom_wp(adapter_t *adapter, int enable); 718 int t3_get_vpd_len(adapter_t *adapter, struct generic_vpd *vpd); 719 int t3_read_vpd(adapter_t *adapter, struct generic_vpd *vpd); 720 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, 721 u32 *data, int byte_oriented); 722 int t3_get_tp_version(adapter_t *adapter, u32 *vers); 723 int t3_check_tpsram_version(adapter_t *adapter); 724 int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size); 725 int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size); 726 int t3_get_fw_version(adapter_t *adapter, u32 *vers); 727 int t3_check_fw_version(adapter_t *adapter); 728 int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size); 729 int t3_init_hw(adapter_t *adapter, u32 fw_params); 730 void mac_prep(struct cmac *mac, adapter_t *adapter, int index); 731 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai); 732 int t3_reset_adapter(adapter_t *adapter); 733 int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset); 734 int t3_reinit_adapter(adapter_t *adap); 735 void t3_led_ready(adapter_t *adapter); 736 void t3_fatal_err(adapter_t *adapter); 737 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on); 738 void t3_enable_filters(adapter_t *adap); 739 void t3_disable_filters(adapter_t *adap); 740 void t3_tp_set_offload_mode(adapter_t *adap, int enable); 741 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, 742 const u16 *rspq); 743 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map); 744 int t3_set_proto_sram(adapter_t *adap, const u8 *data); 745 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask); 746 void t3_port_failover(adapter_t *adapter, int port); 747 void t3_failover_done(adapter_t *adapter, int port); 748 void t3_failover_clear(adapter_t *adapter); 749 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n, 750 unsigned int *valp); 751 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, 752 u64 *buf); 753 754 int t3_mac_init(struct cmac *mac); 755 void t3b_pcs_reset(struct cmac *mac); 756 void t3c_pcs_force_los(struct cmac *mac); 757 void t3_mac_disable_exact_filters(struct cmac *mac); 758 void t3_mac_enable_exact_filters(struct cmac *mac); 759 int t3_mac_enable(struct cmac *mac, int which); 760 int t3_mac_disable(struct cmac *mac, int which); 761 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); 762 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); 763 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); 764 int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n); 765 const struct mac_stats *t3_mac_update_stats(struct cmac *mac); 766 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, 767 int fc); 768 int t3b2_mac_watchdog_task(struct cmac *mac); 769 770 void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode); 771 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 772 unsigned int nroutes); 773 void t3_mc5_intr_handler(struct mc5 *mc5); 774 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, 775 u32 *buf); 776 777 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh); 778 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size); 779 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps); 780 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS], 781 unsigned short alpha[NCCTRL_WIN], 782 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); 783 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]); 784 void t3_get_cong_cntl_tab(adapter_t *adap, 785 unsigned short incr[NMTUS][NCCTRL_WIN]); 786 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, 787 int filter_index, int invert, int enable); 788 void t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp, 789 int filter_index, int *inverted, int *enabled); 790 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched); 791 int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg); 792 void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps, 793 unsigned int *ipg); 794 void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]); 795 void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals, 796 unsigned int start, unsigned int n); 797 798 int t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index, 799 u32 *size, void *data); 800 int t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data); 801 802 void t3_sge_prep(adapter_t *adap, struct sge_params *p); 803 void t3_sge_init(adapter_t *adap, struct sge_params *p); 804 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, 805 enum sge_context_type type, int respq, u64 base_addr, 806 unsigned int size, unsigned int token, int gen, 807 unsigned int cidx); 808 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, 809 u64 base_addr, unsigned int size, unsigned int esize, 810 unsigned int cong_thres, int gen, unsigned int cidx); 811 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, 812 u64 base_addr, unsigned int size, 813 unsigned int fl_thres, int gen, unsigned int cidx); 814 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, 815 unsigned int size, int rspq, int ovfl_mode, 816 unsigned int credits, unsigned int credit_thres); 817 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable); 818 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id); 819 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id); 820 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id); 821 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]); 822 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]); 823 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]); 824 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]); 825 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, 826 unsigned int credits); 827 828 int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n); 829 int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n); 830 int t3_vsc7323_init(adapter_t *adap, int nports); 831 int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port); 832 int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port); 833 int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port); 834 int t3_vsc7323_enable(adapter_t *adap, int port, int which); 835 int t3_vsc7323_disable(adapter_t *adap, int port, int which); 836 const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac); 837 838 int t3_i2c_read8(adapter_t *adapter, int chained, u8 *valp); 839 int t3_i2c_write8(adapter_t *adapter, int chained, u8 val); 840 841 int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, 842 unsigned int *valp); 843 int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, 844 unsigned int val); 845 846 int t3_mv88e1xxx_phy_prep(pinfo_t *pinfo, int phy_addr, 847 const struct mdio_ops *mdio_ops); 848 int t3_vsc8211_phy_prep(pinfo_t *pinfo, int phy_addr, 849 const struct mdio_ops *mdio_ops); 850 int t3_vsc8211_fifo_depth(adapter_t *adap, unsigned int mtu, int port); 851 int t3_ael1002_phy_prep(pinfo_t *pinfo, int phy_addr, 852 const struct mdio_ops *mdio_ops); 853 int t3_ael1006_phy_prep(pinfo_t *pinfo, int phy_addr, 854 const struct mdio_ops *mdio_ops); 855 int t3_ael2005_phy_prep(pinfo_t *pinfo, int phy_addr, 856 const struct mdio_ops *mdio_ops); 857 int t3_ael2020_phy_prep(pinfo_t *pinfo, int phy_addr, 858 const struct mdio_ops *mdio_ops); 859 int t3_qt2045_phy_prep(pinfo_t *pinfo, int phy_addr, 860 const struct mdio_ops *mdio_ops); 861 int t3_tn1010_phy_prep(pinfo_t *pinfo, int phy_addr, 862 const struct mdio_ops *mdio_ops); 863 int t3_xaui_direct_phy_prep(pinfo_t *pinfo, int phy_addr, 864 const struct mdio_ops *mdio_ops); 865 int t3_aq100x_phy_prep(pinfo_t *pinfo, int phy_addr, 866 const struct mdio_ops *mdio_ops); 867 #endif /* __CHELSIO_COMMON_H */ 868