1 /************************************************************************** 2 SPDX-License-Identifier: BSD-2-Clause 3 4 Copyright (c) 2007-2009, Chelsio Inc. 5 All rights reserved. 6 7 Redistribution and use in source and binary forms, with or without 8 modification, are permitted provided that the following conditions are met: 9 10 1. Redistributions of source code must retain the above copyright notice, 11 this list of conditions and the following disclaimer. 12 13 2. Neither the name of the Chelsio Corporation nor the names of its 14 contributors may be used to endorse or promote products derived from 15 this software without specific prior written permission. 16 17 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 18 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 21 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 22 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 23 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 24 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 25 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 26 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 27 POSSIBILITY OF SUCH DAMAGE. 28 29 ***************************************************************************/ 30 #ifndef __CHELSIO_COMMON_H 31 #define __CHELSIO_COMMON_H 32 33 #include <cxgb_osdep.h> 34 35 enum { 36 MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */ 37 EEPROMSIZE = 8192, /* Serial EEPROM size */ 38 SERNUM_LEN = 16, /* Serial # length */ 39 ECNUM_LEN = 16, /* EC # length */ 40 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ 41 TCB_SIZE = 128, /* TCB size */ 42 NMTUS = 16, /* size of MTU table */ 43 NCCTRL_WIN = 32, /* # of congestion control windows */ 44 NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 45 PROTO_SRAM_LINES = 128, /* size of protocol sram */ 46 EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */ 47 }; 48 49 #define MAX_RX_COALESCING_LEN 12288U 50 51 enum { 52 PAUSE_RX = 1 << 0, 53 PAUSE_TX = 1 << 1, 54 PAUSE_AUTONEG = 1 << 2 55 }; 56 57 enum { 58 SUPPORTED_LINK_IRQ = 1 << 24, 59 /* skip 25 */ 60 SUPPORTED_MISC_IRQ = 1 << 26, 61 SUPPORTED_IRQ = (SUPPORTED_LINK_IRQ | SUPPORTED_MISC_IRQ), 62 }; 63 64 enum { /* adapter interrupt-maintained statistics */ 65 STAT_ULP_CH0_PBL_OOB, 66 STAT_ULP_CH1_PBL_OOB, 67 STAT_PCI_CORR_ECC, 68 69 IRQ_NUM_STATS /* keep last */ 70 }; 71 72 enum { 73 TP_VERSION_MAJOR = 1, 74 TP_VERSION_MINOR = 1, 75 TP_VERSION_MICRO = 0 76 }; 77 78 #define S_TP_VERSION_MAJOR 16 79 #define M_TP_VERSION_MAJOR 0xFF 80 #define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) 81 #define G_TP_VERSION_MAJOR(x) \ 82 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR) 83 84 #define S_TP_VERSION_MINOR 8 85 #define M_TP_VERSION_MINOR 0xFF 86 #define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) 87 #define G_TP_VERSION_MINOR(x) \ 88 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR) 89 90 #define S_TP_VERSION_MICRO 0 91 #define M_TP_VERSION_MICRO 0xFF 92 #define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) 93 #define G_TP_VERSION_MICRO(x) \ 94 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) 95 96 enum { 97 FW_VERSION_MAJOR = 7, 98 FW_VERSION_MINOR = 11, 99 FW_VERSION_MICRO = 0 100 }; 101 102 enum { 103 LA_CTRL = 0x80, 104 LA_DATA = 0x84, 105 LA_ENTRIES = 512 106 }; 107 108 enum { 109 IOQ_ENTRIES = 7 110 }; 111 112 enum { 113 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 114 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 115 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 116 }; 117 118 enum sge_context_type { /* SGE egress context types */ 119 SGE_CNTXT_RDMA = 0, 120 SGE_CNTXT_ETH = 2, 121 SGE_CNTXT_OFLD = 4, 122 SGE_CNTXT_CTRL = 5 123 }; 124 125 enum { 126 AN_PKT_SIZE = 32, /* async notification packet size */ 127 IMMED_PKT_SIZE = 48 /* packet size for immediate data */ 128 }; 129 130 struct sg_ent { /* SGE scatter/gather entry */ 131 __be32 len[2]; 132 __be64 addr[2]; 133 }; 134 135 #ifndef SGE_NUM_GENBITS 136 /* Must be 1 or 2 */ 137 # define SGE_NUM_GENBITS 2 138 #endif 139 140 #define TX_DESC_FLITS 16U 141 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) 142 143 #define MAX_PHYINTRS 4 144 145 struct cphy; 146 147 struct mdio_ops { 148 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr, 149 int reg_addr, unsigned int *val); 150 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr, 151 int reg_addr, unsigned int val); 152 }; 153 154 struct adapter_info { 155 unsigned char nports0; /* # of ports on channel 0 */ 156 unsigned char nports1; /* # of ports on channel 1 */ 157 unsigned char phy_base_addr; /* MDIO PHY base address */ 158 unsigned int gpio_out; /* GPIO output settings */ 159 unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */ 160 unsigned long caps; /* adapter capabilities */ 161 const struct mdio_ops *mdio_ops; /* MDIO operations */ 162 const char *desc; /* product description */ 163 }; 164 165 struct mc5_stats { 166 unsigned long parity_err; 167 unsigned long active_rgn_full; 168 unsigned long nfa_srch_err; 169 unsigned long unknown_cmd; 170 unsigned long reqq_parity_err; 171 unsigned long dispq_parity_err; 172 unsigned long del_act_empty; 173 }; 174 175 struct mc7_stats { 176 unsigned long corr_err; 177 unsigned long uncorr_err; 178 unsigned long parity_err; 179 unsigned long addr_err; 180 }; 181 182 struct mac_stats { 183 u64 tx_octets; /* total # of octets in good frames */ 184 u64 tx_octets_bad; /* total # of octets in error frames */ 185 u64 tx_frames; /* all good frames */ 186 u64 tx_mcast_frames; /* good multicast frames */ 187 u64 tx_bcast_frames; /* good broadcast frames */ 188 u64 tx_pause; /* # of transmitted pause frames */ 189 u64 tx_deferred; /* frames with deferred transmissions */ 190 u64 tx_late_collisions; /* # of late collisions */ 191 u64 tx_total_collisions; /* # of total collisions */ 192 u64 tx_excess_collisions; /* frame errors from excessive collisions */ 193 u64 tx_underrun; /* # of Tx FIFO underruns */ 194 u64 tx_len_errs; /* # of Tx length errors */ 195 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ 196 u64 tx_excess_deferral; /* # of frames with excessive deferral */ 197 u64 tx_fcs_errs; /* # of frames with bad FCS */ 198 199 u64 tx_frames_64; /* # of Tx frames in a particular range */ 200 u64 tx_frames_65_127; 201 u64 tx_frames_128_255; 202 u64 tx_frames_256_511; 203 u64 tx_frames_512_1023; 204 u64 tx_frames_1024_1518; 205 u64 tx_frames_1519_max; 206 207 u64 rx_octets; /* total # of octets in good frames */ 208 u64 rx_octets_bad; /* total # of octets in error frames */ 209 u64 rx_frames; /* all good frames */ 210 u64 rx_mcast_frames; /* good multicast frames */ 211 u64 rx_bcast_frames; /* good broadcast frames */ 212 u64 rx_pause; /* # of received pause frames */ 213 u64 rx_fcs_errs; /* # of received frames with bad FCS */ 214 u64 rx_align_errs; /* alignment errors */ 215 u64 rx_symbol_errs; /* symbol errors */ 216 u64 rx_data_errs; /* data errors */ 217 u64 rx_sequence_errs; /* sequence errors */ 218 u64 rx_runt; /* # of runt frames */ 219 u64 rx_jabber; /* # of jabber frames */ 220 u64 rx_short; /* # of short frames */ 221 u64 rx_too_long; /* # of oversized frames */ 222 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ 223 224 u64 rx_frames_64; /* # of Rx frames in a particular range */ 225 u64 rx_frames_65_127; 226 u64 rx_frames_128_255; 227 u64 rx_frames_256_511; 228 u64 rx_frames_512_1023; 229 u64 rx_frames_1024_1518; 230 u64 rx_frames_1519_max; 231 232 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ 233 234 unsigned long tx_fifo_parity_err; 235 unsigned long rx_fifo_parity_err; 236 unsigned long tx_fifo_urun; 237 unsigned long rx_fifo_ovfl; 238 unsigned long serdes_signal_loss; 239 unsigned long xaui_pcs_ctc_err; 240 unsigned long xaui_pcs_align_change; 241 242 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ 243 unsigned long num_resets; /* # times reset due to stuck TX */ 244 245 unsigned long link_faults; /* # detected link faults */ 246 }; 247 248 struct tp_mib_stats { 249 u32 ipInReceive_hi; 250 u32 ipInReceive_lo; 251 u32 ipInHdrErrors_hi; 252 u32 ipInHdrErrors_lo; 253 u32 ipInAddrErrors_hi; 254 u32 ipInAddrErrors_lo; 255 u32 ipInUnknownProtos_hi; 256 u32 ipInUnknownProtos_lo; 257 u32 ipInDiscards_hi; 258 u32 ipInDiscards_lo; 259 u32 ipInDelivers_hi; 260 u32 ipInDelivers_lo; 261 u32 ipOutRequests_hi; 262 u32 ipOutRequests_lo; 263 u32 ipOutDiscards_hi; 264 u32 ipOutDiscards_lo; 265 u32 ipOutNoRoutes_hi; 266 u32 ipOutNoRoutes_lo; 267 u32 ipReasmTimeout; 268 u32 ipReasmReqds; 269 u32 ipReasmOKs; 270 u32 ipReasmFails; 271 272 u32 reserved[8]; 273 274 u32 tcpActiveOpens; 275 u32 tcpPassiveOpens; 276 u32 tcpAttemptFails; 277 u32 tcpEstabResets; 278 u32 tcpOutRsts; 279 u32 tcpCurrEstab; 280 u32 tcpInSegs_hi; 281 u32 tcpInSegs_lo; 282 u32 tcpOutSegs_hi; 283 u32 tcpOutSegs_lo; 284 u32 tcpRetransSeg_hi; 285 u32 tcpRetransSeg_lo; 286 u32 tcpInErrs_hi; 287 u32 tcpInErrs_lo; 288 u32 tcpRtoMin; 289 u32 tcpRtoMax; 290 }; 291 292 struct tp_params { 293 unsigned int nchan; /* # of channels */ 294 unsigned int pmrx_size; /* total PMRX capacity */ 295 unsigned int pmtx_size; /* total PMTX capacity */ 296 unsigned int cm_size; /* total CM capacity */ 297 unsigned int chan_rx_size; /* per channel Rx size */ 298 unsigned int chan_tx_size; /* per channel Tx size */ 299 unsigned int rx_pg_size; /* Rx page size */ 300 unsigned int tx_pg_size; /* Tx page size */ 301 unsigned int rx_num_pgs; /* # of Rx pages */ 302 unsigned int tx_num_pgs; /* # of Tx pages */ 303 unsigned int ntimer_qs; /* # of timer queues */ 304 unsigned int tre; /* log2 of core clocks per TP tick */ 305 unsigned int dack_re; /* DACK timer resolution */ 306 }; 307 308 struct qset_params { /* SGE queue set parameters */ 309 unsigned int polling; /* polling/interrupt service for rspq */ 310 unsigned int lro; /* large receive offload */ 311 unsigned int coalesce_usecs; /* irq coalescing timer */ 312 unsigned int rspq_size; /* # of entries in response queue */ 313 unsigned int fl_size; /* # of entries in regular free list */ 314 unsigned int jumbo_size; /* # of entries in jumbo free list */ 315 unsigned int jumbo_buf_size; /* buffer size of jumbo entry */ 316 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ 317 unsigned int cong_thres; /* FL congestion threshold */ 318 unsigned int vector; /* Interrupt (line or vector) number */ 319 }; 320 321 struct sge_params { 322 unsigned int max_pkt_size; /* max offload pkt size */ 323 struct qset_params qset[SGE_QSETS]; 324 }; 325 326 struct mc5_params { 327 unsigned int mode; /* selects MC5 width */ 328 unsigned int nservers; /* size of server region */ 329 unsigned int nfilters; /* size of filter region */ 330 unsigned int nroutes; /* size of routing region */ 331 }; 332 333 /* Default MC5 region sizes */ 334 enum { 335 DEFAULT_NSERVERS = 512, 336 DEFAULT_NFILTERS = 128 337 }; 338 339 /* MC5 modes, these must be non-0 */ 340 enum { 341 MC5_MODE_144_BIT = 1, 342 MC5_MODE_72_BIT = 2 343 }; 344 345 /* MC5 min active region size */ 346 enum { MC5_MIN_TIDS = 16 }; 347 348 struct vpd_params { 349 unsigned int cclk; 350 unsigned int mclk; 351 unsigned int uclk; 352 unsigned int mdc; 353 unsigned int mem_timing; 354 u8 sn[SERNUM_LEN + 1]; 355 u8 ec[ECNUM_LEN + 1]; 356 u8 eth_base[6]; 357 u8 port_type[MAX_NPORTS]; 358 unsigned short xauicfg[2]; 359 }; 360 361 struct generic_vpd { 362 u32 offset; 363 u32 len; 364 u8 *data; 365 }; 366 367 enum { MAX_VPD_BYTES = 32000 }; 368 369 struct pci_params { 370 unsigned int vpd_cap_addr; 371 unsigned int pcie_cap_addr; 372 unsigned short speed; 373 unsigned char width; 374 unsigned char variant; 375 }; 376 377 enum { 378 PCI_VARIANT_PCI, 379 PCI_VARIANT_PCIX_MODE1_PARITY, 380 PCI_VARIANT_PCIX_MODE1_ECC, 381 PCI_VARIANT_PCIX_266_MODE2, 382 PCI_VARIANT_PCIE 383 }; 384 385 struct adapter_params { 386 struct sge_params sge; 387 struct mc5_params mc5; 388 struct tp_params tp; 389 struct vpd_params vpd; 390 struct pci_params pci; 391 392 const struct adapter_info *info; 393 394 unsigned short mtus[NMTUS]; 395 unsigned short a_wnd[NCCTRL_WIN]; 396 unsigned short b_wnd[NCCTRL_WIN]; 397 unsigned int nports; /* # of ethernet ports */ 398 unsigned int chan_map; /* bitmap of in-use Tx channels */ 399 unsigned int stats_update_period; /* MAC stats accumulation period */ 400 unsigned int linkpoll_period; /* link poll period in 0.1s */ 401 unsigned int rev; /* chip revision */ 402 unsigned int offload; 403 }; 404 405 enum { /* chip revisions */ 406 T3_REV_A = 0, 407 T3_REV_B = 2, 408 T3_REV_B2 = 3, 409 T3_REV_C = 4, 410 }; 411 412 struct trace_params { 413 u32 sip; 414 u32 sip_mask; 415 u32 dip; 416 u32 dip_mask; 417 u16 sport; 418 u16 sport_mask; 419 u16 dport; 420 u16 dport_mask; 421 u32 vlan:12; 422 u32 vlan_mask:12; 423 u32 intf:4; 424 u32 intf_mask:4; 425 u8 proto; 426 u8 proto_mask; 427 }; 428 429 struct link_config { 430 unsigned int supported; /* link capabilities */ 431 unsigned int advertising; /* advertised capabilities */ 432 unsigned short requested_speed; /* speed user has requested */ 433 unsigned short speed; /* actual link speed */ 434 unsigned char requested_duplex; /* duplex user has requested */ 435 unsigned char duplex; /* actual link duplex */ 436 unsigned char requested_fc; /* flow control user has requested */ 437 unsigned char fc; /* actual link flow control */ 438 unsigned char autoneg; /* autonegotiating? */ 439 unsigned int link_ok; /* link up? */ 440 }; 441 442 #define SPEED_INVALID 0xffff 443 #define DUPLEX_INVALID 0xff 444 445 struct mc5 { 446 adapter_t *adapter; 447 unsigned int tcam_size; 448 unsigned char part_type; 449 unsigned char parity_enabled; 450 unsigned char mode; 451 struct mc5_stats stats; 452 }; 453 454 static inline unsigned int t3_mc5_size(const struct mc5 *p) 455 { 456 return p->tcam_size; 457 } 458 459 struct mc7 { 460 adapter_t *adapter; /* backpointer to adapter */ 461 unsigned int size; /* memory size in bytes */ 462 unsigned int width; /* MC7 interface width */ 463 unsigned int offset; /* register address offset for MC7 instance */ 464 const char *name; /* name of MC7 instance */ 465 struct mc7_stats stats; /* MC7 statistics */ 466 }; 467 468 static inline unsigned int t3_mc7_size(const struct mc7 *p) 469 { 470 return p->size; 471 } 472 473 struct cmac { 474 adapter_t *adapter; 475 unsigned int offset; 476 unsigned char nucast; /* # of address filters for unicast MACs */ 477 unsigned char multiport; /* multiple ports connected to this MAC */ 478 unsigned char ext_port; /* external MAC port */ 479 unsigned char promisc_map; /* which external ports are promiscuous */ 480 unsigned int tx_tcnt; 481 unsigned int tx_xcnt; 482 u64 tx_mcnt; 483 unsigned int rx_xcnt; 484 unsigned int rx_ocnt; 485 u64 rx_mcnt; 486 unsigned int toggle_cnt; 487 unsigned int txen; 488 unsigned int was_reset; 489 u64 rx_pause; 490 struct mac_stats stats; 491 }; 492 493 enum { 494 MAC_DIRECTION_RX = 1, 495 MAC_DIRECTION_TX = 2, 496 MAC_RXFIFO_SIZE = 32768 497 }; 498 499 /* IEEE 802.3 specified MDIO devices */ 500 enum { 501 MDIO_DEV_PMA_PMD = 1, 502 MDIO_DEV_WIS = 2, 503 MDIO_DEV_PCS = 3, 504 MDIO_DEV_XGXS = 4, 505 MDIO_DEV_ANEG = 7, 506 MDIO_DEV_VEND1 = 30, 507 MDIO_DEV_VEND2 = 31 508 }; 509 510 /* LASI control and status registers */ 511 enum { 512 RX_ALARM_CTRL = 0x9000, 513 TX_ALARM_CTRL = 0x9001, 514 LASI_CTRL = 0x9002, 515 RX_ALARM_STAT = 0x9003, 516 TX_ALARM_STAT = 0x9004, 517 LASI_STAT = 0x9005 518 }; 519 520 /* PHY loopback direction */ 521 enum { 522 PHY_LOOPBACK_TX = 1, 523 PHY_LOOPBACK_RX = 2 524 }; 525 526 /* PHY interrupt types */ 527 enum { 528 cphy_cause_link_change = 1, 529 cphy_cause_fifo_error = 2, 530 cphy_cause_module_change = 4, 531 cphy_cause_alarm = 8, 532 }; 533 534 /* PHY module types */ 535 enum { 536 phy_modtype_none, 537 phy_modtype_sr, 538 phy_modtype_lr, 539 phy_modtype_lrm, 540 phy_modtype_twinax, 541 phy_modtype_twinax_long, 542 phy_modtype_unknown 543 }; 544 545 enum { 546 PHY_LINK_DOWN = 0, 547 PHY_LINK_UP, 548 PHY_LINK_PARTIAL 549 }; 550 551 /* PHY operations */ 552 struct cphy_ops { 553 int (*reset)(struct cphy *phy, int wait); 554 555 int (*intr_enable)(struct cphy *phy); 556 int (*intr_disable)(struct cphy *phy); 557 int (*intr_clear)(struct cphy *phy); 558 int (*intr_handler)(struct cphy *phy); 559 560 int (*autoneg_enable)(struct cphy *phy); 561 int (*autoneg_restart)(struct cphy *phy); 562 563 int (*advertise)(struct cphy *phy, unsigned int advertise_map); 564 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); 565 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 566 int (*get_link_status)(struct cphy *phy, int *link_state, int *speed, 567 int *duplex, int *fc); 568 int (*power_down)(struct cphy *phy, int enable); 569 }; 570 571 /* A PHY instance */ 572 struct cphy { 573 u8 addr; /* PHY address */ 574 u8 modtype; /* PHY module type */ 575 u8 rst; 576 unsigned int priv; /* scratch pad */ 577 unsigned int caps; /* PHY capabilities */ 578 adapter_t *adapter; /* associated adapter */ 579 pinfo_t *pinfo; /* associated port */ 580 const char *desc; /* PHY description */ 581 unsigned long fifo_errors; /* FIFO over/under-flows */ 582 const struct cphy_ops *ops; /* PHY operations */ 583 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, 584 int reg_addr, unsigned int *val); 585 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr, 586 int reg_addr, unsigned int val); 587 }; 588 589 /* Convenience MDIO read/write wrappers */ 590 static inline int mdio_read(struct cphy *phy, int mmd, int reg, 591 unsigned int *valp) 592 { 593 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp); 594 } 595 596 static inline int mdio_write(struct cphy *phy, int mmd, int reg, 597 unsigned int val) 598 { 599 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val); 600 } 601 602 /* Convenience initializer */ 603 static inline void cphy_init(struct cphy *phy, adapter_t *adapter, pinfo_t *pinfo, 604 int phy_addr, struct cphy_ops *phy_ops, 605 const struct mdio_ops *mdio_ops, unsigned int caps, 606 const char *desc) 607 { 608 phy->addr = (u8)phy_addr; 609 phy->caps = caps; 610 phy->adapter = adapter; 611 phy->pinfo = pinfo; 612 phy->desc = desc; 613 phy->ops = phy_ops; 614 if (mdio_ops) { 615 phy->mdio_read = mdio_ops->read; 616 phy->mdio_write = mdio_ops->write; 617 } 618 } 619 620 /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ 621 #define MAC_STATS_ACCUM_SECS 180 622 623 /* The external MAC needs accumulation every 30 seconds */ 624 #define VSC_STATS_ACCUM_SECS 30 625 626 #define XGM_REG(reg_addr, idx) \ 627 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) 628 629 struct addr_val_pair { 630 unsigned int reg_addr; 631 unsigned int val; 632 }; 633 634 #include <cxgb_adapter.h> 635 636 #ifndef PCI_VENDOR_ID_CHELSIO 637 # define PCI_VENDOR_ID_CHELSIO 0x1425 638 #endif 639 640 #define for_each_port(adapter, iter) \ 641 for (iter = 0; iter < (adapter)->params.nports; ++iter) 642 643 #define adapter_info(adap) ((adap)->params.info) 644 645 static inline int uses_xaui(const adapter_t *adap) 646 { 647 return adapter_info(adap)->caps & SUPPORTED_AUI; 648 } 649 650 static inline int is_10G(const adapter_t *adap) 651 { 652 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; 653 } 654 655 static inline int is_offload(const adapter_t *adap) 656 { 657 return adap->params.offload; 658 } 659 660 static inline unsigned int core_ticks_per_usec(const adapter_t *adap) 661 { 662 return adap->params.vpd.cclk / 1000; 663 } 664 665 static inline unsigned int dack_ticks_to_usec(const adapter_t *adap, 666 unsigned int ticks) 667 { 668 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 669 } 670 671 static inline unsigned int is_pcie(const adapter_t *adap) 672 { 673 return adap->params.pci.variant == PCI_VARIANT_PCIE; 674 } 675 676 void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val); 677 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, 678 unsigned int offset); 679 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, 680 int attempts, int delay, u32 *valp); 681 682 static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask, 683 int polarity, int attempts, int delay) 684 { 685 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, 686 delay, NULL); 687 } 688 689 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, 690 unsigned int set); 691 int t3_phy_reset(struct cphy *phy, int mmd, int wait); 692 int t3_phy_advertise(struct cphy *phy, unsigned int advert); 693 int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert); 694 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); 695 int t3_phy_lasi_intr_enable(struct cphy *phy); 696 int t3_phy_lasi_intr_disable(struct cphy *phy); 697 int t3_phy_lasi_intr_clear(struct cphy *phy); 698 int t3_phy_lasi_intr_handler(struct cphy *phy); 699 700 void t3_intr_enable(adapter_t *adapter); 701 void t3_intr_disable(adapter_t *adapter); 702 void t3_intr_clear(adapter_t *adapter); 703 void t3_xgm_intr_enable(adapter_t *adapter, int idx); 704 void t3_xgm_intr_disable(adapter_t *adapter, int idx); 705 void t3_port_intr_enable(adapter_t *adapter, int idx); 706 void t3_port_intr_disable(adapter_t *adapter, int idx); 707 void t3_port_intr_clear(adapter_t *adapter, int idx); 708 int t3_slow_intr_handler(adapter_t *adapter); 709 710 void t3_link_changed(adapter_t *adapter, int port_id); 711 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 712 const struct adapter_info *t3_get_adapter_info(unsigned int board_id); 713 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data); 714 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data); 715 int t3_seeprom_wp(adapter_t *adapter, int enable); 716 int t3_get_vpd_len(adapter_t *adapter, struct generic_vpd *vpd); 717 int t3_read_vpd(adapter_t *adapter, struct generic_vpd *vpd); 718 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, 719 u32 *data, int byte_oriented); 720 int t3_get_tp_version(adapter_t *adapter, u32 *vers); 721 int t3_check_tpsram_version(adapter_t *adapter); 722 int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size); 723 int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size); 724 int t3_get_fw_version(adapter_t *adapter, u32 *vers); 725 int t3_check_fw_version(adapter_t *adapter); 726 int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size); 727 int t3_init_hw(adapter_t *adapter, u32 fw_params); 728 void mac_prep(struct cmac *mac, adapter_t *adapter, int index); 729 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai); 730 int t3_reset_adapter(adapter_t *adapter); 731 int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset); 732 int t3_reinit_adapter(adapter_t *adap); 733 void t3_led_ready(adapter_t *adapter); 734 void t3_fatal_err(adapter_t *adapter); 735 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on); 736 void t3_enable_filters(adapter_t *adap); 737 void t3_disable_filters(adapter_t *adap); 738 void t3_tp_set_offload_mode(adapter_t *adap, int enable); 739 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, 740 const u16 *rspq); 741 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map); 742 int t3_set_proto_sram(adapter_t *adap, const u8 *data); 743 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask); 744 void t3_port_failover(adapter_t *adapter, int port); 745 void t3_failover_done(adapter_t *adapter, int port); 746 void t3_failover_clear(adapter_t *adapter); 747 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n, 748 unsigned int *valp); 749 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, 750 u64 *buf); 751 752 int t3_mac_init(struct cmac *mac); 753 void t3b_pcs_reset(struct cmac *mac); 754 void t3c_pcs_force_los(struct cmac *mac); 755 void t3_mac_disable_exact_filters(struct cmac *mac); 756 void t3_mac_enable_exact_filters(struct cmac *mac); 757 int t3_mac_enable(struct cmac *mac, int which); 758 int t3_mac_disable(struct cmac *mac, int which); 759 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); 760 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); 761 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); 762 int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n); 763 const struct mac_stats *t3_mac_update_stats(struct cmac *mac); 764 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, 765 int fc); 766 int t3b2_mac_watchdog_task(struct cmac *mac); 767 768 void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode); 769 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 770 unsigned int nroutes); 771 void t3_mc5_intr_handler(struct mc5 *mc5); 772 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, 773 u32 *buf); 774 775 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh); 776 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size); 777 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps); 778 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS], 779 unsigned short alpha[NCCTRL_WIN], 780 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); 781 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]); 782 void t3_get_cong_cntl_tab(adapter_t *adap, 783 unsigned short incr[NMTUS][NCCTRL_WIN]); 784 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, 785 int filter_index, int invert, int enable); 786 void t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp, 787 int filter_index, int *inverted, int *enabled); 788 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched); 789 int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg); 790 void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps, 791 unsigned int *ipg); 792 void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]); 793 void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals, 794 unsigned int start, unsigned int n); 795 796 int t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index, 797 u32 *size, void *data); 798 int t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data); 799 800 void t3_sge_prep(adapter_t *adap, struct sge_params *p); 801 void t3_sge_init(adapter_t *adap, struct sge_params *p); 802 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, 803 enum sge_context_type type, int respq, u64 base_addr, 804 unsigned int size, unsigned int token, int gen, 805 unsigned int cidx); 806 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, 807 u64 base_addr, unsigned int size, unsigned int esize, 808 unsigned int cong_thres, int gen, unsigned int cidx); 809 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, 810 u64 base_addr, unsigned int size, 811 unsigned int fl_thres, int gen, unsigned int cidx); 812 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, 813 unsigned int size, int rspq, int ovfl_mode, 814 unsigned int credits, unsigned int credit_thres); 815 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable); 816 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id); 817 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id); 818 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id); 819 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]); 820 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]); 821 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]); 822 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]); 823 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, 824 unsigned int credits); 825 826 int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n); 827 int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n); 828 int t3_vsc7323_init(adapter_t *adap, int nports); 829 int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port); 830 int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port); 831 int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port); 832 int t3_vsc7323_enable(adapter_t *adap, int port, int which); 833 int t3_vsc7323_disable(adapter_t *adap, int port, int which); 834 const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac); 835 836 int t3_i2c_read8(adapter_t *adapter, int chained, u8 *valp); 837 int t3_i2c_write8(adapter_t *adapter, int chained, u8 val); 838 839 int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, 840 unsigned int *valp); 841 int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, 842 unsigned int val); 843 844 int t3_mv88e1xxx_phy_prep(pinfo_t *pinfo, int phy_addr, 845 const struct mdio_ops *mdio_ops); 846 int t3_vsc8211_phy_prep(pinfo_t *pinfo, int phy_addr, 847 const struct mdio_ops *mdio_ops); 848 int t3_vsc8211_fifo_depth(adapter_t *adap, unsigned int mtu, int port); 849 int t3_ael1002_phy_prep(pinfo_t *pinfo, int phy_addr, 850 const struct mdio_ops *mdio_ops); 851 int t3_ael1006_phy_prep(pinfo_t *pinfo, int phy_addr, 852 const struct mdio_ops *mdio_ops); 853 int t3_ael2005_phy_prep(pinfo_t *pinfo, int phy_addr, 854 const struct mdio_ops *mdio_ops); 855 int t3_ael2020_phy_prep(pinfo_t *pinfo, int phy_addr, 856 const struct mdio_ops *mdio_ops); 857 int t3_qt2045_phy_prep(pinfo_t *pinfo, int phy_addr, 858 const struct mdio_ops *mdio_ops); 859 int t3_tn1010_phy_prep(pinfo_t *pinfo, int phy_addr, 860 const struct mdio_ops *mdio_ops); 861 int t3_xaui_direct_phy_prep(pinfo_t *pinfo, int phy_addr, 862 const struct mdio_ops *mdio_ops); 863 int t3_aq100x_phy_prep(pinfo_t *pinfo, int phy_addr, 864 const struct mdio_ops *mdio_ops); 865 #endif /* __CHELSIO_COMMON_H */ 866