1 /************************************************************************** 2 3 Copyright (c) 2007-2009, Chelsio Inc. 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Neither the name of the Chelsio Corporation nor the names of its 13 contributors may be used to endorse or promote products derived from 14 this software without specific prior written permission. 15 16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 26 POSSIBILITY OF SUCH DAMAGE. 27 28 $FreeBSD$ 29 30 ***************************************************************************/ 31 #ifndef __CHELSIO_COMMON_H 32 #define __CHELSIO_COMMON_H 33 34 #include <cxgb_osdep.h> 35 36 enum { 37 MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */ 38 EEPROMSIZE = 8192, /* Serial EEPROM size */ 39 SERNUM_LEN = 16, /* Serial # length */ 40 ECNUM_LEN = 16, /* EC # length */ 41 RSS_TABLE_SIZE = 64, /* size of RSS lookup and mapping tables */ 42 TCB_SIZE = 128, /* TCB size */ 43 NMTUS = 16, /* size of MTU table */ 44 NCCTRL_WIN = 32, /* # of congestion control windows */ 45 NTX_SCHED = 8, /* # of HW Tx scheduling queues */ 46 PROTO_SRAM_LINES = 128, /* size of protocol sram */ 47 EXACT_ADDR_FILTERS = 8, /* # of HW exact match filters */ 48 }; 49 50 #define MAX_RX_COALESCING_LEN 12288U 51 52 enum { 53 PAUSE_RX = 1 << 0, 54 PAUSE_TX = 1 << 1, 55 PAUSE_AUTONEG = 1 << 2 56 }; 57 58 enum { 59 SUPPORTED_LINK_IRQ = 1 << 24, 60 /* skip 25 */ 61 SUPPORTED_MISC_IRQ = 1 << 26, 62 SUPPORTED_IRQ = (SUPPORTED_LINK_IRQ | SUPPORTED_MISC_IRQ), 63 POLL_LINK_1ST_TIME = 1 << 27 64 }; 65 66 enum { /* adapter interrupt-maintained statistics */ 67 STAT_ULP_CH0_PBL_OOB, 68 STAT_ULP_CH1_PBL_OOB, 69 STAT_PCI_CORR_ECC, 70 71 IRQ_NUM_STATS /* keep last */ 72 }; 73 74 enum { 75 TP_VERSION_MAJOR = 1, 76 TP_VERSION_MINOR = 1, 77 TP_VERSION_MICRO = 0 78 }; 79 80 #define S_TP_VERSION_MAJOR 16 81 #define M_TP_VERSION_MAJOR 0xFF 82 #define V_TP_VERSION_MAJOR(x) ((x) << S_TP_VERSION_MAJOR) 83 #define G_TP_VERSION_MAJOR(x) \ 84 (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR) 85 86 #define S_TP_VERSION_MINOR 8 87 #define M_TP_VERSION_MINOR 0xFF 88 #define V_TP_VERSION_MINOR(x) ((x) << S_TP_VERSION_MINOR) 89 #define G_TP_VERSION_MINOR(x) \ 90 (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR) 91 92 #define S_TP_VERSION_MICRO 0 93 #define M_TP_VERSION_MICRO 0xFF 94 #define V_TP_VERSION_MICRO(x) ((x) << S_TP_VERSION_MICRO) 95 #define G_TP_VERSION_MICRO(x) \ 96 (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO) 97 98 enum { 99 FW_VERSION_MAJOR = 7, 100 FW_VERSION_MINOR = 8, 101 FW_VERSION_MICRO = 0 102 }; 103 104 enum { 105 LA_CTRL = 0x80, 106 LA_DATA = 0x84, 107 LA_ENTRIES = 512 108 }; 109 110 enum { 111 IOQ_ENTRIES = 7 112 }; 113 114 enum { 115 SGE_QSETS = 8, /* # of SGE Tx/Rx/RspQ sets */ 116 SGE_RXQ_PER_SET = 2, /* # of Rx queues per set */ 117 SGE_TXQ_PER_SET = 3 /* # of Tx queues per set */ 118 }; 119 120 enum sge_context_type { /* SGE egress context types */ 121 SGE_CNTXT_RDMA = 0, 122 SGE_CNTXT_ETH = 2, 123 SGE_CNTXT_OFLD = 4, 124 SGE_CNTXT_CTRL = 5 125 }; 126 127 enum { 128 AN_PKT_SIZE = 32, /* async notification packet size */ 129 IMMED_PKT_SIZE = 48 /* packet size for immediate data */ 130 }; 131 132 struct sg_ent { /* SGE scatter/gather entry */ 133 __be32 len[2]; 134 __be64 addr[2]; 135 }; 136 137 #ifndef SGE_NUM_GENBITS 138 /* Must be 1 or 2 */ 139 # define SGE_NUM_GENBITS 2 140 #endif 141 142 #define TX_DESC_FLITS 16U 143 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS) 144 145 #define MAX_PHYINTRS 4 146 147 struct cphy; 148 149 struct mdio_ops { 150 int (*read)(adapter_t *adapter, int phy_addr, int mmd_addr, 151 int reg_addr, unsigned int *val); 152 int (*write)(adapter_t *adapter, int phy_addr, int mmd_addr, 153 int reg_addr, unsigned int val); 154 }; 155 156 struct adapter_info { 157 unsigned char nports0; /* # of ports on channel 0 */ 158 unsigned char nports1; /* # of ports on channel 1 */ 159 unsigned char phy_base_addr; /* MDIO PHY base address */ 160 unsigned int gpio_out; /* GPIO output settings */ 161 unsigned char gpio_intr[MAX_PHYINTRS]; /* GPIO PHY IRQ pins */ 162 unsigned long caps; /* adapter capabilities */ 163 const struct mdio_ops *mdio_ops; /* MDIO operations */ 164 const char *desc; /* product description */ 165 }; 166 167 struct mc5_stats { 168 unsigned long parity_err; 169 unsigned long active_rgn_full; 170 unsigned long nfa_srch_err; 171 unsigned long unknown_cmd; 172 unsigned long reqq_parity_err; 173 unsigned long dispq_parity_err; 174 unsigned long del_act_empty; 175 }; 176 177 struct mc7_stats { 178 unsigned long corr_err; 179 unsigned long uncorr_err; 180 unsigned long parity_err; 181 unsigned long addr_err; 182 }; 183 184 struct mac_stats { 185 u64 tx_octets; /* total # of octets in good frames */ 186 u64 tx_octets_bad; /* total # of octets in error frames */ 187 u64 tx_frames; /* all good frames */ 188 u64 tx_mcast_frames; /* good multicast frames */ 189 u64 tx_bcast_frames; /* good broadcast frames */ 190 u64 tx_pause; /* # of transmitted pause frames */ 191 u64 tx_deferred; /* frames with deferred transmissions */ 192 u64 tx_late_collisions; /* # of late collisions */ 193 u64 tx_total_collisions; /* # of total collisions */ 194 u64 tx_excess_collisions; /* frame errors from excessive collissions */ 195 u64 tx_underrun; /* # of Tx FIFO underruns */ 196 u64 tx_len_errs; /* # of Tx length errors */ 197 u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */ 198 u64 tx_excess_deferral; /* # of frames with excessive deferral */ 199 u64 tx_fcs_errs; /* # of frames with bad FCS */ 200 201 u64 tx_frames_64; /* # of Tx frames in a particular range */ 202 u64 tx_frames_65_127; 203 u64 tx_frames_128_255; 204 u64 tx_frames_256_511; 205 u64 tx_frames_512_1023; 206 u64 tx_frames_1024_1518; 207 u64 tx_frames_1519_max; 208 209 u64 rx_octets; /* total # of octets in good frames */ 210 u64 rx_octets_bad; /* total # of octets in error frames */ 211 u64 rx_frames; /* all good frames */ 212 u64 rx_mcast_frames; /* good multicast frames */ 213 u64 rx_bcast_frames; /* good broadcast frames */ 214 u64 rx_pause; /* # of received pause frames */ 215 u64 rx_fcs_errs; /* # of received frames with bad FCS */ 216 u64 rx_align_errs; /* alignment errors */ 217 u64 rx_symbol_errs; /* symbol errors */ 218 u64 rx_data_errs; /* data errors */ 219 u64 rx_sequence_errs; /* sequence errors */ 220 u64 rx_runt; /* # of runt frames */ 221 u64 rx_jabber; /* # of jabber frames */ 222 u64 rx_short; /* # of short frames */ 223 u64 rx_too_long; /* # of oversized frames */ 224 u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */ 225 226 u64 rx_frames_64; /* # of Rx frames in a particular range */ 227 u64 rx_frames_65_127; 228 u64 rx_frames_128_255; 229 u64 rx_frames_256_511; 230 u64 rx_frames_512_1023; 231 u64 rx_frames_1024_1518; 232 u64 rx_frames_1519_max; 233 234 u64 rx_cong_drops; /* # of Rx drops due to SGE congestion */ 235 236 unsigned long tx_fifo_parity_err; 237 unsigned long rx_fifo_parity_err; 238 unsigned long tx_fifo_urun; 239 unsigned long rx_fifo_ovfl; 240 unsigned long serdes_signal_loss; 241 unsigned long xaui_pcs_ctc_err; 242 unsigned long xaui_pcs_align_change; 243 244 unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */ 245 unsigned long num_resets; /* # times reset due to stuck TX */ 246 247 unsigned long link_faults; /* # detected link faults */ 248 }; 249 250 struct tp_mib_stats { 251 u32 ipInReceive_hi; 252 u32 ipInReceive_lo; 253 u32 ipInHdrErrors_hi; 254 u32 ipInHdrErrors_lo; 255 u32 ipInAddrErrors_hi; 256 u32 ipInAddrErrors_lo; 257 u32 ipInUnknownProtos_hi; 258 u32 ipInUnknownProtos_lo; 259 u32 ipInDiscards_hi; 260 u32 ipInDiscards_lo; 261 u32 ipInDelivers_hi; 262 u32 ipInDelivers_lo; 263 u32 ipOutRequests_hi; 264 u32 ipOutRequests_lo; 265 u32 ipOutDiscards_hi; 266 u32 ipOutDiscards_lo; 267 u32 ipOutNoRoutes_hi; 268 u32 ipOutNoRoutes_lo; 269 u32 ipReasmTimeout; 270 u32 ipReasmReqds; 271 u32 ipReasmOKs; 272 u32 ipReasmFails; 273 274 u32 reserved[8]; 275 276 u32 tcpActiveOpens; 277 u32 tcpPassiveOpens; 278 u32 tcpAttemptFails; 279 u32 tcpEstabResets; 280 u32 tcpOutRsts; 281 u32 tcpCurrEstab; 282 u32 tcpInSegs_hi; 283 u32 tcpInSegs_lo; 284 u32 tcpOutSegs_hi; 285 u32 tcpOutSegs_lo; 286 u32 tcpRetransSeg_hi; 287 u32 tcpRetransSeg_lo; 288 u32 tcpInErrs_hi; 289 u32 tcpInErrs_lo; 290 u32 tcpRtoMin; 291 u32 tcpRtoMax; 292 }; 293 294 struct tp_params { 295 unsigned int nchan; /* # of channels */ 296 unsigned int pmrx_size; /* total PMRX capacity */ 297 unsigned int pmtx_size; /* total PMTX capacity */ 298 unsigned int cm_size; /* total CM capacity */ 299 unsigned int chan_rx_size; /* per channel Rx size */ 300 unsigned int chan_tx_size; /* per channel Tx size */ 301 unsigned int rx_pg_size; /* Rx page size */ 302 unsigned int tx_pg_size; /* Tx page size */ 303 unsigned int rx_num_pgs; /* # of Rx pages */ 304 unsigned int tx_num_pgs; /* # of Tx pages */ 305 unsigned int ntimer_qs; /* # of timer queues */ 306 unsigned int tre; /* log2 of core clocks per TP tick */ 307 unsigned int dack_re; /* DACK timer resolution */ 308 }; 309 310 struct qset_params { /* SGE queue set parameters */ 311 unsigned int polling; /* polling/interrupt service for rspq */ 312 unsigned int lro; /* large receive offload */ 313 unsigned int coalesce_usecs; /* irq coalescing timer */ 314 unsigned int rspq_size; /* # of entries in response queue */ 315 unsigned int fl_size; /* # of entries in regular free list */ 316 unsigned int jumbo_size; /* # of entries in jumbo free list */ 317 unsigned int txq_size[SGE_TXQ_PER_SET]; /* Tx queue sizes */ 318 unsigned int cong_thres; /* FL congestion threshold */ 319 unsigned int vector; /* Interrupt (line or vector) number */ 320 }; 321 322 struct sge_params { 323 unsigned int max_pkt_size; /* max offload pkt size */ 324 struct qset_params qset[SGE_QSETS]; 325 }; 326 327 struct mc5_params { 328 unsigned int mode; /* selects MC5 width */ 329 unsigned int nservers; /* size of server region */ 330 unsigned int nfilters; /* size of filter region */ 331 unsigned int nroutes; /* size of routing region */ 332 }; 333 334 /* Default MC5 region sizes */ 335 enum { 336 DEFAULT_NSERVERS = 512, 337 DEFAULT_NFILTERS = 128 338 }; 339 340 /* MC5 modes, these must be non-0 */ 341 enum { 342 MC5_MODE_144_BIT = 1, 343 MC5_MODE_72_BIT = 2 344 }; 345 346 /* MC5 min active region size */ 347 enum { MC5_MIN_TIDS = 16 }; 348 349 struct vpd_params { 350 unsigned int cclk; 351 unsigned int mclk; 352 unsigned int uclk; 353 unsigned int mdc; 354 unsigned int mem_timing; 355 u8 sn[SERNUM_LEN + 1]; 356 u8 ec[ECNUM_LEN + 1]; 357 u8 eth_base[6]; 358 u8 port_type[MAX_NPORTS]; 359 unsigned short xauicfg[2]; 360 }; 361 362 struct generic_vpd { 363 u32 offset; 364 u32 len; 365 u8 *data; 366 }; 367 368 enum { MAX_VPD_BYTES = 32000 }; 369 370 struct pci_params { 371 unsigned int vpd_cap_addr; 372 unsigned int pcie_cap_addr; 373 unsigned short speed; 374 unsigned char width; 375 unsigned char variant; 376 }; 377 378 enum { 379 PCI_VARIANT_PCI, 380 PCI_VARIANT_PCIX_MODE1_PARITY, 381 PCI_VARIANT_PCIX_MODE1_ECC, 382 PCI_VARIANT_PCIX_266_MODE2, 383 PCI_VARIANT_PCIE 384 }; 385 386 struct adapter_params { 387 struct sge_params sge; 388 struct mc5_params mc5; 389 struct tp_params tp; 390 struct vpd_params vpd; 391 struct pci_params pci; 392 393 const struct adapter_info *info; 394 395 #ifdef CONFIG_CHELSIO_T3_CORE 396 unsigned short mtus[NMTUS]; 397 unsigned short a_wnd[NCCTRL_WIN]; 398 unsigned short b_wnd[NCCTRL_WIN]; 399 #endif 400 unsigned int nports; /* # of ethernet ports */ 401 unsigned int chan_map; /* bitmap of in-use Tx channels */ 402 unsigned int stats_update_period; /* MAC stats accumulation period */ 403 unsigned int linkpoll_period; /* link poll period in 0.1s */ 404 unsigned int rev; /* chip revision */ 405 unsigned int offload; 406 }; 407 408 enum { /* chip revisions */ 409 T3_REV_A = 0, 410 T3_REV_B = 2, 411 T3_REV_B2 = 3, 412 T3_REV_C = 4, 413 }; 414 415 struct trace_params { 416 u32 sip; 417 u32 sip_mask; 418 u32 dip; 419 u32 dip_mask; 420 u16 sport; 421 u16 sport_mask; 422 u16 dport; 423 u16 dport_mask; 424 u32 vlan:12; 425 u32 vlan_mask:12; 426 u32 intf:4; 427 u32 intf_mask:4; 428 u8 proto; 429 u8 proto_mask; 430 }; 431 432 struct link_config { 433 unsigned int supported; /* link capabilities */ 434 unsigned int advertising; /* advertised capabilities */ 435 unsigned short requested_speed; /* speed user has requested */ 436 unsigned short speed; /* actual link speed */ 437 unsigned char requested_duplex; /* duplex user has requested */ 438 unsigned char duplex; /* actual link duplex */ 439 unsigned char requested_fc; /* flow control user has requested */ 440 unsigned char fc; /* actual link flow control */ 441 unsigned char autoneg; /* autonegotiating? */ 442 unsigned int link_ok; /* link up? */ 443 }; 444 445 #define SPEED_INVALID 0xffff 446 #define DUPLEX_INVALID 0xff 447 448 struct mc5 { 449 adapter_t *adapter; 450 unsigned int tcam_size; 451 unsigned char part_type; 452 unsigned char parity_enabled; 453 unsigned char mode; 454 struct mc5_stats stats; 455 }; 456 457 static inline unsigned int t3_mc5_size(const struct mc5 *p) 458 { 459 return p->tcam_size; 460 } 461 462 struct mc7 { 463 adapter_t *adapter; /* backpointer to adapter */ 464 unsigned int size; /* memory size in bytes */ 465 unsigned int width; /* MC7 interface width */ 466 unsigned int offset; /* register address offset for MC7 instance */ 467 const char *name; /* name of MC7 instance */ 468 struct mc7_stats stats; /* MC7 statistics */ 469 }; 470 471 static inline unsigned int t3_mc7_size(const struct mc7 *p) 472 { 473 return p->size; 474 } 475 476 struct cmac { 477 adapter_t *adapter; 478 unsigned int offset; 479 unsigned char nucast; /* # of address filters for unicast MACs */ 480 unsigned char multiport; /* multiple ports connected to this MAC */ 481 unsigned char ext_port; /* external MAC port */ 482 unsigned char promisc_map; /* which external ports are promiscuous */ 483 unsigned int tx_tcnt; 484 unsigned int tx_xcnt; 485 u64 tx_mcnt; 486 unsigned int rx_xcnt; 487 unsigned int rx_ocnt; 488 u64 rx_mcnt; 489 unsigned int toggle_cnt; 490 unsigned int txen; 491 unsigned int was_reset; 492 u64 rx_pause; 493 struct mac_stats stats; 494 }; 495 496 enum { 497 MAC_DIRECTION_RX = 1, 498 MAC_DIRECTION_TX = 2, 499 MAC_RXFIFO_SIZE = 32768 500 }; 501 502 /* IEEE 802.3 specified MDIO devices */ 503 enum { 504 MDIO_DEV_PMA_PMD = 1, 505 MDIO_DEV_WIS = 2, 506 MDIO_DEV_PCS = 3, 507 MDIO_DEV_XGXS = 4, 508 MDIO_DEV_ANEG = 7, 509 MDIO_DEV_VEND1 = 30, 510 MDIO_DEV_VEND2 = 31 511 }; 512 513 /* LASI control and status registers */ 514 enum { 515 RX_ALARM_CTRL = 0x9000, 516 TX_ALARM_CTRL = 0x9001, 517 LASI_CTRL = 0x9002, 518 RX_ALARM_STAT = 0x9003, 519 TX_ALARM_STAT = 0x9004, 520 LASI_STAT = 0x9005 521 }; 522 523 /* PHY loopback direction */ 524 enum { 525 PHY_LOOPBACK_TX = 1, 526 PHY_LOOPBACK_RX = 2 527 }; 528 529 /* PHY interrupt types */ 530 enum { 531 cphy_cause_link_change = 1, 532 cphy_cause_fifo_error = 2, 533 cphy_cause_module_change = 4, 534 cphy_cause_alarm = 8, 535 }; 536 537 /* PHY module types */ 538 enum { 539 phy_modtype_none, 540 phy_modtype_sr, 541 phy_modtype_lr, 542 phy_modtype_lrm, 543 phy_modtype_twinax, 544 phy_modtype_twinax_long, 545 phy_modtype_unknown 546 }; 547 548 /* PHY operations */ 549 struct cphy_ops { 550 int (*reset)(struct cphy *phy, int wait); 551 552 int (*intr_enable)(struct cphy *phy); 553 int (*intr_disable)(struct cphy *phy); 554 int (*intr_clear)(struct cphy *phy); 555 int (*intr_handler)(struct cphy *phy); 556 557 int (*autoneg_enable)(struct cphy *phy); 558 int (*autoneg_restart)(struct cphy *phy); 559 560 int (*advertise)(struct cphy *phy, unsigned int advertise_map); 561 int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable); 562 int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex); 563 int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed, 564 int *duplex, int *fc); 565 int (*power_down)(struct cphy *phy, int enable); 566 }; 567 568 /* A PHY instance */ 569 struct cphy { 570 u8 addr; /* PHY address */ 571 u8 modtype; /* PHY module type */ 572 unsigned int priv; /* scratch pad */ 573 unsigned int caps; /* PHY capabilities */ 574 adapter_t *adapter; /* associated adapter */ 575 pinfo_t *pinfo; /* associated port */ 576 const char *desc; /* PHY description */ 577 unsigned long fifo_errors; /* FIFO over/under-flows */ 578 const struct cphy_ops *ops; /* PHY operations */ 579 int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr, 580 int reg_addr, unsigned int *val); 581 int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr, 582 int reg_addr, unsigned int val); 583 }; 584 585 /* Convenience MDIO read/write wrappers */ 586 static inline int mdio_read(struct cphy *phy, int mmd, int reg, 587 unsigned int *valp) 588 { 589 return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp); 590 } 591 592 static inline int mdio_write(struct cphy *phy, int mmd, int reg, 593 unsigned int val) 594 { 595 return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val); 596 } 597 598 /* Convenience initializer */ 599 static inline void cphy_init(struct cphy *phy, adapter_t *adapter, pinfo_t *pinfo, 600 int phy_addr, struct cphy_ops *phy_ops, 601 const struct mdio_ops *mdio_ops, unsigned int caps, 602 const char *desc) 603 { 604 phy->addr = (u8)phy_addr; 605 phy->caps = caps; 606 phy->adapter = adapter; 607 phy->pinfo = pinfo; 608 phy->desc = desc; 609 phy->ops = phy_ops; 610 if (mdio_ops) { 611 phy->mdio_read = mdio_ops->read; 612 phy->mdio_write = mdio_ops->write; 613 } 614 } 615 616 /* Accumulate MAC statistics every 180 seconds. For 1G we multiply by 10. */ 617 #define MAC_STATS_ACCUM_SECS 180 618 619 /* The external MAC needs accumulation every 30 seconds */ 620 #define VSC_STATS_ACCUM_SECS 30 621 622 #define XGM_REG(reg_addr, idx) \ 623 ((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR)) 624 625 struct addr_val_pair { 626 unsigned int reg_addr; 627 unsigned int val; 628 }; 629 630 #include <cxgb_adapter.h> 631 632 #ifndef PCI_VENDOR_ID_CHELSIO 633 # define PCI_VENDOR_ID_CHELSIO 0x1425 634 #endif 635 636 #define for_each_port(adapter, iter) \ 637 for (iter = 0; iter < (adapter)->params.nports; ++iter) 638 639 #define adapter_info(adap) ((adap)->params.info) 640 641 static inline int uses_xaui(const adapter_t *adap) 642 { 643 return adapter_info(adap)->caps & SUPPORTED_AUI; 644 } 645 646 static inline int is_10G(const adapter_t *adap) 647 { 648 return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full; 649 } 650 651 static inline int is_offload(const adapter_t *adap) 652 { 653 #if defined(CONFIG_CHELSIO_T3_CORE) 654 return adap->params.offload; 655 #else 656 return 0; 657 #endif 658 } 659 660 static inline unsigned int core_ticks_per_usec(const adapter_t *adap) 661 { 662 return adap->params.vpd.cclk / 1000; 663 } 664 665 static inline unsigned int dack_ticks_to_usec(const adapter_t *adap, 666 unsigned int ticks) 667 { 668 return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap); 669 } 670 671 static inline unsigned int is_pcie(const adapter_t *adap) 672 { 673 return adap->params.pci.variant == PCI_VARIANT_PCIE; 674 } 675 676 void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val); 677 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n, 678 unsigned int offset); 679 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity, 680 int attempts, int delay, u32 *valp); 681 682 static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask, 683 int polarity, int attempts, int delay) 684 { 685 return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts, 686 delay, NULL); 687 } 688 689 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear, 690 unsigned int set); 691 int t3_phy_reset(struct cphy *phy, int mmd, int wait); 692 int t3_phy_advertise(struct cphy *phy, unsigned int advert); 693 int t3_phy_advertise_fiber(struct cphy *phy, unsigned int advert); 694 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex); 695 int t3_phy_lasi_intr_enable(struct cphy *phy); 696 int t3_phy_lasi_intr_disable(struct cphy *phy); 697 int t3_phy_lasi_intr_clear(struct cphy *phy); 698 int t3_phy_lasi_intr_handler(struct cphy *phy); 699 700 void t3_intr_enable(adapter_t *adapter); 701 void t3_intr_disable(adapter_t *adapter); 702 void t3_intr_clear(adapter_t *adapter); 703 void t3_xgm_intr_enable(adapter_t *adapter, int idx); 704 void t3_xgm_intr_disable(adapter_t *adapter, int idx); 705 void t3_port_intr_enable(adapter_t *adapter, int idx); 706 void t3_port_intr_disable(adapter_t *adapter, int idx); 707 void t3_port_intr_clear(adapter_t *adapter, int idx); 708 int t3_slow_intr_handler(adapter_t *adapter); 709 int t3_phy_intr_handler(adapter_t *adapter); 710 711 void t3_link_changed(adapter_t *adapter, int port_id); 712 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc); 713 const struct adapter_info *t3_get_adapter_info(unsigned int board_id); 714 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data); 715 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data); 716 int t3_seeprom_wp(adapter_t *adapter, int enable); 717 int t3_get_vpd_len(adapter_t *adapter, struct generic_vpd *vpd); 718 int t3_read_vpd(adapter_t *adapter, struct generic_vpd *vpd); 719 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords, 720 u32 *data, int byte_oriented); 721 int t3_get_tp_version(adapter_t *adapter, u32 *vers); 722 int t3_check_tpsram_version(adapter_t *adapter); 723 int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size); 724 int t3_load_fw(adapter_t *adapter, const u8 *fw_data, unsigned int size); 725 int t3_get_fw_version(adapter_t *adapter, u32 *vers); 726 int t3_check_fw_version(adapter_t *adapter); 727 int t3_load_boot(adapter_t *adapter, u8 *fw_data, unsigned int size); 728 int t3_init_hw(adapter_t *adapter, u32 fw_params); 729 void mac_prep(struct cmac *mac, adapter_t *adapter, int index); 730 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai); 731 int t3_reset_adapter(adapter_t *adapter); 732 int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset); 733 int t3_reinit_adapter(adapter_t *adap); 734 void t3_led_ready(adapter_t *adapter); 735 void t3_fatal_err(adapter_t *adapter); 736 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on); 737 void t3_enable_filters(adapter_t *adap); 738 void t3_disable_filters(adapter_t *adap); 739 void t3_tp_set_offload_mode(adapter_t *adap, int enable); 740 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus, 741 const u16 *rspq); 742 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map); 743 int t3_set_proto_sram(adapter_t *adap, const u8 *data); 744 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask); 745 void t3_port_failover(adapter_t *adapter, int port); 746 void t3_failover_done(adapter_t *adapter, int port); 747 void t3_failover_clear(adapter_t *adapter); 748 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n, 749 unsigned int *valp); 750 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n, 751 u64 *buf); 752 753 int t3_mac_init(struct cmac *mac); 754 void t3b_pcs_reset(struct cmac *mac); 755 void t3_mac_disable_exact_filters(struct cmac *mac); 756 void t3_mac_enable_exact_filters(struct cmac *mac); 757 int t3_mac_enable(struct cmac *mac, int which); 758 int t3_mac_disable(struct cmac *mac, int which); 759 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu); 760 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm); 761 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]); 762 int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n); 763 const struct mac_stats *t3_mac_update_stats(struct cmac *mac); 764 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex, 765 int fc); 766 int t3b2_mac_watchdog_task(struct cmac *mac); 767 768 void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode); 769 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters, 770 unsigned int nroutes); 771 void t3_mc5_intr_handler(struct mc5 *mc5); 772 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n, 773 u32 *buf); 774 775 #ifdef CONFIG_CHELSIO_T3_CORE 776 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh); 777 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size); 778 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps); 779 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS], 780 unsigned short alpha[NCCTRL_WIN], 781 unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap); 782 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]); 783 void t3_get_cong_cntl_tab(adapter_t *adap, 784 unsigned short incr[NMTUS][NCCTRL_WIN]); 785 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp, 786 int filter_index, int invert, int enable); 787 void t3_query_trace_filter(adapter_t *adapter, struct trace_params *tp, 788 int filter_index, int *inverted, int *enabled); 789 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched); 790 int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg); 791 void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps, 792 unsigned int *ipg); 793 void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]); 794 void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals, 795 unsigned int start, unsigned int n); 796 #endif 797 798 int t3_get_up_la(adapter_t *adapter, u32 *stopped, u32 *index, 799 u32 *size, void *data); 800 int t3_get_up_ioqs(adapter_t *adapter, u32 *size, void *data); 801 802 void t3_sge_prep(adapter_t *adap, struct sge_params *p); 803 void t3_sge_init(adapter_t *adap, struct sge_params *p); 804 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable, 805 enum sge_context_type type, int respq, u64 base_addr, 806 unsigned int size, unsigned int token, int gen, 807 unsigned int cidx); 808 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable, 809 u64 base_addr, unsigned int size, unsigned int esize, 810 unsigned int cong_thres, int gen, unsigned int cidx); 811 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx, 812 u64 base_addr, unsigned int size, 813 unsigned int fl_thres, int gen, unsigned int cidx); 814 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr, 815 unsigned int size, int rspq, int ovfl_mode, 816 unsigned int credits, unsigned int credit_thres); 817 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable); 818 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id); 819 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id); 820 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id); 821 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]); 822 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]); 823 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]); 824 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]); 825 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op, 826 unsigned int credits); 827 828 int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n); 829 int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n); 830 int t3_vsc7323_init(adapter_t *adap, int nports); 831 int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port); 832 int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port); 833 int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port); 834 int t3_vsc7323_enable(adapter_t *adap, int port, int which); 835 int t3_vsc7323_disable(adapter_t *adap, int port, int which); 836 const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac); 837 838 int t3_i2c_read8(adapter_t *adapter, int chained, u8 *valp); 839 int t3_i2c_write8(adapter_t *adapter, int chained, u8 val); 840 841 int t3_mi1_read(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, 842 unsigned int *valp); 843 int t3_mi1_write(adapter_t *adapter, int phy_addr, int mmd_addr, int reg_addr, 844 unsigned int val); 845 846 int t3_mv88e1xxx_phy_prep(pinfo_t *pinfo, int phy_addr, 847 const struct mdio_ops *mdio_ops); 848 int t3_vsc8211_phy_prep(pinfo_t *pinfo, int phy_addr, 849 const struct mdio_ops *mdio_ops); 850 int t3_vsc8211_fifo_depth(adapter_t *adap, unsigned int mtu, int port); 851 int t3_ael1002_phy_prep(pinfo_t *pinfo, int phy_addr, 852 const struct mdio_ops *mdio_ops); 853 int t3_ael1006_phy_prep(pinfo_t *pinfo, int phy_addr, 854 const struct mdio_ops *mdio_ops); 855 int t3_ael2005_phy_prep(pinfo_t *pinfo, int phy_addr, 856 const struct mdio_ops *mdio_ops); 857 int t3_ael2020_phy_prep(pinfo_t *pinfo, int phy_addr, 858 const struct mdio_ops *mdio_ops); 859 int t3_qt2045_phy_prep(pinfo_t *pinfo, int phy_addr, 860 const struct mdio_ops *mdio_ops); 861 int t3_tn1010_phy_prep(pinfo_t *pinfo, int phy_addr, 862 const struct mdio_ops *mdio_ops); 863 int t3_xaui_direct_phy_prep(pinfo_t *pinfo, int phy_addr, 864 const struct mdio_ops *mdio_ops); 865 int t3_aq100x_phy_prep(pinfo_t *pinfo, int phy_addr, 866 const struct mdio_ops *mdio_ops); 867 #endif /* __CHELSIO_COMMON_H */ 868