xref: /freebsd/sys/dev/cxgb/common/cxgb_common.h (revision 30d239bc4c510432e65a84fa1c14ed67a3ab1c92)
1 /**************************************************************************
2 
3 Copyright (c) 2007, Chelsio Inc.
4 All rights reserved.
5 
6 Redistribution and use in source and binary forms, with or without
7 modification, are permitted provided that the following conditions are met:
8 
9  1. Redistributions of source code must retain the above copyright notice,
10     this list of conditions and the following disclaimer.
11 
12  2. Neither the name of the Chelsio Corporation nor the names of its
13     contributors may be used to endorse or promote products derived from
14     this software without specific prior written permission.
15 
16 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
17 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
20 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
21 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
22 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
23 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
24 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
25 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
26 POSSIBILITY OF SUCH DAMAGE.
27 
28 $FreeBSD$
29 
30 ***************************************************************************/
31 #ifndef __CHELSIO_COMMON_H
32 #define __CHELSIO_COMMON_H
33 
34 #ifdef CONFIG_DEFINED
35 #include <cxgb_osdep.h>
36 #else
37 #include <dev/cxgb/cxgb_osdep.h>
38 #endif
39 
40 enum {
41 	MAX_FRAME_SIZE = 10240, /* max MAC frame size, includes header + FCS */
42 	EEPROMSIZE     = 8192,  /* Serial EEPROM size */
43 	SERNUM_LEN     = 16,    /* Serial # length */
44 	RSS_TABLE_SIZE = 64,    /* size of RSS lookup and mapping tables */
45 	TCB_SIZE       = 128,   /* TCB size */
46 	NMTUS          = 16,    /* size of MTU table */
47 	NCCTRL_WIN     = 32,    /* # of congestion control windows */
48 	NTX_SCHED      = 8,     /* # of HW Tx scheduling queues */
49 	PROTO_SRAM_LINES = 128, /* size of protocol sram */
50 	MAX_NPORTS     = 4,
51 	TP_TMR_RES     = 200,
52 	TP_SRAM_OFFSET = 4096,	/* TP SRAM content offset in eeprom */
53 	TP_SRAM_LEN    = 2112,	/* TP SRAM content offset in eeprom */
54 };
55 
56 #define MAX_RX_COALESCING_LEN 12288U
57 
58 enum {
59 	PAUSE_RX      = 1 << 0,
60 	PAUSE_TX      = 1 << 1,
61 	PAUSE_AUTONEG = 1 << 2
62 };
63 
64 enum {
65 	SUPPORTED_IRQ      = 1 << 24
66 };
67 
68 enum {                            /* adapter interrupt-maintained statistics */
69 	STAT_ULP_CH0_PBL_OOB,
70 	STAT_ULP_CH1_PBL_OOB,
71 	STAT_PCI_CORR_ECC,
72 
73 	IRQ_NUM_STATS             /* keep last */
74 };
75 
76 enum {
77 	TP_VERSION_MAJOR	= 1,
78 	TP_VERSION_MINOR	= 1,
79 	TP_VERSION_MICRO	= 0
80 };
81 
82 #define S_TP_VERSION_MAJOR		16
83 #define M_TP_VERSION_MAJOR		0xFF
84 #define V_TP_VERSION_MAJOR(x)		((x) << S_TP_VERSION_MAJOR)
85 #define G_TP_VERSION_MAJOR(x)		\
86 	    (((x) >> S_TP_VERSION_MAJOR) & M_TP_VERSION_MAJOR)
87 
88 #define S_TP_VERSION_MINOR		8
89 #define M_TP_VERSION_MINOR		0xFF
90 #define V_TP_VERSION_MINOR(x)		((x) << S_TP_VERSION_MINOR)
91 #define G_TP_VERSION_MINOR(x)		\
92 	    (((x) >> S_TP_VERSION_MINOR) & M_TP_VERSION_MINOR)
93 
94 #define S_TP_VERSION_MICRO		0
95 #define M_TP_VERSION_MICRO		0xFF
96 #define V_TP_VERSION_MICRO(x)		((x) << S_TP_VERSION_MICRO)
97 #define G_TP_VERSION_MICRO(x)		\
98 	    (((x) >> S_TP_VERSION_MICRO) & M_TP_VERSION_MICRO)
99 
100 enum {
101 	FW_VERSION_MAJOR = 4,
102 	FW_VERSION_MINOR = 7,
103 	FW_VERSION_MICRO = 0
104 };
105 
106 enum {
107 	SGE_QSETS = 8,            /* # of SGE Tx/Rx/RspQ sets */
108 	SGE_RXQ_PER_SET = 2,      /* # of Rx queues per set */
109 	SGE_TXQ_PER_SET = 3       /* # of Tx queues per set */
110 };
111 
112 enum sge_context_type {           /* SGE egress context types */
113 	SGE_CNTXT_RDMA  = 0,
114 	SGE_CNTXT_ETH   = 2,
115 	SGE_CNTXT_OFLD  = 4,
116 	SGE_CNTXT_CTRL  = 5
117 };
118 
119 enum {
120 	AN_PKT_SIZE    = 32,      /* async notification packet size */
121 	IMMED_PKT_SIZE = 48       /* packet size for immediate data */
122 };
123 
124 struct sg_ent {                   /* SGE scatter/gather entry */
125 	u32 len[2];
126 	u64 addr[2];
127 };
128 
129 #ifndef SGE_NUM_GENBITS
130 /* Must be 1 or 2 */
131 # define SGE_NUM_GENBITS 2
132 #endif
133 
134 #define TX_DESC_FLITS 16U
135 #define WR_FLITS (TX_DESC_FLITS + 1 - SGE_NUM_GENBITS)
136 
137 struct cphy;
138 
139 struct mdio_ops {
140 	int  (*read)(adapter_t *adapter, int phy_addr, int mmd_addr,
141 		     int reg_addr, unsigned int *val);
142         int  (*write)(adapter_t *adapter, int phy_addr, int mmd_addr,
143 		      int reg_addr, unsigned int val);
144 };
145 
146 struct adapter_info {
147 	unsigned char          nports0;        /* # of ports on channel 0 */
148 	unsigned char          nports1;        /* # of ports on channel 1 */
149 	unsigned char          phy_base_addr;  /* MDIO PHY base address */
150 	unsigned char          mdien:1;
151 	unsigned char          mdiinv:1;
152 	unsigned int           gpio_out;       /* GPIO output settings */
153 	unsigned int           gpio_intr;      /* GPIO IRQ enable mask */
154 	unsigned long          caps;           /* adapter capabilities */
155 	const struct mdio_ops *mdio_ops;       /* MDIO operations */
156 	const char            *desc;           /* product description */
157 };
158 
159 struct port_type_info {
160 	void (*phy_prep)(struct cphy *phy, adapter_t *adapter, int phy_addr,
161 			 const struct mdio_ops *ops);
162 	unsigned int caps;
163 	const char *desc;
164 };
165 
166 struct mc5_stats {
167 	unsigned long parity_err;
168 	unsigned long active_rgn_full;
169 	unsigned long nfa_srch_err;
170 	unsigned long unknown_cmd;
171 	unsigned long reqq_parity_err;
172 	unsigned long dispq_parity_err;
173 	unsigned long del_act_empty;
174 };
175 
176 struct mc7_stats {
177 	unsigned long corr_err;
178 	unsigned long uncorr_err;
179 	unsigned long parity_err;
180 	unsigned long addr_err;
181 };
182 
183 struct mac_stats {
184 	u64 tx_octets;            /* total # of octets in good frames */
185 	u64 tx_octets_bad;        /* total # of octets in error frames */
186 	u64 tx_frames;            /* all good frames */
187 	u64 tx_mcast_frames;      /* good multicast frames */
188 	u64 tx_bcast_frames;      /* good broadcast frames */
189 	u64 tx_pause;             /* # of transmitted pause frames */
190 	u64 tx_deferred;          /* frames with deferred transmissions */
191 	u64 tx_late_collisions;   /* # of late collisions */
192 	u64 tx_total_collisions;  /* # of total collisions */
193 	u64 tx_excess_collisions; /* frame errors from excessive collissions */
194 	u64 tx_underrun;          /* # of Tx FIFO underruns */
195 	u64 tx_len_errs;          /* # of Tx length errors */
196 	u64 tx_mac_internal_errs; /* # of internal MAC errors on Tx */
197 	u64 tx_excess_deferral;   /* # of frames with excessive deferral */
198 	u64 tx_fcs_errs;          /* # of frames with bad FCS */
199 
200 	u64 tx_frames_64;         /* # of Tx frames in a particular range */
201 	u64 tx_frames_65_127;
202 	u64 tx_frames_128_255;
203 	u64 tx_frames_256_511;
204 	u64 tx_frames_512_1023;
205 	u64 tx_frames_1024_1518;
206 	u64 tx_frames_1519_max;
207 
208 	u64 rx_octets;            /* total # of octets in good frames */
209 	u64 rx_octets_bad;        /* total # of octets in error frames */
210 	u64 rx_frames;            /* all good frames */
211 	u64 rx_mcast_frames;      /* good multicast frames */
212 	u64 rx_bcast_frames;      /* good broadcast frames */
213 	u64 rx_pause;             /* # of received pause frames */
214 	u64 rx_fcs_errs;          /* # of received frames with bad FCS */
215 	u64 rx_align_errs;        /* alignment errors */
216 	u64 rx_symbol_errs;       /* symbol errors */
217 	u64 rx_data_errs;         /* data errors */
218 	u64 rx_sequence_errs;     /* sequence errors */
219 	u64 rx_runt;              /* # of runt frames */
220 	u64 rx_jabber;            /* # of jabber frames */
221 	u64 rx_short;             /* # of short frames */
222 	u64 rx_too_long;          /* # of oversized frames */
223 	u64 rx_mac_internal_errs; /* # of internal MAC errors on Rx */
224 
225 	u64 rx_frames_64;         /* # of Rx frames in a particular range */
226 	u64 rx_frames_65_127;
227 	u64 rx_frames_128_255;
228 	u64 rx_frames_256_511;
229 	u64 rx_frames_512_1023;
230 	u64 rx_frames_1024_1518;
231 	u64 rx_frames_1519_max;
232 
233 	u64 rx_cong_drops;        /* # of Rx drops due to SGE congestion */
234 
235 	unsigned long tx_fifo_parity_err;
236 	unsigned long rx_fifo_parity_err;
237 	unsigned long tx_fifo_urun;
238 	unsigned long rx_fifo_ovfl;
239 	unsigned long serdes_signal_loss;
240 	unsigned long xaui_pcs_ctc_err;
241 	unsigned long xaui_pcs_align_change;
242 
243 	unsigned long num_toggled; /* # times toggled TxEn due to stuck TX */
244 	unsigned long num_resets;  /* # times reset due to stuck TX */
245 };
246 
247 struct tp_mib_stats {
248 	u32 ipInReceive_hi;
249 	u32 ipInReceive_lo;
250 	u32 ipInHdrErrors_hi;
251 	u32 ipInHdrErrors_lo;
252 	u32 ipInAddrErrors_hi;
253 	u32 ipInAddrErrors_lo;
254 	u32 ipInUnknownProtos_hi;
255 	u32 ipInUnknownProtos_lo;
256 	u32 ipInDiscards_hi;
257 	u32 ipInDiscards_lo;
258 	u32 ipInDelivers_hi;
259 	u32 ipInDelivers_lo;
260 	u32 ipOutRequests_hi;
261 	u32 ipOutRequests_lo;
262 	u32 ipOutDiscards_hi;
263 	u32 ipOutDiscards_lo;
264 	u32 ipOutNoRoutes_hi;
265 	u32 ipOutNoRoutes_lo;
266 	u32 ipReasmTimeout;
267 	u32 ipReasmReqds;
268 	u32 ipReasmOKs;
269 	u32 ipReasmFails;
270 
271 	u32 reserved[8];
272 
273 	u32 tcpActiveOpens;
274 	u32 tcpPassiveOpens;
275 	u32 tcpAttemptFails;
276 	u32 tcpEstabResets;
277 	u32 tcpOutRsts;
278 	u32 tcpCurrEstab;
279 	u32 tcpInSegs_hi;
280 	u32 tcpInSegs_lo;
281 	u32 tcpOutSegs_hi;
282 	u32 tcpOutSegs_lo;
283 	u32 tcpRetransSeg_hi;
284 	u32 tcpRetransSeg_lo;
285 	u32 tcpInErrs_hi;
286 	u32 tcpInErrs_lo;
287 	u32 tcpRtoMin;
288 	u32 tcpRtoMax;
289 };
290 
291 struct tp_params {
292 	unsigned int nchan;          /* # of channels */
293 	unsigned int pmrx_size;      /* total PMRX capacity */
294 	unsigned int pmtx_size;      /* total PMTX capacity */
295 	unsigned int cm_size;        /* total CM capacity */
296 	unsigned int chan_rx_size;   /* per channel Rx size */
297 	unsigned int chan_tx_size;   /* per channel Tx size */
298 	unsigned int rx_pg_size;     /* Rx page size */
299 	unsigned int tx_pg_size;     /* Tx page size */
300 	unsigned int rx_num_pgs;     /* # of Rx pages */
301 	unsigned int tx_num_pgs;     /* # of Tx pages */
302 	unsigned int ntimer_qs;      /* # of timer queues */
303 	unsigned int tre;            /* log2 of core clocks per TP tick */
304 	unsigned int dack_re;        /* DACK timer resolution */
305 };
306 
307 struct qset_params {                   /* SGE queue set parameters */
308 	unsigned int polling;          /* polling/interrupt service for rspq */
309 	unsigned int lro;              /* large receive offload */
310 	unsigned int coalesce_nsecs;   /* irq coalescing timer */
311 	unsigned int rspq_size;        /* # of entries in response queue */
312 	unsigned int fl_size;          /* # of entries in regular free list */
313 	unsigned int jumbo_size;       /* # of entries in jumbo free list */
314 	unsigned int txq_size[SGE_TXQ_PER_SET];  /* Tx queue sizes */
315 	unsigned int cong_thres;       /* FL congestion threshold */
316 	unsigned int vector;           /* Interrupt (line or vector) number */
317 };
318 
319 struct sge_params {
320 	unsigned int max_pkt_size;     /* max offload pkt size */
321 	struct qset_params qset[SGE_QSETS];
322 };
323 
324 struct mc5_params {
325 	unsigned int mode;       /* selects MC5 width */
326 	unsigned int nservers;   /* size of server region */
327 	unsigned int nfilters;   /* size of filter region */
328 	unsigned int nroutes;    /* size of routing region */
329 };
330 
331 /* Default MC5 region sizes */
332 enum {
333 	DEFAULT_NSERVERS = 512,
334 	DEFAULT_NFILTERS = 128
335 };
336 
337 /* MC5 modes, these must be non-0 */
338 enum {
339 	MC5_MODE_144_BIT = 1,
340 	MC5_MODE_72_BIT  = 2
341 };
342 
343 /* MC5 min active region size */
344 enum { MC5_MIN_TIDS = 16 };
345 
346 struct vpd_params {
347 	unsigned int cclk;
348 	unsigned int mclk;
349 	unsigned int uclk;
350 	unsigned int mdc;
351 	unsigned int mem_timing;
352 	u8 sn[SERNUM_LEN + 1];
353 	u8 eth_base[6];
354 	u8 port_type[MAX_NPORTS];
355 	unsigned short xauicfg[2];
356 };
357 
358 struct pci_params {
359 	unsigned int   vpd_cap_addr;
360 	unsigned int   pcie_cap_addr;
361 	unsigned short speed;
362 	unsigned char  width;
363 	unsigned char  variant;
364 };
365 
366 enum {
367 	PCI_VARIANT_PCI,
368 	PCI_VARIANT_PCIX_MODE1_PARITY,
369 	PCI_VARIANT_PCIX_MODE1_ECC,
370 	PCI_VARIANT_PCIX_266_MODE2,
371 	PCI_VARIANT_PCIE
372 };
373 
374 struct adapter_params {
375 	struct sge_params sge;
376 	struct mc5_params mc5;
377 	struct tp_params  tp;
378 	struct vpd_params vpd;
379 	struct pci_params pci;
380 
381 	const struct adapter_info *info;
382 
383 #ifdef CONFIG_CHELSIO_T3_CORE
384 	unsigned short mtus[NMTUS];
385 	unsigned short a_wnd[NCCTRL_WIN];
386 	unsigned short b_wnd[NCCTRL_WIN];
387 #endif
388 	unsigned int   nports;              /* # of ethernet ports */
389 	unsigned int   chan_map;            /* bitmap of in-use Tx channels */
390 	unsigned int   stats_update_period; /* MAC stats accumulation period */
391 	unsigned int   linkpoll_period;     /* link poll period in 0.1s */
392 	unsigned int   rev;                 /* chip revision */
393 	unsigned int   offload;
394 };
395 
396 enum {					    /* chip revisions */
397 	T3_REV_A  = 0,
398 	T3_REV_B  = 2,
399 	T3_REV_B2 = 3,
400 	T3_REV_C  = 4,
401 };
402 
403 struct trace_params {
404 	u32 sip;
405        	u32 sip_mask;
406 	u32 dip;
407        	u32 dip_mask;
408 	u16 sport;
409 	u16 sport_mask;
410 	u16 dport;
411 	u16 dport_mask;
412 	u32 vlan:12;
413 	u32 vlan_mask:12;
414 	u32 intf:4;
415 	u32 intf_mask:4;
416 	u8  proto;
417 	u8  proto_mask;
418 };
419 
420 struct link_config {
421 	unsigned int   supported;        /* link capabilities */
422 	unsigned int   advertising;      /* advertised capabilities */
423         unsigned short requested_speed;  /* speed user has requested */
424 	unsigned short speed;            /* actual link speed */
425         unsigned char  requested_duplex; /* duplex user has requested */
426 	unsigned char  duplex;           /* actual link duplex */
427 	unsigned char  requested_fc;     /* flow control user has requested */
428 	unsigned char  fc;               /* actual link flow control */
429 	unsigned char  autoneg;          /* autonegotiating? */
430 	unsigned int link_ok;          /* link up? */
431 };
432 
433 #define SPEED_INVALID   0xffff
434 #define DUPLEX_INVALID  0xff
435 
436 struct mc5 {
437 	adapter_t *adapter;
438 	unsigned int tcam_size;
439 	unsigned char part_type;
440 	unsigned char parity_enabled;
441 	unsigned char mode;
442 	struct mc5_stats stats;
443 };
444 
445 static inline unsigned int t3_mc5_size(const struct mc5 *p)
446 {
447 	return p->tcam_size;
448 }
449 
450 struct mc7 {
451 	adapter_t *adapter;     /* backpointer to adapter */
452 	unsigned int size;      /* memory size in bytes */
453 	unsigned int width;     /* MC7 interface width */
454 	unsigned int offset;    /* register address offset for MC7 instance */
455 	const char *name;       /* name of MC7 instance */
456 	struct mc7_stats stats; /* MC7 statistics */
457 };
458 
459 static inline unsigned int t3_mc7_size(const struct mc7 *p)
460 {
461 	return p->size;
462 }
463 
464 struct cmac {
465 	adapter_t *adapter;
466 	unsigned int offset;
467 	unsigned char nucast;    /* # of address filters for unicast MACs */
468 	unsigned char multiport; /* multiple ports connected to this MAC */
469 	unsigned char ext_port;  /* external MAC port */
470 	unsigned char promisc_map;  /* which external ports are promiscuous */
471 	unsigned int tx_tcnt;
472 	unsigned int tx_xcnt;
473 	u64 tx_mcnt;
474 	unsigned int rx_xcnt;
475 	unsigned int rx_ocnt;
476 	u64 rx_mcnt;
477 	unsigned int toggle_cnt;
478 	unsigned int txen;
479 	u64 rx_pause;
480 	struct mac_stats stats;
481 };
482 
483 enum {
484 	MAC_DIRECTION_RX = 1,
485 	MAC_DIRECTION_TX = 2,
486 	MAC_RXFIFO_SIZE  = 32768
487 };
488 
489 /* IEEE 802.3ae specified MDIO devices */
490 enum {
491 	MDIO_DEV_PMA_PMD = 1,
492 	MDIO_DEV_WIS     = 2,
493 	MDIO_DEV_PCS     = 3,
494 	MDIO_DEV_XGXS    = 4
495 };
496 
497 /* PHY loopback direction */
498 enum {
499 	PHY_LOOPBACK_TX = 1,
500 	PHY_LOOPBACK_RX = 2
501 };
502 
503 /* PHY interrupt types */
504 enum {
505 	cphy_cause_link_change = 1,
506 	cphy_cause_fifo_error = 2
507 };
508 
509 /* PHY operations */
510 struct cphy_ops {
511 	void (*destroy)(struct cphy *phy);
512 	int (*reset)(struct cphy *phy, int wait);
513 
514 	int (*intr_enable)(struct cphy *phy);
515 	int (*intr_disable)(struct cphy *phy);
516 	int (*intr_clear)(struct cphy *phy);
517 	int (*intr_handler)(struct cphy *phy);
518 
519 	int (*autoneg_enable)(struct cphy *phy);
520 	int (*autoneg_restart)(struct cphy *phy);
521 
522 	int (*advertise)(struct cphy *phy, unsigned int advertise_map);
523 	int (*set_loopback)(struct cphy *phy, int mmd, int dir, int enable);
524 	int (*set_speed_duplex)(struct cphy *phy, int speed, int duplex);
525 	int (*get_link_status)(struct cphy *phy, int *link_ok, int *speed,
526 			       int *duplex, int *fc);
527 	int (*power_down)(struct cphy *phy, int enable);
528 };
529 
530 /* A PHY instance */
531 struct cphy {
532 	int addr;                            /* PHY address */
533 	adapter_t *adapter;                  /* associated adapter */
534 	unsigned long fifo_errors;           /* FIFO over/under-flows */
535 	const struct cphy_ops *ops;          /* PHY operations */
536 	int (*mdio_read)(adapter_t *adapter, int phy_addr, int mmd_addr,
537 			 int reg_addr, unsigned int *val);
538 	int (*mdio_write)(adapter_t *adapter, int phy_addr, int mmd_addr,
539 			  int reg_addr, unsigned int val);
540 };
541 
542 /* Convenience MDIO read/write wrappers */
543 static inline int mdio_read(struct cphy *phy, int mmd, int reg,
544 			    unsigned int *valp)
545 {
546         return phy->mdio_read(phy->adapter, phy->addr, mmd, reg, valp);
547 }
548 
549 static inline int mdio_write(struct cphy *phy, int mmd, int reg,
550 			     unsigned int val)
551 {
552         return phy->mdio_write(phy->adapter, phy->addr, mmd, reg, val);
553 }
554 
555 /* Convenience initializer */
556 static inline void cphy_init(struct cphy *phy, adapter_t *adapter,
557 			     int phy_addr, struct cphy_ops *phy_ops,
558 			     const struct mdio_ops *mdio_ops)
559 {
560 	phy->adapter = adapter;
561 	phy->addr    = phy_addr;
562 	phy->ops     = phy_ops;
563 	if (mdio_ops) {
564 		phy->mdio_read  = mdio_ops->read;
565 		phy->mdio_write = mdio_ops->write;
566 	}
567 }
568 
569 /* Accumulate MAC statistics every 180 seconds.  For 1G we multiply by 10. */
570 #define MAC_STATS_ACCUM_SECS 180
571 
572 /* The external MAC needs accumulation every 30 seconds */
573 #define VSC_STATS_ACCUM_SECS 30
574 
575 #define XGM_REG(reg_addr, idx) \
576 	((reg_addr) + (idx) * (XGMAC0_1_BASE_ADDR - XGMAC0_0_BASE_ADDR))
577 
578 struct addr_val_pair {
579 	unsigned int reg_addr;
580 	unsigned int val;
581 };
582 
583 #ifdef CONFIG_DEFINED
584 #include <cxgb_adapter.h>
585 #else
586 #include <dev/cxgb/cxgb_adapter.h>
587 #endif
588 
589 #ifndef PCI_VENDOR_ID_CHELSIO
590 # define PCI_VENDOR_ID_CHELSIO 0x1425
591 #endif
592 
593 #define for_each_port(adapter, iter) \
594 	for (iter = 0; iter < (adapter)->params.nports; ++iter)
595 
596 #define adapter_info(adap) ((adap)->params.info)
597 
598 static inline int uses_xaui(const adapter_t *adap)
599 {
600 	return adapter_info(adap)->caps & SUPPORTED_AUI;
601 }
602 
603 static inline int is_10G(const adapter_t *adap)
604 {
605 	return adapter_info(adap)->caps & SUPPORTED_10000baseT_Full;
606 }
607 
608 static inline int is_offload(const adapter_t *adap)
609 {
610 #ifdef CONFIG_CHELSIO_T3_CORE
611 	return adap->params.offload;
612 #else
613 	return 0;
614 #endif
615 }
616 
617 static inline unsigned int core_ticks_per_usec(const adapter_t *adap)
618 {
619 	return adap->params.vpd.cclk / 1000;
620 }
621 
622 static inline unsigned int dack_ticks_to_usec(const adapter_t *adap,
623 					      unsigned int ticks)
624 {
625 	return (ticks << adap->params.tp.dack_re) / core_ticks_per_usec(adap);
626 }
627 
628 static inline unsigned int is_pcie(const adapter_t *adap)
629 {
630 	return adap->params.pci.variant == PCI_VARIANT_PCIE;
631 }
632 
633 void t3_set_reg_field(adapter_t *adap, unsigned int addr, u32 mask, u32 val);
634 void t3_write_regs(adapter_t *adapter, const struct addr_val_pair *p, int n,
635 		   unsigned int offset);
636 int t3_wait_op_done_val(adapter_t *adapter, int reg, u32 mask, int polarity,
637 			int attempts, int delay, u32 *valp);
638 
639 static inline int t3_wait_op_done(adapter_t *adapter, int reg, u32 mask,
640 				  int polarity, int attempts, int delay)
641 {
642 	return t3_wait_op_done_val(adapter, reg, mask, polarity, attempts,
643 				   delay, NULL);
644 }
645 
646 int t3_mdio_change_bits(struct cphy *phy, int mmd, int reg, unsigned int clear,
647 			unsigned int set);
648 int t3_phy_reset(struct cphy *phy, int mmd, int wait);
649 int t3_phy_advertise(struct cphy *phy, unsigned int advert);
650 int t3_set_phy_speed_duplex(struct cphy *phy, int speed, int duplex);
651 
652 void t3_intr_enable(adapter_t *adapter);
653 void t3_intr_disable(adapter_t *adapter);
654 void t3_intr_clear(adapter_t *adapter);
655 void t3_port_intr_enable(adapter_t *adapter, int idx);
656 void t3_port_intr_disable(adapter_t *adapter, int idx);
657 void t3_port_intr_clear(adapter_t *adapter, int idx);
658 int t3_slow_intr_handler(adapter_t *adapter);
659 int t3_phy_intr_handler(adapter_t *adapter);
660 
661 void t3_link_changed(adapter_t *adapter, int port_id);
662 int t3_link_start(struct cphy *phy, struct cmac *mac, struct link_config *lc);
663 const struct adapter_info *t3_get_adapter_info(unsigned int board_id);
664 int t3_seeprom_read(adapter_t *adapter, u32 addr, u32 *data);
665 int t3_seeprom_write(adapter_t *adapter, u32 addr, u32 data);
666 int t3_seeprom_wp(adapter_t *adapter, int enable);
667 int t3_read_flash(adapter_t *adapter, unsigned int addr, unsigned int nwords,
668 		  u32 *data, int byte_oriented);
669 int t3_get_tp_version(adapter_t *adapter, u32 *vers);
670 int t3_check_tpsram_version(adapter_t *adapter);
671 int t3_check_tpsram(adapter_t *adapter, const u8 *tp_ram, unsigned int size);
672 int t3_load_fw(adapter_t *adapter, const const u8 *fw_data, unsigned int size);
673 int t3_get_fw_version(adapter_t *adapter, u32 *vers);
674 int t3_check_fw_version(adapter_t *adapter);
675 int t3_init_hw(adapter_t *adapter, u32 fw_params);
676 void mac_prep(struct cmac *mac, adapter_t *adapter, int index);
677 void early_hw_init(adapter_t *adapter, const struct adapter_info *ai);
678 int t3_prep_adapter(adapter_t *adapter, const struct adapter_info *ai, int reset);
679 void t3_led_ready(adapter_t *adapter);
680 void t3_fatal_err(adapter_t *adapter);
681 void t3_set_vlan_accel(adapter_t *adapter, unsigned int ports, int on);
682 void t3_enable_filters(adapter_t *adap);
683 void t3_config_rss(adapter_t *adapter, unsigned int rss_config, const u8 *cpus,
684 		   const u16 *rspq);
685 int t3_read_rss(adapter_t *adapter, u8 *lkup, u16 *map);
686 int t3_set_proto_sram(adapter_t *adap, const u8 *data);
687 int t3_mps_set_active_ports(adapter_t *adap, unsigned int port_mask);
688 void t3_port_failover(adapter_t *adapter, int port);
689 void t3_failover_done(adapter_t *adapter, int port);
690 void t3_failover_clear(adapter_t *adapter);
691 int t3_cim_ctl_blk_read(adapter_t *adap, unsigned int addr, unsigned int n,
692 			unsigned int *valp);
693 int t3_mc7_bd_read(struct mc7 *mc7, unsigned int start, unsigned int n,
694 		   u64 *buf);
695 
696 int t3_mac_reset(struct cmac *mac);
697 void t3b_pcs_reset(struct cmac *mac);
698 int t3_mac_enable(struct cmac *mac, int which);
699 int t3_mac_disable(struct cmac *mac, int which);
700 int t3_mac_set_mtu(struct cmac *mac, unsigned int mtu);
701 int t3_mac_set_rx_mode(struct cmac *mac, struct t3_rx_mode *rm);
702 int t3_mac_set_address(struct cmac *mac, unsigned int idx, u8 addr[6]);
703 int t3_mac_set_num_ucast(struct cmac *mac, unsigned char n);
704 const struct mac_stats *t3_mac_update_stats(struct cmac *mac);
705 int t3_mac_set_speed_duplex_fc(struct cmac *mac, int speed, int duplex,
706 			       int fc);
707 int t3b2_mac_watchdog_task(struct cmac *mac);
708 
709 void t3_mc5_prep(adapter_t *adapter, struct mc5 *mc5, int mode);
710 int t3_mc5_init(struct mc5 *mc5, unsigned int nservers, unsigned int nfilters,
711 		unsigned int nroutes);
712 void t3_mc5_intr_handler(struct mc5 *mc5);
713 int t3_read_mc5_range(const struct mc5 *mc5, unsigned int start, unsigned int n,
714 		      u32 *buf);
715 
716 #ifdef CONFIG_CHELSIO_T3_CORE
717 int t3_tp_set_coalescing_size(adapter_t *adap, unsigned int size, int psh);
718 void t3_tp_set_max_rxsize(adapter_t *adap, unsigned int size);
719 void t3_tp_set_offload_mode(adapter_t *adap, int enable);
720 void t3_tp_get_mib_stats(adapter_t *adap, struct tp_mib_stats *tps);
721 void t3_load_mtus(adapter_t *adap, unsigned short mtus[NMTUS],
722                   unsigned short alpha[NCCTRL_WIN],
723 		  unsigned short beta[NCCTRL_WIN], unsigned short mtu_cap);
724 void t3_read_hw_mtus(adapter_t *adap, unsigned short mtus[NMTUS]);
725 void t3_get_cong_cntl_tab(adapter_t *adap,
726 			  unsigned short incr[NMTUS][NCCTRL_WIN]);
727 void t3_config_trace_filter(adapter_t *adapter, const struct trace_params *tp,
728 			    int filter_index, int invert, int enable);
729 int t3_config_sched(adapter_t *adap, unsigned int kbps, int sched);
730 int t3_set_sched_ipg(adapter_t *adap, int sched, unsigned int ipg);
731 void t3_get_tx_sched(adapter_t *adap, unsigned int sched, unsigned int *kbps,
732 		     unsigned int *ipg);
733 void t3_read_pace_tbl(adapter_t *adap, unsigned int pace_vals[NTX_SCHED]);
734 void t3_set_pace_tbl(adapter_t *adap, unsigned int *pace_vals,
735 		     unsigned int start, unsigned int n);
736 #endif
737 
738 void t3_sge_prep(adapter_t *adap, struct sge_params *p);
739 void t3_sge_init(adapter_t *adap, struct sge_params *p);
740 int t3_sge_init_ecntxt(adapter_t *adapter, unsigned int id, int gts_enable,
741 		       enum sge_context_type type, int respq, u64 base_addr,
742 		       unsigned int size, unsigned int token, int gen,
743 		       unsigned int cidx);
744 int t3_sge_init_flcntxt(adapter_t *adapter, unsigned int id, int gts_enable,
745 			u64 base_addr, unsigned int size, unsigned int esize,
746 			unsigned int cong_thres, int gen, unsigned int cidx);
747 int t3_sge_init_rspcntxt(adapter_t *adapter, unsigned int id, int irq_vec_idx,
748 			 u64 base_addr, unsigned int size,
749 			 unsigned int fl_thres, int gen, unsigned int cidx);
750 int t3_sge_init_cqcntxt(adapter_t *adapter, unsigned int id, u64 base_addr,
751  			unsigned int size, int rspq, int ovfl_mode,
752 			unsigned int credits, unsigned int credit_thres);
753 int t3_sge_enable_ecntxt(adapter_t *adapter, unsigned int id, int enable);
754 int t3_sge_disable_fl(adapter_t *adapter, unsigned int id);
755 int t3_sge_disable_rspcntxt(adapter_t *adapter, unsigned int id);
756 int t3_sge_disable_cqcntxt(adapter_t *adapter, unsigned int id);
757 int t3_sge_read_ecntxt(adapter_t *adapter, unsigned int id, u32 data[4]);
758 int t3_sge_read_fl(adapter_t *adapter, unsigned int id, u32 data[4]);
759 int t3_sge_read_cq(adapter_t *adapter, unsigned int id, u32 data[4]);
760 int t3_sge_read_rspq(adapter_t *adapter, unsigned int id, u32 data[4]);
761 int t3_sge_cqcntxt_op(adapter_t *adapter, unsigned int id, unsigned int op,
762 		      unsigned int credits);
763 
764 int t3_elmr_blk_write(adapter_t *adap, int start, const u32 *vals, int n);
765 int t3_elmr_blk_read(adapter_t *adap, int start, u32 *vals, int n);
766 int t3_vsc7323_init(adapter_t *adap, int nports);
767 int t3_vsc7323_set_speed_fc(adapter_t *adap, int speed, int fc, int port);
768 int t3_vsc7323_set_mtu(adapter_t *adap, unsigned int mtu, int port);
769 int t3_vsc7323_set_addr(adapter_t *adap, u8 addr[6], int port);
770 int t3_vsc7323_enable(adapter_t *adap, int port, int which);
771 int t3_vsc7323_disable(adapter_t *adap, int port, int which);
772 const struct mac_stats *t3_vsc7323_update_stats(struct cmac *mac);
773 
774 void t3_mv88e1xxx_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
775 			   const struct mdio_ops *mdio_ops);
776 void t3_vsc8211_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
777 			 const struct mdio_ops *mdio_ops);
778 void t3_ael1002_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
779 			 const struct mdio_ops *mdio_ops);
780 void t3_ael1006_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
781 			 const struct mdio_ops *mdio_ops);
782 void t3_qt2045_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
783 			const struct mdio_ops *mdio_ops);
784 void t3_xaui_direct_phy_prep(struct cphy *phy, adapter_t *adapter, int phy_addr,
785 			     const struct mdio_ops *mdio_ops);
786 #endif /* __CHELSIO_COMMON_H */
787