1 /*- 2 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2010 Broadcom Corporation 4 * All rights reserved. 5 * 6 * This file is derived from the sbchipc.h header distributed with 7 * Broadcom's initial brcm80211 Linux driver release, as 8 * contributed to the Linux staging repository. 9 * 10 * Permission to use, copy, modify, and/or distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 17 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 19 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 20 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 * 22 * $FreeBSD$ 23 */ 24 25 #ifndef _BHND_CORES_CHIPC_CHIPCREG_H_ 26 #define _BHND_CORES_CHIPC_CHIPCREG_H_ 27 28 #define CHIPC_CHIPID_SIZE 0x100 /**< size of the register block 29 containing the chip 30 identification registers 31 required during bus 32 enumeration */ 33 34 /** Evaluates to true if the given ChipCommon core revision provides 35 * the core count via the chip identification register. */ 36 #define CHIPC_NCORES_MIN_HWREV(hwrev) ((hwrev) == 4 || (hwrev) >= 6) 37 38 #define CHIPC_GET_FLAG(_value, _flag) (((_value) & _flag) != 0) 39 #define CHIPC_GET_BITS(_value, _field) \ 40 ((_value & _field ## _MASK) >> _field ## _SHIFT) 41 42 43 #define CHIPC_ID 0x00 44 #define CHIPC_CAPABILITIES 0x04 45 #define CHIPC_CORECTRL 0x08 /* rev >= 1 */ 46 #define CHIPC_BIST 0x0C 47 48 #define CHIPC_OTPST 0x10 /**< otp status */ 49 #define CHIPC_OTPCTRL 0x14 /**< otp control */ 50 #define CHIPC_OTPPROG 0x18 51 #define CHIPC_OTPLAYOUT 0x1C /**< otp layout (IPX OTP) */ 52 53 #define CHIPC_INTST 0x20 /**< interrupt status */ 54 #define CHIPC_INTM 0x24 /**< interrupt mask */ 55 56 #define CHIPC_CHIPCTRL 0x28 /**< chip control (rev >= 11) */ 57 #define CHIPC_CHIPST 0x2C /**< chip status (rev >= 11) */ 58 59 #define CHIPC_JTAGCMD 0x30 60 #define CHIPC_JTAGIR 0x34 61 #define CHIPC_JTAGDR 0x38 62 #define CHIPC_JTAGCTRL 0x3c 63 64 #define CHIPC_SFLASH_BASE 0x40 65 #define CHIPC_SFLASH_SIZE 12 66 #define CHIPC_SFLASHCTRL 0x40 67 #define CHIPC_SFLASHADDR 0x44 68 #define CHIPC_SFLASHDATA 0x48 69 70 /* siba backplane configuration broadcast (siba-only) */ 71 #define CHIPC_SBBCAST_ADDR 0x50 72 #define CHIPC_SBBCAST_DATA 0x54 73 74 #define CHIPC_GPIOPU 0x58 /**< pull-up mask (rev >= 20) */ 75 #define CHIPC_GPIOPD 0x5C /**< pull down mask (rev >= 20) */ 76 #define CHIPC_GPIOIN 0x60 77 #define CHIPC_GPIOOUT 0x64 78 #define CHIPC_GPIOOUTEN 0x68 79 #define CHIPC_GPIOCTRL 0x6C 80 #define CHIPC_GPIOPOL 0x70 81 #define CHIPC_GPIOINTM 0x74 /**< gpio interrupt mask */ 82 83 #define CHIPC_GPIOEVENT 0x78 /**< gpio event (rev >= 11) */ 84 #define CHIPC_GPIOEVENT_INTM 0x7C /**< gpio event interrupt mask (rev >= 11) */ 85 86 #define CHIPC_WATCHDOG 0x80 /**< watchdog timer */ 87 88 #define CHIPC_GPIOEVENT_INTPOLARITY 0x84 /**< gpio even interrupt polarity (rev >= 11) */ 89 90 #define CHIPC_GPIOTIMERVAL 0x88 /**< gpio-based LED duty cycle (rev >= 16) */ 91 #define CHIPC_GPIOTIMEROUTMASK 0x8C 92 93 /* clock control block */ 94 #define CHIPC_CLKC_N 0x90 95 #define CHIPC_CLKC_SB 0x94 /* m0 (backplane) */ 96 #define CHIPC_CLKC_PCI 0x98 /* m1 */ 97 #define CHIPC_CLKC_M2 0x9C /* mii/uart/mipsref */ 98 #define CHIPC_CLKC_M3 0xA0 /* cpu */ 99 #define CHIPC_CLKDIV 0xA4 /* rev >= 3 */ 100 #define CHIPC_GPIODEBUGSEL 0xA8 /* rev >= 28 */ 101 #define CHIPC_CAPABILITIES_EXT 0xAC 102 103 /* pll delay (registers rev >= 4) */ 104 #define CHIPC_PLL_ON_DELAY 0xB0 105 #define CHIPC_PLL_FREFSEL_DELAY 0xB4 106 #define CHIPC_PLL_SLOWCLK_CTL 0xB8 /* revs 6-9 */ 107 108 /* "instaclock" registers */ 109 #define CHIPC_SYS_CLK_CTL 0xC0 /* rev >= 10 */ 110 #define CHIPC_SYS_CLKSTATESTRETCH 0xC4 /* rev >= 10 */ 111 112 /* indirect backplane access (rev >= 10) */ 113 #define CHIPC_BP_ADDRLOW 0xD0 114 #define CHIPC_BP_ADDRHIGH 0xD4 115 #define CHIPC_BP_DATA 0xD8 116 #define CHIPC_BP_INDACCESS 0xE0 117 118 /* SPI/I2C (rev >= 37) */ 119 #define CHIPC_GSIO_CTRL 0xE4 120 #define CHIPC_GSIO_ADDR 0xE8 121 #define CHIPC_GSIO_DATA 0xEC 122 123 /* More clock dividers (corerev >= 32) */ 124 #define CHIPC_CLKDIV2 0xF0 125 126 #define CHIPC_EROMPTR 0xFC /**< 32-bit EROM base address 127 * on BCMA devices */ 128 129 /* ExtBus control registers (rev >= 3) */ 130 #define CHIPC_PCMCIA_CFG 0x100 131 #define CHIPC_PCMCIA_MEMWAIT 0x104 132 #define CHIPC_PCMCIA_ATTRWAIT 0x108 133 #define CHIPC_PCMCIA_IOWAIT 0x10C 134 #define CHIPC_IDE_CFG 0x110 135 #define CHIPC_IDE_MEMWAIT 0x114 136 #define CHIPC_IDE_ATTRWAIT 0x118 137 #define CHIPC_IDE_IOWAIT 0x11C 138 #define CHIPC_PROG_CFG 0x120 139 #define CHIPC_PROG_WAITCOUNT 0x124 140 #define CHIPC_FLASH_CFG 0x128 141 #define CHIPC_FLASH_WAITCOUNT 0x12C 142 #define CHIPC_SECI_CFG 0x130 143 #define CHIPC_SECI_ST 0x134 144 #define CHIPC_SECI_STM 0x138 145 #define CHIPC_SECI_RXNBC 0x13C 146 147 /* Enhanced Coexistence Interface (ECI) registers (rev 21-34) */ 148 #define CHIPC_ECI_OUTPUT 0x140 149 #define CHIPC_ECI_CTRL 0x144 150 #define CHIPC_ECI_INPUTLO 0x148 151 #define CHIPC_ECI_INPUTMI 0x14C 152 #define CHIPC_ECI_INPUTHI 0x150 153 #define CHIPC_ECI_INPUTINTPOLARITYLO 0x154 154 #define CHIPC_ECI_INPUTINTPOLARITYMI 0x158 155 #define CHIPC_ECI_INPUTINTPOLARITYHI 0x15C 156 #define CHIPC_ECI_INTMASKLO 0x160 157 #define CHIPC_ECI_INTMASKMI 0x164 158 #define CHIPC_ECI_INTMASKHI 0x168 159 #define CHIPC_ECI_EVENTLO 0x16C 160 #define CHIPC_ECI_EVENTMI 0x170 161 #define CHIPC_ECI_EVENTHI 0x174 162 #define CHIPC_ECI_EVENTMASKLO 0x178 163 #define CHIPC_ECI_EVENTMASKMI 0x17C 164 #define CHIPC_ECI_EVENTMASKHI 0x180 165 166 #define CHIPC_FLASHSTRCFG 0x18C /**< BCM4706 NAND flash config */ 167 168 #define CHIPC_SPROM_CTRL 0x190 /**< SPROM interface (rev >= 32) */ 169 #define CHIPC_SPROM_ADDR 0x194 170 #define CHIPC_SPROM_DATA 0x198 171 172 /* Clock control and hardware workarounds (corerev >= 20) */ 173 #define CHIPC_CLK_CTL_ST 0x1E0 174 #define CHIPC_SPROM_HWWAR 0x19 175 176 #define CHIPC_UART_BASE 0x300 177 #define CHIPC_UART_SIZE 0x100 178 #define CHIPC_UART0_BASE CHIPC_UART_BASE 179 #define CHIPC_UART1_BASE (CHIPC_UART_BASE + CHIPC_UART_SIZE) 180 181 /* PMU registers (rev >= 20) */ 182 #define CHIPC_PMU_BASE 0x600 183 #define CHIPC_PMU_SIZE 0x70 184 185 #define CHIPC_PMU_CTRL 0x600 186 #define CHIPC_PMU_CAP 0x604 187 #define CHIPC_PMU_ST 0x608 188 #define CHIPC_PMU_RES_STATE 0x60c 189 #define CHIPC_PMU_RES_PENDING 0x610 190 #define CHIPC_PMU_TIMER 0x614 191 #define CHIPC_PMU_MIN_RES_MASK 0x618 192 #define CHIPC_PMU_MAX_RES_MASK 0x61c 193 #define CHIPC_PMU_RES_TABLE_SEL 0x620 194 #define CHIPC_PMU_RES_DEP_MASK 0x624 195 #define CHIPC_PMU_RES_UPDN_TIMER 0x628 196 #define CHIPC_PMU_RES_TIMER 0x62C 197 #define CHIPC_PMU_CLKSTRETCH 0x630 198 #define CHIPC_PMU_WATCHDOG 0x634 199 #define CHIPC_PMU_GPIOSEL 0x638 /* pmu rev >= 1 ? */ 200 #define CHIPC_PMU_GPIOEN 0x63C /* pmu rev >= 1 ? */ 201 #define CHIPC_PMU_RES_REQ_TIMER_SEL 0x640 202 #define CHIPC_PMU_RES_REQ_TIMER 0x644 203 #define CHIPC_PMU_RES_REQ_MASK 0x648 204 #define CHIPC_CHIPCTL_ADDR 0x650 205 #define CHIPC_CHIPCTL_DATA 0x654 206 #define CHIPC_PMU_REG_CONTROL_ADDR 0x658 207 #define CHIPC_PMU_REG_CONTROL_DATA 0x65C 208 #define CHIPC_PMU_PLL_CONTROL_ADDR 0x660 209 #define CHIPC_PMU_PLL_CONTROL_DATA 0x664 210 #define CHIPC_PMU_STRAPOPT 0x668 /* chipc rev >= 28 */ 211 #define CHIPC_PMU_XTALFREQ 0x66C /* pmu rev >= 10 */ 212 213 #define CHIPC_SPROM_OTP 0x800 /* SPROM/OTP address space */ 214 #define CHIPC_SPROM_OTP_SIZE 0x400 215 216 /** chipid */ 217 #define CHIPC_ID_CHIP_MASK 0x0000FFFF /**< chip id */ 218 #define CHIPC_ID_CHIP_SHIFT 0 219 #define CHIPC_ID_REV_MASK 0x000F0000 /**< chip revision */ 220 #define CHIPC_ID_REV_SHIFT 16 221 #define CHIPC_ID_PKG_MASK 0x00F00000 /**< physical package ID */ 222 #define CHIPC_ID_PKG_SHIFT 20 223 #define CHIPC_ID_NUMCORE_MASK 0x0F000000 /**< number of cores on chip (rev >= 4) */ 224 #define CHIPC_ID_NUMCORE_SHIFT 24 225 #define CHIPC_ID_BUS_MASK 0xF0000000 /**< chip/interconnect type (BHND_CHIPTYPE_*) */ 226 #define CHIPC_ID_BUS_SHIFT 28 227 228 /* capabilities */ 229 #define CHIPC_CAP_NUM_UART_MASK 0x00000003 /* Number of UARTs (1-3) */ 230 #define CHIPC_CAP_NUM_UART_SHIFT 0 231 #define CHIPC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */ 232 #define CHIPC_CAP_UCLKSEL_MASK 0x00000018 /* UARTs clock select */ 233 #define CHIPC_CAP_UCLKSEL_SHIFT 3 234 #define CHIPC_CAP_UCLKSEL_UINTCLK 0x1 /* UARTs are driven by internal divided clock */ 235 #define CHIPC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */ 236 #define CHIPC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ 237 #define CHIPC_CAP_EXTBUS_SHIFT 6 238 #define CHIPC_CAP_EXTBUS_NONE 0x0 /* No ExtBus present */ 239 #define CHIPC_CAP_EXTBUS_FULL 0x1 /* ExtBus: PCMCIA, IDE & Prog */ 240 #define CHIPC_CAP_EXTBUS_PROG 0x2 /* ExtBus: ProgIf only */ 241 #define CHIPC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ 242 #define CHIPC_CAP_FLASH_SHIFT 8 243 #define CHIPC_CAP_FLASH_NONE 0x0 /* No flash */ 244 #define CHIPC_CAP_SFLASH_ST 0x1 /* ST serial flash */ 245 #define CHIPC_CAP_SFLASH_AT 0x2 /* Atmel serial flash */ 246 #define CHIPC_CAP_NFLASH 0x3 /* NAND flash */ 247 #define CHIPC_CAP_PFLASH 0x7 /* Parallel flash */ 248 #define CHIPC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ 249 #define CHIPC_CAP_PLL_SHIFT 15 250 #define CHIPC_CAP_PWR_CTL 0x00040000 /* Power control */ 251 #define CHIPC_CAP_OTP_SIZE_MASK 0x00380000 /* OTP Size (0 = none) */ 252 #define CHIPC_CAP_OTP_SIZE_SHIFT 19 /* OTP Size shift */ 253 #define CHIPC_CAP_OTP_SIZE_BASE 5 /* OTP Size base */ 254 #define CHIPC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ 255 #define CHIPC_CAP_ROM 0x00800000 /* Internal boot rom active */ 256 #define CHIPC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ 257 #define CHIPC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ 258 #define CHIPC_CAP_ECI 0x20000000 /* Enhanced Coexistence Interface */ 259 #define CHIPC_CAP_SPROM 0x40000000 /* SPROM Present, rev >= 32 */ 260 #define CHIPC_CAP_4706_NFLASH 0x80000000 /* NAND flash present, BCM4706 or chipc rev38 (BCM5357)? */ 261 262 #define CHIPC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */ 263 #define CHIPC_CAP2_GSIO 0x00000002 /* GSIO (spi/i2c) present, rev >= 37 */ 264 #define CHIPC_CAP2_GCI 0x00000004 /* GCI present (rev >= ??) */ 265 #define CHIPC_CAP2_AOB 0x00000040 /* Always on Bus present (rev >= 49) 266 * 267 * If set, PMU and GCI registers 268 * are found in dedicated cores. 269 * 270 * This appears to be a lower power 271 * APB bus, bridged via ARM APB IP. */ 272 273 /* 274 * ChipStatus (Common) 275 */ 276 277 /** ChipStatus CIS/OTP/SPROM values used to advertise OTP/SPROM availability in 278 * chipcommon revs 11-31. */ 279 enum { 280 CHIPC_CST_DEFCIS_SEL = 0, /**< OTP is powered up, use default CIS, no SPROM */ 281 CHIPC_CST_SPROM_SEL = 1, /**< OTP is powered up, SPROM is present */ 282 CHIPC_CST_OTP_SEL = 2, /**< OTP is powered up, no SPROM */ 283 CHIPC_CST_OTP_PWRDN = 3 /**< OTP is powered down, SPROM is present (rev <= 22 only) */ 284 }; 285 286 287 #define CHIPC_CST_SPROM_OTP_SEL_R22_MASK 0x00000003 /**< chipstatus OTP/SPROM SEL value (rev 22) */ 288 #define CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 0 289 #define CHIPC_CST_SPROM_OTP_SEL_R23_MASK 0x000000c0 /**< chipstatus OTP/SPROM SEL value (revs 23-31) 290 * 291 * it is unknown whether this is supported on 292 * any CC revs >= 32 that also vend CHIPC_CAP_* 293 * constants for OTP/SPROM/NVRAM availability. 294 */ 295 #define CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 6 296 297 /* PLL type */ 298 #define CHIPC_PLL_NONE 0x00000000 299 #define CHIPC_PLL_TYPE1 0x00010000 /* 48MHz base, 3 dividers */ 300 #define CHIPC_PLL_TYPE2 0x00020000 /* 48MHz, 4 dividers */ 301 #define CHIPC_PLL_TYPE3 0x00030000 /* 25MHz, 2 dividers */ 302 #define CHIPC_PLL_TYPE4 0x00008000 /* 48MHz, 4 dividers */ 303 #define CHIPC_PLL_TYPE5 0x00018000 /* 25MHz, 4 dividers */ 304 #define CHIPC_PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */ 305 #define CHIPC_PLL_TYPE7 0x00038000 /* 25MHz, 4 dividers */ 306 307 /* ILP clock */ 308 #define CHIPC_ILP_CLOCK 32000 309 310 /* ALP clock on pre-PMU chips */ 311 #define CHIPC_ALP_CLOCK 20000000 312 313 /* HT clock */ 314 #define CHIPC_HT_CLOCK 80000000 315 316 /* corecontrol */ 317 #define CHIPC_UARTCLKO 0x00000001 /* Drive UART with internal clock */ 318 #define CHIPC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ 319 #define CHIPC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */ 320 321 /* chipcontrol */ 322 #define CHIPCTRL_4321A0_DEFAULT 0x3a4 323 #define CHIPCTRL_4321A1_DEFAULT 0x0a4 324 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */ 325 326 /* Fields in the otpstatus register in rev >= 21 */ 327 #define CHIPC_OTPS_OL_MASK 0x000000ff 328 #define CHIPC_OTPS_OL_MFG 0x00000001 /* manuf row is locked */ 329 #define CHIPC_OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */ 330 #define CHIPC_OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */ 331 #define CHIPC_OTPS_OL_GU 0x00000008 /* general use region is locked */ 332 #define CHIPC_OTPS_GUP_MASK 0x00000f00 333 #define CHIPC_OTPS_GUP_SHIFT 8 334 #define CHIPC_OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */ 335 #define CHIPC_OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */ 336 #define CHIPC_OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */ 337 #define CHIPC_OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */ 338 #define CHIPC_OTPS_READY 0x00001000 339 #define CHIPC_OTPS_RV(x) (1 << (16 + (x))) /* redundancy entry valid */ 340 #define CHIPC_OTPS_RV_MASK 0x0fff0000 341 342 /* IPX OTP fields in the otpcontrol register */ 343 #define CHIPC_OTPC_PROGSEL 0x00000001 344 #define CHIPC_OTPC_PCOUNT_MASK 0x0000000e 345 #define CHIPC_OTPC_PCOUNT_SHIFT 1 346 #define CHIPC_OTPC_VSEL_MASK 0x000000f0 347 #define CHIPC_OTPC_VSEL_SHIFT 4 348 #define CHIPC_OTPC_TMM_MASK 0x00000700 349 #define CHIPC_OTPC_TMM_SHIFT 8 350 #define CHIPC_OTPC_ODM 0x00000800 351 #define CHIPC_OTPC_PROGEN 0x80000000 352 353 /* Fields in otpprog in IPX OTP and HND OTP */ 354 #define CHIPC_OTPP_COL_MASK 0x000000ff 355 #define CHIPC_OTPP_COL_SHIFT 0 356 #define CHIPC_OTPP_ROW_MASK 0x0000ff00 357 #define CHIPC_OTPP_ROW_SHIFT 8 358 #define CHIPC_OTPP_OC_MASK 0x0f000000 359 #define CHIPC_OTPP_OC_SHIFT 24 360 #define CHIPC_OTPP_READERR 0x10000000 361 #define CHIPC_OTPP_VALUE_MASK 0x20000000 362 #define CHIPC_OTPP_VALUE_SHIFT 29 363 #define CHIPC_OTPP_START_BUSY 0x80000000 364 #define CHIPC_OTPP_READ 0x40000000 /* HND OTP */ 365 366 /* otplayout */ 367 #define CHIPC_OTPL_SIZE_MASK 0x0000f000 /* rev >= 49 */ 368 #define CHIPC_OTPL_SIZE_SHIFT 12 369 #define CHIPC_OTPL_GUP_MASK 0x00000FFF /* bit offset to general use region */ 370 #define CHIPC_OTPL_GUP_SHIFT 0 371 #define CHIPC_OTPL_CISFORMAT_NEW 0x80000000 /* rev >= 36 */ 372 373 /* Opcodes for OTPP_OC field */ 374 #define CHIPC_OTPPOC_READ 0 375 #define CHIPC_OTPPOC_BIT_PROG 1 376 #define CHIPC_OTPPOC_VERIFY 3 377 #define CHIPC_OTPPOC_INIT 4 378 #define CHIPC_OTPPOC_SET 5 379 #define CHIPC_OTPPOC_RESET 6 380 #define CHIPC_OTPPOC_OCST 7 381 #define CHIPC_OTPPOC_ROW_LOCK 8 382 #define CHIPC_OTPPOC_PRESCN_TEST 9 383 384 /* Jtagm characteristics that appeared at a given corerev */ 385 #define CHIPC_JTAGM_CREV_OLD 10 /* Old command set, 16bit max IR */ 386 #define CHIPC_JTAGM_CREV_IRP 22 /* Able to do pause-ir */ 387 #define CHIPC_JTAGM_CREV_RTI 28 /* Able to do return-to-idle */ 388 389 /* jtagcmd */ 390 #define CHIPC_JCMD_START 0x80000000 391 #define CHIPC_JCMD_BUSY 0x80000000 392 #define CHIPC_JCMD_STATE_MASK 0x60000000 393 #define CHIPC_JCMD_STATE_TLR 0x00000000 /* Test-logic-reset */ 394 #define CHIPC_JCMD_STATE_PIR 0x20000000 /* Pause IR */ 395 #define CHIPC_JCMD_STATE_PDR 0x40000000 /* Pause DR */ 396 #define CHIPC_JCMD_STATE_RTI 0x60000000 /* Run-test-idle */ 397 #define CHIPC_JCMD0_ACC_MASK 0x0000f000 398 #define CHIPC_JCMD0_ACC_IRDR 0x00000000 399 #define CHIPC_JCMD0_ACC_DR 0x00001000 400 #define CHIPC_JCMD0_ACC_IR 0x00002000 401 #define CHIPC_JCMD0_ACC_RESET 0x00003000 402 #define CHIPC_JCMD0_ACC_IRPDR 0x00004000 403 #define CHIPC_JCMD0_ACC_PDR 0x00005000 404 #define CHIPC_JCMD0_IRW_MASK 0x00000f00 405 #define CHIPC_JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */ 406 #define CHIPC_JCMD_ACC_IRDR 0x00000000 407 #define CHIPC_JCMD_ACC_DR 0x00010000 408 #define CHIPC_JCMD_ACC_IR 0x00020000 409 #define CHIPC_JCMD_ACC_RESET 0x00030000 410 #define CHIPC_JCMD_ACC_IRPDR 0x00040000 411 #define CHIPC_JCMD_ACC_PDR 0x00050000 412 #define CHIPC_JCMD_ACC_PIR 0x00060000 413 #define CHIPC_JCMD_ACC_IRDR_I 0x00070000 /* rev 28: return to run-test-idle */ 414 #define CHIPC_JCMD_ACC_DR_I 0x00080000 /* rev 28: return to run-test-idle */ 415 #define CHIPC_JCMD_IRW_MASK 0x00001f00 416 #define CHIPC_JCMD_IRW_SHIFT 8 417 #define CHIPC_JCMD_DRW_MASK 0x0000003f 418 419 /* jtagctrl */ 420 #define CHIPC_JCTRL_FORCE_CLK 4 /* Force clock */ 421 #define CHIPC_JCTRL_EXT_EN 2 /* Enable external targets */ 422 #define CHIPC_JCTRL_EN 1 /* Enable Jtag master */ 423 424 /* Fields in clkdiv */ 425 #define CHIPC_CLKD_SFLASH 0x0f000000 426 #define CHIPC_CLKD_SFLASH_SHIFT 24 427 #define CHIPC_CLKD_OTP 0x000f0000 428 #define CHIPC_CLKD_OTP_SHIFT 16 429 #define CHIPC_CLKD_JTAG 0x00000f00 430 #define CHIPC_CLKD_JTAG_SHIFT 8 431 #define CHIPC_CLKD_UART 0x000000ff 432 433 #define CHIPC_CLKD2_SPROM 0x00000003 434 435 /* intstatus/intmask */ 436 #define CHIPC_CI_GPIO 0x00000001 /* gpio intr */ 437 #define CHIPC_CI_EI 0x00000002 /* extif intr (corerev >= 3) */ 438 #define CHIPC_CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */ 439 #define CHIPC_CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */ 440 #define CHIPC_CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */ 441 #define CHIPC_CI_UART 0x00000040 /* uart intr (corerev >= 21) */ 442 #define CHIPC_CI_WDRESET 0x80000000 /* watchdog reset occurred */ 443 444 /* slow_clk_ctl */ 445 #define CHIPC_SCC_SS_MASK 0x00000007 /* slow clock source mask */ 446 #define CHIPC_SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */ 447 #define CHIPC_SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */ 448 #define CHIPC_SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */ 449 #define CHIPC_SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ 450 #define CHIPC_SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 451 * 0: LPO is enabled 452 */ 453 #define CHIPC_SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 454 * 0: power logic control 455 */ 456 #define CHIPC_SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors 457 * PLL clock disable requests from core 458 */ 459 #define CHIPC_SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't 460 * disable crystal when appropriate 461 */ 462 #define CHIPC_SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ 463 #define CHIPC_SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ 464 #define CHIPC_SCC_CD_SHIFT 16 465 466 /* system_clk_ctl */ 467 #define CHIPC_SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */ 468 #define CHIPC_SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */ 469 #define CHIPC_SYCC_FP 0x00000004 /* ForcePLLOn */ 470 #define CHIPC_SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */ 471 #define CHIPC_SYCC_HR 0x00000010 /* Force HT */ 472 #define CHIPC_SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ 473 #define CHIPC_SYCC_CD_SHIFT 16 474 475 /* Indirect backplane access */ 476 #define CHIPC_BPIA_BYTEEN 0x0000000f 477 #define CHIPC_BPIA_SZ1 0x00000001 478 #define CHIPC_BPIA_SZ2 0x00000003 479 #define CHIPC_BPIA_SZ4 0x00000007 480 #define CHIPC_BPIA_SZ8 0x0000000f 481 #define CHIPC_BPIA_WRITE 0x00000100 482 #define CHIPC_BPIA_START 0x00000200 483 #define CHIPC_BPIA_BUSY 0x00000200 484 #define CHIPC_BPIA_ERROR 0x00000400 485 486 /* pcmcia/prog/flash_config */ 487 #define CHIPC_CF_EN 0x00000001 /* enable */ 488 #define CHIPC_CF_EM_MASK 0x0000000e /* mode */ 489 #define CHIPC_CF_EM_SHIFT 1 490 #define CHIPC_CF_EM_FLASH 0 /* flash/asynchronous mode */ 491 #define CHIPC_CF_EM_SYNC 2 /* synchronous mode */ 492 #define CHIPC_CF_EM_PCMCIA 4 /* pcmcia mode */ 493 #define CHIPC_CF_DS 0x00000010 /* destsize: 0=8bit, 1=16bit */ 494 #define CHIPC_CF_BS 0x00000020 /* byteswap */ 495 #define CHIPC_CF_CD_MASK 0x000000c0 /* clock divider */ 496 #define CHIPC_CF_CD_SHIFT 6 497 #define CHIPC_CF_CD_DIV2 0x00000000 /* backplane/2 */ 498 #define CHIPC_CF_CD_DIV3 0x00000040 /* backplane/3 */ 499 #define CHIPC_CF_CD_DIV4 0x00000080 /* backplane/4 */ 500 #define CHIPC_CF_CE 0x00000100 /* clock enable */ 501 #define CHIPC_CF_SB 0x00000200 /* size/bytestrobe (synch only) */ 502 503 /* pcmcia_memwait */ 504 #define CHIPC_PM_W0_MASK 0x0000003f /* waitcount0 */ 505 #define CHIPC_PM_W1_MASK 0x00001f00 /* waitcount1 */ 506 #define CHIPC_PM_W1_SHIFT 8 507 #define CHIPC_PM_W2_MASK 0x001f0000 /* waitcount2 */ 508 #define CHIPC_PM_W2_SHIFT 16 509 #define CHIPC_PM_W3_MASK 0x1f000000 /* waitcount3 */ 510 #define CHIPC_PM_W3_SHIFT 24 511 512 /* pcmcia_attrwait */ 513 #define CHIPC_PA_W0_MASK 0x0000003f /* waitcount0 */ 514 #define CHIPC_PA_W1_MASK 0x00001f00 /* waitcount1 */ 515 #define CHIPC_PA_W1_SHIFT 8 516 #define CHIPC_PA_W2_MASK 0x001f0000 /* waitcount2 */ 517 #define CHIPC_PA_W2_SHIFT 16 518 #define CHIPC_PA_W3_MASK 0x1f000000 /* waitcount3 */ 519 #define CHIPC_PA_W3_SHIFT 24 520 521 /* pcmcia_iowait */ 522 #define CHIPC_PI_W0_MASK 0x0000003f /* waitcount0 */ 523 #define CHIPC_PI_W1_MASK 0x00001f00 /* waitcount1 */ 524 #define CHIPC_PI_W1_SHIFT 8 525 #define CHIPC_PI_W2_MASK 0x001f0000 /* waitcount2 */ 526 #define CHIPC_PI_W2_SHIFT 16 527 #define CHIPC_PI_W3_MASK 0x1f000000 /* waitcount3 */ 528 #define CHIPC_PI_W3_SHIFT 24 529 530 /* prog_waitcount */ 531 #define CHIPC_PW_W0_MASK 0x0000001f /* waitcount0 */ 532 #define CHIPC_PW_W1_MASK 0x00001f00 /* waitcount1 */ 533 #define CHIPC_PW_W1_SHIFT 8 534 #define CHIPC_PW_W2_MASK 0x001f0000 /* waitcount2 */ 535 #define CHIPC_PW_W2_SHIFT 16 536 #define CHIPC_PW_W3_MASK 0x1f000000 /* waitcount3 */ 537 #define CHIPC_PW_W3_SHIFT 24 538 539 #define CHIPC_PW_W0 0x0000000c 540 #define CHIPC_PW_W1 0x00000a00 541 #define CHIPC_PW_W2 0x00020000 542 #define CHIPC_PW_W3 0x01000000 543 544 /* flash_waitcount */ 545 #define CHIPC_FW_W0_MASK 0x0000003f /* waitcount0 */ 546 #define CHIPC_FW_W1_MASK 0x00001f00 /* waitcount1 */ 547 #define CHIPC_FW_W1_SHIFT 8 548 #define CHIPC_FW_W2_MASK 0x001f0000 /* waitcount2 */ 549 #define CHIPC_FW_W2_SHIFT 16 550 #define CHIPC_FW_W3_MASK 0x1f000000 /* waitcount3 */ 551 #define CHIPC_FW_W3_SHIFT 24 552 553 /* When SPROM support present, fields in spromcontrol */ 554 #define CHIPC_SRC_START 0x80000000 555 #define CHIPC_SRC_BUSY 0x80000000 556 #define CHIPC_SRC_OPCODE 0x60000000 557 #define CHIPC_SRC_OP_READ 0x00000000 558 #define CHIPC_SRC_OP_WRITE 0x20000000 559 #define CHIPC_SRC_OP_WRDIS 0x40000000 560 #define CHIPC_SRC_OP_WREN 0x60000000 561 #define CHIPC_SRC_OTPSEL 0x00000010 562 #define CHIPC_SRC_LOCK 0x00000008 563 #define CHIPC_SRC_SIZE_MASK 0x00000006 564 #define CHIPC_SRC_SIZE_1K 0x00000000 565 #define CHIPC_SRC_SIZE_4K 0x00000002 566 #define CHIPC_SRC_SIZE_16K 0x00000004 567 #define CHIPC_SRC_SIZE_SHIFT 1 568 #define CHIPC_SRC_PRESENT 0x00000001 569 570 /* Fields in pmucontrol */ 571 #define CHIPC_PCTL_ILP_DIV_MASK 0xffff0000 572 #define CHIPC_PCTL_ILP_DIV_SHIFT 16 573 #define CHIPC_PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */ 574 #define CHIPC_PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */ 575 #define CHIPC_PCTL_HT_REQ_EN 0x00000100 576 #define CHIPC_PCTL_ALP_REQ_EN 0x00000080 577 #define CHIPC_PCTL_XTALFREQ_MASK 0x0000007c 578 #define CHIPC_PCTL_XTALFREQ_SHIFT 2 579 #define CHIPC_PCTL_ILP_DIV_EN 0x00000002 580 #define CHIPC_PCTL_LPO_SEL 0x00000001 581 582 /* Fields in clkstretch */ 583 #define CHIPC_CSTRETCH_HT 0xffff0000 584 #define CHIPC_CSTRETCH_ALP 0x0000ffff 585 586 /* gpiotimerval */ 587 #define CHIPC_GPIO_ONTIME_SHIFT 16 588 589 /* clockcontrol_n */ 590 #define CHIPC_CN_N1_MASK 0x3f /* n1 control */ 591 #define CHIPC_CN_N2_MASK 0x3f00 /* n2 control */ 592 #define CHIPC_CN_N2_SHIFT 8 593 #define CHIPC_CN_PLLC_MASK 0xf0000 /* pll control */ 594 #define CHIPC_CN_PLLC_SHIFT 16 595 596 /* clockcontrol_sb/pci/uart */ 597 #define CHIPC_M1_MASK 0x3f /* m1 control */ 598 #define CHIPC_M2_MASK 0x3f00 /* m2 control */ 599 #define CHIPC_M2_SHIFT 8 600 #define CHIPC_M3_MASK 0x3f0000 /* m3 control */ 601 #define CHIPC_M3_SHIFT 16 602 #define CHIPC_MC_MASK 0x1f000000 /* mux control */ 603 #define CHIPC_MC_SHIFT 24 604 605 /* N3M Clock control magic field values */ 606 #define CHIPC_F6_2 0x02 /* A factor of 2 in */ 607 #define CHIPC_F6_3 0x03 /* 6-bit fields like */ 608 #define CHIPC_F6_4 0x05 /* N1, M1 or M3 */ 609 #define CHIPC_F6_5 0x09 610 #define CHIPC_F6_6 0x11 611 #define CHIPC_F6_7 0x21 612 613 #define CHIPC_F5_BIAS 5 /* 5-bit fields get this added */ 614 615 #define CHIPC_MC_BYPASS 0x08 616 #define CHIPC_MC_M1 0x04 617 #define CHIPC_MC_M1M2 0x02 618 #define CHIPC_MC_M1M2M3 0x01 619 #define CHIPC_MC_M1M3 0x11 620 621 /* Type 2 Clock control magic field values */ 622 #define CHIPC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ 623 #define CHIPC_T2M2_BIAS 3 /* m2 bias */ 624 625 #define CHIPC_T2MC_M1BYP 1 626 #define CHIPC_T2MC_M2BYP 2 627 #define CHIPC_T2MC_M3BYP 4 628 629 /* Type 6 Clock control magic field values */ 630 #define CHIPC_T6_MMASK 1 /* bits of interest in m */ 631 #define CHIPC_T6_M0 120000000 /* sb clock for m = 0 */ 632 #define CHIPC_T6_M1 100000000 /* sb clock for m = 1 */ 633 #define CHIPC_SB2MIPS_T6(sb) (2 * (sb)) 634 635 /* Common clock base */ 636 #define CHIPC_CLOCK_BASE1 24000000 /* Half the clock freq */ 637 #define CHIPC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLLs */ 638 639 /* Clock control values for 200MHz in 5350 */ 640 #define CHIPC_CLKC_5350_N 0x0311 641 #define CHIPC_CLKC_5350_M 0x04020009 642 643 /* Bits in the ExtBus config registers */ 644 #define CHIPC_CFG_EN 0x0001 /* Enable */ 645 #define CHIPC_CFG_EM_MASK 0x000e /* Extif Mode */ 646 #define CHIPC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */ 647 #define CHIPC_CFG_EM_SYNC 0x0002 /* Synchronous */ 648 #define CHIPC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */ 649 #define CHIPC_CFG_EM_IDE 0x0006 /* IDE */ 650 #define CHIPC_FLASH_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ 651 #define CHIPC_FLASH_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */ 652 #define CHIPC_FLASH_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */ 653 #define CHIPC_FLASH_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */ 654 #define CHIPC_FLASH_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */ 655 656 /* ExtBus address space */ 657 #define CHIPC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */ 658 #define CHIPC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */ 659 #define CHIPC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */ 660 #define CHIPC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */ 661 #define CHIPC_EB_IDE 0x1a800000 /* IDE memory base */ 662 #define CHIPC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */ 663 #define CHIPC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */ 664 #define CHIPC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */ 665 #define CHIPC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */ 666 667 /* Start/busy bit in flashcontrol */ 668 #define CHIPC_SFLASH_OPCODE 0x000000ff 669 #define CHIPC_SFLASH_ACTION 0x00000700 670 #define CHIPC_SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ 671 #define CHIPC_SFLASH_START 0x80000000 672 #define CHIPC_SFLASH_BUSY SFLASH_START 673 674 /* flashcontrol action codes */ 675 #define CHIPC_SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */ 676 #define CHIPC_SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */ 677 #define CHIPC_SFLASH_ACT_OP3A 0x0200 /* opcode + 3 addr bytes */ 678 #define CHIPC_SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addr & 1 data bytes */ 679 #define CHIPC_SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addr & 4 data bytes */ 680 #define CHIPC_SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addr, 4 don't care & 4 data bytes */ 681 #define CHIPC_SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addr, 1 don't care & 4 data bytes */ 682 683 /* flashcontrol action+opcodes for ST flashes */ 684 #define CHIPC_SFLASH_ST_WREN 0x0006 /* Write Enable */ 685 #define CHIPC_SFLASH_ST_WRDIS 0x0004 /* Write Disable */ 686 #define CHIPC_SFLASH_ST_RDSR 0x0105 /* Read Status Register */ 687 #define CHIPC_SFLASH_ST_WRSR 0x0101 /* Write Status Register */ 688 #define CHIPC_SFLASH_ST_READ 0x0303 /* Read Data Bytes */ 689 #define CHIPC_SFLASH_ST_PP 0x0302 /* Page Program */ 690 #define CHIPC_SFLASH_ST_SE 0x02d8 /* Sector Erase */ 691 #define CHIPC_SFLASH_ST_BE 0x00c7 /* Bulk Erase */ 692 #define CHIPC_SFLASH_ST_DP 0x00b9 /* Deep Power-down */ 693 #define CHIPC_SFLASH_ST_RES 0x03ab /* Read Electronic Signature */ 694 #define CHIPC_SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */ 695 #define CHIPC_SFLASH_ST_SSE 0x0220 /* Sub-sector Erase */ 696 697 /* Status register bits for ST flashes */ 698 #define CHIPC_SFLASH_ST_WIP 0x01 /* Write In Progress */ 699 #define CHIPC_SFLASH_ST_WEL 0x02 /* Write Enable Latch */ 700 #define CHIPC_SFLASH_ST_BP_MASK 0x1c /* Block Protect */ 701 #define CHIPC_SFLASH_ST_BP_SHIFT 2 702 #define CHIPC_SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */ 703 704 /* flashcontrol action+opcodes for Atmel flashes */ 705 #define CHIPC_SFLASH_AT_READ 0x07e8 706 #define CHIPC_SFLASH_AT_PAGE_READ 0x07d2 707 #define CHIPC_SFLASH_AT_BUF1_READ 708 #define CHIPC_SFLASH_AT_BUF2_READ 709 #define CHIPC_SFLASH_AT_STATUS 0x01d7 710 #define CHIPC_SFLASH_AT_BUF1_WRITE 0x0384 711 #define CHIPC_SFLASH_AT_BUF2_WRITE 0x0387 712 #define CHIPC_SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 713 #define CHIPC_SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 714 #define CHIPC_SFLASH_AT_BUF1_PROGRAM 0x0288 715 #define CHIPC_SFLASH_AT_BUF2_PROGRAM 0x0289 716 #define CHIPC_SFLASH_AT_PAGE_ERASE 0x0281 717 #define CHIPC_SFLASH_AT_BLOCK_ERASE 0x0250 718 #define CHIPC_SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 719 #define CHIPC_SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 720 #define CHIPC_SFLASH_AT_BUF1_LOAD 0x0253 721 #define CHIPC_SFLASH_AT_BUF2_LOAD 0x0255 722 #define CHIPC_SFLASH_AT_BUF1_COMPARE 0x0260 723 #define CHIPC_SFLASH_AT_BUF2_COMPARE 0x0261 724 #define CHIPC_SFLASH_AT_BUF1_REPROGRAM 0x0258 725 #define CHIPC_SFLASH_AT_BUF2_REPROGRAM 0x0259 726 727 /* Status register bits for Atmel flashes */ 728 #define CHIPC_SFLASH_AT_READY 0x80 729 #define CHIPC_SFLASH_AT_MISMATCH 0x40 730 #define CHIPC_SFLASH_AT_ID_MASK 0x38 731 #define CHIPC_SFLASH_AT_ID_SHIFT 3 732 733 /* 734 * These are the UART port assignments, expressed as offsets from the base 735 * register. These assignments should hold for any serial port based on 736 * a 8250, 16450, or 16550(A). 737 */ 738 739 #define CHIPC_UART_RX 0 /* In: Receive buffer (DLAB=0) */ 740 #define CHIPC_UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ 741 #define CHIPC_UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ 742 #define CHIPC_UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */ 743 #define CHIPC_UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ 744 #define CHIPC_UART_IIR 2 /* In: Interrupt Identity Register */ 745 #define CHIPC_UART_FCR 2 /* Out: FIFO Control Register */ 746 #define CHIPC_UART_LCR 3 /* Out: Line Control Register */ 747 #define CHIPC_UART_MCR 4 /* Out: Modem Control Register */ 748 #define CHIPC_UART_LSR 5 /* In: Line Status Register */ 749 #define CHIPC_UART_MSR 6 /* In: Modem Status Register */ 750 #define CHIPC_UART_SCR 7 /* I/O: Scratch Register */ 751 #define CHIPC_UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 752 #define CHIPC_UART_LCR_WLEN8 0x03 /* Word length: 8 bits */ 753 #define CHIPC_UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */ 754 #define CHIPC_UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 755 #define CHIPC_UART_LSR_RX_FIFO 0x80 /* Receive FIFO error */ 756 #define CHIPC_UART_LSR_TDHR 0x40 /* Data-hold-register empty */ 757 #define CHIPC_UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 758 #define CHIPC_UART_LSR_BREAK 0x10 /* Break interrupt */ 759 #define CHIPC_UART_LSR_FRAMING 0x08 /* Framing error */ 760 #define CHIPC_UART_LSR_PARITY 0x04 /* Parity error */ 761 #define CHIPC_UART_LSR_OVERRUN 0x02 /* Overrun error */ 762 #define CHIPC_UART_LSR_RXRDY 0x01 /* Receiver ready */ 763 #define CHIPC_UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */ 764 765 /* Interrupt Identity Register (IIR) bits */ 766 #define CHIPC_UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */ 767 #define CHIPC_UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */ 768 #define CHIPC_UART_IIR_MDM_CHG 0x0 /* Modem status changed */ 769 #define CHIPC_UART_IIR_NOINT 0x1 /* No interrupt pending */ 770 #define CHIPC_UART_IIR_THRE 0x2 /* THR empty */ 771 #define CHIPC_UART_IIR_RCVD_DATA 0x4 /* Received data available */ 772 #define CHIPC_UART_IIR_RCVR_STATUS 0x6 /* Receiver status */ 773 #define CHIPC_UART_IIR_CHAR_TIME 0xc /* Character time */ 774 775 /* Interrupt Enable Register (IER) bits */ 776 #define CHIPC_UART_IER_EDSSI 8 /* enable modem status interrupt */ 777 #define CHIPC_UART_IER_ELSI 4 /* enable receiver line status interrupt */ 778 #define CHIPC_UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */ 779 #define CHIPC_UART_IER_ERBFI 1 /* enable data available interrupt */ 780 781 /* pmustatus */ 782 #define CHIPC_PST_EXTLPOAVAIL 0x0100 783 #define CHIPC_PST_WDRESET 0x0080 784 #define CHIPC_PST_INTPEND 0x0040 785 #define CHIPC_PST_SBCLKST 0x0030 786 #define CHIPC_PST_SBCLKST_ILP 0x0010 787 #define CHIPC_PST_SBCLKST_ALP 0x0020 788 #define CHIPC_PST_SBCLKST_HT 0x0030 789 #define CHIPC_PST_ALPAVAIL 0x0008 790 #define CHIPC_PST_HTAVAIL 0x0004 791 #define CHIPC_PST_RESINIT 0x0003 792 793 /* pmucapabilities */ 794 #define CHIPC_PCAP_REV_MASK 0x000000ff 795 #define CHIPC_PCAP_RC_MASK 0x00001f00 796 #define CHIPC_PCAP_RC_SHIFT 8 797 #define CHIPC_PCAP_TC_MASK 0x0001e000 798 #define CHIPC_PCAP_TC_SHIFT 13 799 #define CHIPC_PCAP_PC_MASK 0x001e0000 800 #define CHIPC_PCAP_PC_SHIFT 17 801 #define CHIPC_PCAP_VC_MASK 0x01e00000 802 #define CHIPC_PCAP_VC_SHIFT 21 803 #define CHIPC_PCAP_CC_MASK 0x1e000000 804 #define CHIPC_PCAP_CC_SHIFT 25 805 #define CHIPC_PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */ 806 #define CHIPC_PCAP5_PC_SHIFT 17 807 #define CHIPC_PCAP5_VC_MASK 0x07c00000 808 #define CHIPC_PCAP5_VC_SHIFT 22 809 #define CHIPC_PCAP5_CC_MASK 0xf8000000 810 #define CHIPC_PCAP5_CC_SHIFT 27 811 812 /* PMU Resource Request Timer registers */ 813 /* This is based on PmuRev0 */ 814 #define CHIPC_PRRT_TIME_MASK 0x03ff 815 #define CHIPC_PRRT_INTEN 0x0400 816 #define CHIPC_PRRT_REQ_ACTIVE 0x0800 817 #define CHIPC_PRRT_ALP_REQ 0x1000 818 #define CHIPC_PRRT_HT_REQ 0x2000 819 820 /* PMU resource bit position */ 821 #define CHIPC_PMURES_BIT(bit) (1 << (bit)) 822 823 /* PMU resource number limit */ 824 #define CHIPC_PMURES_MAX_RESNUM 30 825 826 /* PMU chip control0 register */ 827 #define CHIPC_PMU_CHIPCTL0 0 828 829 /* PMU chip control1 register */ 830 #define CHIPC_PMU_CHIPCTL1 1 831 #define CHIPC_PMU_CC1_RXC_DLL_BYPASS 0x00010000 832 833 #define CHIPC_PMU_CC1_IF_TYPE_MASK 0x00000030 834 #define CHIPC_PMU_CC1_IF_TYPE_RMII 0x00000000 835 #define CHIPC_PMU_CC1_IF_TYPE_MII 0x00000010 836 #define CHIPC_PMU_CC1_IF_TYPE_RGMII 0x00000020 837 838 #define CHIPC_PMU_CC1_SW_TYPE_MASK 0x000000c0 839 #define CHIPC_PMU_CC1_SW_TYPE_EPHY 0x00000000 840 #define CHIPC_PMU_CC1_SW_TYPE_EPHYMII 0x00000040 841 #define CHIPC_PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 842 #define CHIPC_PMU_CC1_SW_TYPE_RGMII 0x000000c0 843 844 /* PMU corerev and chip specific PLL controls. 845 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number 846 * to differentiate different PLLs controlled by the same PMU rev. 847 */ 848 /* pllcontrol registers */ 849 /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ 850 #define CHIPC_PMU0_PLL0_PLLCTL0 0 851 #define CHIPC_PMU0_PLL0_PC0_PDIV_MASK 1 852 #define CHIPC_PMU0_PLL0_PC0_PDIV_FREQ 25000 853 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 854 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 855 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_BASE 8 856 857 /* PC0_DIV_ARM for PLLOUT_ARM */ 858 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 859 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 860 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 861 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ 862 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 863 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 864 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 865 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 866 867 /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ 868 #define CHIPC_PMU0_PLL0_PLLCTL1 1 869 #define CHIPC_PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 870 #define CHIPC_PMU0_PLL0_PC1_WILD_INT_SHIFT 28 871 #define CHIPC_PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 872 #define CHIPC_PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 873 #define CHIPC_PMU0_PLL0_PC1_STOP_MOD 0x00000040 874 875 /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ 876 #define CHIPC_PMU0_PLL0_PLLCTL2 2 877 #define CHIPC_PMU0_PLL0_PC2_WILD_INT_MASK 0xf 878 #define CHIPC_PMU0_PLL0_PC2_WILD_INT_SHIFT 4 879 880 /* pllcontrol registers */ 881 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 882 #define CHIPC_PMU1_PLL0_PLLCTL0 0 883 #define CHIPC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 884 #define CHIPC_PMU1_PLL0_PC0_P1DIV_SHIFT 20 885 #define CHIPC_PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 886 #define CHIPC_PMU1_PLL0_PC0_P2DIV_SHIFT 24 887 888 /* m<x>div */ 889 #define CHIPC_PMU1_PLL0_PLLCTL1 1 890 #define CHIPC_PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff 891 #define CHIPC_PMU1_PLL0_PC1_M1DIV_SHIFT 0 892 #define CHIPC_PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 893 #define CHIPC_PMU1_PLL0_PC1_M2DIV_SHIFT 8 894 #define CHIPC_PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 895 #define CHIPC_PMU1_PLL0_PC1_M3DIV_SHIFT 16 896 #define CHIPC_PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 897 #define CHIPC_PMU1_PLL0_PC1_M4DIV_SHIFT 24 898 899 #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 900 #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 901 #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 902 903 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 904 #define CHIPC_PMU1_PLL0_PLLCTL2 2 905 #define CHIPC_PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff 906 #define CHIPC_PMU1_PLL0_PC2_M5DIV_SHIFT 0 907 #define CHIPC_PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 908 #define CHIPC_PMU1_PLL0_PC2_M6DIV_SHIFT 8 909 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 910 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 911 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASH 1 912 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */ 913 #define CHIPC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 914 #define CHIPC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 915 916 /* ndiv_frac */ 917 #define CHIPC_PMU1_PLL0_PLLCTL3 3 918 #define CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff 919 #define CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 920 921 /* pll_ctrl */ 922 #define CHIPC_PMU1_PLL0_PLLCTL4 4 923 924 /* pll_ctrl, vco_rng, clkdrive_ch<x> */ 925 #define CHIPC_PMU1_PLL0_PLLCTL5 5 926 #define CHIPC_PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 927 #define CHIPC_PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 928 929 /* PMU rev 2 control words */ 930 #define CHIPC_PMU2_PHY_PLL_PLLCTL 4 931 #define CHIPC_PMU2_SI_PLL_PLLCTL 10 932 933 /* PMU rev 2 */ 934 /* pllcontrol registers */ 935 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 936 #define CHIPC_PMU2_PLL_PLLCTL0 0 937 #define CHIPC_PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 938 #define CHIPC_PMU2_PLL_PC0_P1DIV_SHIFT 20 939 #define CHIPC_PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 940 #define CHIPC_PMU2_PLL_PC0_P2DIV_SHIFT 24 941 942 /* m<x>div */ 943 #define CHIPC_PMU2_PLL_PLLCTL1 1 944 #define CHIPC_PMU2_PLL_PC1_M1DIV_MASK 0x000000ff 945 #define CHIPC_PMU2_PLL_PC1_M1DIV_SHIFT 0 946 #define CHIPC_PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 947 #define CHIPC_PMU2_PLL_PC1_M2DIV_SHIFT 8 948 #define CHIPC_PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 949 #define CHIPC_PMU2_PLL_PC1_M3DIV_SHIFT 16 950 #define CHIPC_PMU2_PLL_PC1_M4DIV_MASK 0xff000000 951 #define CHIPC_PMU2_PLL_PC1_M4DIV_SHIFT 24 952 953 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 954 #define CHIPC_PMU2_PLL_PLLCTL2 2 955 #define CHIPC_PMU2_PLL_PC2_M5DIV_MASK 0x000000ff 956 #define CHIPC_PMU2_PLL_PC2_M5DIV_SHIFT 0 957 #define CHIPC_PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 958 #define CHIPC_PMU2_PLL_PC2_M6DIV_SHIFT 8 959 #define CHIPC_PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 960 #define CHIPC_PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 961 #define CHIPC_PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 962 #define CHIPC_PMU2_PLL_PC2_NDIV_INT_SHIFT 20 963 964 /* ndiv_frac */ 965 #define CHIPC_PMU2_PLL_PLLCTL3 3 966 #define CHIPC_PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff 967 #define CHIPC_PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 968 969 /* pll_ctrl */ 970 #define CHIPC_PMU2_PLL_PLLCTL4 4 971 972 /* pll_ctrl, vco_rng, clkdrive_ch<x> */ 973 #define CHIPC_PMU2_PLL_PLLCTL5 5 974 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 975 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 976 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 977 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 978 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 979 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 980 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 981 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 982 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 983 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 984 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 985 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 986 987 /* PMU rev 5 (& 6) */ 988 #define CHIPC_PMU5_PLL_P1P2_OFF 0 989 #define CHIPC_PMU5_PLL_P1_MASK 0x0f000000 990 #define CHIPC_PMU5_PLL_P1_SHIFT 24 991 #define CHIPC_PMU5_PLL_P2_MASK 0x00f00000 992 #define CHIPC_PMU5_PLL_P2_SHIFT 20 993 #define CHIPC_PMU5_PLL_M14_OFF 1 994 #define CHIPC_PMU5_PLL_MDIV_MASK 0x000000ff 995 #define CHIPC_PMU5_PLL_MDIV_WIDTH 8 996 #define CHIPC_PMU5_PLL_NM5_OFF 2 997 #define CHIPC_PMU5_PLL_NDIV_MASK 0xfff00000 998 #define CHIPC_PMU5_PLL_NDIV_SHIFT 20 999 #define CHIPC_PMU5_PLL_NDIV_MODE_MASK 0x000e0000 1000 #define CHIPC_PMU5_PLL_NDIV_MODE_SHIFT 17 1001 #define CHIPC_PMU5_PLL_FMAB_OFF 3 1002 #define CHIPC_PMU5_PLL_MRAT_MASK 0xf0000000 1003 #define CHIPC_PMU5_PLL_MRAT_SHIFT 28 1004 #define CHIPC_PMU5_PLL_ABRAT_MASK 0x08000000 1005 #define CHIPC_PMU5_PLL_ABRAT_SHIFT 27 1006 #define CHIPC_PMU5_PLL_FDIV_MASK 0x07ffffff 1007 #define CHIPC_PMU5_PLL_PLLCTL_OFF 4 1008 #define CHIPC_PMU5_PLL_PCHI_OFF 5 1009 #define CHIPC_PMU5_PLL_PCHI_MASK 0x0000003f 1010 1011 /* pmu XtalFreqRatio */ 1012 #define CHIPC_PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF 1013 #define CHIPC_PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 1014 #define CHIPC_PMU_XTALFREQ_REG_MEASURE_SHIFT 31 1015 1016 /* Divider allocation in 4716/47162/5356/5357 */ 1017 #define CHIPC_PMU5_MAINPLL_CPU 1 1018 #define CHIPC_PMU5_MAINPLL_MEM 2 1019 #define CHIPC_PMU5_MAINPLL_SI 3 1020 1021 #define CHIPC_PMU7_PLL_PLLCTL7 7 1022 #define CHIPC_PMU7_PLL_PLLCTL8 8 1023 #define CHIPC_PMU7_PLL_PLLCTL11 11 1024 1025 /* PLL usage in 4716/47162 */ 1026 #define CHIPC_PMU4716_MAINPLL_PLL0 12 1027 1028 /* PLL usage in 5356/5357 */ 1029 #define CHIPC_PMU5356_MAINPLL_PLL0 0 1030 #define CHIPC_PMU5357_MAINPLL_PLL0 0 1031 1032 /* 4716/47162 resources */ 1033 #define CHIPC_RES4716_PROC_PLL_ON 0x00000040 1034 #define CHIPC_RES4716_PROC_HT_AVAIL 0x00000080 1035 1036 /* 4716/4717/4718 Chip specific ChipControl register bits */ 1037 #define CHIPC_CCTRL471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared with pflash */ 1038 1039 /* 5354 resources */ 1040 #define CHIPC_RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */ 1041 #define CHIPC_RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */ 1042 #define CHIPC_RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */ 1043 #define CHIPC_RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ 1044 #define CHIPC_RES5354_ILP_REQUEST 4 /* 0x00010 */ 1045 #define CHIPC_RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */ 1046 #define CHIPC_RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */ 1047 #define CHIPC_RES5354_ROM_SWITCH 7 /* 0x00080 */ 1048 #define CHIPC_RES5354_PA_REF_LDO 8 /* 0x00100 */ 1049 #define CHIPC_RES5354_RADIO_LDO 9 /* 0x00200 */ 1050 #define CHIPC_RES5354_AFE_LDO 10 /* 0x00400 */ 1051 #define CHIPC_RES5354_PLL_LDO 11 /* 0x00800 */ 1052 #define CHIPC_RES5354_BG_FILTBYP 12 /* 0x01000 */ 1053 #define CHIPC_RES5354_TX_FILTBYP 13 /* 0x02000 */ 1054 #define CHIPC_RES5354_RX_FILTBYP 14 /* 0x04000 */ 1055 #define CHIPC_RES5354_XTAL_PU 15 /* 0x08000 */ 1056 #define CHIPC_RES5354_XTAL_EN 16 /* 0x10000 */ 1057 #define CHIPC_RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ 1058 #define CHIPC_RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ 1059 #define CHIPC_RES5354_BB_PLL_PU 19 /* 0x80000 */ 1060 1061 /* 5357 Chip specific ChipControl register bits */ 1062 #define CHIPC_CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ 1063 #define CHIPC_CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ 1064 1065 /* 4328 resources */ 1066 #define CHIPC_RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ 1067 #define CHIPC_RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ 1068 #define CHIPC_RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ 1069 #define CHIPC_RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ 1070 #define CHIPC_RES4328_ILP_REQUEST 4 /* 0x00010 */ 1071 #define CHIPC_RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */ 1072 #define CHIPC_RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */ 1073 #define CHIPC_RES4328_ROM_SWITCH 7 /* 0x00080 */ 1074 #define CHIPC_RES4328_PA_REF_LDO 8 /* 0x00100 */ 1075 #define CHIPC_RES4328_RADIO_LDO 9 /* 0x00200 */ 1076 #define CHIPC_RES4328_AFE_LDO 10 /* 0x00400 */ 1077 #define CHIPC_RES4328_PLL_LDO 11 /* 0x00800 */ 1078 #define CHIPC_RES4328_BG_FILTBYP 12 /* 0x01000 */ 1079 #define CHIPC_RES4328_TX_FILTBYP 13 /* 0x02000 */ 1080 #define CHIPC_RES4328_RX_FILTBYP 14 /* 0x04000 */ 1081 #define CHIPC_RES4328_XTAL_PU 15 /* 0x08000 */ 1082 #define CHIPC_RES4328_XTAL_EN 16 /* 0x10000 */ 1083 #define CHIPC_RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */ 1084 #define CHIPC_RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */ 1085 #define CHIPC_RES4328_BB_PLL_PU 19 /* 0x80000 */ 1086 1087 /* 4325 A0/A1 resources */ 1088 #define CHIPC_RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */ 1089 #define CHIPC_RES4325_CBUCK_BURST 1 /* 0x00000002 */ 1090 #define CHIPC_RES4325_CBUCK_PWM 2 /* 0x00000004 */ 1091 #define CHIPC_RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */ 1092 #define CHIPC_RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */ 1093 #define CHIPC_RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */ 1094 #define CHIPC_RES4325_ILP_REQUEST 6 /* 0x00000040 */ 1095 #define CHIPC_RES4325_ABUCK_BURST 7 /* 0x00000080 */ 1096 #define CHIPC_RES4325_ABUCK_PWM 8 /* 0x00000100 */ 1097 #define CHIPC_RES4325_LNLDO1_PU 9 /* 0x00000200 */ 1098 #define CHIPC_RES4325_OTP_PU 10 /* 0x00000400 */ 1099 #define CHIPC_RES4325_LNLDO3_PU 11 /* 0x00000800 */ 1100 #define CHIPC_RES4325_LNLDO4_PU 12 /* 0x00001000 */ 1101 #define CHIPC_RES4325_XTAL_PU 13 /* 0x00002000 */ 1102 #define CHIPC_RES4325_ALP_AVAIL 14 /* 0x00004000 */ 1103 #define CHIPC_RES4325_RX_PWRSW_PU 15 /* 0x00008000 */ 1104 #define CHIPC_RES4325_TX_PWRSW_PU 16 /* 0x00010000 */ 1105 #define CHIPC_RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1106 #define CHIPC_RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1107 #define CHIPC_RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */ 1108 #define CHIPC_RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1109 #define CHIPC_RES4325_HT_AVAIL 21 /* 0x00200000 */ 1110 1111 /* 4325 B0/C0 resources */ 1112 #define CHIPC_RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */ 1113 #define CHIPC_RES4325B0_CBUCK_BURST 2 /* 0x00000004 */ 1114 #define CHIPC_RES4325B0_CBUCK_PWM 3 /* 0x00000008 */ 1115 #define CHIPC_RES4325B0_CLDO_PU 4 /* 0x00000010 */ 1116 1117 /* 4325 C1 resources */ 1118 #define CHIPC_RES4325C1_LNLDO2_PU 12 /* 0x00001000 */ 1119 1120 /* 4325 chip-specific ChipStatus register bits */ 1121 #define CHIPC_CST4325_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK 1122 #define CHIPC_CST4325_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 1123 #define CHIPC_CST4325_SDIO_USB_MODE_MASK 0x00000004 1124 #define CHIPC_CST4325_SDIO_USB_MODE_SHIFT 2 1125 #define CHIPC_CST4325_RCAL_VALID_MASK 0x00000008 1126 #define CHIPC_CST4325_RCAL_VALID_SHIFT 3 1127 #define CHIPC_CST4325_RCAL_VALUE_MASK 0x000001f0 1128 #define CHIPC_CST4325_RCAL_VALUE_SHIFT 4 1129 #define CHIPC_CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */ 1130 #define CHIPC_CST4325_PMUTOP_2B_SHIFT 9 1131 1132 #define CHIPC_RES4329_RESERVED0 0 /* 0x00000001 */ 1133 #define CHIPC_RES4329_CBUCK_LPOM 1 /* 0x00000002 */ 1134 #define CHIPC_RES4329_CBUCK_BURST 2 /* 0x00000004 */ 1135 #define CHIPC_RES4329_CBUCK_PWM 3 /* 0x00000008 */ 1136 #define CHIPC_RES4329_CLDO_PU 4 /* 0x00000010 */ 1137 #define CHIPC_RES4329_PALDO_PU 5 /* 0x00000020 */ 1138 #define CHIPC_RES4329_ILP_REQUEST 6 /* 0x00000040 */ 1139 #define CHIPC_RES4329_RESERVED7 7 /* 0x00000080 */ 1140 #define CHIPC_RES4329_RESERVED8 8 /* 0x00000100 */ 1141 #define CHIPC_RES4329_LNLDO1_PU 9 /* 0x00000200 */ 1142 #define CHIPC_RES4329_OTP_PU 10 /* 0x00000400 */ 1143 #define CHIPC_RES4329_RESERVED11 11 /* 0x00000800 */ 1144 #define CHIPC_RES4329_LNLDO2_PU 12 /* 0x00001000 */ 1145 #define CHIPC_RES4329_XTAL_PU 13 /* 0x00002000 */ 1146 #define CHIPC_RES4329_ALP_AVAIL 14 /* 0x00004000 */ 1147 #define CHIPC_RES4329_RX_PWRSW_PU 15 /* 0x00008000 */ 1148 #define CHIPC_RES4329_TX_PWRSW_PU 16 /* 0x00010000 */ 1149 #define CHIPC_RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1150 #define CHIPC_RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1151 #define CHIPC_RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */ 1152 #define CHIPC_RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1153 #define CHIPC_RES4329_HT_AVAIL 21 /* 0x00200000 */ 1154 1155 /* 4329 chip-specific ChipStatus register bits */ 1156 #define CHIPC_CST4329_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK 1157 #define CHIPC_CST4329_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 1158 #define CHIPC_CST4329_SPI_SDIO_MODE_MASK 0x00000004 1159 #define CHIPC_CST4329_SPI_SDIO_MODE_SHIFT 2 1160 1161 /* 4312 chip-specific ChipStatus register bits */ 1162 #define CHIPC_CST4312_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK 1163 #define CHIPC_CST4312_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 1164 1165 /* 4312 resources (all PMU chips with little memory constraint) */ 1166 #define CHIPC_RES4312_SWITCHER_BURST 0 /* 0x00000001 */ 1167 #define CHIPC_RES4312_SWITCHER_PWM 1 /* 0x00000002 */ 1168 #define CHIPC_RES4312_PA_REF_LDO 2 /* 0x00000004 */ 1169 #define CHIPC_RES4312_CORE_LDO_BURST 3 /* 0x00000008 */ 1170 #define CHIPC_RES4312_CORE_LDO_PWM 4 /* 0x00000010 */ 1171 #define CHIPC_RES4312_RADIO_LDO 5 /* 0x00000020 */ 1172 #define CHIPC_RES4312_ILP_REQUEST 6 /* 0x00000040 */ 1173 #define CHIPC_RES4312_BG_FILTBYP 7 /* 0x00000080 */ 1174 #define CHIPC_RES4312_TX_FILTBYP 8 /* 0x00000100 */ 1175 #define CHIPC_RES4312_RX_FILTBYP 9 /* 0x00000200 */ 1176 #define CHIPC_RES4312_XTAL_PU 10 /* 0x00000400 */ 1177 #define CHIPC_RES4312_ALP_AVAIL 11 /* 0x00000800 */ 1178 #define CHIPC_RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */ 1179 #define CHIPC_RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */ 1180 #define CHIPC_RES4312_HT_AVAIL 14 /* 0x00004000 */ 1181 1182 /* 4322 resources */ 1183 #define CHIPC_RES4322_RF_LDO 0 1184 #define CHIPC_RES4322_ILP_REQUEST 1 1185 #define CHIPC_RES4322_XTAL_PU 2 1186 #define CHIPC_RES4322_ALP_AVAIL 3 1187 #define CHIPC_RES4322_SI_PLL_ON 4 1188 #define CHIPC_RES4322_HT_SI_AVAIL 5 1189 #define CHIPC_RES4322_PHY_PLL_ON 6 1190 #define CHIPC_RES4322_HT_PHY_AVAIL 7 1191 #define CHIPC_RES4322_OTP_PU 8 1192 1193 /* 4322 chip-specific ChipStatus register bits */ 1194 #define CHIPC_CST4322_XTAL_FREQ_20_40MHZ 0x00000020 1195 #define CHIPC_CST4322_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK 1196 #define CHIPC_CST4322_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 1197 #define CHIPC_CST4322_PCI_OR_USB 0x00000100 1198 #define CHIPC_CST4322_BOOT_MASK 0x00000600 1199 #define CHIPC_CST4322_BOOT_SHIFT 9 1200 #define CHIPC_CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 1201 #define CHIPC_CST4322_BOOT_FROM_ROM 1 /* boot from ROM */ 1202 #define CHIPC_CST4322_BOOT_FROM_FLASH 2 /* boot from FLASH */ 1203 #define CHIPC_CST4322_BOOT_FROM_INVALID 3 1204 #define CHIPC_CST4322_ILP_DIV_EN 0x00000800 1205 #define CHIPC_CST4322_FLASH_TYPE_MASK 0x00001000 1206 #define CHIPC_CST4322_FLASH_TYPE_SHIFT 12 1207 #define CHIPC_CST4322_FLASH_TYPE_SHIFT_ST 0 /* ST serial FLASH */ 1208 #define CHIPC_CST4322_FLASH_TYPE_SHIFT_ATMEL 1 /* ATMEL flash */ 1209 #define CHIPC_CST4322_ARM_TAP_SEL 0x00002000 1210 #define CHIPC_CST4322_RES_INIT_MODE_MASK 0x0000c000 1211 #define CHIPC_CST4322_RES_INIT_MODE_SHIFT 14 1212 #define CHIPC_CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */ 1213 #define CHIPC_CST4322_RES_INIT_MODE_ILPREQ 1 /* resinitmode: ILP request */ 1214 #define CHIPC_CST4322_RES_INIT_MODE_ALPAVAIL 2 /* resinitmode: ALP available */ 1215 #define CHIPC_CST4322_RES_INIT_MODE_HTAVAIL 3 /* resinitmode: HT available */ 1216 #define CHIPC_CST4322_PCIPLLCLK_GATING 0x00010000 1217 #define CHIPC_CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 1218 #define CHIPC_CST4322_PCI_CARDBUS_MODE 0x00040000 1219 1220 /* 43224 chip-specific ChipControl register bits */ 1221 #define CHIPC_CCTRL43224_GPIO_TOGGLE 0x8000 1222 #define CHIPC_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ 1223 #define CHIPC_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ 1224 1225 /* 43236 resources */ 1226 #define CHIPC_RES43236_REGULATOR 0 1227 #define CHIPC_RES43236_ILP_REQUEST 1 1228 #define CHIPC_RES43236_XTAL_PU 2 1229 #define CHIPC_RES43236_ALP_AVAIL 3 1230 #define CHIPC_RES43236_SI_PLL_ON 4 1231 #define CHIPC_RES43236_HT_SI_AVAIL 5 1232 1233 /* 43236 chip-specific ChipControl register bits */ 1234 #define CHIPC_CCTRL43236_BT_COEXIST (1<<0) /* 0 disable */ 1235 #define CHIPC_CCTRL43236_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 1236 #define CHIPC_CCTRL43236_EXT_LNA (1<<2) /* 0 disable */ 1237 #define CHIPC_CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */ 1238 #define CHIPC_CCTRL43236_GSIO (1<<4) /* 0 disable */ 1239 1240 /* 43236 Chip specific ChipStatus register bits */ 1241 #define CHIPC_CST43236_SFLASH_MASK 0x00000040 1242 #define CHIPC_CST43236_OTP_SEL_MASK 0x00000080 1243 #define CHIPC_CST43236_OTP_SEL_SHIFT 7 1244 #define CHIPC_CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ 1245 #define CHIPC_CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ 1246 #define CHIPC_CST43236_BOOT_MASK 0x00001800 1247 #define CHIPC_CST43236_BOOT_SHIFT 11 1248 #define CHIPC_CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 1249 #define CHIPC_CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ 1250 #define CHIPC_CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ 1251 #define CHIPC_CST43236_BOOT_FROM_INVALID 3 1252 1253 /* 4331 resources */ 1254 #define CHIPC_RES4331_REGULATOR 0 1255 #define CHIPC_RES4331_ILP_REQUEST 1 1256 #define CHIPC_RES4331_XTAL_PU 2 1257 #define CHIPC_RES4331_ALP_AVAIL 3 1258 #define CHIPC_RES4331_SI_PLL_ON 4 1259 #define CHIPC_RES4331_HT_SI_AVAIL 5 1260 1261 /* 4331 chip-specific ChipControl register bits */ 1262 #define CHIPC_CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */ 1263 #define CHIPC_CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 1264 #define CHIPC_CCTRL4331_EXT_LNA (1<<2) /* 0 disable */ 1265 #define CHIPC_CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */ 1266 #define CHIPC_CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */ 1267 #define CHIPC_CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */ 1268 #define CHIPC_CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */ 1269 #define CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */ 1270 #define CHIPC_CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */ 1271 #define CHIPC_CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */ 1272 #define CHIPC_CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */ 1273 #define CHIPC_CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */ 1274 #define CHIPC_CCTRL4331_EXTPA_EN2 (1<<12) /* 0 ext pa2 disable, 1 ext pa2 enabled */ 1275 #define CHIPC_CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */ 1276 #define CHIPC_CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */ 1277 1278 /* 4331 Chip specific ChipStatus register bits */ 1279 #define CHIPC_CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */ 1280 #define CHIPC_CST4331_SPROM_PRESENT 0x00000002 1281 #define CHIPC_CST4331_OTP_PRESENT 0x00000004 1282 #define CHIPC_CST4331_LDO_RF 0x00000008 1283 #define CHIPC_CST4331_LDO_PAR 0x00000010 1284 1285 /* 4315 resources */ 1286 #define CHIPC_RES4315_CBUCK_LPOM 1 /* 0x00000002 */ 1287 #define CHIPC_RES4315_CBUCK_BURST 2 /* 0x00000004 */ 1288 #define CHIPC_RES4315_CBUCK_PWM 3 /* 0x00000008 */ 1289 #define CHIPC_RES4315_CLDO_PU 4 /* 0x00000010 */ 1290 #define CHIPC_RES4315_PALDO_PU 5 /* 0x00000020 */ 1291 #define CHIPC_RES4315_ILP_REQUEST 6 /* 0x00000040 */ 1292 #define CHIPC_RES4315_LNLDO1_PU 9 /* 0x00000200 */ 1293 #define CHIPC_RES4315_OTP_PU 10 /* 0x00000400 */ 1294 #define CHIPC_RES4315_LNLDO2_PU 12 /* 0x00001000 */ 1295 #define CHIPC_RES4315_XTAL_PU 13 /* 0x00002000 */ 1296 #define CHIPC_RES4315_ALP_AVAIL 14 /* 0x00004000 */ 1297 #define CHIPC_RES4315_RX_PWRSW_PU 15 /* 0x00008000 */ 1298 #define CHIPC_RES4315_TX_PWRSW_PU 16 /* 0x00010000 */ 1299 #define CHIPC_RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1300 #define CHIPC_RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1301 #define CHIPC_RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */ 1302 #define CHIPC_RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1303 #define CHIPC_RES4315_HT_AVAIL 21 /* 0x00200000 */ 1304 1305 /* 4315 chip-specific ChipStatus register bits */ 1306 #define CHIPC_CST4315_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK 1307 #define CHIPC_CST4315_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 1308 #define CHIPC_CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */ 1309 #define CHIPC_CST4315_RCAL_VALID 0x00000008 1310 #define CHIPC_CST4315_RCAL_VALUE_MASK 0x000001f0 1311 #define CHIPC_CST4315_RCAL_VALUE_SHIFT 4 1312 #define CHIPC_CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */ 1313 #define CHIPC_CST4315_CBUCK_MODE_MASK 0x00000c00 1314 #define CHIPC_CST4315_CBUCK_MODE_BURST 0x00000400 1315 #define CHIPC_CST4315_CBUCK_MODE_LPBURST 0x00000c00 1316 1317 /* 4319 resources */ 1318 #define CHIPC_RES4319_CBUCK_LPOM 1 /* 0x00000002 */ 1319 #define CHIPC_RES4319_CBUCK_BURST 2 /* 0x00000004 */ 1320 #define CHIPC_RES4319_CBUCK_PWM 3 /* 0x00000008 */ 1321 #define CHIPC_RES4319_CLDO_PU 4 /* 0x00000010 */ 1322 #define CHIPC_RES4319_PALDO_PU 5 /* 0x00000020 */ 1323 #define CHIPC_RES4319_ILP_REQUEST 6 /* 0x00000040 */ 1324 #define CHIPC_RES4319_LNLDO1_PU 9 /* 0x00000200 */ 1325 #define CHIPC_RES4319_OTP_PU 10 /* 0x00000400 */ 1326 #define CHIPC_RES4319_LNLDO2_PU 12 /* 0x00001000 */ 1327 #define CHIPC_RES4319_XTAL_PU 13 /* 0x00002000 */ 1328 #define CHIPC_RES4319_ALP_AVAIL 14 /* 0x00004000 */ 1329 #define CHIPC_RES4319_RX_PWRSW_PU 15 /* 0x00008000 */ 1330 #define CHIPC_RES4319_TX_PWRSW_PU 16 /* 0x00010000 */ 1331 #define CHIPC_RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1332 #define CHIPC_RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1333 #define CHIPC_RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */ 1334 #define CHIPC_RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1335 #define CHIPC_RES4319_HT_AVAIL 21 /* 0x00200000 */ 1336 1337 /* 4319 chip-specific ChipStatus register bits */ 1338 #define CHIPC_CST4319_SPI_CPULESSUSB 0x00000001 1339 #define CHIPC_CST4319_SPI_CLK_POL 0x00000002 1340 #define CHIPC_CST4319_SPI_CLK_PH 0x00000008 1341 #define CHIPC_CST4319_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK /* gpio [7:6], SDIO CIS selection */ 1342 #define CHIPC_CST4319_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 1343 #define CHIPC_CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */ 1344 #define CHIPC_CST4319_REMAP_SEL_MASK 0x00000600 1345 #define CHIPC_CST4319_ILPDIV_EN 0x00000800 1346 #define CHIPC_CST4319_XTAL_PD_POL 0x00001000 1347 #define CHIPC_CST4319_LPO_SEL 0x00002000 1348 #define CHIPC_CST4319_RES_INIT_MODE 0x0000c000 1349 #define CHIPC_CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */ 1350 #define CHIPC_CST4319_CBUCK_MODE_MASK 0x00060000 1351 #define CHIPC_CST4319_CBUCK_MODE_BURST 0x00020000 1352 #define CHIPC_CST4319_CBUCK_MODE_LPBURST 0x00060000 1353 #define CHIPC_CST4319_RCAL_VALID 0x01000000 1354 #define CHIPC_CST4319_RCAL_VALUE_MASK 0x3e000000 1355 #define CHIPC_CST4319_RCAL_VALUE_SHIFT 25 1356 1357 #define CHIPC_PMU1_PLL0_CHIPCTL0 0 1358 #define CHIPC_PMU1_PLL0_CHIPCTL1 1 1359 #define CHIPC_PMU1_PLL0_CHIPCTL2 2 1360 #define CHIPC_CCTL_4319USB_XTAL_SEL_MASK 0x00180000 1361 #define CHIPC_CCTL_4319USB_XTAL_SEL_SHIFT 19 1362 #define CHIPC_CCTL_4319USB_48MHZ_PLL_SEL 1 1363 #define CHIPC_CCTL_4319USB_24MHZ_PLL_SEL 2 1364 1365 /* PMU resources for 4336 */ 1366 #define CHIPC_RES4336_CBUCK_LPOM 0 1367 #define CHIPC_RES4336_CBUCK_BURST 1 1368 #define CHIPC_RES4336_CBUCK_LP_PWM 2 1369 #define CHIPC_RES4336_CBUCK_PWM 3 1370 #define CHIPC_RES4336_CLDO_PU 4 1371 #define CHIPC_RES4336_DIS_INT_RESET_PD 5 1372 #define CHIPC_RES4336_ILP_REQUEST 6 1373 #define CHIPC_RES4336_LNLDO_PU 7 1374 #define CHIPC_RES4336_LDO3P3_PU 8 1375 #define CHIPC_RES4336_OTP_PU 9 1376 #define CHIPC_RES4336_XTAL_PU 10 1377 #define CHIPC_RES4336_ALP_AVAIL 11 1378 #define CHIPC_RES4336_RADIO_PU 12 1379 #define CHIPC_RES4336_BG_PU 13 1380 #define CHIPC_RES4336_VREG1p4_PU_PU 14 1381 #define CHIPC_RES4336_AFE_PWRSW_PU 15 1382 #define CHIPC_RES4336_RX_PWRSW_PU 16 1383 #define CHIPC_RES4336_TX_PWRSW_PU 17 1384 #define CHIPC_RES4336_BB_PWRSW_PU 18 1385 #define CHIPC_RES4336_SYNTH_PWRSW_PU 19 1386 #define CHIPC_RES4336_MISC_PWRSW_PU 20 1387 #define CHIPC_RES4336_LOGEN_PWRSW_PU 21 1388 #define CHIPC_RES4336_BBPLL_PWRSW_PU 22 1389 #define CHIPC_RES4336_MACPHY_CLKAVAIL 23 1390 #define CHIPC_RES4336_HT_AVAIL 24 1391 #define CHIPC_RES4336_RSVD 25 1392 1393 /* 4336 chip-specific ChipStatus register bits */ 1394 #define CHIPC_CST4336_SPI_MODE_MASK 0x00000001 1395 #define CHIPC_CST4336_SPROM_PRESENT 0x00000002 1396 #define CHIPC_CST4336_OTP_PRESENT 0x00000004 1397 #define CHIPC_CST4336_ARMREMAP_0 0x00000008 1398 #define CHIPC_CST4336_ILPDIV_EN_MASK 0x00000010 1399 #define CHIPC_CST4336_ILPDIV_EN_SHIFT 4 1400 #define CHIPC_CST4336_XTAL_PD_POL_MASK 0x00000020 1401 #define CHIPC_CST4336_XTAL_PD_POL_SHIFT 5 1402 #define CHIPC_CST4336_LPO_SEL_MASK 0x00000040 1403 #define CHIPC_CST4336_LPO_SEL_SHIFT 6 1404 #define CHIPC_CST4336_RES_INIT_MODE_MASK 0x00000180 1405 #define CHIPC_CST4336_RES_INIT_MODE_SHIFT 7 1406 #define CHIPC_CST4336_CBUCK_MODE_MASK 0x00000600 1407 #define CHIPC_CST4336_CBUCK_MODE_SHIFT 9 1408 1409 /* 4330 resources */ 1410 #define CHIPC_RES4330_CBUCK_LPOM 0 1411 #define CHIPC_RES4330_CBUCK_BURST 1 1412 #define CHIPC_RES4330_CBUCK_LP_PWM 2 1413 #define CHIPC_RES4330_CBUCK_PWM 3 1414 #define CHIPC_RES4330_CLDO_PU 4 1415 #define CHIPC_RES4330_DIS_INT_RESET_PD 5 1416 #define CHIPC_RES4330_ILP_REQUEST 6 1417 #define CHIPC_RES4330_LNLDO_PU 7 1418 #define CHIPC_RES4330_LDO3P3_PU 8 1419 #define CHIPC_RES4330_OTP_PU 9 1420 #define CHIPC_RES4330_XTAL_PU 10 1421 #define CHIPC_RES4330_ALP_AVAIL 11 1422 #define CHIPC_RES4330_RADIO_PU 12 1423 #define CHIPC_RES4330_BG_PU 13 1424 #define CHIPC_RES4330_VREG1p4_PU_PU 14 1425 #define CHIPC_RES4330_AFE_PWRSW_PU 15 1426 #define CHIPC_RES4330_RX_PWRSW_PU 16 1427 #define CHIPC_RES4330_TX_PWRSW_PU 17 1428 #define CHIPC_RES4330_BB_PWRSW_PU 18 1429 #define CHIPC_RES4330_SYNTH_PWRSW_PU 19 1430 #define CHIPC_RES4330_MISC_PWRSW_PU 20 1431 #define CHIPC_RES4330_LOGEN_PWRSW_PU 21 1432 #define CHIPC_RES4330_BBPLL_PWRSW_PU 22 1433 #define CHIPC_RES4330_MACPHY_CLKAVAIL 23 1434 #define CHIPC_RES4330_HT_AVAIL 24 1435 #define CHIPC_RES4330_5gRX_PWRSW_PU 25 1436 #define CHIPC_RES4330_5gTX_PWRSW_PU 26 1437 #define CHIPC_RES4330_5g_LOGEN_PWRSW_PU 27 1438 1439 /* 4330 chip-specific ChipStatus register bits */ 1440 #define CHIPC_CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */ 1441 #define CHIPC_CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */ 1442 #define CHIPC_CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */ 1443 #define CHIPC_CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */ 1444 #define CHIPC_CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */ 1445 #define CHIPC_CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */ 1446 #define CHIPC_CST4330_OTP_PRESENT 0x00000010 1447 #define CHIPC_CST4330_LPO_AUTODET_EN 0x00000020 1448 #define CHIPC_CST4330_ARMREMAP_0 0x00000040 1449 #define CHIPC_CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */ 1450 #define CHIPC_CST4330_ILPDIV_EN 0x00000100 1451 #define CHIPC_CST4330_LPO_SEL 0x00000200 1452 #define CHIPC_CST4330_RES_INIT_MODE_SHIFT 10 1453 #define CHIPC_CST4330_RES_INIT_MODE_MASK 0x00000c00 1454 #define CHIPC_CST4330_CBUCK_MODE_SHIFT 12 1455 #define CHIPC_CST4330_CBUCK_MODE_MASK 0x00003000 1456 #define CHIPC_CST4330_CBUCK_POWER_OK 0x00004000 1457 #define CHIPC_CST4330_BB_PLL_LOCKED 0x00008000 1458 #define CHIPC_SOCDEVRAM_4330_BP_ADDR 0x1E000000 1459 #define CHIPC_SOCDEVRAM_4330_ARM_ADDR 0x00800000 1460 1461 /* 4313 resources */ 1462 #define CHIPC_RES4313_BB_PU_RSRC 0 1463 #define CHIPC_RES4313_ILP_REQ_RSRC 1 1464 #define CHIPC_RES4313_XTAL_PU_RSRC 2 1465 #define CHIPC_RES4313_ALP_AVAIL_RSRC 3 1466 #define CHIPC_RES4313_RADIO_PU_RSRC 4 1467 #define CHIPC_RES4313_BG_PU_RSRC 5 1468 #define CHIPC_RES4313_VREG1P4_PU_RSRC 6 1469 #define CHIPC_RES4313_AFE_PWRSW_RSRC 7 1470 #define CHIPC_RES4313_RX_PWRSW_RSRC 8 1471 #define CHIPC_RES4313_TX_PWRSW_RSRC 9 1472 #define CHIPC_RES4313_BB_PWRSW_RSRC 10 1473 #define CHIPC_RES4313_SYNTH_PWRSW_RSRC 11 1474 #define CHIPC_RES4313_MISC_PWRSW_RSRC 12 1475 #define CHIPC_RES4313_BB_PLL_PWRSW_RSRC 13 1476 #define CHIPC_RES4313_HT_AVAIL_RSRC 14 1477 #define CHIPC_RES4313_MACPHY_CLK_AVAIL_RSRC 15 1478 1479 /* 4313 chip-specific ChipStatus register bits */ 1480 #define CHIPC_CST4313_SPROM_PRESENT 1 1481 #define CHIPC_CST4313_OTP_PRESENT 2 1482 #define CHIPC_CST4313_SPROM_OTP_SEL_MASK 0x00000002 1483 #define CHIPC_CST4313_SPROM_OTP_SEL_SHIFT 0 1484 1485 /* 4313 Chip specific ChipControl register bits */ 1486 #define CHIPC_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ 1487 1488 /* 43228 resources */ 1489 #define CHIPC_RES43228_NOT_USED 0 1490 #define CHIPC_RES43228_ILP_REQUEST 1 1491 #define CHIPC_RES43228_XTAL_PU 2 1492 #define CHIPC_RES43228_ALP_AVAIL 3 1493 #define CHIPC_RES43228_PLL_EN 4 1494 #define CHIPC_RES43228_HT_PHY_AVAIL 5 1495 1496 /* 43228 chipstatus reg bits */ 1497 #define CHIPC_CST43228_ILP_DIV_EN 0x1 1498 #define CHIPC_CST43228_OTP_PRESENT 0x2 1499 #define CHIPC_CST43228_SERDES_REFCLK_PADSEL 0x4 1500 #define CHIPC_CST43228_SDIO_MODE 0x8 1501 1502 #define CHIPC_CST43228_SDIO_OTP_PRESENT 0x10 1503 #define CHIPC_CST43228_SDIO_RESET 0x20 1504 1505 /* 1506 * Maximum delay for the PMU state transition in us. 1507 * This is an upper bound intended for spinwaits etc. 1508 */ 1509 #define CHIPC_PMU_MAX_TRANSITION_DLY 15000 1510 1511 /* PMU resource up transition time in ILP cycles */ 1512 #define CHIPC_PMURES_UP_TRANSITION 2 1513 1514 /* 1515 * Register eci_inputlo bitfield values. 1516 * - BT packet type information bits [7:0] 1517 */ 1518 /* [3:0] - Task (link) type */ 1519 #define CHIPC_BT_ACL 0x00 1520 #define CHIPC_BT_SCO 0x01 1521 #define CHIPC_BT_eSCO 0x02 1522 #define CHIPC_BT_A2DP 0x03 1523 #define CHIPC_BT_SNIFF 0x04 1524 #define CHIPC_BT_PAGE_SCAN 0x05 1525 #define CHIPC_BT_INQUIRY_SCAN 0x06 1526 #define CHIPC_BT_PAGE 0x07 1527 #define CHIPC_BT_INQUIRY 0x08 1528 #define CHIPC_BT_MSS 0x09 1529 #define CHIPC_BT_PARK 0x0a 1530 #define CHIPC_BT_RSSISCAN 0x0b 1531 #define CHIPC_BT_MD_ACL 0x0c 1532 #define CHIPC_BT_MD_eSCO 0x0d 1533 #define CHIPC_BT_SCAN_WITH_SCO_LINK 0x0e 1534 #define CHIPC_BT_SCAN_WITHOUT_SCO_LINK 0x0f 1535 /* [7:4] = packet duration code */ 1536 /* [8] - Master / Slave */ 1537 #define CHIPC_BT_MASTER 0 1538 #define CHIPC_BT_SLAVE 1 1539 /* [11:9] - multi-level priority */ 1540 #define CHIPC_BT_LOWEST_PRIO 0x0 1541 #define CHIPC_BT_HIGHEST_PRIO 0x3 1542 1543 #endif /* _BHND_CORES_CHIPC_CHIPCREG_H_ */ 1544