1 /*- 2 * Copyright (c) 2015 Landon Fuller <landon@landonf.org> 3 * Copyright (c) 2010 Broadcom Corporation 4 * All rights reserved. 5 * 6 * This file is derived from the sbchipc.h header distributed with 7 * Broadcom's initial brcm80211 Linux driver release, as 8 * contributed to the Linux staging repository. 9 * 10 * Permission to use, copy, modify, and/or distribute this software for any 11 * purpose with or without fee is hereby granted, provided that the above 12 * copyright notice and this permission notice appear in all copies. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 17 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 19 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 20 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 21 * 22 * $FreeBSD$ 23 */ 24 25 #ifndef _BHND_CORES_CHIPC_CHIPCREG_H_ 26 #define _BHND_CORES_CHIPC_CHIPCREG_H_ 27 28 #define CHIPC_CHIPID_SIZE 0x100 /**< size of the register block 29 containing the chip 30 identification registers. */ 31 32 /** Evaluates to true if the given ChipCommon core revision provides 33 * the core count via the chip identification register. */ 34 #define CHIPC_NCORES_MIN_HWREV(hwrev) ((hwrev) == 4 || (hwrev) >= 6) 35 36 #define CHIPC_GET_ATTR(_entry, _attr) \ 37 ((_entry & CHIPC_ ## _attr ## _MASK) >> CHIPC_ ## _attr ## _SHIFT) 38 39 #define CHIPC_ID 0x0 40 #define CHIPC_CAPABILITIES 0x04 41 #define CHIPC_CHIPST 0x2c 42 #define CHIPC_EROMPTR 0xfc /**< 32-bit EROM base address 43 * on BCMA devices */ 44 45 /** chipid */ 46 #define CHIPC_ID 0x0 /**< identification register */ 47 #define CHIPC_ID_CHIP_MASK 0x0000FFFF /**< chip id */ 48 #define CHIPC_ID_CHIP_SHIFT 0 49 #define CHIPC_ID_REV_MASK 0x000F0000 /**< chip revision */ 50 #define CHIPC_ID_REV_SHIFT 16 51 #define CHIPC_ID_PKG_MASK 0x00F00000 /**< physical package ID */ 52 #define CHIPC_ID_PKG_SHIFT 20 53 #define CHIPC_ID_NUMCORE_MASK 0x0F000000 /**< number of cores on chip (rev >= 4) */ 54 #define CHIPC_ID_NUMCORE_SHIFT 24 55 #define CHIPC_ID_BUS_MASK 0xF0000000 /**< chip/interconnect type (BHND_CHIPTYPE_*) */ 56 #define CHIPC_ID_BUS_SHIFT 28 57 58 #define CHIPC_OTPST 0x10 59 #define CHIPC_JTAGCMD 0x30 60 #define CHIPC_JTAGIR 0x34 61 #define CHIPC_JTAGDR 0x38 62 #define CHIPC_JTAGCTRL 0x3c 63 #define CHIPC_GPIOPU 0x58 64 #define CHIPC_GPIOPD 0x5c 65 #define CHIPC_GPIOIN 0x60 66 #define CHIPC_GPIOOUT 0x64 67 #define CHIPC_GPIOOUTEN 0x68 68 #define CHIPC_GPIOCTRL 0x6c 69 #define CHIPC_GPIOPOL 0x70 70 #define CHIPC_GPIOINTM 0x74 71 #define CHIPC_WATCHDOG 0x80 72 #define CHIPC_CLKC_N 0x90 73 #define CHIPC_CLKC_M0 0x94 74 #define CHIPC_CLKC_M1 0x98 75 #define CHIPC_CLKC_M2 0x9c 76 #define CHIPC_CLKC_M3 0xa0 77 #define CHIPC_CLKDIV 0xa4 78 #define CHIPC_SYS_CLK_CTL 0xc0 79 #define CHIPC_SPROM_CTRL 0x190 /**< SPROM interface (rev >= 32) */ 80 #define CHIPC_SPROM_ADDR 0x194 81 #define CHIPC_SPROM_DATA 0x198 82 #define CHIPC_CLK_CTL_ST SI_CLK_CTL_ST 83 #define CHIPC_PMU_CTL 0x600 84 #define CHIPC_PMU_CAP 0x604 85 #define CHIPC_PMU_ST 0x608 86 #define CHIPC_PMU_RES_STATE 0x60c 87 #define CHIPC_PMU_TIMER 0x614 88 #define CHIPC_PMU_MIN_RES_MASK 0x618 89 #define CHIPC_PMU_MAX_RES_MASK 0x61c 90 #define CHIPC_CHIPCTL_ADDR 0x650 91 #define CHIPC_CHIPCTL_DATA 0x654 92 #define CHIPC_PMU_REG_CONTROL_ADDR 0x658 93 #define CHIPC_PMU_REG_CONTROL_DATA 0x65C 94 #define CHIPC_PMU_PLL_CONTROL_ADDR 0x660 95 #define CHIPC_PMU_PLL_CONTROL_DATA 0x664 96 #define CHIPC_SPROM_OTP 0x800 /* SPROM/OTP address space */ 97 98 /* capabilities */ 99 #define CHIPC_CAP_UARTS_MASK 0x00000003 /* Number of UARTs */ 100 #define CHIPC_CAP_MIPSEB 0x00000004 /* MIPS is in big-endian mode */ 101 #define CHIPC_CAP_UCLKSEL 0x00000018 /* UARTs clock select */ 102 #define CHIPC_CAP_UINTCLK 0x00000008 /* UARTs are driven by internal divided clock */ 103 #define CHIPC_CAP_UARTGPIO 0x00000020 /* UARTs own GPIOs 15:12 */ 104 #define CHIPC_CAP_EXTBUS_MASK 0x000000c0 /* External bus mask */ 105 #define CHIPC_CAP_EXTBUS_NONE 0x00000000 /* No ExtBus present */ 106 #define CHIPC_CAP_EXTBUS_FULL 0x00000040 /* ExtBus: PCMCIA, IDE & Prog */ 107 #define CHIPC_CAP_EXTBUS_PROG 0x00000080 /* ExtBus: ProgIf only */ 108 #define CHIPC_CAP_FLASH_MASK 0x00000700 /* Type of flash */ 109 #define CHIPC_CAP_PLL_MASK 0x00038000 /* Type of PLL */ 110 #define CHIPC_CAP_PWR_CTL 0x00040000 /* Power control */ 111 #define CHIPC_CAP_OTP_SIZE 0x00380000 /* OTP Size (0 = none) */ 112 #define CHIPC_CAP_OTP_SIZE_SHIFT 19 /* OTP Size shift */ 113 #define CHIPC_CAP_OTP_SIZE_BASE 5 /* OTP Size base */ 114 #define CHIPC_CAP_JTAGP 0x00400000 /* JTAG Master Present */ 115 #define CHIPC_CAP_ROM 0x00800000 /* Internal boot rom active */ 116 #define CHIPC_CAP_BKPLN64 0x08000000 /* 64-bit backplane */ 117 #define CHIPC_CAP_PMU 0x10000000 /* PMU Present, rev >= 20 */ 118 #define CHIPC_CAP_SPROM 0x40000000 /* SPROM Present, rev >= 32 */ 119 #define CHIPC_CAP_NFLASH 0x80000000 /* Nand flash present, rev >= 35 */ 120 121 #define CHIPC_CAP2_SECI 0x00000001 /* SECI Present, rev >= 36 */ 122 #define CHIPC_CAP2_GSIO 0x00000002 /* GSIO (spi/i2c) present, rev >= 37 */ 123 124 /* 125 * ChipStatus (Common) 126 */ 127 128 /** ChipStatus CIS/OTP/SPROM values used to advertise OTP/SPROM availability in 129 * chipcommon revs 11-31. */ 130 enum { 131 CHIPC_CST_DEFCIS_SEL = 0, /**< OTP is powered up, use default CIS, no SPROM */ 132 CHIPC_CST_SPROM_SEL = 1, /**< OTP is powered up, SPROM is present */ 133 CHIPC_CST_OTP_SEL = 2, /**< OTP is powered up, no SPROM */ 134 CHIPC_CST_OTP_PWRDN = 3 /**< OTP is powered down, SPROM is present (rev <= 22 only) */ 135 }; 136 137 138 #define CHIPC_CST_SPROM_OTP_SEL_R22_MASK 0x00000003 /**< chipstatus OTP/SPROM SEL value (rev 22) */ 139 #define CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 0 140 #define CHIPC_CST_SPROM_OTP_SEL_R23_MASK 0x000000c0 /**< chipstatus OTP/SPROM SEL value (revs 23-31) 141 * 142 * it is unknown whether this is supported on 143 * any CC revs >= 32 that also vend CHIPC_CAP_* 144 * constants for OTP/SPROM/NVRAM availability. 145 */ 146 #define CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 6 147 148 /* PLL type */ 149 #define CHIPC_PLL_NONE 0x00000000 150 #define CHIPC_PLL_TYPE1 0x00010000 /* 48MHz base, 3 dividers */ 151 #define CHIPC_PLL_TYPE2 0x00020000 /* 48MHz, 4 dividers */ 152 #define CHIPC_PLL_TYPE3 0x00030000 /* 25MHz, 2 dividers */ 153 #define CHIPC_PLL_TYPE4 0x00008000 /* 48MHz, 4 dividers */ 154 #define CHIPC_PLL_TYPE5 0x00018000 /* 25MHz, 4 dividers */ 155 #define CHIPC_PLL_TYPE6 0x00028000 /* 100/200 or 120/240 only */ 156 #define CHIPC_PLL_TYPE7 0x00038000 /* 25MHz, 4 dividers */ 157 158 /* ILP clock */ 159 #define CHIPC_ILP_CLOCK 32000 160 161 /* ALP clock on pre-PMU chips */ 162 #define CHIPC_ALP_CLOCK 20000000 163 164 /* HT clock */ 165 #define CHIPC_HT_CLOCK 80000000 166 167 /* corecontrol */ 168 #define CHIPC_UARTCLKO 0x00000001 /* Drive UART with internal clock */ 169 #define CHIPC_SE 0x00000002 /* sync clk out enable (corerev >= 3) */ 170 #define CHIPC_UARTCLKEN 0x00000008 /* enable UART Clock (corerev > = 21 */ 171 172 /* chipcontrol */ 173 #define CHIPCTRL_4321A0_DEFAULT 0x3a4 174 #define CHIPCTRL_4321A1_DEFAULT 0x0a4 175 #define CHIPCTRL_4321_PLL_DOWN 0x800000 /* serdes PLL down override */ 176 177 /* Fields in the otpstatus register in rev >= 21 */ 178 #define CHIPC_OTPS_OL_MASK 0x000000ff 179 #define CHIPC_OTPS_OL_MFG 0x00000001 /* manuf row is locked */ 180 #define CHIPC_OTPS_OL_OR1 0x00000002 /* otp redundancy row 1 is locked */ 181 #define CHIPC_OTPS_OL_OR2 0x00000004 /* otp redundancy row 2 is locked */ 182 #define CHIPC_OTPS_OL_GU 0x00000008 /* general use region is locked */ 183 #define CHIPC_OTPS_GUP_MASK 0x00000f00 184 #define CHIPC_OTPS_GUP_SHIFT 8 185 #define CHIPC_OTPS_GUP_HW 0x00000100 /* h/w subregion is programmed */ 186 #define CHIPC_OTPS_GUP_SW 0x00000200 /* s/w subregion is programmed */ 187 #define CHIPC_OTPS_GUP_CI 0x00000400 /* chipid/pkgopt subregion is programmed */ 188 #define CHIPC_OTPS_GUP_FUSE 0x00000800 /* fuse subregion is programmed */ 189 #define CHIPC_OTPS_READY 0x00001000 190 #define CHIPC_OTPS_RV(x) (1 << (16 + (x))) /* redundancy entry valid */ 191 #define CHIPC_OTPS_RV_MASK 0x0fff0000 192 193 /* Fields in the otpcontrol register in rev >= 21 */ 194 #define CHIPC_OTPC_PROGSEL 0x00000001 195 #define CHIPC_OTPC_PCOUNT_MASK 0x0000000e 196 #define CHIPC_OTPC_PCOUNT_SHIFT 1 197 #define CHIPC_OTPC_VSEL_MASK 0x000000f0 198 #define CHIPC_OTPC_VSEL_SHIFT 4 199 #define CHIPC_OTPC_TMM_MASK 0x00000700 200 #define CHIPC_OTPC_TMM_SHIFT 8 201 #define CHIPC_OTPC_ODM 0x00000800 202 #define CHIPC_OTPC_PROGEN 0x80000000 203 204 /* Fields in otpprog in rev >= 21 and HND OTP */ 205 #define CHIPC_OTPP_COL_MASK 0x000000ff 206 #define CHIPC_OTPP_COL_SHIFT 0 207 #define CHIPC_OTPP_ROW_MASK 0x0000ff00 208 #define CHIPC_OTPP_ROW_SHIFT 8 209 #define CHIPC_OTPP_OC_MASK 0x0f000000 210 #define CHIPC_OTPP_OC_SHIFT 24 211 #define CHIPC_OTPP_READERR 0x10000000 212 #define CHIPC_OTPP_VALUE_MASK 0x20000000 213 #define CHIPC_OTPP_VALUE_SHIFT 29 214 #define CHIPC_OTPP_START_BUSY 0x80000000 215 #define CHIPC_OTPP_READ 0x40000000 /* HND OTP */ 216 217 /* otplayout reg corerev >= 36 */ 218 #define CHIPC_OTP_CISFORMAT_NEW 0x80000000 219 220 /* Opcodes for OTPP_OC field */ 221 #define CHIPC_OTPPOC_READ 0 222 #define CHIPC_OTPPOC_BIT_PROG 1 223 #define CHIPC_OTPPOC_VERIFY 3 224 #define CHIPC_OTPPOC_INIT 4 225 #define CHIPC_OTPPOC_SET 5 226 #define CHIPC_OTPPOC_RESET 6 227 #define CHIPC_OTPPOC_OCST 7 228 #define CHIPC_OTPPOC_ROW_LOCK 8 229 #define CHIPC_OTPPOC_PRESCN_TEST 9 230 231 /* Jtagm characteristics that appeared at a given corerev */ 232 #define CHIPC_JTAGM_CREV_OLD 10 /* Old command set, 16bit max IR */ 233 #define CHIPC_JTAGM_CREV_IRP 22 /* Able to do pause-ir */ 234 #define CHIPC_JTAGM_CREV_RTI 28 /* Able to do return-to-idle */ 235 236 /* jtagcmd */ 237 #define CHIPC_JCMD_START 0x80000000 238 #define CHIPC_JCMD_BUSY 0x80000000 239 #define CHIPC_JCMD_STATE_MASK 0x60000000 240 #define CHIPC_JCMD_STATE_TLR 0x00000000 /* Test-logic-reset */ 241 #define CHIPC_JCMD_STATE_PIR 0x20000000 /* Pause IR */ 242 #define CHIPC_JCMD_STATE_PDR 0x40000000 /* Pause DR */ 243 #define CHIPC_JCMD_STATE_RTI 0x60000000 /* Run-test-idle */ 244 #define CHIPC_JCMD0_ACC_MASK 0x0000f000 245 #define CHIPC_JCMD0_ACC_IRDR 0x00000000 246 #define CHIPC_JCMD0_ACC_DR 0x00001000 247 #define CHIPC_JCMD0_ACC_IR 0x00002000 248 #define CHIPC_JCMD0_ACC_RESET 0x00003000 249 #define CHIPC_JCMD0_ACC_IRPDR 0x00004000 250 #define CHIPC_JCMD0_ACC_PDR 0x00005000 251 #define CHIPC_JCMD0_IRW_MASK 0x00000f00 252 #define CHIPC_JCMD_ACC_MASK 0x000f0000 /* Changes for corerev 11 */ 253 #define CHIPC_JCMD_ACC_IRDR 0x00000000 254 #define CHIPC_JCMD_ACC_DR 0x00010000 255 #define CHIPC_JCMD_ACC_IR 0x00020000 256 #define CHIPC_JCMD_ACC_RESET 0x00030000 257 #define CHIPC_JCMD_ACC_IRPDR 0x00040000 258 #define CHIPC_JCMD_ACC_PDR 0x00050000 259 #define CHIPC_JCMD_ACC_PIR 0x00060000 260 #define CHIPC_JCMD_ACC_IRDR_I 0x00070000 /* rev 28: return to run-test-idle */ 261 #define CHIPC_JCMD_ACC_DR_I 0x00080000 /* rev 28: return to run-test-idle */ 262 #define CHIPC_JCMD_IRW_MASK 0x00001f00 263 #define CHIPC_JCMD_IRW_SHIFT 8 264 #define CHIPC_JCMD_DRW_MASK 0x0000003f 265 266 /* jtagctrl */ 267 #define CHIPC_JCTRL_FORCE_CLK 4 /* Force clock */ 268 #define CHIPC_JCTRL_EXT_EN 2 /* Enable external targets */ 269 #define CHIPC_JCTRL_EN 1 /* Enable Jtag master */ 270 271 /* Fields in clkdiv */ 272 #define CHIPC_CLKD_SFLASH 0x0f000000 273 #define CHIPC_CLKD_SFLASH_SHIFT 24 274 #define CHIPC_CLKD_OTP 0x000f0000 275 #define CHIPC_CLKD_OTP_SHIFT 16 276 #define CHIPC_CLKD_JTAG 0x00000f00 277 #define CHIPC_CLKD_JTAG_SHIFT 8 278 #define CHIPC_CLKD_UART 0x000000ff 279 280 #define CHIPC_CLKD2_SPROM 0x00000003 281 282 /* intstatus/intmask */ 283 #define CHIPC_CI_GPIO 0x00000001 /* gpio intr */ 284 #define CHIPC_CI_EI 0x00000002 /* extif intr (corerev >= 3) */ 285 #define CHIPC_CI_TEMP 0x00000004 /* temp. ctrl intr (corerev >= 15) */ 286 #define CHIPC_CI_SIRQ 0x00000008 /* serial IRQ intr (corerev >= 15) */ 287 #define CHIPC_CI_PMU 0x00000020 /* pmu intr (corerev >= 21) */ 288 #define CHIPC_CI_UART 0x00000040 /* uart intr (corerev >= 21) */ 289 #define CHIPC_CI_WDRESET 0x80000000 /* watchdog reset occurred */ 290 291 /* slow_clk_ctl */ 292 #define CHIPC_SCC_SS_MASK 0x00000007 /* slow clock source mask */ 293 #define CHIPC_SCC_SS_LPO 0x00000000 /* source of slow clock is LPO */ 294 #define CHIPC_SCC_SS_XTAL 0x00000001 /* source of slow clock is crystal */ 295 #define CHIPC_SCC_SS_PCI 0x00000002 /* source of slow clock is PCI */ 296 #define CHIPC_SCC_LF 0x00000200 /* LPOFreqSel, 1: 160Khz, 0: 32KHz */ 297 #define CHIPC_SCC_LP 0x00000400 /* LPOPowerDown, 1: LPO is disabled, 298 * 0: LPO is enabled 299 */ 300 #define CHIPC_SCC_FS 0x00000800 /* ForceSlowClk, 1: sb/cores running on slow clock, 301 * 0: power logic control 302 */ 303 #define CHIPC_SCC_IP 0x00001000 /* IgnorePllOffReq, 1/0: power logic ignores/honors 304 * PLL clock disable requests from core 305 */ 306 #define CHIPC_SCC_XC 0x00002000 /* XtalControlEn, 1/0: power logic does/doesn't 307 * disable crystal when appropriate 308 */ 309 #define CHIPC_SCC_XP 0x00004000 /* XtalPU (RO), 1/0: crystal running/disabled */ 310 #define CHIPC_SCC_CD_MASK 0xffff0000 /* ClockDivider (SlowClk = 1/(4+divisor)) */ 311 #define CHIPC_SCC_CD_SHIFT 16 312 313 /* system_clk_ctl */ 314 #define CHIPC_SYCC_IE 0x00000001 /* ILPen: Enable Idle Low Power */ 315 #define CHIPC_SYCC_AE 0x00000002 /* ALPen: Enable Active Low Power */ 316 #define CHIPC_SYCC_FP 0x00000004 /* ForcePLLOn */ 317 #define CHIPC_SYCC_AR 0x00000008 /* Force ALP (or HT if ALPen is not set */ 318 #define CHIPC_SYCC_HR 0x00000010 /* Force HT */ 319 #define CHIPC_SYCC_CD_MASK 0xffff0000 /* ClkDiv (ILP = 1/(4 * (divisor + 1)) */ 320 #define CHIPC_SYCC_CD_SHIFT 16 321 322 /* Indirect backplane access */ 323 #define CHIPC_BPIA_BYTEEN 0x0000000f 324 #define CHIPC_BPIA_SZ1 0x00000001 325 #define CHIPC_BPIA_SZ2 0x00000003 326 #define CHIPC_BPIA_SZ4 0x00000007 327 #define CHIPC_BPIA_SZ8 0x0000000f 328 #define CHIPC_BPIA_WRITE 0x00000100 329 #define CHIPC_BPIA_START 0x00000200 330 #define CHIPC_BPIA_BUSY 0x00000200 331 #define CHIPC_BPIA_ERROR 0x00000400 332 333 /* pcmcia/prog/flash_config */ 334 #define CHIPC_CF_EN 0x00000001 /* enable */ 335 #define CHIPC_CF_EM_MASK 0x0000000e /* mode */ 336 #define CHIPC_CF_EM_SHIFT 1 337 #define CHIPC_CF_EM_FLASH 0 /* flash/asynchronous mode */ 338 #define CHIPC_CF_EM_SYNC 2 /* synchronous mode */ 339 #define CHIPC_CF_EM_PCMCIA 4 /* pcmcia mode */ 340 #define CHIPC_CF_DS 0x00000010 /* destsize: 0=8bit, 1=16bit */ 341 #define CHIPC_CF_BS 0x00000020 /* byteswap */ 342 #define CHIPC_CF_CD_MASK 0x000000c0 /* clock divider */ 343 #define CHIPC_CF_CD_SHIFT 6 344 #define CHIPC_CF_CD_DIV2 0x00000000 /* backplane/2 */ 345 #define CHIPC_CF_CD_DIV3 0x00000040 /* backplane/3 */ 346 #define CHIPC_CF_CD_DIV4 0x00000080 /* backplane/4 */ 347 #define CHIPC_CF_CE 0x00000100 /* clock enable */ 348 #define CHIPC_CF_SB 0x00000200 /* size/bytestrobe (synch only) */ 349 350 /* pcmcia_memwait */ 351 #define CHIPC_PM_W0_MASK 0x0000003f /* waitcount0 */ 352 #define CHIPC_PM_W1_MASK 0x00001f00 /* waitcount1 */ 353 #define CHIPC_PM_W1_SHIFT 8 354 #define CHIPC_PM_W2_MASK 0x001f0000 /* waitcount2 */ 355 #define CHIPC_PM_W2_SHIFT 16 356 #define CHIPC_PM_W3_MASK 0x1f000000 /* waitcount3 */ 357 #define CHIPC_PM_W3_SHIFT 24 358 359 /* pcmcia_attrwait */ 360 #define CHIPC_PA_W0_MASK 0x0000003f /* waitcount0 */ 361 #define CHIPC_PA_W1_MASK 0x00001f00 /* waitcount1 */ 362 #define CHIPC_PA_W1_SHIFT 8 363 #define CHIPC_PA_W2_MASK 0x001f0000 /* waitcount2 */ 364 #define CHIPC_PA_W2_SHIFT 16 365 #define CHIPC_PA_W3_MASK 0x1f000000 /* waitcount3 */ 366 #define CHIPC_PA_W3_SHIFT 24 367 368 /* pcmcia_iowait */ 369 #define CHIPC_PI_W0_MASK 0x0000003f /* waitcount0 */ 370 #define CHIPC_PI_W1_MASK 0x00001f00 /* waitcount1 */ 371 #define CHIPC_PI_W1_SHIFT 8 372 #define CHIPC_PI_W2_MASK 0x001f0000 /* waitcount2 */ 373 #define CHIPC_PI_W2_SHIFT 16 374 #define CHIPC_PI_W3_MASK 0x1f000000 /* waitcount3 */ 375 #define CHIPC_PI_W3_SHIFT 24 376 377 /* prog_waitcount */ 378 #define CHIPC_PW_W0_MASK 0x0000001f /* waitcount0 */ 379 #define CHIPC_PW_W1_MASK 0x00001f00 /* waitcount1 */ 380 #define CHIPC_PW_W1_SHIFT 8 381 #define CHIPC_PW_W2_MASK 0x001f0000 /* waitcount2 */ 382 #define CHIPC_PW_W2_SHIFT 16 383 #define CHIPC_PW_W3_MASK 0x1f000000 /* waitcount3 */ 384 #define CHIPC_PW_W3_SHIFT 24 385 386 #define CHIPC_PW_W0 0x0000000c 387 #define CHIPC_PW_W1 0x00000a00 388 #define CHIPC_PW_W2 0x00020000 389 #define CHIPC_PW_W3 0x01000000 390 391 /* flash_waitcount */ 392 #define CHIPC_FW_W0_MASK 0x0000003f /* waitcount0 */ 393 #define CHIPC_FW_W1_MASK 0x00001f00 /* waitcount1 */ 394 #define CHIPC_FW_W1_SHIFT 8 395 #define CHIPC_FW_W2_MASK 0x001f0000 /* waitcount2 */ 396 #define CHIPC_FW_W2_SHIFT 16 397 #define CHIPC_FW_W3_MASK 0x1f000000 /* waitcount3 */ 398 #define CHIPC_FW_W3_SHIFT 24 399 400 /* When SPROM support present, fields in spromcontrol */ 401 #define CHIPC_SRC_START 0x80000000 402 #define CHIPC_SRC_BUSY 0x80000000 403 #define CHIPC_SRC_OPCODE 0x60000000 404 #define CHIPC_SRC_OP_READ 0x00000000 405 #define CHIPC_SRC_OP_WRITE 0x20000000 406 #define CHIPC_SRC_OP_WRDIS 0x40000000 407 #define CHIPC_SRC_OP_WREN 0x60000000 408 #define CHIPC_SRC_OTPSEL 0x00000010 409 #define CHIPC_SRC_LOCK 0x00000008 410 #define CHIPC_SRC_SIZE_MASK 0x00000006 411 #define CHIPC_SRC_SIZE_1K 0x00000000 412 #define CHIPC_SRC_SIZE_4K 0x00000002 413 #define CHIPC_SRC_SIZE_16K 0x00000004 414 #define CHIPC_SRC_SIZE_SHIFT 1 415 #define CHIPC_SRC_PRESENT 0x00000001 416 417 /* Fields in pmucontrol */ 418 #define CHIPC_PCTL_ILP_DIV_MASK 0xffff0000 419 #define CHIPC_PCTL_ILP_DIV_SHIFT 16 420 #define CHIPC_PCTL_PLL_PLLCTL_UPD 0x00000400 /* rev 2 */ 421 #define CHIPC_PCTL_NOILP_ON_WAIT 0x00000200 /* rev 1 */ 422 #define CHIPC_PCTL_HT_REQ_EN 0x00000100 423 #define CHIPC_PCTL_ALP_REQ_EN 0x00000080 424 #define CHIPC_PCTL_XTALFREQ_MASK 0x0000007c 425 #define CHIPC_PCTL_XTALFREQ_SHIFT 2 426 #define CHIPC_PCTL_ILP_DIV_EN 0x00000002 427 #define CHIPC_PCTL_LPO_SEL 0x00000001 428 429 /* Fields in clkstretch */ 430 #define CHIPC_CSTRETCH_HT 0xffff0000 431 #define CHIPC_CSTRETCH_ALP 0x0000ffff 432 433 /* gpiotimerval */ 434 #define CHIPC_GPIO_ONTIME_SHIFT 16 435 436 /* clockcontrol_n */ 437 #define CHIPC_CN_N1_MASK 0x3f /* n1 control */ 438 #define CHIPC_CN_N2_MASK 0x3f00 /* n2 control */ 439 #define CHIPC_CN_N2_SHIFT 8 440 #define CHIPC_CN_PLLC_MASK 0xf0000 /* pll control */ 441 #define CHIPC_CN_PLLC_SHIFT 16 442 443 /* clockcontrol_sb/pci/uart */ 444 #define CHIPC_M1_MASK 0x3f /* m1 control */ 445 #define CHIPC_M2_MASK 0x3f00 /* m2 control */ 446 #define CHIPC_M2_SHIFT 8 447 #define CHIPC_M3_MASK 0x3f0000 /* m3 control */ 448 #define CHIPC_M3_SHIFT 16 449 #define CHIPC_MC_MASK 0x1f000000 /* mux control */ 450 #define CHIPC_MC_SHIFT 24 451 452 /* N3M Clock control magic field values */ 453 #define CHIPC_F6_2 0x02 /* A factor of 2 in */ 454 #define CHIPC_F6_3 0x03 /* 6-bit fields like */ 455 #define CHIPC_F6_4 0x05 /* N1, M1 or M3 */ 456 #define CHIPC_F6_5 0x09 457 #define CHIPC_F6_6 0x11 458 #define CHIPC_F6_7 0x21 459 460 #define CHIPC_F5_BIAS 5 /* 5-bit fields get this added */ 461 462 #define CHIPC_MC_BYPASS 0x08 463 #define CHIPC_MC_M1 0x04 464 #define CHIPC_MC_M1M2 0x02 465 #define CHIPC_MC_M1M2M3 0x01 466 #define CHIPC_MC_M1M3 0x11 467 468 /* Type 2 Clock control magic field values */ 469 #define CHIPC_T2_BIAS 2 /* n1, n2, m1 & m3 bias */ 470 #define CHIPC_T2M2_BIAS 3 /* m2 bias */ 471 472 #define CHIPC_T2MC_M1BYP 1 473 #define CHIPC_T2MC_M2BYP 2 474 #define CHIPC_T2MC_M3BYP 4 475 476 /* Type 6 Clock control magic field values */ 477 #define CHIPC_T6_MMASK 1 /* bits of interest in m */ 478 #define CHIPC_T6_M0 120000000 /* sb clock for m = 0 */ 479 #define CHIPC_T6_M1 100000000 /* sb clock for m = 1 */ 480 #define CHIPC_SB2MIPS_T6(sb) (2 * (sb)) 481 482 /* Common clock base */ 483 #define CHIPC_CLOCK_BASE1 24000000 /* Half the clock freq */ 484 #define CHIPC_CLOCK_BASE2 12500000 /* Alternate crystal on some PLLs */ 485 486 /* Clock control values for 200MHz in 5350 */ 487 #define CHIPC_CLKC_5350_N 0x0311 488 #define CHIPC_CLKC_5350_M 0x04020009 489 490 /* Flash types in the chipcommon capabilities register */ 491 #define CHIPC_FLASH_NONE 0x000 /* No flash */ 492 #define CHIPC_SFLASH_ST 0x100 /* ST serial flash */ 493 #define CHIPC_SFLASH_AT 0x200 /* Atmel serial flash */ 494 #define CHIPC_PFLASH 0x700 /* Parallel flash */ 495 496 /* Bits in the ExtBus config registers */ 497 #define CHIPC_CFG_EN 0x0001 /* Enable */ 498 #define CHIPC_CFG_EM_MASK 0x000e /* Extif Mode */ 499 #define CHIPC_CFG_EM_ASYNC 0x0000 /* Async/Parallel flash */ 500 #define CHIPC_CFG_EM_SYNC 0x0002 /* Synchronous */ 501 #define CHIPC_CFG_EM_PCMCIA 0x0004 /* PCMCIA */ 502 #define CHIPC_CFG_EM_IDE 0x0006 /* IDE */ 503 #define CHIPC_CFG_DS 0x0010 /* Data size, 0=8bit, 1=16bit */ 504 #define CHIPC_CFG_CD_MASK 0x00e0 /* Sync: Clock divisor, rev >= 20 */ 505 #define CHIPC_CFG_CE 0x0100 /* Sync: Clock enable, rev >= 20 */ 506 #define CHIPC_CFG_SB 0x0200 /* Sync: Size/Bytestrobe, rev >= 20 */ 507 #define CHIPC_CFG_IS 0x0400 /* Extif Sync Clk Select, rev >= 20 */ 508 509 /* ExtBus address space */ 510 #define CHIPC_EB_BASE 0x1a000000 /* Chipc ExtBus base address */ 511 #define CHIPC_EB_PCMCIA_MEM 0x1a000000 /* PCMCIA 0 memory base address */ 512 #define CHIPC_EB_PCMCIA_IO 0x1a200000 /* PCMCIA 0 I/O base address */ 513 #define CHIPC_EB_PCMCIA_CFG 0x1a400000 /* PCMCIA 0 config base address */ 514 #define CHIPC_EB_IDE 0x1a800000 /* IDE memory base */ 515 #define CHIPC_EB_PCMCIA1_MEM 0x1a800000 /* PCMCIA 1 memory base address */ 516 #define CHIPC_EB_PCMCIA1_IO 0x1aa00000 /* PCMCIA 1 I/O base address */ 517 #define CHIPC_EB_PCMCIA1_CFG 0x1ac00000 /* PCMCIA 1 config base address */ 518 #define CHIPC_EB_PROGIF 0x1b000000 /* ProgIF Async/Sync base address */ 519 520 /* Start/busy bit in flashcontrol */ 521 #define CHIPC_SFLASH_OPCODE 0x000000ff 522 #define CHIPC_SFLASH_ACTION 0x00000700 523 #define CHIPC_SFLASH_CS_ACTIVE 0x00001000 /* Chip Select Active, rev >= 20 */ 524 #define CHIPC_SFLASH_START 0x80000000 525 #define CHIPC_SFLASH_BUSY SFLASH_START 526 527 /* flashcontrol action codes */ 528 #define CHIPC_SFLASH_ACT_OPONLY 0x0000 /* Issue opcode only */ 529 #define CHIPC_SFLASH_ACT_OP1D 0x0100 /* opcode + 1 data byte */ 530 #define CHIPC_SFLASH_ACT_OP3A 0x0200 /* opcode + 3 addr bytes */ 531 #define CHIPC_SFLASH_ACT_OP3A1D 0x0300 /* opcode + 3 addr & 1 data bytes */ 532 #define CHIPC_SFLASH_ACT_OP3A4D 0x0400 /* opcode + 3 addr & 4 data bytes */ 533 #define CHIPC_SFLASH_ACT_OP3A4X4D 0x0500 /* opcode + 3 addr, 4 don't care & 4 data bytes */ 534 #define CHIPC_SFLASH_ACT_OP3A1X4D 0x0700 /* opcode + 3 addr, 1 don't care & 4 data bytes */ 535 536 /* flashcontrol action+opcodes for ST flashes */ 537 #define CHIPC_SFLASH_ST_WREN 0x0006 /* Write Enable */ 538 #define CHIPC_SFLASH_ST_WRDIS 0x0004 /* Write Disable */ 539 #define CHIPC_SFLASH_ST_RDSR 0x0105 /* Read Status Register */ 540 #define CHIPC_SFLASH_ST_WRSR 0x0101 /* Write Status Register */ 541 #define CHIPC_SFLASH_ST_READ 0x0303 /* Read Data Bytes */ 542 #define CHIPC_SFLASH_ST_PP 0x0302 /* Page Program */ 543 #define CHIPC_SFLASH_ST_SE 0x02d8 /* Sector Erase */ 544 #define CHIPC_SFLASH_ST_BE 0x00c7 /* Bulk Erase */ 545 #define CHIPC_SFLASH_ST_DP 0x00b9 /* Deep Power-down */ 546 #define CHIPC_SFLASH_ST_RES 0x03ab /* Read Electronic Signature */ 547 #define CHIPC_SFLASH_ST_CSA 0x1000 /* Keep chip select asserted */ 548 #define CHIPC_SFLASH_ST_SSE 0x0220 /* Sub-sector Erase */ 549 550 /* Status register bits for ST flashes */ 551 #define CHIPC_SFLASH_ST_WIP 0x01 /* Write In Progress */ 552 #define CHIPC_SFLASH_ST_WEL 0x02 /* Write Enable Latch */ 553 #define CHIPC_SFLASH_ST_BP_MASK 0x1c /* Block Protect */ 554 #define CHIPC_SFLASH_ST_BP_SHIFT 2 555 #define CHIPC_SFLASH_ST_SRWD 0x80 /* Status Register Write Disable */ 556 557 /* flashcontrol action+opcodes for Atmel flashes */ 558 #define CHIPC_SFLASH_AT_READ 0x07e8 559 #define CHIPC_SFLASH_AT_PAGE_READ 0x07d2 560 #define CHIPC_SFLASH_AT_BUF1_READ 561 #define CHIPC_SFLASH_AT_BUF2_READ 562 #define CHIPC_SFLASH_AT_STATUS 0x01d7 563 #define CHIPC_SFLASH_AT_BUF1_WRITE 0x0384 564 #define CHIPC_SFLASH_AT_BUF2_WRITE 0x0387 565 #define CHIPC_SFLASH_AT_BUF1_ERASE_PROGRAM 0x0283 566 #define CHIPC_SFLASH_AT_BUF2_ERASE_PROGRAM 0x0286 567 #define CHIPC_SFLASH_AT_BUF1_PROGRAM 0x0288 568 #define CHIPC_SFLASH_AT_BUF2_PROGRAM 0x0289 569 #define CHIPC_SFLASH_AT_PAGE_ERASE 0x0281 570 #define CHIPC_SFLASH_AT_BLOCK_ERASE 0x0250 571 #define CHIPC_SFLASH_AT_BUF1_WRITE_ERASE_PROGRAM 0x0382 572 #define CHIPC_SFLASH_AT_BUF2_WRITE_ERASE_PROGRAM 0x0385 573 #define CHIPC_SFLASH_AT_BUF1_LOAD 0x0253 574 #define CHIPC_SFLASH_AT_BUF2_LOAD 0x0255 575 #define CHIPC_SFLASH_AT_BUF1_COMPARE 0x0260 576 #define CHIPC_SFLASH_AT_BUF2_COMPARE 0x0261 577 #define CHIPC_SFLASH_AT_BUF1_REPROGRAM 0x0258 578 #define CHIPC_SFLASH_AT_BUF2_REPROGRAM 0x0259 579 580 /* Status register bits for Atmel flashes */ 581 #define CHIPC_SFLASH_AT_READY 0x80 582 #define CHIPC_SFLASH_AT_MISMATCH 0x40 583 #define CHIPC_SFLASH_AT_ID_MASK 0x38 584 #define CHIPC_SFLASH_AT_ID_SHIFT 3 585 586 /* 587 * These are the UART port assignments, expressed as offsets from the base 588 * register. These assignments should hold for any serial port based on 589 * a 8250, 16450, or 16550(A). 590 */ 591 592 #define CHIPC_UART_RX 0 /* In: Receive buffer (DLAB=0) */ 593 #define CHIPC_UART_TX 0 /* Out: Transmit buffer (DLAB=0) */ 594 #define CHIPC_UART_DLL 0 /* Out: Divisor Latch Low (DLAB=1) */ 595 #define CHIPC_UART_IER 1 /* In/Out: Interrupt Enable Register (DLAB=0) */ 596 #define CHIPC_UART_DLM 1 /* Out: Divisor Latch High (DLAB=1) */ 597 #define CHIPC_UART_IIR 2 /* In: Interrupt Identity Register */ 598 #define CHIPC_UART_FCR 2 /* Out: FIFO Control Register */ 599 #define CHIPC_UART_LCR 3 /* Out: Line Control Register */ 600 #define CHIPC_UART_MCR 4 /* Out: Modem Control Register */ 601 #define CHIPC_UART_LSR 5 /* In: Line Status Register */ 602 #define CHIPC_UART_MSR 6 /* In: Modem Status Register */ 603 #define CHIPC_UART_SCR 7 /* I/O: Scratch Register */ 604 #define CHIPC_UART_LCR_DLAB 0x80 /* Divisor latch access bit */ 605 #define CHIPC_UART_LCR_WLEN8 0x03 /* Word length: 8 bits */ 606 #define CHIPC_UART_MCR_OUT2 0x08 /* MCR GPIO out 2 */ 607 #define CHIPC_UART_MCR_LOOP 0x10 /* Enable loopback test mode */ 608 #define CHIPC_UART_LSR_RX_FIFO 0x80 /* Receive FIFO error */ 609 #define CHIPC_UART_LSR_TDHR 0x40 /* Data-hold-register empty */ 610 #define CHIPC_UART_LSR_THRE 0x20 /* Transmit-hold-register empty */ 611 #define CHIPC_UART_LSR_BREAK 0x10 /* Break interrupt */ 612 #define CHIPC_UART_LSR_FRAMING 0x08 /* Framing error */ 613 #define CHIPC_UART_LSR_PARITY 0x04 /* Parity error */ 614 #define CHIPC_UART_LSR_OVERRUN 0x02 /* Overrun error */ 615 #define CHIPC_UART_LSR_RXRDY 0x01 /* Receiver ready */ 616 #define CHIPC_UART_FCR_FIFO_ENABLE 1 /* FIFO control register bit controlling FIFO enable/disable */ 617 618 /* Interrupt Identity Register (IIR) bits */ 619 #define CHIPC_UART_IIR_FIFO_MASK 0xc0 /* IIR FIFO disable/enabled mask */ 620 #define CHIPC_UART_IIR_INT_MASK 0xf /* IIR interrupt ID source */ 621 #define CHIPC_UART_IIR_MDM_CHG 0x0 /* Modem status changed */ 622 #define CHIPC_UART_IIR_NOINT 0x1 /* No interrupt pending */ 623 #define CHIPC_UART_IIR_THRE 0x2 /* THR empty */ 624 #define CHIPC_UART_IIR_RCVD_DATA 0x4 /* Received data available */ 625 #define CHIPC_UART_IIR_RCVR_STATUS 0x6 /* Receiver status */ 626 #define CHIPC_UART_IIR_CHAR_TIME 0xc /* Character time */ 627 628 /* Interrupt Enable Register (IER) bits */ 629 #define CHIPC_UART_IER_EDSSI 8 /* enable modem status interrupt */ 630 #define CHIPC_UART_IER_ELSI 4 /* enable receiver line status interrupt */ 631 #define CHIPC_UART_IER_ETBEI 2 /* enable transmitter holding register empty interrupt */ 632 #define CHIPC_UART_IER_ERBFI 1 /* enable data available interrupt */ 633 634 /* pmustatus */ 635 #define CHIPC_PST_EXTLPOAVAIL 0x0100 636 #define CHIPC_PST_WDRESET 0x0080 637 #define CHIPC_PST_INTPEND 0x0040 638 #define CHIPC_PST_SBCLKST 0x0030 639 #define CHIPC_PST_SBCLKST_ILP 0x0010 640 #define CHIPC_PST_SBCLKST_ALP 0x0020 641 #define CHIPC_PST_SBCLKST_HT 0x0030 642 #define CHIPC_PST_ALPAVAIL 0x0008 643 #define CHIPC_PST_HTAVAIL 0x0004 644 #define CHIPC_PST_RESINIT 0x0003 645 646 /* pmucapabilities */ 647 #define CHIPC_PCAP_REV_MASK 0x000000ff 648 #define CHIPC_PCAP_RC_MASK 0x00001f00 649 #define CHIPC_PCAP_RC_SHIFT 8 650 #define CHIPC_PCAP_TC_MASK 0x0001e000 651 #define CHIPC_PCAP_TC_SHIFT 13 652 #define CHIPC_PCAP_PC_MASK 0x001e0000 653 #define CHIPC_PCAP_PC_SHIFT 17 654 #define CHIPC_PCAP_VC_MASK 0x01e00000 655 #define CHIPC_PCAP_VC_SHIFT 21 656 #define CHIPC_PCAP_CC_MASK 0x1e000000 657 #define CHIPC_PCAP_CC_SHIFT 25 658 #define CHIPC_PCAP5_PC_MASK 0x003e0000 /* PMU corerev >= 5 */ 659 #define CHIPC_PCAP5_PC_SHIFT 17 660 #define CHIPC_PCAP5_VC_MASK 0x07c00000 661 #define CHIPC_PCAP5_VC_SHIFT 22 662 #define CHIPC_PCAP5_CC_MASK 0xf8000000 663 #define CHIPC_PCAP5_CC_SHIFT 27 664 665 /* PMU Resource Request Timer registers */ 666 /* This is based on PmuRev0 */ 667 #define CHIPC_PRRT_TIME_MASK 0x03ff 668 #define CHIPC_PRRT_INTEN 0x0400 669 #define CHIPC_PRRT_REQ_ACTIVE 0x0800 670 #define CHIPC_PRRT_ALP_REQ 0x1000 671 #define CHIPC_PRRT_HT_REQ 0x2000 672 673 /* PMU resource bit position */ 674 #define CHIPC_PMURES_BIT(bit) (1 << (bit)) 675 676 /* PMU resource number limit */ 677 #define CHIPC_PMURES_MAX_RESNUM 30 678 679 /* PMU chip control0 register */ 680 #define CHIPC_PMU_CHIPCTL0 0 681 682 /* PMU chip control1 register */ 683 #define CHIPC_PMU_CHIPCTL1 1 684 #define CHIPC_PMU_CC1_RXC_DLL_BYPASS 0x00010000 685 686 #define CHIPC_PMU_CC1_IF_TYPE_MASK 0x00000030 687 #define CHIPC_PMU_CC1_IF_TYPE_RMII 0x00000000 688 #define CHIPC_PMU_CC1_IF_TYPE_MII 0x00000010 689 #define CHIPC_PMU_CC1_IF_TYPE_RGMII 0x00000020 690 691 #define CHIPC_PMU_CC1_SW_TYPE_MASK 0x000000c0 692 #define CHIPC_PMU_CC1_SW_TYPE_EPHY 0x00000000 693 #define CHIPC_PMU_CC1_SW_TYPE_EPHYMII 0x00000040 694 #define CHIPC_PMU_CC1_SW_TYPE_EPHYRMII 0x00000080 695 #define CHIPC_PMU_CC1_SW_TYPE_RGMII 0x000000c0 696 697 /* PMU corerev and chip specific PLL controls. 698 * PMU<rev>_PLL<num>_XX where <rev> is PMU corerev and <num> is an arbitrary number 699 * to differentiate different PLLs controlled by the same PMU rev. 700 */ 701 /* pllcontrol registers */ 702 /* PDIV, div_phy, div_arm, div_adc, dith_sel, ioff, kpd_scale, lsb_sel, mash_sel, lf_c & lf_r */ 703 #define CHIPC_PMU0_PLL0_PLLCTL0 0 704 #define CHIPC_PMU0_PLL0_PC0_PDIV_MASK 1 705 #define CHIPC_PMU0_PLL0_PC0_PDIV_FREQ 25000 706 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_MASK 0x00000038 707 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_SHIFT 3 708 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_BASE 8 709 710 /* PC0_DIV_ARM for PLLOUT_ARM */ 711 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_110MHZ 0 712 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_97_7MHZ 1 713 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_88MHZ 2 714 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_80MHZ 3 /* Default */ 715 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_73_3MHZ 4 716 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_67_7MHZ 5 717 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_62_9MHZ 6 718 #define CHIPC_PMU0_PLL0_PC0_DIV_ARM_58_6MHZ 7 719 720 /* Wildcard base, stop_mod, en_lf_tp, en_cal & lf_r2 */ 721 #define CHIPC_PMU0_PLL0_PLLCTL1 1 722 #define CHIPC_PMU0_PLL0_PC1_WILD_INT_MASK 0xf0000000 723 #define CHIPC_PMU0_PLL0_PC1_WILD_INT_SHIFT 28 724 #define CHIPC_PMU0_PLL0_PC1_WILD_FRAC_MASK 0x0fffff00 725 #define CHIPC_PMU0_PLL0_PC1_WILD_FRAC_SHIFT 8 726 #define CHIPC_PMU0_PLL0_PC1_STOP_MOD 0x00000040 727 728 /* Wildcard base, vco_calvar, vco_swc, vco_var_selref, vso_ical & vco_sel_avdd */ 729 #define CHIPC_PMU0_PLL0_PLLCTL2 2 730 #define CHIPC_PMU0_PLL0_PC2_WILD_INT_MASK 0xf 731 #define CHIPC_PMU0_PLL0_PC2_WILD_INT_SHIFT 4 732 733 /* pllcontrol registers */ 734 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 735 #define CHIPC_PMU1_PLL0_PLLCTL0 0 736 #define CHIPC_PMU1_PLL0_PC0_P1DIV_MASK 0x00f00000 737 #define CHIPC_PMU1_PLL0_PC0_P1DIV_SHIFT 20 738 #define CHIPC_PMU1_PLL0_PC0_P2DIV_MASK 0x0f000000 739 #define CHIPC_PMU1_PLL0_PC0_P2DIV_SHIFT 24 740 741 /* m<x>div */ 742 #define CHIPC_PMU1_PLL0_PLLCTL1 1 743 #define CHIPC_PMU1_PLL0_PC1_M1DIV_MASK 0x000000ff 744 #define CHIPC_PMU1_PLL0_PC1_M1DIV_SHIFT 0 745 #define CHIPC_PMU1_PLL0_PC1_M2DIV_MASK 0x0000ff00 746 #define CHIPC_PMU1_PLL0_PC1_M2DIV_SHIFT 8 747 #define CHIPC_PMU1_PLL0_PC1_M3DIV_MASK 0x00ff0000 748 #define CHIPC_PMU1_PLL0_PC1_M3DIV_SHIFT 16 749 #define CHIPC_PMU1_PLL0_PC1_M4DIV_MASK 0xff000000 750 #define CHIPC_PMU1_PLL0_PC1_M4DIV_SHIFT 24 751 752 #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT 8 753 #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_MASK (0xFF << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 754 #define CHIPC_DOT11MAC_880MHZ_CLK_DIVISOR_VAL (0xE << DOT11MAC_880MHZ_CLK_DIVISOR_SHIFT) 755 756 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 757 #define CHIPC_PMU1_PLL0_PLLCTL2 2 758 #define CHIPC_PMU1_PLL0_PC2_M5DIV_MASK 0x000000ff 759 #define CHIPC_PMU1_PLL0_PC2_M5DIV_SHIFT 0 760 #define CHIPC_PMU1_PLL0_PC2_M6DIV_MASK 0x0000ff00 761 #define CHIPC_PMU1_PLL0_PC2_M6DIV_SHIFT 8 762 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASK 0x000e0000 763 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_SHIFT 17 764 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MASH 1 765 #define CHIPC_PMU1_PLL0_PC2_NDIV_MODE_MFB 2 /* recommended for 4319 */ 766 #define CHIPC_PMU1_PLL0_PC2_NDIV_INT_MASK 0x1ff00000 767 #define CHIPC_PMU1_PLL0_PC2_NDIV_INT_SHIFT 20 768 769 /* ndiv_frac */ 770 #define CHIPC_PMU1_PLL0_PLLCTL3 3 771 #define CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_MASK 0x00ffffff 772 #define CHIPC_PMU1_PLL0_PC3_NDIV_FRAC_SHIFT 0 773 774 /* pll_ctrl */ 775 #define CHIPC_PMU1_PLL0_PLLCTL4 4 776 777 /* pll_ctrl, vco_rng, clkdrive_ch<x> */ 778 #define CHIPC_PMU1_PLL0_PLLCTL5 5 779 #define CHIPC_PMU1_PLL0_PC5_CLK_DRV_MASK 0xffffff00 780 #define CHIPC_PMU1_PLL0_PC5_CLK_DRV_SHIFT 8 781 782 /* PMU rev 2 control words */ 783 #define CHIPC_PMU2_PHY_PLL_PLLCTL 4 784 #define CHIPC_PMU2_SI_PLL_PLLCTL 10 785 786 /* PMU rev 2 */ 787 /* pllcontrol registers */ 788 /* ndiv_pwrdn, pwrdn_ch<x>, refcomp_pwrdn, dly_ch<x>, p1div, p2div, _bypass_sdmod */ 789 #define CHIPC_PMU2_PLL_PLLCTL0 0 790 #define CHIPC_PMU2_PLL_PC0_P1DIV_MASK 0x00f00000 791 #define CHIPC_PMU2_PLL_PC0_P1DIV_SHIFT 20 792 #define CHIPC_PMU2_PLL_PC0_P2DIV_MASK 0x0f000000 793 #define CHIPC_PMU2_PLL_PC0_P2DIV_SHIFT 24 794 795 /* m<x>div */ 796 #define CHIPC_PMU2_PLL_PLLCTL1 1 797 #define CHIPC_PMU2_PLL_PC1_M1DIV_MASK 0x000000ff 798 #define CHIPC_PMU2_PLL_PC1_M1DIV_SHIFT 0 799 #define CHIPC_PMU2_PLL_PC1_M2DIV_MASK 0x0000ff00 800 #define CHIPC_PMU2_PLL_PC1_M2DIV_SHIFT 8 801 #define CHIPC_PMU2_PLL_PC1_M3DIV_MASK 0x00ff0000 802 #define CHIPC_PMU2_PLL_PC1_M3DIV_SHIFT 16 803 #define CHIPC_PMU2_PLL_PC1_M4DIV_MASK 0xff000000 804 #define CHIPC_PMU2_PLL_PC1_M4DIV_SHIFT 24 805 806 /* m<x>div, ndiv_dither_mfb, ndiv_mode, ndiv_int */ 807 #define CHIPC_PMU2_PLL_PLLCTL2 2 808 #define CHIPC_PMU2_PLL_PC2_M5DIV_MASK 0x000000ff 809 #define CHIPC_PMU2_PLL_PC2_M5DIV_SHIFT 0 810 #define CHIPC_PMU2_PLL_PC2_M6DIV_MASK 0x0000ff00 811 #define CHIPC_PMU2_PLL_PC2_M6DIV_SHIFT 8 812 #define CHIPC_PMU2_PLL_PC2_NDIV_MODE_MASK 0x000e0000 813 #define CHIPC_PMU2_PLL_PC2_NDIV_MODE_SHIFT 17 814 #define CHIPC_PMU2_PLL_PC2_NDIV_INT_MASK 0x1ff00000 815 #define CHIPC_PMU2_PLL_PC2_NDIV_INT_SHIFT 20 816 817 /* ndiv_frac */ 818 #define CHIPC_PMU2_PLL_PLLCTL3 3 819 #define CHIPC_PMU2_PLL_PC3_NDIV_FRAC_MASK 0x00ffffff 820 #define CHIPC_PMU2_PLL_PC3_NDIV_FRAC_SHIFT 0 821 822 /* pll_ctrl */ 823 #define CHIPC_PMU2_PLL_PLLCTL4 4 824 825 /* pll_ctrl, vco_rng, clkdrive_ch<x> */ 826 #define CHIPC_PMU2_PLL_PLLCTL5 5 827 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_MASK 0x00000f00 828 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH1_SHIFT 8 829 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_MASK 0x0000f000 830 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH2_SHIFT 12 831 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_MASK 0x000f0000 832 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH3_SHIFT 16 833 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_MASK 0x00f00000 834 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH4_SHIFT 20 835 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_MASK 0x0f000000 836 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH5_SHIFT 24 837 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_MASK 0xf0000000 838 #define CHIPC_PMU2_PLL_PC5_CLKDRIVE_CH6_SHIFT 28 839 840 /* PMU rev 5 (& 6) */ 841 #define CHIPC_PMU5_PLL_P1P2_OFF 0 842 #define CHIPC_PMU5_PLL_P1_MASK 0x0f000000 843 #define CHIPC_PMU5_PLL_P1_SHIFT 24 844 #define CHIPC_PMU5_PLL_P2_MASK 0x00f00000 845 #define CHIPC_PMU5_PLL_P2_SHIFT 20 846 #define CHIPC_PMU5_PLL_M14_OFF 1 847 #define CHIPC_PMU5_PLL_MDIV_MASK 0x000000ff 848 #define CHIPC_PMU5_PLL_MDIV_WIDTH 8 849 #define CHIPC_PMU5_PLL_NM5_OFF 2 850 #define CHIPC_PMU5_PLL_NDIV_MASK 0xfff00000 851 #define CHIPC_PMU5_PLL_NDIV_SHIFT 20 852 #define CHIPC_PMU5_PLL_NDIV_MODE_MASK 0x000e0000 853 #define CHIPC_PMU5_PLL_NDIV_MODE_SHIFT 17 854 #define CHIPC_PMU5_PLL_FMAB_OFF 3 855 #define CHIPC_PMU5_PLL_MRAT_MASK 0xf0000000 856 #define CHIPC_PMU5_PLL_MRAT_SHIFT 28 857 #define CHIPC_PMU5_PLL_ABRAT_MASK 0x08000000 858 #define CHIPC_PMU5_PLL_ABRAT_SHIFT 27 859 #define CHIPC_PMU5_PLL_FDIV_MASK 0x07ffffff 860 #define CHIPC_PMU5_PLL_PLLCTL_OFF 4 861 #define CHIPC_PMU5_PLL_PCHI_OFF 5 862 #define CHIPC_PMU5_PLL_PCHI_MASK 0x0000003f 863 864 /* pmu XtalFreqRatio */ 865 #define CHIPC_PMU_XTALFREQ_REG_ILPCTR_MASK 0x00001FFF 866 #define CHIPC_PMU_XTALFREQ_REG_MEASURE_MASK 0x80000000 867 #define CHIPC_PMU_XTALFREQ_REG_MEASURE_SHIFT 31 868 869 /* Divider allocation in 4716/47162/5356/5357 */ 870 #define CHIPC_PMU5_MAINPLL_CPU 1 871 #define CHIPC_PMU5_MAINPLL_MEM 2 872 #define CHIPC_PMU5_MAINPLL_SI 3 873 874 #define CHIPC_PMU7_PLL_PLLCTL7 7 875 #define CHIPC_PMU7_PLL_PLLCTL8 8 876 #define CHIPC_PMU7_PLL_PLLCTL11 11 877 878 /* PLL usage in 4716/47162 */ 879 #define CHIPC_PMU4716_MAINPLL_PLL0 12 880 881 /* PLL usage in 5356/5357 */ 882 #define CHIPC_PMU5356_MAINPLL_PLL0 0 883 #define CHIPC_PMU5357_MAINPLL_PLL0 0 884 885 /* 4716/47162 resources */ 886 #define CHIPC_RES4716_PROC_PLL_ON 0x00000040 887 #define CHIPC_RES4716_PROC_HT_AVAIL 0x00000080 888 889 /* 4716/4717/4718 Chip specific ChipControl register bits */ 890 #define CHIPC_CCTRL471X_I2S_PINS_ENABLE 0x0080 /* I2S pins off by default, shared with pflash */ 891 892 /* 5354 resources */ 893 #define CHIPC_RES5354_EXT_SWITCHER_PWM 0 /* 0x00001 */ 894 #define CHIPC_RES5354_BB_SWITCHER_PWM 1 /* 0x00002 */ 895 #define CHIPC_RES5354_BB_SWITCHER_BURST 2 /* 0x00004 */ 896 #define CHIPC_RES5354_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ 897 #define CHIPC_RES5354_ILP_REQUEST 4 /* 0x00010 */ 898 #define CHIPC_RES5354_RADIO_SWITCHER_PWM 5 /* 0x00020 */ 899 #define CHIPC_RES5354_RADIO_SWITCHER_BURST 6 /* 0x00040 */ 900 #define CHIPC_RES5354_ROM_SWITCH 7 /* 0x00080 */ 901 #define CHIPC_RES5354_PA_REF_LDO 8 /* 0x00100 */ 902 #define CHIPC_RES5354_RADIO_LDO 9 /* 0x00200 */ 903 #define CHIPC_RES5354_AFE_LDO 10 /* 0x00400 */ 904 #define CHIPC_RES5354_PLL_LDO 11 /* 0x00800 */ 905 #define CHIPC_RES5354_BG_FILTBYP 12 /* 0x01000 */ 906 #define CHIPC_RES5354_TX_FILTBYP 13 /* 0x02000 */ 907 #define CHIPC_RES5354_RX_FILTBYP 14 /* 0x04000 */ 908 #define CHIPC_RES5354_XTAL_PU 15 /* 0x08000 */ 909 #define CHIPC_RES5354_XTAL_EN 16 /* 0x10000 */ 910 #define CHIPC_RES5354_BB_PLL_FILTBYP 17 /* 0x20000 */ 911 #define CHIPC_RES5354_RF_PLL_FILTBYP 18 /* 0x40000 */ 912 #define CHIPC_RES5354_BB_PLL_PU 19 /* 0x80000 */ 913 914 /* 5357 Chip specific ChipControl register bits */ 915 #define CHIPC_CCTRL5357_EXTPA (1<<14) /* extPA in ChipControl 1, bit 14 */ 916 #define CHIPC_CCTRL5357_ANT_MUX_2o3 (1<<15) /* 2o3 in ChipControl 1, bit 15 */ 917 918 /* 4328 resources */ 919 #define CHIPC_RES4328_EXT_SWITCHER_PWM 0 /* 0x00001 */ 920 #define CHIPC_RES4328_BB_SWITCHER_PWM 1 /* 0x00002 */ 921 #define CHIPC_RES4328_BB_SWITCHER_BURST 2 /* 0x00004 */ 922 #define CHIPC_RES4328_BB_EXT_SWITCHER_BURST 3 /* 0x00008 */ 923 #define CHIPC_RES4328_ILP_REQUEST 4 /* 0x00010 */ 924 #define CHIPC_RES4328_RADIO_SWITCHER_PWM 5 /* 0x00020 */ 925 #define CHIPC_RES4328_RADIO_SWITCHER_BURST 6 /* 0x00040 */ 926 #define CHIPC_RES4328_ROM_SWITCH 7 /* 0x00080 */ 927 #define CHIPC_RES4328_PA_REF_LDO 8 /* 0x00100 */ 928 #define CHIPC_RES4328_RADIO_LDO 9 /* 0x00200 */ 929 #define CHIPC_RES4328_AFE_LDO 10 /* 0x00400 */ 930 #define CHIPC_RES4328_PLL_LDO 11 /* 0x00800 */ 931 #define CHIPC_RES4328_BG_FILTBYP 12 /* 0x01000 */ 932 #define CHIPC_RES4328_TX_FILTBYP 13 /* 0x02000 */ 933 #define CHIPC_RES4328_RX_FILTBYP 14 /* 0x04000 */ 934 #define CHIPC_RES4328_XTAL_PU 15 /* 0x08000 */ 935 #define CHIPC_RES4328_XTAL_EN 16 /* 0x10000 */ 936 #define CHIPC_RES4328_BB_PLL_FILTBYP 17 /* 0x20000 */ 937 #define CHIPC_RES4328_RF_PLL_FILTBYP 18 /* 0x40000 */ 938 #define CHIPC_RES4328_BB_PLL_PU 19 /* 0x80000 */ 939 940 /* 4325 A0/A1 resources */ 941 #define CHIPC_RES4325_BUCK_BOOST_BURST 0 /* 0x00000001 */ 942 #define CHIPC_RES4325_CBUCK_BURST 1 /* 0x00000002 */ 943 #define CHIPC_RES4325_CBUCK_PWM 2 /* 0x00000004 */ 944 #define CHIPC_RES4325_CLDO_CBUCK_BURST 3 /* 0x00000008 */ 945 #define CHIPC_RES4325_CLDO_CBUCK_PWM 4 /* 0x00000010 */ 946 #define CHIPC_RES4325_BUCK_BOOST_PWM 5 /* 0x00000020 */ 947 #define CHIPC_RES4325_ILP_REQUEST 6 /* 0x00000040 */ 948 #define CHIPC_RES4325_ABUCK_BURST 7 /* 0x00000080 */ 949 #define CHIPC_RES4325_ABUCK_PWM 8 /* 0x00000100 */ 950 #define CHIPC_RES4325_LNLDO1_PU 9 /* 0x00000200 */ 951 #define CHIPC_RES4325_OTP_PU 10 /* 0x00000400 */ 952 #define CHIPC_RES4325_LNLDO3_PU 11 /* 0x00000800 */ 953 #define CHIPC_RES4325_LNLDO4_PU 12 /* 0x00001000 */ 954 #define CHIPC_RES4325_XTAL_PU 13 /* 0x00002000 */ 955 #define CHIPC_RES4325_ALP_AVAIL 14 /* 0x00004000 */ 956 #define CHIPC_RES4325_RX_PWRSW_PU 15 /* 0x00008000 */ 957 #define CHIPC_RES4325_TX_PWRSW_PU 16 /* 0x00010000 */ 958 #define CHIPC_RES4325_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 959 #define CHIPC_RES4325_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 960 #define CHIPC_RES4325_AFE_PWRSW_PU 19 /* 0x00080000 */ 961 #define CHIPC_RES4325_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 962 #define CHIPC_RES4325_HT_AVAIL 21 /* 0x00200000 */ 963 964 /* 4325 B0/C0 resources */ 965 #define CHIPC_RES4325B0_CBUCK_LPOM 1 /* 0x00000002 */ 966 #define CHIPC_RES4325B0_CBUCK_BURST 2 /* 0x00000004 */ 967 #define CHIPC_RES4325B0_CBUCK_PWM 3 /* 0x00000008 */ 968 #define CHIPC_RES4325B0_CLDO_PU 4 /* 0x00000010 */ 969 970 /* 4325 C1 resources */ 971 #define CHIPC_RES4325C1_LNLDO2_PU 12 /* 0x00001000 */ 972 973 /* 4325 chip-specific ChipStatus register bits */ 974 #define CHIPC_CST4325_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK 975 #define CHIPC_CST4325_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 976 #define CHIPC_CST4325_SDIO_USB_MODE_MASK 0x00000004 977 #define CHIPC_CST4325_SDIO_USB_MODE_SHIFT 2 978 #define CHIPC_CST4325_RCAL_VALID_MASK 0x00000008 979 #define CHIPC_CST4325_RCAL_VALID_SHIFT 3 980 #define CHIPC_CST4325_RCAL_VALUE_MASK 0x000001f0 981 #define CHIPC_CST4325_RCAL_VALUE_SHIFT 4 982 #define CHIPC_CST4325_PMUTOP_2B_MASK 0x00000200 /* 1 for 2b, 0 for to 2a */ 983 #define CHIPC_CST4325_PMUTOP_2B_SHIFT 9 984 985 #define CHIPC_RES4329_RESERVED0 0 /* 0x00000001 */ 986 #define CHIPC_RES4329_CBUCK_LPOM 1 /* 0x00000002 */ 987 #define CHIPC_RES4329_CBUCK_BURST 2 /* 0x00000004 */ 988 #define CHIPC_RES4329_CBUCK_PWM 3 /* 0x00000008 */ 989 #define CHIPC_RES4329_CLDO_PU 4 /* 0x00000010 */ 990 #define CHIPC_RES4329_PALDO_PU 5 /* 0x00000020 */ 991 #define CHIPC_RES4329_ILP_REQUEST 6 /* 0x00000040 */ 992 #define CHIPC_RES4329_RESERVED7 7 /* 0x00000080 */ 993 #define CHIPC_RES4329_RESERVED8 8 /* 0x00000100 */ 994 #define CHIPC_RES4329_LNLDO1_PU 9 /* 0x00000200 */ 995 #define CHIPC_RES4329_OTP_PU 10 /* 0x00000400 */ 996 #define CHIPC_RES4329_RESERVED11 11 /* 0x00000800 */ 997 #define CHIPC_RES4329_LNLDO2_PU 12 /* 0x00001000 */ 998 #define CHIPC_RES4329_XTAL_PU 13 /* 0x00002000 */ 999 #define CHIPC_RES4329_ALP_AVAIL 14 /* 0x00004000 */ 1000 #define CHIPC_RES4329_RX_PWRSW_PU 15 /* 0x00008000 */ 1001 #define CHIPC_RES4329_TX_PWRSW_PU 16 /* 0x00010000 */ 1002 #define CHIPC_RES4329_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1003 #define CHIPC_RES4329_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1004 #define CHIPC_RES4329_AFE_PWRSW_PU 19 /* 0x00080000 */ 1005 #define CHIPC_RES4329_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1006 #define CHIPC_RES4329_HT_AVAIL 21 /* 0x00200000 */ 1007 1008 /* 4329 chip-specific ChipStatus register bits */ 1009 #define CHIPC_CST4329_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK 1010 #define CHIPC_CST4329_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 1011 #define CHIPC_CST4329_SPI_SDIO_MODE_MASK 0x00000004 1012 #define CHIPC_CST4329_SPI_SDIO_MODE_SHIFT 2 1013 1014 /* 4312 chip-specific ChipStatus register bits */ 1015 #define CHIPC_CST4312_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK 1016 #define CHIPC_CST4312_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 1017 1018 /* 4312 resources (all PMU chips with little memory constraint) */ 1019 #define CHIPC_RES4312_SWITCHER_BURST 0 /* 0x00000001 */ 1020 #define CHIPC_RES4312_SWITCHER_PWM 1 /* 0x00000002 */ 1021 #define CHIPC_RES4312_PA_REF_LDO 2 /* 0x00000004 */ 1022 #define CHIPC_RES4312_CORE_LDO_BURST 3 /* 0x00000008 */ 1023 #define CHIPC_RES4312_CORE_LDO_PWM 4 /* 0x00000010 */ 1024 #define CHIPC_RES4312_RADIO_LDO 5 /* 0x00000020 */ 1025 #define CHIPC_RES4312_ILP_REQUEST 6 /* 0x00000040 */ 1026 #define CHIPC_RES4312_BG_FILTBYP 7 /* 0x00000080 */ 1027 #define CHIPC_RES4312_TX_FILTBYP 8 /* 0x00000100 */ 1028 #define CHIPC_RES4312_RX_FILTBYP 9 /* 0x00000200 */ 1029 #define CHIPC_RES4312_XTAL_PU 10 /* 0x00000400 */ 1030 #define CHIPC_RES4312_ALP_AVAIL 11 /* 0x00000800 */ 1031 #define CHIPC_RES4312_BB_PLL_FILTBYP 12 /* 0x00001000 */ 1032 #define CHIPC_RES4312_RF_PLL_FILTBYP 13 /* 0x00002000 */ 1033 #define CHIPC_RES4312_HT_AVAIL 14 /* 0x00004000 */ 1034 1035 /* 4322 resources */ 1036 #define CHIPC_RES4322_RF_LDO 0 1037 #define CHIPC_RES4322_ILP_REQUEST 1 1038 #define CHIPC_RES4322_XTAL_PU 2 1039 #define CHIPC_RES4322_ALP_AVAIL 3 1040 #define CHIPC_RES4322_SI_PLL_ON 4 1041 #define CHIPC_RES4322_HT_SI_AVAIL 5 1042 #define CHIPC_RES4322_PHY_PLL_ON 6 1043 #define CHIPC_RES4322_HT_PHY_AVAIL 7 1044 #define CHIPC_RES4322_OTP_PU 8 1045 1046 /* 4322 chip-specific ChipStatus register bits */ 1047 #define CHIPC_CST4322_XTAL_FREQ_20_40MHZ 0x00000020 1048 #define CHIPC_CST4322_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK 1049 #define CHIPC_CST4322_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 1050 #define CHIPC_CST4322_PCI_OR_USB 0x00000100 1051 #define CHIPC_CST4322_BOOT_MASK 0x00000600 1052 #define CHIPC_CST4322_BOOT_SHIFT 9 1053 #define CHIPC_CST4322_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 1054 #define CHIPC_CST4322_BOOT_FROM_ROM 1 /* boot from ROM */ 1055 #define CHIPC_CST4322_BOOT_FROM_FLASH 2 /* boot from FLASH */ 1056 #define CHIPC_CST4322_BOOT_FROM_INVALID 3 1057 #define CHIPC_CST4322_ILP_DIV_EN 0x00000800 1058 #define CHIPC_CST4322_FLASH_TYPE_MASK 0x00001000 1059 #define CHIPC_CST4322_FLASH_TYPE_SHIFT 12 1060 #define CHIPC_CST4322_FLASH_TYPE_SHIFT_ST 0 /* ST serial FLASH */ 1061 #define CHIPC_CST4322_FLASH_TYPE_SHIFT_ATMEL 1 /* ATMEL flash */ 1062 #define CHIPC_CST4322_ARM_TAP_SEL 0x00002000 1063 #define CHIPC_CST4322_RES_INIT_MODE_MASK 0x0000c000 1064 #define CHIPC_CST4322_RES_INIT_MODE_SHIFT 14 1065 #define CHIPC_CST4322_RES_INIT_MODE_ILPAVAIL 0 /* resinitmode: ILP available */ 1066 #define CHIPC_CST4322_RES_INIT_MODE_ILPREQ 1 /* resinitmode: ILP request */ 1067 #define CHIPC_CST4322_RES_INIT_MODE_ALPAVAIL 2 /* resinitmode: ALP available */ 1068 #define CHIPC_CST4322_RES_INIT_MODE_HTAVAIL 3 /* resinitmode: HT available */ 1069 #define CHIPC_CST4322_PCIPLLCLK_GATING 0x00010000 1070 #define CHIPC_CST4322_CLK_SWITCH_PCI_TO_ALP 0x00020000 1071 #define CHIPC_CST4322_PCI_CARDBUS_MODE 0x00040000 1072 1073 /* 43224 chip-specific ChipControl register bits */ 1074 #define CHIPC_CCTRL43224_GPIO_TOGGLE 0x8000 1075 #define CHIPC_CCTRL_43224A0_12MA_LED_DRIVE 0x00F000F0 /* 12 mA drive strength */ 1076 #define CHIPC_CCTRL_43224B0_12MA_LED_DRIVE 0xF0 /* 12 mA drive strength for later 43224s */ 1077 1078 /* 43236 resources */ 1079 #define CHIPC_RES43236_REGULATOR 0 1080 #define CHIPC_RES43236_ILP_REQUEST 1 1081 #define CHIPC_RES43236_XTAL_PU 2 1082 #define CHIPC_RES43236_ALP_AVAIL 3 1083 #define CHIPC_RES43236_SI_PLL_ON 4 1084 #define CHIPC_RES43236_HT_SI_AVAIL 5 1085 1086 /* 43236 chip-specific ChipControl register bits */ 1087 #define CHIPC_CCTRL43236_BT_COEXIST (1<<0) /* 0 disable */ 1088 #define CHIPC_CCTRL43236_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 1089 #define CHIPC_CCTRL43236_EXT_LNA (1<<2) /* 0 disable */ 1090 #define CHIPC_CCTRL43236_ANT_MUX_2o3 (1<<3) /* 2o3 mux, chipcontrol bit 3 */ 1091 #define CHIPC_CCTRL43236_GSIO (1<<4) /* 0 disable */ 1092 1093 /* 43236 Chip specific ChipStatus register bits */ 1094 #define CHIPC_CST43236_SFLASH_MASK 0x00000040 1095 #define CHIPC_CST43236_OTP_SEL_MASK 0x00000080 1096 #define CHIPC_CST43236_OTP_SEL_SHIFT 7 1097 #define CHIPC_CST43236_HSIC_MASK 0x00000100 /* USB/HSIC */ 1098 #define CHIPC_CST43236_BP_CLK 0x00000200 /* 120/96Mbps */ 1099 #define CHIPC_CST43236_BOOT_MASK 0x00001800 1100 #define CHIPC_CST43236_BOOT_SHIFT 11 1101 #define CHIPC_CST43236_BOOT_FROM_SRAM 0 /* boot from SRAM, ARM in reset */ 1102 #define CHIPC_CST43236_BOOT_FROM_ROM 1 /* boot from ROM */ 1103 #define CHIPC_CST43236_BOOT_FROM_FLASH 2 /* boot from FLASH */ 1104 #define CHIPC_CST43236_BOOT_FROM_INVALID 3 1105 1106 /* 4331 resources */ 1107 #define CHIPC_RES4331_REGULATOR 0 1108 #define CHIPC_RES4331_ILP_REQUEST 1 1109 #define CHIPC_RES4331_XTAL_PU 2 1110 #define CHIPC_RES4331_ALP_AVAIL 3 1111 #define CHIPC_RES4331_SI_PLL_ON 4 1112 #define CHIPC_RES4331_HT_SI_AVAIL 5 1113 1114 /* 4331 chip-specific ChipControl register bits */ 1115 #define CHIPC_CCTRL4331_BT_COEXIST (1<<0) /* 0 disable */ 1116 #define CHIPC_CCTRL4331_SECI (1<<1) /* 0 SECI is disabled (JATG functional) */ 1117 #define CHIPC_CCTRL4331_EXT_LNA (1<<2) /* 0 disable */ 1118 #define CHIPC_CCTRL4331_SPROM_GPIO13_15 (1<<3) /* sprom/gpio13-15 mux */ 1119 #define CHIPC_CCTRL4331_EXTPA_EN (1<<4) /* 0 ext pa disable, 1 ext pa enabled */ 1120 #define CHIPC_CCTRL4331_GPIOCLK_ON_SPROMCS (1<<5) /* set drive out GPIO_CLK on sprom_cs pin */ 1121 #define CHIPC_CCTRL4331_PCIE_MDIO_ON_SPROMCS (1<<6) /* use sprom_cs pin as PCIE mdio interface */ 1122 #define CHIPC_CCTRL4331_EXTPA_ON_GPIO2_5 (1<<7) /* aband extpa will be at gpio2/5 and sprom_dout */ 1123 #define CHIPC_CCTRL4331_OVR_PIPEAUXCLKEN (1<<8) /* override core control on pipe_AuxClkEnable */ 1124 #define CHIPC_CCTRL4331_OVR_PIPEAUXPWRDOWN (1<<9) /* override core control on pipe_AuxPowerDown */ 1125 #define CHIPC_CCTRL4331_PCIE_AUXCLKEN (1<<10) /* pcie_auxclkenable */ 1126 #define CHIPC_CCTRL4331_PCIE_PIPE_PLLDOWN (1<<11) /* pcie_pipe_pllpowerdown */ 1127 #define CHIPC_CCTRL4331_BT_SHD0_ON_GPIO4 (1<<16) /* enable bt_shd0 at gpio4 */ 1128 #define CHIPC_CCTRL4331_BT_SHD1_ON_GPIO5 (1<<17) /* enable bt_shd1 at gpio5 */ 1129 1130 /* 4331 Chip specific ChipStatus register bits */ 1131 #define CHIPC_CST4331_XTAL_FREQ 0x00000001 /* crystal frequency 20/40Mhz */ 1132 #define CHIPC_CST4331_SPROM_PRESENT 0x00000002 1133 #define CHIPC_CST4331_OTP_PRESENT 0x00000004 1134 #define CHIPC_CST4331_LDO_RF 0x00000008 1135 #define CHIPC_CST4331_LDO_PAR 0x00000010 1136 1137 /* 4315 resources */ 1138 #define CHIPC_RES4315_CBUCK_LPOM 1 /* 0x00000002 */ 1139 #define CHIPC_RES4315_CBUCK_BURST 2 /* 0x00000004 */ 1140 #define CHIPC_RES4315_CBUCK_PWM 3 /* 0x00000008 */ 1141 #define CHIPC_RES4315_CLDO_PU 4 /* 0x00000010 */ 1142 #define CHIPC_RES4315_PALDO_PU 5 /* 0x00000020 */ 1143 #define CHIPC_RES4315_ILP_REQUEST 6 /* 0x00000040 */ 1144 #define CHIPC_RES4315_LNLDO1_PU 9 /* 0x00000200 */ 1145 #define CHIPC_RES4315_OTP_PU 10 /* 0x00000400 */ 1146 #define CHIPC_RES4315_LNLDO2_PU 12 /* 0x00001000 */ 1147 #define CHIPC_RES4315_XTAL_PU 13 /* 0x00002000 */ 1148 #define CHIPC_RES4315_ALP_AVAIL 14 /* 0x00004000 */ 1149 #define CHIPC_RES4315_RX_PWRSW_PU 15 /* 0x00008000 */ 1150 #define CHIPC_RES4315_TX_PWRSW_PU 16 /* 0x00010000 */ 1151 #define CHIPC_RES4315_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1152 #define CHIPC_RES4315_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1153 #define CHIPC_RES4315_AFE_PWRSW_PU 19 /* 0x00080000 */ 1154 #define CHIPC_RES4315_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1155 #define CHIPC_RES4315_HT_AVAIL 21 /* 0x00200000 */ 1156 1157 /* 4315 chip-specific ChipStatus register bits */ 1158 #define CHIPC_CST4315_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R22_MASK 1159 #define CHIPC_CST4315_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R22_SHIFT 1160 #define CHIPC_CST4315_SDIO_MODE 0x00000004 /* gpio [8], sdio/usb mode */ 1161 #define CHIPC_CST4315_RCAL_VALID 0x00000008 1162 #define CHIPC_CST4315_RCAL_VALUE_MASK 0x000001f0 1163 #define CHIPC_CST4315_RCAL_VALUE_SHIFT 4 1164 #define CHIPC_CST4315_PALDO_EXTPNP 0x00000200 /* PALDO is configured with external PNP */ 1165 #define CHIPC_CST4315_CBUCK_MODE_MASK 0x00000c00 1166 #define CHIPC_CST4315_CBUCK_MODE_BURST 0x00000400 1167 #define CHIPC_CST4315_CBUCK_MODE_LPBURST 0x00000c00 1168 1169 /* 4319 resources */ 1170 #define CHIPC_RES4319_CBUCK_LPOM 1 /* 0x00000002 */ 1171 #define CHIPC_RES4319_CBUCK_BURST 2 /* 0x00000004 */ 1172 #define CHIPC_RES4319_CBUCK_PWM 3 /* 0x00000008 */ 1173 #define CHIPC_RES4319_CLDO_PU 4 /* 0x00000010 */ 1174 #define CHIPC_RES4319_PALDO_PU 5 /* 0x00000020 */ 1175 #define CHIPC_RES4319_ILP_REQUEST 6 /* 0x00000040 */ 1176 #define CHIPC_RES4319_LNLDO1_PU 9 /* 0x00000200 */ 1177 #define CHIPC_RES4319_OTP_PU 10 /* 0x00000400 */ 1178 #define CHIPC_RES4319_LNLDO2_PU 12 /* 0x00001000 */ 1179 #define CHIPC_RES4319_XTAL_PU 13 /* 0x00002000 */ 1180 #define CHIPC_RES4319_ALP_AVAIL 14 /* 0x00004000 */ 1181 #define CHIPC_RES4319_RX_PWRSW_PU 15 /* 0x00008000 */ 1182 #define CHIPC_RES4319_TX_PWRSW_PU 16 /* 0x00010000 */ 1183 #define CHIPC_RES4319_RFPLL_PWRSW_PU 17 /* 0x00020000 */ 1184 #define CHIPC_RES4319_LOGEN_PWRSW_PU 18 /* 0x00040000 */ 1185 #define CHIPC_RES4319_AFE_PWRSW_PU 19 /* 0x00080000 */ 1186 #define CHIPC_RES4319_BBPLL_PWRSW_PU 20 /* 0x00100000 */ 1187 #define CHIPC_RES4319_HT_AVAIL 21 /* 0x00200000 */ 1188 1189 /* 4319 chip-specific ChipStatus register bits */ 1190 #define CHIPC_CST4319_SPI_CPULESSUSB 0x00000001 1191 #define CHIPC_CST4319_SPI_CLK_POL 0x00000002 1192 #define CHIPC_CST4319_SPI_CLK_PH 0x00000008 1193 #define CHIPC_CST4319_SPROM_OTP_SEL_MASK CHIPC_CST_SPROM_OTP_SEL_R23_MASK /* gpio [7:6], SDIO CIS selection */ 1194 #define CHIPC_CST4319_SPROM_OTP_SEL_SHIFT CHIPC_CST_SPROM_OTP_SEL_R23_SHIFT 1195 #define CHIPC_CST4319_SDIO_USB_MODE 0x00000100 /* gpio [8], sdio/usb mode */ 1196 #define CHIPC_CST4319_REMAP_SEL_MASK 0x00000600 1197 #define CHIPC_CST4319_ILPDIV_EN 0x00000800 1198 #define CHIPC_CST4319_XTAL_PD_POL 0x00001000 1199 #define CHIPC_CST4319_LPO_SEL 0x00002000 1200 #define CHIPC_CST4319_RES_INIT_MODE 0x0000c000 1201 #define CHIPC_CST4319_PALDO_EXTPNP 0x00010000 /* PALDO is configured with external PNP */ 1202 #define CHIPC_CST4319_CBUCK_MODE_MASK 0x00060000 1203 #define CHIPC_CST4319_CBUCK_MODE_BURST 0x00020000 1204 #define CHIPC_CST4319_CBUCK_MODE_LPBURST 0x00060000 1205 #define CHIPC_CST4319_RCAL_VALID 0x01000000 1206 #define CHIPC_CST4319_RCAL_VALUE_MASK 0x3e000000 1207 #define CHIPC_CST4319_RCAL_VALUE_SHIFT 25 1208 1209 #define CHIPC_PMU1_PLL0_CHIPCTL0 0 1210 #define CHIPC_PMU1_PLL0_CHIPCTL1 1 1211 #define CHIPC_PMU1_PLL0_CHIPCTL2 2 1212 #define CHIPC_CCTL_4319USB_XTAL_SEL_MASK 0x00180000 1213 #define CHIPC_CCTL_4319USB_XTAL_SEL_SHIFT 19 1214 #define CHIPC_CCTL_4319USB_48MHZ_PLL_SEL 1 1215 #define CHIPC_CCTL_4319USB_24MHZ_PLL_SEL 2 1216 1217 /* PMU resources for 4336 */ 1218 #define CHIPC_RES4336_CBUCK_LPOM 0 1219 #define CHIPC_RES4336_CBUCK_BURST 1 1220 #define CHIPC_RES4336_CBUCK_LP_PWM 2 1221 #define CHIPC_RES4336_CBUCK_PWM 3 1222 #define CHIPC_RES4336_CLDO_PU 4 1223 #define CHIPC_RES4336_DIS_INT_RESET_PD 5 1224 #define CHIPC_RES4336_ILP_REQUEST 6 1225 #define CHIPC_RES4336_LNLDO_PU 7 1226 #define CHIPC_RES4336_LDO3P3_PU 8 1227 #define CHIPC_RES4336_OTP_PU 9 1228 #define CHIPC_RES4336_XTAL_PU 10 1229 #define CHIPC_RES4336_ALP_AVAIL 11 1230 #define CHIPC_RES4336_RADIO_PU 12 1231 #define CHIPC_RES4336_BG_PU 13 1232 #define CHIPC_RES4336_VREG1p4_PU_PU 14 1233 #define CHIPC_RES4336_AFE_PWRSW_PU 15 1234 #define CHIPC_RES4336_RX_PWRSW_PU 16 1235 #define CHIPC_RES4336_TX_PWRSW_PU 17 1236 #define CHIPC_RES4336_BB_PWRSW_PU 18 1237 #define CHIPC_RES4336_SYNTH_PWRSW_PU 19 1238 #define CHIPC_RES4336_MISC_PWRSW_PU 20 1239 #define CHIPC_RES4336_LOGEN_PWRSW_PU 21 1240 #define CHIPC_RES4336_BBPLL_PWRSW_PU 22 1241 #define CHIPC_RES4336_MACPHY_CLKAVAIL 23 1242 #define CHIPC_RES4336_HT_AVAIL 24 1243 #define CHIPC_RES4336_RSVD 25 1244 1245 /* 4336 chip-specific ChipStatus register bits */ 1246 #define CHIPC_CST4336_SPI_MODE_MASK 0x00000001 1247 #define CHIPC_CST4336_SPROM_PRESENT 0x00000002 1248 #define CHIPC_CST4336_OTP_PRESENT 0x00000004 1249 #define CHIPC_CST4336_ARMREMAP_0 0x00000008 1250 #define CHIPC_CST4336_ILPDIV_EN_MASK 0x00000010 1251 #define CHIPC_CST4336_ILPDIV_EN_SHIFT 4 1252 #define CHIPC_CST4336_XTAL_PD_POL_MASK 0x00000020 1253 #define CHIPC_CST4336_XTAL_PD_POL_SHIFT 5 1254 #define CHIPC_CST4336_LPO_SEL_MASK 0x00000040 1255 #define CHIPC_CST4336_LPO_SEL_SHIFT 6 1256 #define CHIPC_CST4336_RES_INIT_MODE_MASK 0x00000180 1257 #define CHIPC_CST4336_RES_INIT_MODE_SHIFT 7 1258 #define CHIPC_CST4336_CBUCK_MODE_MASK 0x00000600 1259 #define CHIPC_CST4336_CBUCK_MODE_SHIFT 9 1260 1261 /* 4330 resources */ 1262 #define CHIPC_RES4330_CBUCK_LPOM 0 1263 #define CHIPC_RES4330_CBUCK_BURST 1 1264 #define CHIPC_RES4330_CBUCK_LP_PWM 2 1265 #define CHIPC_RES4330_CBUCK_PWM 3 1266 #define CHIPC_RES4330_CLDO_PU 4 1267 #define CHIPC_RES4330_DIS_INT_RESET_PD 5 1268 #define CHIPC_RES4330_ILP_REQUEST 6 1269 #define CHIPC_RES4330_LNLDO_PU 7 1270 #define CHIPC_RES4330_LDO3P3_PU 8 1271 #define CHIPC_RES4330_OTP_PU 9 1272 #define CHIPC_RES4330_XTAL_PU 10 1273 #define CHIPC_RES4330_ALP_AVAIL 11 1274 #define CHIPC_RES4330_RADIO_PU 12 1275 #define CHIPC_RES4330_BG_PU 13 1276 #define CHIPC_RES4330_VREG1p4_PU_PU 14 1277 #define CHIPC_RES4330_AFE_PWRSW_PU 15 1278 #define CHIPC_RES4330_RX_PWRSW_PU 16 1279 #define CHIPC_RES4330_TX_PWRSW_PU 17 1280 #define CHIPC_RES4330_BB_PWRSW_PU 18 1281 #define CHIPC_RES4330_SYNTH_PWRSW_PU 19 1282 #define CHIPC_RES4330_MISC_PWRSW_PU 20 1283 #define CHIPC_RES4330_LOGEN_PWRSW_PU 21 1284 #define CHIPC_RES4330_BBPLL_PWRSW_PU 22 1285 #define CHIPC_RES4330_MACPHY_CLKAVAIL 23 1286 #define CHIPC_RES4330_HT_AVAIL 24 1287 #define CHIPC_RES4330_5gRX_PWRSW_PU 25 1288 #define CHIPC_RES4330_5gTX_PWRSW_PU 26 1289 #define CHIPC_RES4330_5g_LOGEN_PWRSW_PU 27 1290 1291 /* 4330 chip-specific ChipStatus register bits */ 1292 #define CHIPC_CST4330_CHIPMODE_SDIOD(cs) (((cs) & 0x7) < 6) /* SDIO || gSPI */ 1293 #define CHIPC_CST4330_CHIPMODE_USB20D(cs) (((cs) & 0x7) >= 6) /* USB || USBDA */ 1294 #define CHIPC_CST4330_CHIPMODE_SDIO(cs) (((cs) & 0x4) == 0) /* SDIO */ 1295 #define CHIPC_CST4330_CHIPMODE_GSPI(cs) (((cs) & 0x6) == 4) /* gSPI */ 1296 #define CHIPC_CST4330_CHIPMODE_USB(cs) (((cs) & 0x7) == 6) /* USB packet-oriented */ 1297 #define CHIPC_CST4330_CHIPMODE_USBDA(cs) (((cs) & 0x7) == 7) /* USB Direct Access */ 1298 #define CHIPC_CST4330_OTP_PRESENT 0x00000010 1299 #define CHIPC_CST4330_LPO_AUTODET_EN 0x00000020 1300 #define CHIPC_CST4330_ARMREMAP_0 0x00000040 1301 #define CHIPC_CST4330_SPROM_PRESENT 0x00000080 /* takes priority over OTP if both set */ 1302 #define CHIPC_CST4330_ILPDIV_EN 0x00000100 1303 #define CHIPC_CST4330_LPO_SEL 0x00000200 1304 #define CHIPC_CST4330_RES_INIT_MODE_SHIFT 10 1305 #define CHIPC_CST4330_RES_INIT_MODE_MASK 0x00000c00 1306 #define CHIPC_CST4330_CBUCK_MODE_SHIFT 12 1307 #define CHIPC_CST4330_CBUCK_MODE_MASK 0x00003000 1308 #define CHIPC_CST4330_CBUCK_POWER_OK 0x00004000 1309 #define CHIPC_CST4330_BB_PLL_LOCKED 0x00008000 1310 #define CHIPC_SOCDEVRAM_4330_BP_ADDR 0x1E000000 1311 #define CHIPC_SOCDEVRAM_4330_ARM_ADDR 0x00800000 1312 1313 /* 4313 resources */ 1314 #define CHIPC_RES4313_BB_PU_RSRC 0 1315 #define CHIPC_RES4313_ILP_REQ_RSRC 1 1316 #define CHIPC_RES4313_XTAL_PU_RSRC 2 1317 #define CHIPC_RES4313_ALP_AVAIL_RSRC 3 1318 #define CHIPC_RES4313_RADIO_PU_RSRC 4 1319 #define CHIPC_RES4313_BG_PU_RSRC 5 1320 #define CHIPC_RES4313_VREG1P4_PU_RSRC 6 1321 #define CHIPC_RES4313_AFE_PWRSW_RSRC 7 1322 #define CHIPC_RES4313_RX_PWRSW_RSRC 8 1323 #define CHIPC_RES4313_TX_PWRSW_RSRC 9 1324 #define CHIPC_RES4313_BB_PWRSW_RSRC 10 1325 #define CHIPC_RES4313_SYNTH_PWRSW_RSRC 11 1326 #define CHIPC_RES4313_MISC_PWRSW_RSRC 12 1327 #define CHIPC_RES4313_BB_PLL_PWRSW_RSRC 13 1328 #define CHIPC_RES4313_HT_AVAIL_RSRC 14 1329 #define CHIPC_RES4313_MACPHY_CLK_AVAIL_RSRC 15 1330 1331 /* 4313 chip-specific ChipStatus register bits */ 1332 #define CHIPC_CST4313_SPROM_PRESENT 1 1333 #define CHIPC_CST4313_OTP_PRESENT 2 1334 #define CHIPC_CST4313_SPROM_OTP_SEL_MASK 0x00000002 1335 #define CHIPC_CST4313_SPROM_OTP_SEL_SHIFT 0 1336 1337 /* 4313 Chip specific ChipControl register bits */ 1338 #define CHIPC_CCTRL_4313_12MA_LED_DRIVE 0x00000007 /* 12 mA drive strengh for later 4313 */ 1339 1340 /* 43228 resources */ 1341 #define CHIPC_RES43228_NOT_USED 0 1342 #define CHIPC_RES43228_ILP_REQUEST 1 1343 #define CHIPC_RES43228_XTAL_PU 2 1344 #define CHIPC_RES43228_ALP_AVAIL 3 1345 #define CHIPC_RES43228_PLL_EN 4 1346 #define CHIPC_RES43228_HT_PHY_AVAIL 5 1347 1348 /* 43228 chipstatus reg bits */ 1349 #define CHIPC_CST43228_ILP_DIV_EN 0x1 1350 #define CHIPC_CST43228_OTP_PRESENT 0x2 1351 #define CHIPC_CST43228_SERDES_REFCLK_PADSEL 0x4 1352 #define CHIPC_CST43228_SDIO_MODE 0x8 1353 1354 #define CHIPC_CST43228_SDIO_OTP_PRESENT 0x10 1355 #define CHIPC_CST43228_SDIO_RESET 0x20 1356 1357 /* 1358 * Maximum delay for the PMU state transition in us. 1359 * This is an upper bound intended for spinwaits etc. 1360 */ 1361 #define CHIPC_PMU_MAX_TRANSITION_DLY 15000 1362 1363 /* PMU resource up transition time in ILP cycles */ 1364 #define CHIPC_PMURES_UP_TRANSITION 2 1365 1366 /* 1367 * Register eci_inputlo bitfield values. 1368 * - BT packet type information bits [7:0] 1369 */ 1370 /* [3:0] - Task (link) type */ 1371 #define CHIPC_BT_ACL 0x00 1372 #define CHIPC_BT_SCO 0x01 1373 #define CHIPC_BT_eSCO 0x02 1374 #define CHIPC_BT_A2DP 0x03 1375 #define CHIPC_BT_SNIFF 0x04 1376 #define CHIPC_BT_PAGE_SCAN 0x05 1377 #define CHIPC_BT_INQUIRY_SCAN 0x06 1378 #define CHIPC_BT_PAGE 0x07 1379 #define CHIPC_BT_INQUIRY 0x08 1380 #define CHIPC_BT_MSS 0x09 1381 #define CHIPC_BT_PARK 0x0a 1382 #define CHIPC_BT_RSSISCAN 0x0b 1383 #define CHIPC_BT_MD_ACL 0x0c 1384 #define CHIPC_BT_MD_eSCO 0x0d 1385 #define CHIPC_BT_SCAN_WITH_SCO_LINK 0x0e 1386 #define CHIPC_BT_SCAN_WITHOUT_SCO_LINK 0x0f 1387 /* [7:4] = packet duration code */ 1388 /* [8] - Master / Slave */ 1389 #define CHIPC_BT_MASTER 0 1390 #define CHIPC_BT_SLAVE 1 1391 /* [11:9] - multi-level priority */ 1392 #define CHIPC_BT_LOWEST_PRIO 0x0 1393 #define CHIPC_BT_HIGHEST_PRIO 0x3 1394 1395 #endif /* _BHND_CORES_CHIPC_CHIPCREG_H_ */ 1396