1 /*- 2 * SPDX-License-Identifier: ISC 3 * 4 * Copyright (c) 2015-2016 Landon Fuller <landon@landonf.org> 5 * Copyright (c) 1999-2015, Broadcom Corporation 6 * 7 * This file is derived from the bcmdevs.h header contributed by Broadcom 8 * to Android's bcmdhd driver module, later revisions of bcmdevs.h distributed 9 * with the dd-wrt project, and the hndsoc.h header distributed with Broadcom's 10 * initial brcm80211 Linux driver release as contributed to the Linux staging 11 * repository. 12 * 13 * Permission to use, copy, modify, and/or distribute this software for any 14 * purpose with or without fee is hereby granted, provided that the above 15 * copyright notice and this permission notice appear in all copies. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 18 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 19 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY 20 * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 21 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION 22 * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN 23 * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 24 */ 25 26 #ifndef _BHND_BHND_IDS_H_ 27 #define _BHND_BHND_IDS_H_ 28 29 /* 30 * JEDEC JEP-106 Core Vendor IDs 31 * 32 * These are the JEDEC JEP-106 manufacturer ID representions (with ARM's 33 * non-standard 4-bit continutation code), as used in ARM's PrimeCell 34 * identification registers, bcma(4) EROM core descriptors, etc. 35 * 36 * @note 37 * Bus implementations that predate the adoption of ARM IP 38 * will need to convert bus-specific vendor IDs to their BHND_MFGID 39 * JEP-106 equivalents. 40 * 41 * @par ARM 4-bit Continuation Code 42 * 43 * BHND MFGIDs are encoded using ARM's non-standard 4-bit continuation code 44 * format: 45 * 46 * @code{.unparsed} 47 * [11:8 ][7:0 ] 48 * [cont code][mfg id] 49 * @endcode 50 * 51 * The 4-bit continuation code field specifies the number of JEP-106 52 * continuation codes that prefix the manufacturer's ID code. In the case of 53 * ARM's JEP-106 ID of `0x7F 0x7F 0x7F 0x7F 0x3B`, the four 0x7F continuations 54 * are encoded as '4' in the 4-bit continuation code field (i.e. 0x43B). 55 */ 56 #define BHND_MFGID_ARM 0x043b /**< arm JEP-106 vendor id */ 57 #define BHND_MFGID_BCM 0x04bf /**< broadcom JEP-106 vendor id */ 58 #define BHND_MFGID_MIPS 0x04a7 /**< mips JEP-106 vendor id */ 59 #define BHND_MFGID_INVALID 0x0000 /**< invalid JEP-106 vendor id */ 60 61 /* 62 * OCP (Open Core Protocol) Vendor IDs. 63 * 64 * OCP-IP assigned vendor codes are used by siba(4) 65 */ 66 #define OCP_VENDOR_BCM 0x4243 /**< Broadcom OCP vendor id */ 67 68 /* PCI vendor IDs */ 69 #define PCI_VENDOR_ASUSTEK 0x1043 70 #define PCI_VENDOR_EPIGRAM 0xfeda 71 #define PCI_VENDOR_BROADCOM 0x14e4 72 #define PCI_VENDOR_3COM 0x10b7 73 #define PCI_VENDOR_NETGEAR 0x1385 74 #define PCI_VENDOR_DIAMOND 0x1092 75 #define PCI_VENDOR_INTEL 0x8086 76 #define PCI_VENDOR_DELL 0x1028 77 #define PCI_VENDOR_HP 0x103c 78 #define PCI_VENDOR_HP_COMPAQ 0x0e11 79 #define PCI_VENDOR_LINKSYS 0x1737 80 #define PCI_VENDOR_MOTOROLA 0x1057 81 #define PCI_VENDOR_APPLE 0x106b 82 #define PCI_VENDOR_SI_IMAGE 0x1095 /* Silicon Image, used by Arasan SDIO Host */ 83 #define PCI_VENDOR_BUFFALO 0x1154 /* Buffalo vendor id */ 84 #define PCI_VENDOR_TI 0x104c /* Texas Instruments */ 85 #define PCI_VENDOR_RICOH 0x1180 /* Ricoh */ 86 #define PCI_VENDOR_JMICRON 0x197b 87 88 /* PCMCIA vendor IDs */ 89 #define PCMCIA_VENDOR_BROADCOM 0x02d0 90 91 /* SDIO vendor IDs */ 92 #define SDIO_VENDOR_BROADCOM 0x00BF 93 94 /* USB dongle VID/PIDs */ 95 #define USB_VID_BROADCOM 0x0a5c 96 #define USB_PID_BCM4328 0xbd12 97 #define USB_PID_BCM4322 0xbd13 98 #define USB_PID_BCM4319 0xbd16 99 #define USB_PID_BCM43236 0xbd17 100 #define USB_PID_BCM4332 0xbd18 101 #define USB_PID_BCM4330 0xbd19 102 #define USB_PID_BCM4334 0xbd1a 103 #define USB_PID_BCM43239 0xbd1b 104 #define USB_PID_BCM4324 0xbd1c 105 #define USB_PID_BCM4360 0xbd1d 106 #define USB_PID_BCM43143 0xbd1e 107 #define USB_PID_BCM43242 0xbd1f 108 #define USB_PID_BCM43342 0xbd21 109 #define USB_PID_BCM4335 0xbd20 110 #define USB_PID_BCM4350 0xbd23 111 #define USB_PID_BCM43341 0xbd22 112 113 #define USB_PID_BCM_DNGL_BDC 0x0bdc /* BDC USB device controller IP? */ 114 #define USB_PID_BCM_DNGL_JTAG 0x4a44 115 116 /* HW USB BLOCK [CPULESS USB] PIDs */ 117 #define USB_PID_CCM_HWUSB_43239 43239 118 119 /* PCI Device IDs */ 120 #define PCI_DEVID_BCM4210 0x1072 /* never used */ 121 #define PCI_DEVID_BCM4230 0x1086 /* never used */ 122 #define PCI_DEVID_BCM4401_ENET 0x170c /* 4401b0 production enet cards */ 123 #define PCI_DEVID_BCM3352 0x3352 /* bcm3352 device id */ 124 #define PCI_DEVID_BCM3360 0x3360 /* bcm3360 device id */ 125 #define PCI_DEVID_BCM4211 0x4211 126 #define PCI_DEVID_BCM4231 0x4231 127 #define PCI_DEVID_BCM4301 0x4301 /* 4031 802.11b */ 128 #define PCI_DEVID_BCM4303_D11B 0x4303 /* 4303 802.11b */ 129 #define PCI_DEVID_BCM4306 0x4306 /* 4306 802.11b/g */ 130 #define PCI_DEVID_BCM4307 0x4307 /* 4307 802.11b, 10/100 ethernet, V.92 modem */ 131 #define PCI_DEVID_BCM4311_D11G 0x4311 /* 4311 802.11b/g id */ 132 #define PCI_DEVID_BCM4311_D11DUAL 0x4312 /* 4311 802.11a/b/g id */ 133 #define PCI_DEVID_BCM4311_D11A 0x4313 /* 4311 802.11a id */ 134 #define PCI_DEVID_BCM4328_D11DUAL 0x4314 /* 4328/4312 802.11a/g id */ 135 #define PCI_DEVID_BCM4328_D11G 0x4315 /* 4328/4312 802.11g id */ 136 #define PCI_DEVID_BCM4328_D11A 0x4316 /* 4328/4312 802.11a id */ 137 #define PCI_DEVID_BCM4318_D11G 0x4318 /* 4318 802.11b/g id */ 138 #define PCI_DEVID_BCM4318_D11DUAL 0x4319 /* 4318 802.11a/b/g id */ 139 #define PCI_DEVID_BCM4318_D11A 0x431a /* 4318 802.11a id */ 140 #define PCI_DEVID_BCM4325_D11DUAL 0x431b /* 4325 802.11a/g id */ 141 #define PCI_DEVID_BCM4325_D11G 0x431c /* 4325 802.11g id */ 142 #define PCI_DEVID_BCM4325_D11A 0x431d /* 4325 802.11a id */ 143 #define PCI_DEVID_BCM4306_D11G 0x4320 /* 4306 802.11g */ 144 #define PCI_DEVID_BCM4306_D11A 0x4321 /* 4306 802.11a */ 145 #define PCI_DEVID_BCM4306_UART 0x4322 /* 4306 uart */ 146 #define PCI_DEVID_BCM4306_V90 0x4323 /* 4306 v90 codec */ 147 #define PCI_DEVID_BCM4306_D11DUAL 0x4324 /* 4306 dual A+B */ 148 #define PCI_DEVID_BCM4306_D11G_ID2 0x4325 /* BCM4306_D11G; INF w/loose binding war */ 149 #define PCI_DEVID_BCM4321_D11N 0x4328 /* 4321 802.11n dualband id */ 150 #define PCI_DEVID_BCM4321_D11N2G 0x4329 /* 4321 802.11n 2.4Ghz band id */ 151 #define PCI_DEVID_BCM4321_D11N5G 0x432a /* 4321 802.11n 5Ghz band id */ 152 #define PCI_DEVID_BCM4322_D11N 0x432b /* 4322 802.11n dualband device */ 153 #define PCI_DEVID_BCM4322_D11N2G 0x432c /* 4322 802.11n 2.4GHz device */ 154 #define PCI_DEVID_BCM4322_D11N5G 0x432d /* 4322 802.11n 5GHz device */ 155 #define PCI_DEVID_BCM4329_D11N 0x432e /* 4329 802.11n dualband device */ 156 #define PCI_DEVID_BCM4329_D11N2G 0x432f /* 4329 802.11n 2.4G device */ 157 #define PCI_DEVID_BCM4329_D11N5G 0x4330 /* 4329 802.11n 5G device */ 158 #define PCI_DEVID_BCM4315_D11DUAL 0x4334 /* 4315 802.11a/g id */ 159 #define PCI_DEVID_BCM4315_D11G 0x4335 /* 4315 802.11g id */ 160 #define PCI_DEVID_BCM4315_D11A 0x4336 /* 4315 802.11a id */ 161 #define PCI_DEVID_BCM4319_D11N 0x4337 /* 4319 802.11n dualband device */ 162 #define PCI_DEVID_BCM4319_D11N2G 0x4338 /* 4319 802.11n 2.4G device */ 163 #define PCI_DEVID_BCM4319_D11N5G 0x4339 /* 4319 802.11n 5G device */ 164 #define PCI_DEVID_BCM43231_D11N2G 0x4340 /* 43231 802.11n 2.4GHz device */ 165 #define PCI_DEVID_BCM43221_D11N2G 0x4341 /* 43221 802.11n 2.4GHz device */ 166 #define PCI_DEVID_BCM43222_D11N 0x4350 /* 43222 802.11n dualband device */ 167 #define PCI_DEVID_BCM43222_D11N2G 0x4351 /* 43222 802.11n 2.4GHz device */ 168 #define PCI_DEVID_BCM43222_D11N5G 0x4352 /* 43222 802.11n 5GHz device */ 169 #define PCI_DEVID_BCM43224_D11N 0x4353 /* 43224 802.11n dualband device */ 170 #define PCI_DEVID_BCM43224_D11N_ID_VEN1 0x0576 /* Vendor specific 43224 802.11n db device */ 171 #define PCI_DEVID_BCM43226_D11N 0x4354 /* 43226 802.11n dualband device */ 172 #define PCI_DEVID_BCM43236_D11N 0x4346 /* 43236 802.11n dualband device */ 173 #define PCI_DEVID_BCM43236_D11N2G 0x4347 /* 43236 802.11n 2.4GHz device */ 174 #define PCI_DEVID_BCM43236_D11N5G 0x4348 /* 43236 802.11n 5GHz device */ 175 #define PCI_DEVID_BCM43225_D11N2G 0x4357 /* 43225 802.11n 2.4GHz device */ 176 #define PCI_DEVID_BCM43421_D11N 0xA99D /* 43421 802.11n dualband device */ 177 #define PCI_DEVID_BCM4313_D11N2G 0x4727 /* 4313 802.11n 2.4G device */ 178 #define PCI_DEVID_BCM4330_D11N 0x4360 /* 4330 802.11n dualband device */ 179 #define PCI_DEVID_BCM4330_D11N2G 0x4361 /* 4330 802.11n 2.4G device */ 180 #define PCI_DEVID_BCM4330_D11N5G 0x4362 /* 4330 802.11n 5G device */ 181 #define PCI_DEVID_BCM4336_D11N 0x4343 /* 4336 802.11n 2.4GHz device */ 182 #define PCI_DEVID_BCM6362_D11N 0x435f /* 6362 802.11n dualband device */ 183 #define PCI_DEVID_BCM6362_D11N2G 0x433f /* 6362 802.11n 2.4Ghz band id */ 184 #define PCI_DEVID_BCM6362_D11N5G 0x434f /* 6362 802.11n 5Ghz band id */ 185 #define PCI_DEVID_BCM4331_D11N 0x4331 /* 4331 802.11n dualband id */ 186 #define PCI_DEVID_BCM4331_D11N2G 0x4332 /* 4331 802.11n 2.4Ghz band id */ 187 #define PCI_DEVID_BCM4331_D11N5G 0x4333 /* 4331 802.11n 5Ghz band id */ 188 #define PCI_DEVID_BCM43237_D11N 0x4355 /* 43237 802.11n dualband device */ 189 #define PCI_DEVID_BCM43237_D11N5G 0x4356 /* 43237 802.11n 5GHz device */ 190 #define PCI_DEVID_BCM43227_D11N2G 0x4358 /* 43228 802.11n 2.4GHz device */ 191 #define PCI_DEVID_BCM43228_D11N 0x4359 /* 43228 802.11n DualBand device */ 192 #define PCI_DEVID_BCM43228_D11N5G 0x435a /* 43228 802.11n 5GHz device */ 193 #define PCI_DEVID_BCM43362_D11N 0x4363 /* 43362 802.11n 2.4GHz device */ 194 #define PCI_DEVID_BCM43239_D11N 0x4370 /* 43239 802.11n dualband device */ 195 #define PCI_DEVID_BCM4324_D11N 0x4374 /* 4324 802.11n dualband device */ 196 #define PCI_DEVID_BCM43217_D11N2G 0x43a9 /* 43217 802.11n 2.4GHz device */ 197 #define PCI_DEVID_BCM43131_D11N2G 0x43aa /* 43131 802.11n 2.4GHz device */ 198 #define PCI_DEVID_BCM4314_D11N2G 0x4364 /* 4314 802.11n 2.4G device */ 199 #define PCI_DEVID_BCM43142_D11N2G 0x4365 /* 43142 802.11n 2.4G device */ 200 #define PCI_DEVID_BCM43143_D11N2G 0x4366 /* 43143 802.11n 2.4G device */ 201 #define PCI_DEVID_BCM4334_D11N 0x4380 /* 4334 802.11n dualband device */ 202 #define PCI_DEVID_BCM4334_D11N2G 0x4381 /* 4334 802.11n 2.4G device */ 203 #define PCI_DEVID_BCM4334_D11N5G 0x4382 /* 4334 802.11n 5G device */ 204 #define PCI_DEVID_BCM43342_D11N 0x4383 /* 43342 802.11n dualband device */ 205 #define PCI_DEVID_BCM43342_D11N2G 0x4384 /* 43342 802.11n 2.4G device */ 206 #define PCI_DEVID_BCM43342_D11N5G 0x4385 /* 43342 802.11n 5G device */ 207 #define PCI_DEVID_BCM43341_D11N 0x4386 /* 43341 802.11n dualband device */ 208 #define PCI_DEVID_BCM43341_D11N2G 0x4387 /* 43341 802.11n 2.4G device */ 209 #define PCI_DEVID_BCM43341_D11N5G 0x4388 /* 43341 802.11n 5G device */ 210 #define PCI_DEVID_BCM4360_D11AC 0x43a0 211 #define PCI_DEVID_BCM4360_D11AC2G 0x43a1 212 #define PCI_DEVID_BCM4360_D11AC5G 0x43a2 213 #define PCI_DEVID_BCM4335_D11AC 0x43ae 214 #define PCI_DEVID_BCM4335_D11AC2G 0x43af 215 #define PCI_DEVID_BCM4335_D11AC5G 0x43b0 216 #define PCI_DEVID_BCM4352_D11AC 0x43b1 /* 4352 802.11ac dualband device */ 217 #define PCI_DEVID_BCM4352_D11AC2G 0x43b2 /* 4352 802.11ac 2.4G device */ 218 #define PCI_DEVID_BCM4352_D11AC5G 0x43b3 /* 4352 802.11ac 5G device */ 219 220 #define PCI_DEVID_PCIXX21_FLASHMEDIA0 0x8033 /* TI PCI xx21 Standard Host Controller */ 221 #define PCI_DEVID_PCIXX21_SDIOH0 0x8034 /* TI PCI xx21 Standard Host Controller */ 222 223 /* PCI Subsystem Vendor IDs */ 224 #define PCI_SUBVENDOR_BCM943228HMB 0x0607 225 #define PCI_SUBVENDOR_BCM94313HMGBL 0x0608 226 #define PCI_SUBVENDOR_BCM94313HMG 0x0609 227 #define PCI_SUBVENDOR_BCM943142HM 0x0611 228 229 /* PCI Subsystem Device IDs */ 230 #define PCI_SUBDEVID_BCM43143_D11N2G 0x4366 /* 43143 802.11n 2.4G device */ 231 232 #define PCI_SUBDEVID_BCM43242_D11N 0x4367 /* 43242 802.11n dualband device */ 233 #define PCI_SUBDEVID_BCM43242_D11N2G 0x4368 /* 43242 802.11n 2.4G device */ 234 #define PCI_SUBDEVID_BCM43242_D11N5G 0x4369 /* 43242 802.11n 5G device */ 235 236 #define PCI_SUBDEVID_BCM4350_D11AC 0x43a3 237 #define PCI_SUBDEVID_BCM4350_D11AC2G 0x43a4 238 #define PCI_SUBDEVID_BCM4350_D11AC5G 0x43a5 239 240 #define PCI_SUBDEVID_BCMGPRS_UART 0x4333 /* Uart id used by 4306/gprs card */ 241 #define PCI_SUBDEVID_BCMGPRS2_UART 0x4344 /* Uart id used by 4306/gprs card */ 242 #define PCI_SUBDEVID_BCM_FPGA_JTAGM 0x43f0 /* FPGA jtagm device id */ 243 #define PCI_SUBDEVID_BCM_JTAGM 0x43f1 /* BCM jtagm device id */ 244 #define PCI_SUBDEVID_BCM_SDIOH_FPGA 0x43f2 /* sdio host fpga */ 245 #define PCI_SUBDEVID_BCM_SDIOH 0x43f3 /* BCM sdio host id */ 246 #define PCI_SUBDEVID_BCM_SDIOD_FPGA 0x43f4 /* sdio device fpga */ 247 #define PCI_SUBDEVID_BCM_SPIH_FPGA 0x43f5 /* PCI SPI Host Controller FPGA */ 248 #define PCI_SUBDEVID_BCM_SPIH 0x43f6 /* Synopsis SPI Host Controller */ 249 #define PCI_SUBDEVID_BCM_MIMO_FPGA 0x43f8 /* FPGA mimo minimacphy device id */ 250 #define PCI_SUBDEVID_BCM_JTAGM2 0x43f9 /* PCI_SUBDEVID_BCM alternate jtagm device id */ 251 #define PCI_SUBDEVID_BCM_SDHCI_FPGA 0x43fa /* Standard SDIO Host Controller FPGA */ 252 #define PCI_SUBDEVID_BCM4402_ENET 0x4402 /* 4402 enet */ 253 #define PCI_SUBDEVID_BCM4402_V90 0x4403 /* 4402 v90 codec */ 254 #define PCI_SUBDEVID_BCM4410 0x4410 /* bcm44xx family pci iline */ 255 #define PCI_SUBDEVID_BCM4412 0x4412 /* bcm44xx family pci enet */ 256 #define PCI_SUBDEVID_BCM4430 0x4430 /* bcm44xx family cardbus iline */ 257 #define PCI_SUBDEVID_BCM4432 0x4432 /* bcm44xx family cardbus enet */ 258 #define PCI_SUBDEVID_BCM4704_ENET 0x4706 /* 4704 enet (Use 47XX_ENET_ID instead!) */ 259 #define PCI_SUBDEVID_BCM4710 0x4710 /* 4710 primary function 0 */ 260 #define PCI_SUBDEVID_BCM47XX_AUDIO 0x4711 /* 47xx audio codec */ 261 #define PCI_SUBDEVID_BCM47XX_V90 0x4712 /* 47xx v90 codec */ 262 #define PCI_SUBDEVID_BCM47XX_ENET 0x4713 /* 47xx enet */ 263 #define PCI_SUBDEVID_BCM47XX_EXT 0x4714 /* 47xx external i/f */ 264 #define PCI_SUBDEVID_BCM47XX_GMAC 0x4715 /* 47xx Unimac based GbE */ 265 #define PCI_SUBDEVID_BCM47XX_USBH 0x4716 /* 47xx usb host */ 266 #define PCI_SUBDEVID_BCM47XX_USBD 0x4717 /* 47xx usb device */ 267 #define PCI_SUBDEVID_BCM47XX_IPSEC 0x4718 /* 47xx ipsec */ 268 #define PCI_SUBDEVID_BCM47XX_ROBO 0x4719 /* 47xx/53xx roboswitch core */ 269 #define PCI_SUBDEVID_BCM47XX_USB20H 0x471a /* 47xx usb 2.0 host */ 270 #define PCI_SUBDEVID_BCM47XX_USB20D 0x471b /* 47xx usb 2.0 device */ 271 #define PCI_SUBDEVID_BCM47XX_ATA100 0x471d /* 47xx parallel ATA */ 272 #define PCI_SUBDEVID_BCM47XX_SATAXOR 0x471e /* 47xx serial ATA & XOR DMA */ 273 #define PCI_SUBDEVID_BCM47XX_GIGETH 0x471f /* 47xx GbE (5700) */ 274 #define PCI_SUBDEVID_BCM4712_MIPS 0x4720 /* 4712 base devid */ 275 #define PCI_SUBDEVID_BCM4716 0x4722 /* 4716 base devid */ 276 #define PCI_SUBDEVID_BCM47XX_USB30H 0x472a /* 47xx usb 3.0 host */ 277 #define PCI_SUBDEVID_BCM47XX_USB30D 0x472b /* 47xx usb 3.0 device */ 278 #define PCI_SUBDEVID_BCM47XX_SMBUS_EMU 0x47fe /* 47xx emulated SMBus device */ 279 #define PCI_SUBDEVID_BCM47XX_XOR_EMU 0x47ff /* 47xx emulated XOR engine */ 280 #define PCI_SUBDEVID_BCM_EPI41210 0xa0fa /* bcm4210 */ 281 #define PCI_SUBDEVID_BCM_EPI41230 0xa10e /* bcm4230 */ 282 #define PCI_SUBDEVID_BCM_JINVANI_SDIOH 0x4743 /* Jinvani SDIO Gold Host */ 283 #define PCI_SUBDEVID_BCM27XX_SDIOH 0x2702 /* PCI_SUBDEVID_BCM27xx Standard SDIO Host */ 284 #define PCI_SUBDEVID_BCM_PCIXX21_FLASHMEDIA 0x803b /* TI PCI xx21 Standard Host Controller */ 285 #define PCI_SUBDEVID_BCM_PCIXX21_SDIOH 0x803c /* TI PCI xx21 Standard Host Controller */ 286 #define PCI_SUBDEVID_BCM_R5C822_SDIOH 0x0822 /* Ricoh Co Ltd R5C822 SD/SDIO/MMC/MS/MSPro Host */ 287 #define PCI_SUBDEVID_BCM_JMICRON_SDIOH 0x2381 /* JMicron Standard SDIO Host Controller */ 288 289 /* Broadcom ChipCommon Chip IDs */ 290 #define BHND_CHIPID_BCM4306 0x4306 /* 4306 chipcommon chipid */ 291 #define BHND_CHIPID_BCM4311 0x4311 /* 4311 PCIe 802.11a/b/g */ 292 #define BHND_CHIPID_BCM43111 43111 /* 43111 chipcommon chipid (OTP chipid) */ 293 #define BHND_CHIPID_BCM43112 43112 /* 43112 chipcommon chipid (OTP chipid) */ 294 #define BHND_CHIPID_BCM4312 0x4312 /* 4312 chipcommon chipid */ 295 #define BHND_CHIPID_BCM4313 0x4313 /* 4313 chip id */ 296 #define BHND_CHIPID_BCM43131 43131 /* 43131 chip id (OTP chipid) */ 297 #define BHND_CHIPID_BCM4315 0x4315 /* 4315 chip id */ 298 #define BHND_CHIPID_BCM4318 0x4318 /* 4318 chipcommon chipid */ 299 #define BHND_CHIPID_BCM4319 0x4319 /* 4319 chip id */ 300 #define BHND_CHIPID_BCM4320 0x4320 /* 4320 chipcommon chipid */ 301 #define BHND_CHIPID_BCM4321 0x4321 /* 4321 chipcommon chipid */ 302 #define BHND_CHIPID_BCM43217 43217 /* 43217 chip id (OTP chipid) */ 303 #define BHND_CHIPID_BCM4322 0x4322 /* 4322 chipcommon chipid */ 304 #define BHND_CHIPID_BCM43221 43221 /* 43221 chipcommon chipid (OTP chipid) */ 305 #define BHND_CHIPID_BCM43222 43222 /* 43222 chipcommon chipid */ 306 #define BHND_CHIPID_BCM43224 43224 /* 43224 chipcommon chipid */ 307 #define BHND_CHIPID_BCM43225 43225 /* 43225 chipcommon chipid */ 308 #define BHND_CHIPID_BCM43227 43227 /* 43227 chipcommon chipid */ 309 #define BHND_CHIPID_BCM43228 43228 /* 43228 chipcommon chipid */ 310 #define BHND_CHIPID_BCM43226 43226 /* 43226 chipcommon chipid */ 311 #define BHND_CHIPID_BCM43231 43231 /* 43231 chipcommon chipid (OTP chipid) */ 312 #define BHND_CHIPID_BCM43234 43234 /* 43234 chipcommon chipid */ 313 #define BHND_CHIPID_BCM43235 43235 /* 43235 chipcommon chipid */ 314 #define BHND_CHIPID_BCM43236 43236 /* 43236 chipcommon chipid */ 315 #define BHND_CHIPID_BCM43237 43237 /* 43237 chipcommon chipid */ 316 #define BHND_CHIPID_BCM43238 43238 /* 43238 chipcommon chipid */ 317 #define BHND_CHIPID_BCM43239 43239 /* 43239 chipcommon chipid */ 318 #define BHND_CHIPID_BCM43420 43420 /* 43222 chipcommon chipid (OTP, RBBU) */ 319 #define BHND_CHIPID_BCM43421 43421 /* 43224 chipcommon chipid (OTP, RBBU) */ 320 #define BHND_CHIPID_BCM43428 43428 /* 43228 chipcommon chipid (OTP, RBBU) */ 321 #define BHND_CHIPID_BCM43431 43431 /* 4331 chipcommon chipid (OTP, RBBU) */ 322 #define BHND_CHIPID_BCM43460 43460 /* 4360 chipcommon chipid (OTP, RBBU) */ 323 #define BHND_CHIPID_BCM43462 0xA9C6 /* 43462 chipcommon chipid */ 324 #define BHND_CHIPID_BCM4325 0x4325 /* 4325 chip id */ 325 #define BHND_CHIPID_BCM4328 0x4328 /* 4328 chip id */ 326 #define BHND_CHIPID_BCM4329 0x4329 /* 4329 chipcommon chipid */ 327 #define BHND_CHIPID_BCM4331 0x4331 /* 4331 chipcommon chipid */ 328 #define BHND_CHIPID_BCM4336 0x4336 /* 4336 chipcommon chipid */ 329 #define BHND_CHIPID_BCM43362 43362 /* 43362 chipcommon chipid */ 330 #define BHND_CHIPID_BCM4330 0x4330 /* 4330 chipcommon chipid */ 331 #define BHND_CHIPID_BCM6362 0x6362 /* 6362 chipcommon chipid */ 332 #define BHND_CHIPID_BCM4314 0x4314 /* 4314 chipcommon chipid */ 333 #define BHND_CHIPID_BCM43142 43142 /* 43142 chipcommon chipid */ 334 #define BHND_CHIPID_BCM43143 43143 /* 43143 chipcommon chipid */ 335 #define BHND_CHIPID_BCM4324 0x4324 /* 4324 chipcommon chipid */ 336 #define BHND_CHIPID_BCM43242 43242 /* 43242 chipcommon chipid */ 337 #define BHND_CHIPID_BCM43243 43243 /* 43243 chipcommon chipid */ 338 #define BHND_CHIPID_BCM4334 0x4334 /* 4334 chipcommon chipid */ 339 #define BHND_CHIPID_BCM4335 0x4335 /* 4335 chipcommon chipid */ 340 #define BHND_CHIPID_BCM4360 0x4360 /* 4360 chipcommon chipid */ 341 #define BHND_CHIPID_BCM43602 0xaa52 /* 43602 chipcommon chipid */ 342 #define BHND_CHIPID_BCM4352 0x4352 /* 4352 chipcommon chipid */ 343 #define BHND_CHIPID_BCM43526 0xAA06 344 #define BHND_CHIPID_BCM43341 43341 /* 43341 chipcommon chipid */ 345 #define BHND_CHIPID_BCM43342 43342 /* 43342 chipcommon chipid */ 346 #define BHND_CHIPID_BCM4335 0x4335 347 #define BHND_CHIPID_BCM4350 0x4350 /* 4350 chipcommon chipid */ 348 349 #define BHND_CHIPID_BCM4342 4342 /* 4342 chipcommon chipid (OTP, RBBU) */ 350 #define BHND_CHIPID_BCM4402 0x4402 /* 4402 chipid */ 351 #define BHND_CHIPID_BCM4704 0x4704 /* 4704 chipcommon chipid */ 352 #define BHND_CHIPID_BCM4706 0x5300 /* 4706 chipcommon chipid */ 353 #define BHND_CHIPID_BCM4707 53010 /* 4707 chipcommon chipid */ 354 #define BHND_CHIPID_BCM53018 53018 /* 53018 chipcommon chipid */ 355 #define BHND_CHIPID_IS_BCM4707(chipid) \ 356 (((chipid) == BHND_CHIPID_BCM4707) || \ 357 ((chipid) == BHND_CHIPID_BCM53018)) 358 #define BHND_CHIPID_BCM4710 0x4710 /* 4710 chipid */ 359 #define BHND_CHIPID_BCM4712 0x4712 /* 4712 chipcommon chipid */ 360 #define BHND_CHIPID_BCM4716 0x4716 /* 4716 chipcommon chipid */ 361 #define BHND_CHIPID_BCM47162 47162 /* 47162 chipcommon chipid */ 362 #define BHND_CHIPID_BCM4748 0x4748 /* 4716 chipcommon chipid (OTP, RBBU) */ 363 #define BHND_CHIPID_BCM4749 0x4749 /* 5357 chipcommon chipid (OTP, RBBU) */ 364 #define BHND_CHIPID_BCM4785 0x4785 /* 4785 chipcommon chipid */ 365 #define BHND_CHIPID_BCM5350 0x5350 /* 5350 chipcommon chipid */ 366 #define BHND_CHIPID_BCM5352 0x5352 /* 5352 chipcommon chipid */ 367 #define BHND_CHIPID_BCM5354 0x5354 /* 5354 chipcommon chipid */ 368 #define BHND_CHIPID_BCM5365 0x5365 /* 5365 chipcommon chipid */ 369 #define BHND_CHIPID_BCM5356 0x5356 /* 5356 chipcommon chipid */ 370 #define BHND_CHIPID_BCM5357 0x5357 /* 5357 chipcommon chipid */ 371 #define BHND_CHIPID_BCM53572 53572 /* 53572 chipcommon chipid */ 372 373 /* Broadcom ChipCommon Package IDs */ 374 #define BHND_PKGID_BCM4303 2 /* 4303 package id */ 375 #define BHND_PKGID_BCM4309 1 /* 4309 package id */ 376 #define BHND_PKGID_BCM4712LARGE 0 /* 340pin 4712 package id */ 377 #define BHND_PKGID_BCM4712SMALL 1 /* 200pin 4712 package id */ 378 #define BHND_PKGID_BCM4712MID 2 /* 225pin 4712 package id */ 379 #define BHND_PKGID_BCM4328USBD11G 2 /* 4328 802.11g USB package id */ 380 #define BHND_PKGID_BCM4328USBDUAL 3 /* 4328 802.11a/g USB package id */ 381 #define BHND_PKGID_BCM4328SDIOD11G 4 /* 4328 802.11g SDIO package id */ 382 #define BHND_PKGID_BCM4328SDIODUAL 5 /* 4328 802.11a/g SDIO package id */ 383 #define BHND_PKGID_BCM4329_289PIN 0 /* 4329 289-pin package id */ 384 #define BHND_PKGID_BCM4329_182PIN 1 /* 4329N 182-pin package id */ 385 #define BHND_PKGID_BCM5354E 1 /* 5354E package id */ 386 #define BHND_PKGID_BCM4716 8 /* 4716 package id */ 387 #define BHND_PKGID_BCM4717 9 /* 4717 package id */ 388 #define BHND_PKGID_BCM4718 10 /* 4718 package id */ 389 #define BHND_PKGID_BCM5356_NONMODE 1 /* 5356 package without nmode suppport */ 390 #define BHND_PKGID_BCM5358U 8 /* 5358U package id */ 391 #define BHND_PKGID_BCM5358 9 /* 5358 package id */ 392 #define BHND_PKGID_BCM47186 10 /* 47186 package id */ 393 #define BHND_PKGID_BCM5357 11 /* 5357 package id */ 394 #define BHND_PKGID_BCM5356U 12 /* 5356U package id */ 395 #define BHND_PKGID_BCM53572 8 /* 53572 package id */ 396 #define BHND_PKGID_BCM5357C0 8 /* 5357c0 package id (the same as 53572) */ 397 #define BHND_PKGID_BCM47188 9 /* 47188 package id */ 398 #define BHND_PKGID_BCM5358C0 0xa /* 5358c0 package id */ 399 #define BHND_PKGID_BCM5356C0 0xb /* 5356c0 package id */ 400 #define BHND_PKGID_BCM4331TT 8 /* 4331 12x12 package id */ 401 #define BHND_PKGID_BCM4331TN 9 /* 4331 12x9 package id */ 402 #define BHND_PKGID_BCM4331TNA0 0xb /* 4331 12x9 package id */ 403 #define BHND_PKGID_BCM4706L 1 /* 4706L package id */ 404 405 #define BHND_PKGID_HDLSIM5350 1 /* HDL simulator package id for a 5350 */ 406 #define BHND_PKGID_HDLSIM 14 /* HDL simulator package id */ 407 #define BHND_PKGID_HWSIM 15 /* Hardware simulator package id */ 408 #define BHND_PKGID_BCM43224_FAB_CSM 0x8 /* the chip is manufactured by CSM */ 409 #define BHND_PKGID_BCM43224_FAB_SMIC 0xa /* the chip is manufactured by SMIC */ 410 #define BHND_PKGID_BCM4336_WLBGA 0x8 411 #define BHND_PKGID_BCM4330_WLBGA 0x0 412 #define BHND_PKGID_BCM4314PCIE_ARM (8 | 0) /* 4314 QFN PCI package id, bit 3 tie high */ 413 #define BHND_PKGID_BCM4314SDIO (8 | 1) /* 4314 QFN SDIO package id */ 414 #define BHND_PKGID_BCM4314PCIE (8 | 2) /* 4314 QFN PCI (ARM-less) package id */ 415 #define BHND_PKGID_BCM4314SDIO_ARM (8 | 3) /* 4314 QFN SDIO (ARM-less) package id */ 416 #define BHND_PKGID_BCM4314SDIO_FPBGA (8 | 4) /* 4314 FpBGA SDIO package id */ 417 #define BHND_PKGID_BCM4314DEV (8 | 6) /* 4314 Development package id */ 418 419 #define BHND_PKGID_BCM4707 1 /* 4707 package id */ 420 #define BHND_PKGID_BCM4708 2 /* 4708 package id */ 421 #define BHND_PKGID_BCM4709 0 /* 4709 package id */ 422 423 #define BHND_PKGID_BCM4335_WLCSP (0x0) /* WLCSP Module/Mobile SDIO/HSIC. */ 424 #define BHND_PKGID_BCM4335_FCBGA (0x1) /* FCBGA PC/Embedded/Media PCIE/SDIO */ 425 #define BHND_PKGID_BCM4335_WLBGA (0x2) /* WLBGA COB/Mobile SDIO/HSIC. */ 426 #define BHND_PKGID_BCM4335_FCBGAD (0x3) /* FCBGA Debug Debug/Dev All if's. */ 427 #define BHND_PKGID_PKG_MASK_BCM4335 (0x3) 428 429 /* Broadcom Core IDs */ 430 #define BHND_COREID_INVALID 0x700 /* Invalid coreid */ 431 #define BHND_COREID_CC 0x800 /* chipcommon core */ 432 #define BHND_COREID_ILINE20 0x801 /* iline20 core */ 433 #define BHND_COREID_SRAM 0x802 /* sram core */ 434 #define BHND_COREID_SDRAM 0x803 /* sdram core */ 435 #define BHND_COREID_PCI 0x804 /* pci core */ 436 #define BHND_COREID_MIPS 0x805 /* mips core */ 437 #define BHND_COREID_ENET 0x806 /* enet mac core */ 438 #define BHND_COREID_V90_CODEC 0x807 /* v90 codec core */ 439 #define BHND_COREID_USB 0x808 /* usb 1.1 host/device core */ 440 #define BHND_COREID_ADSL 0x809 /* ADSL core */ 441 #define BHND_COREID_ILINE100 0x80a /* iline100 core */ 442 #define BHND_COREID_IPSEC 0x80b /* ipsec core */ 443 #define BHND_COREID_UTOPIA 0x80c /* utopia core */ 444 #define BHND_COREID_PCMCIA 0x80d /* pcmcia core */ 445 #define BHND_COREID_SOCRAM 0x80e /* internal memory core */ 446 #define BHND_COREID_MEMC 0x80f /* memc sdram core */ 447 #define BHND_COREID_OFDM 0x810 /* OFDM phy core */ 448 #define BHND_COREID_EXTIF 0x811 /* external interface core */ 449 #define BHND_COREID_D11 0x812 /* 802.11 MAC core */ 450 #define BHND_COREID_APHY 0x813 /* 802.11a phy core */ 451 #define BHND_COREID_BPHY 0x814 /* 802.11b phy core */ 452 #define BHND_COREID_GPHY 0x815 /* 802.11g phy core */ 453 #define BHND_COREID_MIPS33 0x816 /* mips3302 core */ 454 #define BHND_COREID_USB11H 0x817 /* usb 1.1 host core */ 455 #define BHND_COREID_USB11D 0x818 /* usb 1.1 device core */ 456 #define BHND_COREID_USB20H 0x819 /* usb 2.0 host core */ 457 #define BHND_COREID_USB20D 0x81a /* usb 2.0 device core */ 458 #define BHND_COREID_SDIOH 0x81b /* sdio host core */ 459 #define BHND_COREID_ROBO 0x81c /* roboswitch core */ 460 #define BHND_COREID_ATA100 0x81d /* parallel ATA core */ 461 #define BHND_COREID_SATAXOR 0x81e /* serial ATA & XOR DMA core */ 462 #define BHND_COREID_GIGETH 0x81f /* gigabit ethernet core */ 463 #define BHND_COREID_PCIE 0x820 /* pci express core */ 464 #define BHND_COREID_NPHY 0x821 /* 802.11n 2x2 phy core */ 465 #define BHND_COREID_SRAMC 0x822 /* SRAM controller core */ 466 #define BHND_COREID_MINIMAC 0x823 /* MINI MAC/phy core */ 467 #define BHND_COREID_ARM11 0x824 /* ARM 1176 core */ 468 #define BHND_COREID_ARM7S 0x825 /* ARM7tdmi-s core */ 469 #define BHND_COREID_LPPHY 0x826 /* 802.11a/b/g phy core */ 470 #define BHND_COREID_PMU 0x827 /* PMU core */ 471 #define BHND_COREID_SSNPHY 0x828 /* 802.11n single-stream phy core */ 472 #define BHND_COREID_SDIOD 0x829 /* SDIO device core */ 473 #define BHND_COREID_ARMCM3 0x82a /* ARM Cortex M3 core */ 474 #define BHND_COREID_HTPHY 0x82b /* 802.11n 4x4 phy core */ 475 #define BHND_COREID_MIPS74K 0x82c /* mips 74k core */ 476 #define BHND_COREID_GMAC 0x82d /* Gigabit MAC core */ 477 #define BHND_COREID_DMEMC 0x82e /* DDR1/2 memory controller core */ 478 #define BHND_COREID_PCIERC 0x82f /* PCIE Root Complex core */ 479 #define BHND_COREID_OCP 0x830 /* OCP2OCP bridge core */ 480 #define BHND_COREID_SC 0x831 /* shared common core */ 481 #define BHND_COREID_AHB 0x832 /* OCP2AHB bridge core */ 482 #define BHND_COREID_SPIH 0x833 /* SPI host core */ 483 #define BHND_COREID_I2S 0x834 /* I2S core */ 484 #define BHND_COREID_DMEMS 0x835 /* SDR/DDR1 memory controller core */ 485 #define BHND_COREID_UBUS_SHIM 0x837 /* SHIM component in ubus/6362 */ 486 #define BHND_COREID_PCIE2 0x83c /* pci express (gen2) core */ 487 /* ARM/AMBA Core IDs */ 488 #define BHND_COREID_APB_BRIDGE 0x135 /* BP135 AMBA AXI-APB bridge */ 489 #define BHND_COREID_PL301 0x301 /* PL301 AMBA AXI Interconnect */ 490 #define BHND_COREID_EROM 0x366 /* Enumeration ROM */ 491 #define BHND_COREID_OOB_ROUTER 0x367 /* OOB router core ID */ 492 #define BHND_COREID_AXI_UNMAPPED 0xfff /* AXI "Default Slave"; maps all unused address 493 * ranges, returning DECERR on read or write. */ 494 /* Northstar Plus and BCM4706 Core IDs */ 495 #define BHND_COREID_4706_CC 0x500 /* chipcommon core */ 496 #define BHND_COREID_NS_PCIE2 0x501 /* pci express (gen2) core */ 497 #define BHND_COREID_NS_DMA 0x502 /* dma core */ 498 #define BHND_COREID_NS_SDIO 0x503 /* sdio host core */ 499 #define BHND_COREID_NS_USB20H 0x504 /* usb 2.0 host core */ 500 #define BHND_COREID_NS_USB30H 0x505 /* usb 3.0 host core */ 501 #define BHND_COREID_NS_A9JTAG 0x506 /* ARM Cortex A9 JTAG core */ 502 #define BHND_COREID_NS_DDR23_MEMC 0x507 /* DDR2/3 cadence/denali memory controller core () */ 503 #define BHND_COREID_NS_ROM 0x508 /* device ROM core */ 504 #define BHND_COREID_NS_NAND 0x509 /* NAND flash controller core */ 505 #define BHND_COREID_NS_QSPI 0x50a /* QSPI flash controller core */ 506 #define BHND_COREID_NS_CC_B 0x50b /* chipcommon `b' (auxiliary) core */ 507 #define BHND_COREID_4706_SOCRAM 0x50e /* internal memory core */ 508 #define BHND_COREID_IHOST_ARMCA9 0x510 /* ARM Cortex A9 core */ 509 #define BHND_COREID_4706_GMAC_CMN 0x5dc /* Gigabit MAC common core */ 510 #define BHND_COREID_4706_GMAC 0x52d /* Gigabit MAC core */ 511 #define BHND_COREID_AMEMC 0x52e /* DDR1/2 cadence/denali memory controller core */ 512 513 /* ARM PrimeCell Peripherial IDs. These were derived from inspection of the 514 * PrimeCell-compatible BCM4331 cores, but due to lack of documentation, the 515 * surmised core name/description may be incorrect. */ 516 #define BHND_PRIMEID_EROM 0x364 /* Enumeration ROM's primecell ID */ 517 #define BHND_PRIMEID_SWRAP 0x368 /* PL368 Device Management Interface (Slave) */ 518 #define BHND_PRIMEID_MWRAP 0x369 /* PL369 Device Management Interface (Master) */ 519 520 /* Core HW Revision Numbers */ 521 #define BHND_HWREV_INVALID 0xFF /* Invalid hardware revision ID */ 522 523 /* Chip Types */ 524 #define BHND_CHIPTYPE_SIBA 0 /**< siba(4) interconnect */ 525 #define BHND_CHIPTYPE_BCMA 1 /**< bcma(4) interconnect */ 526 #define BHND_CHIPTYPE_UBUS 2 /**< ubus interconnect found in bcm63xx devices */ 527 #define BHND_CHIPTYPE_BCMA_ALT 3 /**< bcma(4) interconnect */ 528 529 /** Evaluates to true if @p _type is a BCMA or BCMA-compatible interconenct */ 530 #define BHND_CHIPTYPE_IS_BCMA_COMPATIBLE(_type) \ 531 ((_type) == BHND_CHIPTYPE_BCMA || \ 532 (_type) == BHND_CHIPTYPE_BCMA_ALT || \ 533 (_type) == BHND_CHIPTYPE_UBUS) 534 535 /** Evaluates to true if @p _type uses a BCMA EROM table */ 536 #define BHND_CHIPTYPE_HAS_EROM(_type) \ 537 BHND_CHIPTYPE_IS_BCMA_COMPATIBLE(_type) 538 539 /* Boardflags */ 540 #define BHND_BFL_BTC2WIRE 0x00000001 /* old 2wire Bluetooth coexistence, OBSOLETE */ 541 #define BHND_BFL_BTCOEX 0x00000001 /* Board supports BTCOEX */ 542 #define BHND_BFL_PACTRL 0x00000002 /* Board has gpio 9 controlling the PA */ 543 #define BHND_BFL_AIRLINEMODE 0x00000004 /* Board implements gpio 13 radio disable indication, UNUSED */ 544 #define BHND_BFL_ADCDIV 0x00000008 /* Board has the rssi ADC divider */ 545 #define BHND_BFL_DIS_256QAM 0x00000008 546 #define BHND_BFL_ENETROBO 0x00000010 /* Board has robo switch or core */ 547 #define BHND_BFL_NOPLLDOWN 0x00000020 /* Not ok to power down the chip pll and oscillator */ 548 #define BHND_BFL_CCKHIPWR 0x00000040 /* Can do high-power CCK transmission */ 549 #define BHND_BFL_ENETADM 0x00000080 /* Board has ADMtek switch */ 550 #define BHND_BFL_ENETVLAN 0x00000100 /* Board has VLAN capability */ 551 #define BHND_BFL_LTECOEX 0x00000200 /* Board has LTE coex capability */ 552 #define BHND_BFL_NOPCI 0x00000400 /* Board leaves PCI floating */ 553 #define BHND_BFL_FEM 0x00000800 /* Board supports the Front End Module */ 554 #define BHND_BFL_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ 555 #define BHND_BFL_HGPA 0x00002000 /* Board has a high gain PA */ 556 #define BHND_BFL_BTC2WIRE_ALTGPIO 0x00004000 557 /* Board's BTC 2wire is in the alternate gpios OBSLETE */ 558 #define BHND_BFL_ALTIQ 0x00008000 /* Alternate I/Q settings */ 559 #define BHND_BFL_NOPA 0x00010000 /* Board has no PA */ 560 #define BHND_BFL_RSSIINV 0x00020000 /* Board's RSSI uses positive slope(not TSSI) */ 561 #define BHND_BFL_PAREF 0x00040000 /* Board uses the PARef LDO */ 562 #define BHND_BFL_3TSWITCH 0x00080000 /* Board uses a triple throw switch shared with BT */ 563 #define BHND_BFL_PHASESHIFT 0x00100000 /* Board can support phase shifter */ 564 #define BHND_BFL_BUCKBOOST 0x00200000 /* Power topology uses BUCKBOOST */ 565 #define BHND_BFL_FEM_BT 0x00400000 /* Board has FEM and switch to share antenna w/ BT */ 566 #define BHND_BFL_RXCHAIN_OFF_BT 0x00400000 /* one rxchain is to be shut off when BT is active */ 567 #define BHND_BFL_NOCBUCK 0x00800000 /* Power topology doesn't use CBUCK */ 568 #define BHND_BFL_CCKFAVOREVM 0x01000000 /* Favor CCK EVM over spectral mask */ 569 #define BHND_BFL_PALDO 0x02000000 /* Power topology uses PALDO */ 570 #define BHND_BFL_LNLDO2_2P5 0x04000000 /* Select 2.5V as LNLDO2 output voltage */ 571 #define BHND_BFL_FASTPWR 0x08000000 572 #define BHND_BFL_UCPWRCTL_MININDX 0x08000000 /* Enforce min power index to avoid FEM damage */ 573 #define BHND_BFL_EXTLNA_5GHZ 0x10000000 /* Board has an external LNA in 5GHz band */ 574 #define BHND_BFL_TRSW_1BY2 0x20000000 /* Board has 2 TRSW's in 1by2 designs */ 575 #define BHND_BFL_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ 576 #define BHND_BFL_LO_TRSW_R_5GHZ 0x40000000 /* In 5G do not throw TRSW to T for clipLO gain */ 577 #define BHND_BFL_ELNA_GAINDEF 0x80000000 /* Backoff InitGain based on elna_2g/5g field 578 * when this flag is set 579 */ 580 #define BHND_BFL_EXTLNA_TX 0x20000000 /* Temp boardflag to indicate to */ 581 582 /* Boardflags2 */ 583 #define BHND_BFL2_RXBB_INT_REG_DIS 0x00000001 /* Board has an external rxbb regulator */ 584 #define BHND_BFL2_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ 585 #define BHND_BFL2_TXPWRCTRL_EN 0x00000004 /* Board permits enabling TX Power Control */ 586 #define BHND_BFL2_2X4_DIV 0x00000008 /* Board supports the 2X4 diversity switch */ 587 #define BHND_BFL2_5G_PWRGAIN 0x00000010 /* Board supports 5G band power gain */ 588 #define BHND_BFL2_PCIEWAR_OVR 0x00000020 /* Board overrides ASPM and Clkreq settings */ 589 #define BHND_BFL2_CAESERS_BRD 0x00000040 /* Board is Caesers brd (unused by sw) */ 590 #define BHND_BFL2_BTC3WIRE 0x00000080 /* Board support legacy 3 wire or 4 wire */ 591 #define BHND_BFL2_BTCLEGACY 0x00000080 /* Board support legacy 3/4 wire, to replace 592 * BHND_BFL2_BTC3WIRE 593 */ 594 #define BHND_BFL2_SKWRKFEM_BRD 0x00000100 /* 4321mcm93 board uses Skyworks FEM */ 595 #define BHND_BFL2_SPUR_WAR 0x00000200 /* Board has a WAR for clock-harmonic spurs */ 596 #define BHND_BFL2_GPLL_WAR 0x00000400 /* Flag to narrow G-band PLL loop b/w */ 597 #define BHND_BFL2_TRISTATE_LED 0x00000800 /* Tri-state the LED */ 598 #define BHND_BFL2_SINGLEANT_CCK 0x00001000 /* Tx CCK pkts on Ant 0 only */ 599 #define BHND_BFL2_2G_SPUR_WAR 0x00002000 /* WAR to reduce and avoid clock-harmonic spurs in 2G */ 600 #define BHND_BFL2_BPHY_ALL_TXCORES 0x00004000 /* Transmit bphy frames using all tx cores */ 601 #define BHND_BFL2_FCC_BANDEDGE_WAR 0x00008000 /* Activates WAR to improve FCC bandedge performance */ 602 #define BHND_BFL2_GPLL_WAR2 0x00010000 /* Flag to widen G-band PLL loop b/w */ 603 #define BHND_BFL2_IPALVLSHIFT_3P3 0x00020000 604 #define BHND_BFL2_INTERNDET_TXIQCAL 0x00040000 /* Use internal envelope detector for TX IQCAL */ 605 #define BHND_BFL2_XTALBUFOUTEN 0x00080000 /* Keep the buffered Xtal output from radio on */ 606 /* Most drivers will turn it off without this flag */ 607 /* to save power. */ 608 609 #define BHND_BFL2_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are controlled by analog PA ctrl lines */ 610 #define BHND_BFL2_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are controlled by analog PA ctrl lines */ 611 #define BHND_BFL2_ELNACTRL_TRSW_2G 0x00400000 /* AZW4329: 2G gmode_elna_gain controls TR Switch */ 612 #define BHND_BFL2_BT_SHARE_ANT0 0x00800000 /* WLAN/BT share antenna 0 */ 613 #define BHND_BFL2_BT_SHARE_BM_BIT0 0x00800000 /* bit 0 of WLAN/BT shared core bitmap */ 614 #define BHND_BFL2_TEMPSENSE_HIGHER 0x01000000 /* The tempsense threshold can sustain higher value 615 * than programmed. The exact delta is decided by 616 * driver per chip/boardtype. This can be used 617 * when tempsense qualification happens after shipment 618 */ 619 #define BHND_BFL2_BTC3WIREONLY 0x02000000 /* standard 3 wire btc only. 4 wire not supported */ 620 #define BHND_BFL2_PWR_NOMINAL 0x04000000 /* 0: power reduction on, 1: no power reduction */ 621 #define BHND_BFL2_EXTLNA_PWRSAVE 0x08000000 /* boardflag to enable ucode to apply power save 622 * ucode control of eLNA during Tx */ 623 #define BHND_BFL2_4313_RADIOREG 0x10000000 624 /* board rework */ 625 #define BHND_BFL2_DYNAMIC_VMID 0x10000000 /* boardflag to enable dynamic Vmid idle TSSI CAL */ 626 #define BHND_BFL2_SDR_EN 0x20000000 /* SDR enabled or disabled */ 627 #define BHND_BFL2_LNA1BYPFORTR2G 0x40000000 /* acphy, enable lna1 bypass for clip gain, 2g */ 628 #define BHND_BFL2_LNA1BYPFORTR5G 0x80000000 /* acphy, enable lna1 bypass for clip gain, 5g */ 629 630 /* SROM 11 - 11ac boardflag definitions */ 631 #define BHND_BFL_SROM11_BTCOEX 0x00000001 /* Board supports BTCOEX */ 632 #define BHND_BFL_SROM11_WLAN_BT_SH_XTL 0x00000002 /* bluetooth and wlan share same crystal */ 633 #define BHND_BFL_SROM11_EXTLNA 0x00001000 /* Board has an external LNA in 2.4GHz band */ 634 #define BHND_BFL_SROM11_EXTLNA_5GHZ 0x10000000 /* Board has an external LNA in 5GHz band */ 635 #define BHND_BFL_SROM11_GAINBOOSTA01 0x20000000 /* 5g Gainboost for core0 and core1 */ 636 #define BHND_BFL2_SROM11_APLL_WAR 0x00000002 /* Flag to implement alternative A-band PLL settings */ 637 #define BHND_BFL2_SROM11_ANAPACTRL_2G 0x00100000 /* 2G ext PAs are ctrl-ed by analog PA ctrl lines */ 638 #define BHND_BFL2_SROM11_ANAPACTRL_5G 0x00200000 /* 5G ext PAs are ctrl-ed by analog PA ctrl lines */ 639 640 /* Boardflags3 */ 641 #define BHND_BFL3_FEMCTRL_SUB 0x00000007 /* acphy, subrevs of femctrl on top of srom_femctrl */ 642 #define BHND_BFL3_RCAL_WAR 0x00000008 /* acphy, rcal war active on this board (4335a0) */ 643 #define BHND_BFL3_TXGAINTBLID 0x00000070 /* acphy, txgain table id */ 644 #define BHND_BFL3_TXGAINTBLID_SHIFT 0x4 /* acphy, txgain table id shift bit */ 645 #define BHND_BFL3_TSSI_DIV_WAR 0x00000080 /* acphy, Separate paparam for 20/40/80 */ 646 #define BHND_BFL3_TSSI_DIV_WAR_SHIFT 0x7 /* acphy, Separate paparam for 20/40/80 shift bit */ 647 #define BHND_BFL3_FEMTBL_FROM_NVRAM 0x00000100 /* acphy, femctrl table is read from nvram */ 648 #define BHND_BFL3_FEMTBL_FROM_NVRAM_SHIFT 0x8 /* acphy, femctrl table is read from nvram */ 649 #define BHND_BFL3_AGC_CFG_2G 0x00000200 /* acphy, gain control configuration for 2G */ 650 #define BHND_BFL3_AGC_CFG_5G 0x00000400 /* acphy, gain control configuration for 5G */ 651 #define BHND_BFL3_PPR_BIT_EXT 0x00000800 /* acphy, bit position for 1bit extension for ppr */ 652 #define BHND_BFL3_PPR_BIT_EXT_SHIFT 11 /* acphy, bit shift for 1bit extension for ppr */ 653 #define BHND_BFL3_BBPLL_SPR_MODE_DIS 0x00001000 /* acphy, disables bbpll spur modes */ 654 #define BHND_BFL3_RCAL_OTP_VAL_EN 0x00002000 /* acphy, to read rcal_trim value from otp */ 655 #define BHND_BFL3_2GTXGAINTBL_BLANK 0x00004000 /* acphy, blank the first X ticks of 2g gaintbl */ 656 #define BHND_BFL3_2GTXGAINTBL_BLANK_SHIFT 14 /* acphy, blank the first X ticks of 2g gaintbl */ 657 #define BHND_BFL3_5GTXGAINTBL_BLANK 0x00008000 /* acphy, blank the first X ticks of 5g gaintbl */ 658 #define BHND_BFL3_5GTXGAINTBL_BLANK_SHIFT 15 /* acphy, blank the first X ticks of 5g gaintbl */ 659 #define BHND_BFL3_BT_SHARE_BM_BIT1 0x40000000 /* bit 1 of WLAN/BT shared core bitmap */ 660 #define BHND_BFL3_PHASETRACK_MAX_ALPHABETA 0x00010000 /* acphy, to max out alpha,beta to 511 */ 661 #define BHND_BFL3_PHASETRACK_MAX_ALPHABETA_SHIFT 16 /* acphy, to max out alpha,beta to 511 */ 662 #define BHND_BFL3_BT_SHARE_BM_BIT1 0x40000000 /* bit 1 of WLAN/BT shared core bitmap */ 663 #define BHND_BFL3_EN_NONBRCM_TXBF 0x10000000 /* acphy, enable non-brcm TXBF */ 664 #define BHND_BFL3_EN_P2PLINK_TXBF 0x20000000 /* acphy, enable TXBF in p2p links */ 665 666 /* board specific GPIO assignment, gpio 0-3 are also customer-configurable led */ 667 #define BHND_GPIO_BOARD_BTC3W_IN 0x850 /* bit 4 is RF_ACTIVE, bit 6 is STATUS, bit 11 is PRI */ 668 #define BHND_GPIO_BOARD_BTC3W_OUT 0x020 /* bit 5 is TX_CONF */ 669 #define BHND_GPIO_BOARD_BTCMOD_IN 0x010 /* bit 4 is the alternate BT Coexistence Input */ 670 #define BHND_GPIO_BOARD_BTCMOD_OUT 0x020 /* bit 5 is the alternate BT Coexistence Out */ 671 #define BHND_GPIO_BOARD_BTC_IN 0x080 /* bit 7 is BT Coexistence Input */ 672 #define BHND_GPIO_BOARD_BTC_OUT 0x100 /* bit 8 is BT Coexistence Out */ 673 #define BHND_GPIO_BOARD_PACTRL 0x200 /* bit 9 controls the PA on new 4306 boards */ 674 #define BHND_GPIO_BOARD_12 0x1000 /* gpio 12 */ 675 #define BHND_GPIO_BOARD_13 0x2000 /* gpio 13 */ 676 #define BHND_GPIO_BOARD_BTC4_IN 0x0800 /* gpio 11, coex4, in */ 677 #define BHND_GPIO_BOARD_BTC4_BT 0x2000 /* gpio 12, coex4, bt active */ 678 #define BHND_GPIO_BOARD_BTC4_STAT 0x4000 /* gpio 14, coex4, status */ 679 #define BHND_GPIO_BOARD_BTC4_WLAN 0x8000 /* gpio 15, coex4, wlan active */ 680 #define BHND_GPIO_BOARD_1_WLAN_PWR 0x02 /* throttle WLAN power on X21 board */ 681 #define BHND_GPIO_BOARD_3_WLAN_PWR 0x08 /* throttle WLAN power on X28 board */ 682 #define BHND_GPIO_BOARD_4_WLAN_PWR 0x10 /* throttle WLAN power on X19 board */ 683 684 #define BHND_GPIO_BTC4W_OUT_4312 0x010 /* bit 4 is BT_IODISABLE */ 685 #define BHND_GPIO_BTC4W_OUT_43224 0x020 /* bit 5 is BT_IODISABLE */ 686 #define BHND_GPIO_BTC4W_OUT_43224_SHARED 0x0e0 /* bit 5 is BT_IODISABLE */ 687 #define BHND_GPIO_BTC4W_OUT_43225 0x0e0 /* bit 5 BT_IODISABLE, bit 6 SW_BT, bit 7 SW_WL */ 688 #define BHND_GPIO_BTC4W_OUT_43421 0x020 /* bit 5 is BT_IODISABLE */ 689 #define BHND_GPIO_BTC4W_OUT_4313 0x060 /* bit 5 SW_BT, bit 6 SW_WL */ 690 #define BHND_GPIO_BTC4W_OUT_4331_SHARED 0x010 /* GPIO 4 */ 691 692 /* Board Types */ 693 #define BHND_BOARD_BU4710 0x0400 694 #define BHND_BOARD_VSIM4710 0x0401 695 #define BHND_BOARD_QT4710 0x0402 696 697 #define BHND_BOARD_BU4309 0x040a 698 #define BHND_BOARD_BCM94309CB 0x040b 699 #define BHND_BOARD_BCM94309MP 0x040c 700 #define BHND_BOARD_BCM4309AP 0x040d 701 702 #define BHND_BOARD_BCM94302MP 0x040e 703 704 #define BHND_BOARD_BU4306 0x0416 705 #define BHND_BOARD_BCM94306CB 0x0417 706 #define BHND_BOARD_BCM94306MP 0x0418 707 708 #define BHND_BOARD_BCM94710D 0x041a 709 #define BHND_BOARD_BCM94710R1 0x041b 710 #define BHND_BOARD_BCM94710R4 0x041c 711 #define BHND_BOARD_BCM94710AP 0x041d 712 713 #define BHND_BOARD_BU2050 0x041f 714 715 #define BHND_BOARD_BCM94309G 0x0421 716 717 #define BHND_BOARD_BU4704 0x0423 718 #define BHND_BOARD_BU4702 0x0424 719 720 #define BHND_BOARD_BCM94306PC 0x0425 /* pcmcia 3.3v 4306 card */ 721 722 #define BHND_BOARD_BCM94702MN 0x0428 723 724 /* BCM4702 1U CompactPCI Board */ 725 #define BHND_BOARD_BCM94702CPCI 0x0429 726 727 /* BCM4702 with BCM95380 VLAN Router */ 728 #define BHND_BOARD_BCM95380RR 0x042a 729 730 /* cb4306 with SiGe PA */ 731 #define BHND_BOARD_BCM94306CBSG 0x042b 732 733 /* cb4306 with SiGe PA */ 734 #define BHND_BOARD_PCSG94306 0x042d 735 736 /* bu4704 with sdram */ 737 #define BHND_BOARD_BU4704SD 0x042e 738 739 /* Dual 11a/11g Router */ 740 #define BHND_BOARD_BCM94704AGR 0x042f 741 742 /* 11a-only minipci */ 743 #define BHND_BOARD_BCM94308MP 0x0430 744 745 #define BHND_BOARD_BU4712 0x0444 746 #define BHND_BOARD_BU4712SD 0x045d 747 #define BHND_BOARD_BU4712L 0x045f 748 749 /* BCM4712 boards */ 750 #define BHND_BOARD_BCM94712AP 0x0445 751 #define BHND_BOARD_BCM94712P 0x0446 752 753 /* BCM4318 boards */ 754 #define BHND_BOARD_BU4318 0x0447 755 #define BHND_BOARD_CB4318 0x0448 756 #define BHND_BOARD_MPG4318 0x0449 757 #define BHND_BOARD_MP4318 0x044a 758 #define BHND_BOARD_SD4318 0x044b 759 760 /* BCM4313 boards */ 761 #define BHND_BOARD_BCM94313BU 0x050f 762 #define BHND_BOARD_BCM94313HM 0x0510 763 #define BHND_BOARD_BCM94313EPA 0x0511 764 #define BHND_BOARD_BCM94313HMG 0x051C 765 766 /* BCM63XX boards */ 767 #define BHND_BOARD_BCM96338 0x6338 768 #define BHND_BOARD_BCM96348 0x6348 769 #define BHND_BOARD_BCM96358 0x6358 770 #define BHND_BOARD_BCM96368 0x6368 771 772 /* Another mp4306 with SiGe */ 773 #define BHND_BOARD_BCM94306P 0x044c 774 775 /* mp4303 */ 776 #define BHND_BOARD_BCM94303MP 0x044e 777 778 /* mpsgh4306 */ 779 #define BHND_BOARD_BCM94306MPSGH 0x044f 780 781 /* BRCM 4306 w/ Front End Modules */ 782 #define BHND_BOARD_BCM94306MPM 0x0450 783 #define BHND_BOARD_BCM94306MPL 0x0453 784 785 /* 4712agr */ 786 #define BHND_BOARD_BCM94712AGR 0x0451 787 788 /* pcmcia 4303 */ 789 #define BHND_BOARD_PC4303 0x0454 790 791 /* 5350K */ 792 #define BHND_BOARD_BCM95350K 0x0455 793 794 /* 5350R */ 795 #define BHND_BOARD_BCM95350R 0x0456 796 797 /* 4306mplna */ 798 #define BHND_BOARD_BCM94306MPLNA 0x0457 799 800 /* 4320 boards */ 801 #define BHND_BOARD_BU4320 0x0458 802 #define BHND_BOARD_BU4320S 0x0459 803 #define BHND_BOARD_BCM94320PH 0x045a 804 805 /* 4306mph */ 806 #define BHND_BOARD_BCM94306MPH 0x045b 807 808 /* 4306pciv */ 809 #define BHND_BOARD_BCM94306PCIV 0x045c 810 811 #define BHND_BOARD_BU4712SD 0x045d 812 813 #define BHND_BOARD_BCM94320PFLSH 0x045e 814 815 #define BHND_BOARD_BU4712L 0x045f 816 #define BHND_BOARD_BCM94712LGR 0x0460 817 #define BHND_BOARD_BCM94320R 0x0461 818 819 #define BHND_BOARD_BU5352 0x0462 820 821 #define BHND_BOARD_BCM94318MPGH 0x0463 822 823 #define BHND_BOARD_BU4311 0x0464 824 #define BHND_BOARD_BCM94311MC 0x0465 825 #define BHND_BOARD_BCM94311MCAG 0x0466 826 827 #define BHND_BOARD_BCM95352GR 0x0467 828 829 /* bcm95351agr */ 830 #define BHND_BOARD_BCM95351AGR 0x0470 831 832 /* bcm94704mpcb */ 833 #define BHND_BOARD_BCM94704MPCB 0x0472 834 835 /* 4785 boards */ 836 #define BHND_BOARD_BU4785 0x0478 837 838 /* 4321 boards */ 839 #define BHND_BOARD_BCM4321BU 0x046b 840 #define BHND_BOARD_BCM4321BUE 0x047c 841 #define BHND_BOARD_BCM4321MP 0x046c 842 #define BHND_BOARD_BCM4321CB2 0x046d 843 #define BHND_BOARD_BCM4321CB2_AG 0x0066 844 #define BHND_BOARD_BCM4321MC 0x046e 845 846 /* 4328 boards */ 847 #define BHND_BOARD_BU4328 0x0481 848 #define BHND_BOARD_BCM4328SDG 0x0482 849 #define BHND_BOARD_BCM4328SDAG 0x0483 850 #define BHND_BOARD_BCM4328UG 0x0484 851 #define BHND_BOARD_BCM4328UAG 0x0485 852 #define BHND_BOARD_BCM4328PC 0x0486 853 #define BHND_BOARD_BCM4328CF 0x0487 854 855 /* 4325 boards */ 856 #define BHND_BOARD_BCM94325DEVBU 0x0490 857 #define BHND_BOARD_BCM94325BGABU 0x0491 858 859 #define BHND_BOARD_BCM94325SDGWB 0x0492 860 861 #define BHND_BOARD_BCM94325SDGMDL 0x04aa 862 #define BHND_BOARD_BCM94325SDGMDL2 0x04c6 863 #define BHND_BOARD_BCM94325SDGMDL3 0x04c9 864 865 #define BHND_BOARD_BCM94325SDABGWBA 0x04e1 866 867 /* 4322 boards */ 868 #define BHND_BOARD_BCM94322MC 0x04a4 869 #define BHND_BOARD_BCM94322USB 0x04a8 /* dualband */ 870 #define BHND_BOARD_BCM94322HM 0x04b0 871 #define BHND_BOARD_BCM94322USB2D 0x04bf /* single band discrete front end */ 872 873 /* 4312 boards */ 874 #define BHND_BOARD_BCM4312MCGSG 0x04b5 875 876 /* 4315 boards */ 877 #define BHND_BOARD_BCM94315DEVBU 0x04c2 878 #define BHND_BOARD_BCM94315USBGP 0x04c7 879 #define BHND_BOARD_BCM94315BGABU 0x04ca 880 #define BHND_BOARD_BCM94315USBGP41 0x04cb 881 882 /* 4319 boards */ 883 #define BHND_BOARD_BCM94319DEVBU 0X04e5 884 #define BHND_BOARD_BCM94319USB 0X04e6 885 #define BHND_BOARD_BCM94319SD 0X04e7 886 887 /* 4716 boards */ 888 #define BHND_BOARD_BCM94716NR2 0x04cd 889 890 /* 4319 boards */ 891 #define BHND_BOARD_BCM94319DEVBU 0X04e5 892 #define BHND_BOARD_BCM94319USBNP4L 0X04e6 893 #define BHND_BOARD_BCM94319WLUSBN4L 0X04e7 894 #define BHND_BOARD_BCM94319SDG 0X04ea 895 #define BHND_BOARD_BCM94319LCUSBSDN4L 0X04eb 896 #define BHND_BOARD_BCM94319USBB 0x04ee 897 #define BHND_BOARD_BCM94319LCSDN4L 0X0507 898 #define BHND_BOARD_BCM94319LSUSBN4L 0X0508 899 #define BHND_BOARD_BCM94319SDNA4L 0X0517 900 #define BHND_BOARD_BCM94319SDELNA4L 0X0518 901 #define BHND_BOARD_BCM94319SDELNA6L 0X0539 902 #define BHND_BOARD_BCM94319ARCADYAN 0X0546 903 #define BHND_BOARD_BCM94319WINDSOR 0x0561 904 #define BHND_BOARD_BCM94319MLAP 0x0562 905 #define BHND_BOARD_BCM94319SDNA 0x058b 906 #define BHND_BOARD_BCM94319BHEMU3 0x0563 907 #define BHND_BOARD_BCM94319SDHMB 0x058c 908 #define BHND_BOARD_BCM94319SDBREF 0x05a1 909 #define BHND_BOARD_BCM94319USBSDB 0x05a2 910 911 /* 4329 boards */ 912 #define BHND_BOARD_BCM94329AGB 0X04b9 913 #define BHND_BOARD_BCM94329TDKMDL1 0X04ba 914 #define BHND_BOARD_BCM94329TDKMDL11 0X04fc 915 #define BHND_BOARD_BCM94329OLYMPICN18 0X04fd 916 #define BHND_BOARD_BCM94329OLYMPICN90 0X04fe 917 #define BHND_BOARD_BCM94329OLYMPICN90U 0X050c 918 #define BHND_BOARD_BCM94329OLYMPICN90M 0X050b 919 #define BHND_BOARD_BCM94329AGBF 0X04ff 920 #define BHND_BOARD_BCM94329OLYMPICX17 0X0504 921 #define BHND_BOARD_BCM94329OLYMPICX17M 0X050a 922 #define BHND_BOARD_BCM94329OLYMPICX17U 0X0509 923 #define BHND_BOARD_BCM94329OLYMPICUNO 0X0564 924 #define BHND_BOARD_BCM94329MOTOROLA 0X0565 925 #define BHND_BOARD_BCM94329OLYMPICLOCO 0X0568 926 927 /* 4336 SDIO board types */ 928 #define BHND_BOARD_BCM94336SD_WLBGABU 0x0511 929 #define BHND_BOARD_BCM94336SD_WLBGAREF 0x0519 930 #define BHND_BOARD_BCM94336SDGP 0x0538 931 #define BHND_BOARD_BCM94336SDG 0x0519 932 #define BHND_BOARD_BCM94336SDGN 0x0538 933 #define BHND_BOARD_BCM94336SDGFC 0x056B 934 935 /* 4330 SDIO board types */ 936 #define BHND_BOARD_BCM94330SDG 0x0528 937 #define BHND_BOARD_BCM94330SD_FCBGABU 0x052e 938 #define BHND_BOARD_BCM94330SD_WLBGABU 0x052f 939 #define BHND_BOARD_BCM94330SD_FCBGA 0x0530 940 #define BHND_BOARD_BCM94330FCSDAGB 0x0532 941 #define BHND_BOARD_BCM94330OLYMPICAMG 0x0549 942 #define BHND_BOARD_BCM94330OLYMPICAMGEPA 0x054F 943 #define BHND_BOARD_BCM94330OLYMPICUNO3 0x0551 944 #define BHND_BOARD_BCM94330WLSDAGB 0x0547 945 #define BHND_BOARD_BCM94330CSPSDAGBB 0x054A 946 947 /* 43224 boards */ 948 #define BHND_BOARD_BCM943224X21 0x056e 949 #define BHND_BOARD_BCM943224X21_FCC 0x00d1 950 #define BHND_BOARD_BCM943224X21B 0x00e9 951 #define BHND_BOARD_BCM943224M93 0x008b 952 #define BHND_BOARD_BCM943224M93A 0x0090 953 #define BHND_BOARD_BCM943224X16 0x0093 954 #define BHND_BOARD_BCM94322X9 0x008d 955 #define BHND_BOARD_BCM94322M35e 0x008e 956 957 /* 43228 Boards */ 958 #define BHND_BOARD_BCM943228BU8 0x0540 959 #define BHND_BOARD_BCM943228BU9 0x0541 960 #define BHND_BOARD_BCM943228BU 0x0542 961 #define BHND_BOARD_BCM943227HM4L 0x0543 962 #define BHND_BOARD_BCM943227HMB 0x0544 963 #define BHND_BOARD_BCM943228HM4L 0x0545 964 #define BHND_BOARD_BCM943228SD 0x0573 965 966 /* 43239 Boards */ 967 #define BHND_BOARD_BCM943239MOD 0x05ac 968 #define BHND_BOARD_BCM943239REF 0x05aa 969 970 /* 4331 boards */ 971 #define BHND_BOARD_BCM94331X19 0x00D6 /* X19B */ 972 #define BHND_BOARD_BCM94331X28 0x00E4 /* X28 */ 973 #define BHND_BOARD_BCM94331X28B 0x010E /* X28B */ 974 #define BHND_BOARD_BCM94331PCIEBT3Ax BCM94331X28 975 #define BHND_BOARD_BCM94331X12_2G 0x00EC /* X12 2G */ 976 #define BHND_BOARD_BCM94331X12_5G 0x00ED /* X12 5G */ 977 #define BHND_BOARD_BCM94331X29B 0x00EF /* X29B */ 978 #define BHND_BOARD_BCM94331X29D 0x010F /* X29D */ 979 #define BHND_BOARD_BCM94331CSAX BCM94331X29B 980 #define BHND_BOARD_BCM94331X19C 0x00F5 /* X19C */ 981 #define BHND_BOARD_BCM94331X33 0x00F4 /* X33 */ 982 #define BHND_BOARD_BCM94331BU 0x0523 983 #define BHND_BOARD_BCM94331S9BU 0x0524 984 #define BHND_BOARD_BCM94331MC 0x0525 985 #define BHND_BOARD_BCM94331MCI 0x0526 986 #define BHND_BOARD_BCM94331PCIEBT4 0x0527 987 #define BHND_BOARD_BCM94331HM 0x0574 988 #define BHND_BOARD_BCM94331PCIEDUAL 0x059B 989 #define BHND_BOARD_BCM94331MCH5 0x05A9 990 #define BHND_BOARD_BCM94331CS 0x05C6 991 #define BHND_BOARD_BCM94331CD 0x05DA 992 993 /* 4314 Boards */ 994 #define BHND_BOARD_BCM94314BU 0x05b1 995 996 /* 53572 Boards */ 997 #define BHND_BOARD_BCM953572BU 0x058D 998 #define BHND_BOARD_BCM953572NR2 0x058E 999 #define BHND_BOARD_BCM947188NR2 0x058F 1000 #define BHND_BOARD_BCM953572SDRNR2 0x0590 1001 1002 /* 43236 boards */ 1003 #define BHND_BOARD_BCM943236OLYMPICSULLEY 0x594 1004 #define BHND_BOARD_BCM943236PREPROTOBLU2O3 0x5b9 1005 #define BHND_BOARD_BCM943236USBELNA 0x5f8 1006 1007 /* 4314 Boards */ 1008 #define BHND_BOARD_BCM94314BUSDIO 0x05c8 1009 #define BHND_BOARD_BCM94314BGABU 0x05c9 1010 #define BHND_BOARD_BCM94314HMEPA 0x05ca 1011 #define BHND_BOARD_BCM94314HMEPABK 0x05cb 1012 #define BHND_BOARD_BCM94314SUHMEPA 0x05cc 1013 #define BHND_BOARD_BCM94314SUHM 0x05cd 1014 #define BHND_BOARD_BCM94314HM 0x05d1 1015 1016 /* 4334 Boards */ 1017 #define BHND_BOARD_BCM94334FCAGBI 0x05df 1018 #define BHND_BOARD_BCM94334WLAGBI 0x05dd 1019 1020 /* 4335 Boards */ 1021 #define BHND_BOARD_BCM94335X52 0x0114 1022 1023 /* 4345 Boards */ 1024 #define BHND_BOARD_BCM94345 0x0687 1025 1026 /* 4360 Boards */ 1027 #define BHND_BOARD_BCM94360X52C 0X0117 1028 #define BHND_BOARD_BCM94360X52D 0X0137 1029 #define BHND_BOARD_BCM94360X29C 0X0112 1030 #define BHND_BOARD_BCM94360X29CP2 0X0134 1031 #define BHND_BOARD_BCM94360X51 0x0111 1032 #define BHND_BOARD_BCM94360X51P2 0x0129 1033 #define BHND_BOARD_BCM94360X51A 0x0135 1034 #define BHND_BOARD_BCM94360X51B 0x0136 1035 #define BHND_BOARD_BCM94360CS 0x061B 1036 #define BHND_BOARD_BCM94360J28_D11AC2G 0x0c00 1037 #define BHND_BOARD_BCM94360J28_D11AC5G 0x0c01 1038 #define BHND_BOARD_BCM94360USBH5_D11AC5G 0x06aa 1039 1040 /* 4350 Boards */ 1041 #define BHND_BOARD_BCM94350X52B 0X0116 1042 #define BHND_BOARD_BCM94350X14 0X0131 1043 1044 /* 43217 Boards */ 1045 #define BHND_BOARD_BCM943217BU 0x05d5 1046 #define BHND_BOARD_BCM943217HM2L 0x05d6 1047 #define BHND_BOARD_BCM943217HMITR2L 0x05d7 1048 1049 /* 43142 Boards */ 1050 #define BHND_BOARD_BCM943142HM 0x05e0 1051 1052 /* 43341 Boards */ 1053 #define BHND_BOARD_BCM943341WLABGS 0x062d 1054 1055 /* 43342 Boards */ 1056 #define BHND_BOARD_BCM943342FCAGBI 0x0641 1057 1058 /* 43602 Boards, unclear yet what boards will be created. */ 1059 #define BHND_BOARD_BCM943602RSVD1 0x06a5 1060 #define BHND_BOARD_BCM943602RSVD2 0x06a6 1061 #define BHND_BOARD_BCM943602X87 0X0133 1062 #define BHND_BOARD_BCM943602X238 0X0132 1063 1064 /* 4354 board types */ 1065 #define BHND_BOARD_BCM94354WLSAGBI 0x06db 1066 #define BHND_BOARD_BCM94354Z 0x0707 1067 1068 /* # of GPIO pins */ 1069 #define BHND_BCM43XX_GPIO_NUMPINS 32 1070 1071 /* These values are used by dhd USB host driver. */ 1072 #define BHND_USB_RDL_RAM_BASE_4319 0x60000000 1073 #define BHND_USB_RDL_RAM_BASE_4329 0x60000000 1074 #define BHND_USB_RDL_RAM_SIZE_4319 0x48000 1075 #define BHND_USB_RDL_RAM_SIZE_4329 0x48000 1076 #define BHND_USB_RDL_RAM_SIZE_43236 0x70000 1077 #define BHND_USB_RDL_RAM_BASE_43236 0x60000000 1078 #define BHND_USB_RDL_RAM_SIZE_4328 0x60000 1079 #define BHND_USB_RDL_RAM_BASE_4328 0x80000000 1080 #define BHND_USB_RDL_RAM_SIZE_4322 0x60000 1081 #define BHND_USB_RDL_RAM_BASE_4322 0x60000000 1082 #define BHND_USB_RDL_RAM_SIZE_4360 0xA0000 1083 #define BHND_USB_RDL_RAM_BASE_4360 0x60000000 1084 #define BHND_USB_RDL_RAM_SIZE_43242 0x90000 1085 #define BHND_USB_RDL_RAM_BASE_43242 0x60000000 1086 #define BHND_USB_RDL_RAM_SIZE_43143 0x70000 1087 #define BHND_USB_RDL_RAM_BASE_43143 0x60000000 1088 #define BHND_USB_RDL_RAM_SIZE_4350 0xC0000 1089 #define BHND_USB_RDL_RAM_BASE_4350 0x180800 1090 1091 /* generic defs for nvram "muxenab" bits 1092 * Note: these differ for 4335a0. refer bcmchipc.h for specific mux options. 1093 */ 1094 #define BHND_NVRAM_MUXENAB_UART 0x00000001 1095 #define BHND_NVRAM_MUXENAB_GPIO 0x00000002 1096 #define BHND_NVRAM_MUXENAB_ERCX 0x00000004 /* External Radio BT coex */ 1097 #define BHND_NVRAM_MUXENAB_JTAG 0x00000008 1098 #define BHND_NVRAM_MUXENAB_HOST_WAKE 0x00000010 /* configure GPIO for SDIO host_wake */ 1099 #define BHND_NVRAM_MUXENAB_I2S_EN 0x00000020 1100 #define BHND_NVRAM_MUXENAB_I2S_MASTER 0x00000040 1101 #define BHND_NVRAM_MUXENAB_I2S_FULL 0x00000080 1102 #define BHND_NVRAM_MUXENAB_SFLASH 0x00000100 1103 #define BHND_NVRAM_MUXENAB_RFSWCTRL0 0x00000200 1104 #define BHND_NVRAM_MUXENAB_RFSWCTRL1 0x00000400 1105 #define BHND_NVRAM_MUXENAB_RFSWCTRL2 0x00000800 1106 #define BHND_NVRAM_MUXENAB_SECI 0x00001000 1107 #define BHND_NVRAM_MUXENAB_BT_LEGACY 0x00002000 1108 #define BHND_NVRAM_MUXENAB_HOST_WAKE1 0x00004000 /* configure alternative GPIO for SDIO host_wake */ 1109 1110 /* Boot flags */ 1111 #define BHND_BOOTFLAG_FLASH_KERNEL_NFLASH 0x00000001 1112 #define BHND_BOOTFLAG_FLASH_BOOT_NFLASH 0x00000002 1113 1114 #endif /* _BHND_BHND_IDS_H_ */ 1115