1 /*- 2 * Copyright (c) 2002-2005 Sam Leffler, Errno Consulting 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification. 11 * 2. Redistributions in binary form must reproduce at minimum a disclaimer 12 * similar to the "NO WARRANTY" disclaimer below ("Disclaimer") and any 13 * redistribution must be conditioned upon including a substantially 14 * similar Disclaimer requirement for further binary redistribution. 15 * 3. Neither the names of the above-listed copyright holders nor the names 16 * of any contributors may be used to endorse or promote products derived 17 * from this software without specific prior written permission. 18 * 19 * Alternatively, this software may be distributed under the terms of the 20 * GNU General Public License ("GPL") version 2 as published by the Free 21 * Software Foundation. 22 * 23 * NO WARRANTY 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 25 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 26 * LIMITED TO, THE IMPLIED WARRANTIES OF NONINFRINGEMENT, MERCHANTIBILITY 27 * AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL 28 * THE COPYRIGHT HOLDERS OR CONTRIBUTORS BE LIABLE FOR SPECIAL, EXEMPLARY, 29 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 30 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 31 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER 32 * IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 33 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 34 * THE POSSIBILITY OF SUCH DAMAGES. 35 * 36 * $FreeBSD$ 37 */ 38 39 /* 40 * Ioctl-related defintions for the Atheros Wireless LAN controller driver. 41 */ 42 #ifndef _DEV_ATH_ATHIOCTL_H 43 #define _DEV_ATH_ATHIOCTL_H 44 45 struct ath_stats { 46 u_int32_t ast_watchdog; /* device reset by watchdog */ 47 u_int32_t ast_hardware; /* fatal hardware error interrupts */ 48 u_int32_t ast_bmiss; /* beacon miss interrupts */ 49 u_int32_t ast_bstuck; /* beacon stuck interrupts */ 50 u_int32_t ast_rxorn; /* rx overrun interrupts */ 51 u_int32_t ast_rxeol; /* rx eol interrupts */ 52 u_int32_t ast_txurn; /* tx underrun interrupts */ 53 u_int32_t ast_mib; /* mib interrupts */ 54 u_int32_t ast_intrcoal; /* interrupts coalesced */ 55 u_int32_t ast_tx_packets; /* packet sent on the interface */ 56 u_int32_t ast_tx_mgmt; /* management frames transmitted */ 57 u_int32_t ast_tx_discard; /* frames discarded prior to assoc */ 58 u_int32_t ast_tx_qstop; /* output stopped 'cuz no buffer */ 59 u_int32_t ast_tx_encap; /* tx encapsulation failed */ 60 u_int32_t ast_tx_nonode; /* tx failed 'cuz no node */ 61 u_int32_t ast_tx_nombuf; /* tx failed 'cuz no mbuf */ 62 u_int32_t ast_tx_nomcl; /* tx failed 'cuz no cluster */ 63 u_int32_t ast_tx_linear; /* tx linearized to cluster */ 64 u_int32_t ast_tx_nodata; /* tx discarded empty frame */ 65 u_int32_t ast_tx_busdma; /* tx failed for dma resrcs */ 66 u_int32_t ast_tx_xretries;/* tx failed 'cuz too many retries */ 67 u_int32_t ast_tx_fifoerr; /* tx failed 'cuz FIFO underrun */ 68 u_int32_t ast_tx_filtered;/* tx failed 'cuz xmit filtered */ 69 u_int32_t ast_tx_shortretry;/* tx on-chip retries (short) */ 70 u_int32_t ast_tx_longretry;/* tx on-chip retries (long) */ 71 u_int32_t ast_tx_badrate; /* tx failed 'cuz bogus xmit rate */ 72 u_int32_t ast_tx_noack; /* tx frames with no ack marked */ 73 u_int32_t ast_tx_rts; /* tx frames with rts enabled */ 74 u_int32_t ast_tx_cts; /* tx frames with cts enabled */ 75 u_int32_t ast_tx_shortpre;/* tx frames with short preamble */ 76 u_int32_t ast_tx_altrate; /* tx frames with alternate rate */ 77 u_int32_t ast_tx_protect; /* tx frames with protection */ 78 u_int32_t ast_rx_nombuf; /* rx setup failed 'cuz no mbuf */ 79 u_int32_t ast_rx_busdma; /* rx setup failed for dma resrcs */ 80 u_int32_t ast_rx_orn; /* rx failed 'cuz of desc overrun */ 81 u_int32_t ast_rx_crcerr; /* rx failed 'cuz of bad CRC */ 82 u_int32_t ast_rx_fifoerr; /* rx failed 'cuz of FIFO overrun */ 83 u_int32_t ast_rx_badcrypt;/* rx failed 'cuz decryption */ 84 u_int32_t ast_rx_badmic; /* rx failed 'cuz MIC failure */ 85 u_int32_t ast_rx_phyerr; /* rx failed 'cuz of PHY err */ 86 u_int32_t ast_rx_phy[32]; /* rx PHY error per-code counts */ 87 u_int32_t ast_rx_tooshort;/* rx discarded 'cuz frame too short */ 88 u_int32_t ast_rx_toobig; /* rx discarded 'cuz frame too large */ 89 u_int32_t ast_rx_packets; /* packet recv on the interface */ 90 u_int32_t ast_rx_mgt; /* management frames received */ 91 u_int32_t ast_rx_ctl; /* rx discarded 'cuz ctl frame */ 92 int8_t ast_tx_rssi; /* tx rssi of last ack */ 93 int8_t ast_rx_rssi; /* rx rssi from histogram */ 94 u_int32_t ast_be_xmit; /* beacons transmitted */ 95 u_int32_t ast_be_nombuf; /* beacon setup failed 'cuz no mbuf */ 96 u_int32_t ast_per_cal; /* periodic calibration calls */ 97 u_int32_t ast_per_calfail;/* periodic calibration failed */ 98 u_int32_t ast_per_rfgain; /* periodic calibration rfgain reset */ 99 u_int32_t ast_rate_calls; /* rate control checks */ 100 u_int32_t ast_rate_raise; /* rate control raised xmit rate */ 101 u_int32_t ast_rate_drop; /* rate control dropped xmit rate */ 102 u_int32_t ast_ant_defswitch;/* rx/default antenna switches */ 103 u_int32_t ast_ant_txswitch;/* tx antenna switches */ 104 u_int32_t ast_ant_rx[8]; /* rx frames with antenna */ 105 u_int32_t ast_ant_tx[8]; /* tx frames with antenna */ 106 }; 107 108 #define SIOCGATHSTATS _IOWR('i', 137, struct ifreq) 109 110 struct ath_diag { 111 char ad_name[IFNAMSIZ]; /* if name, e.g. "ath0" */ 112 u_int16_t ad_id; 113 #define ATH_DIAG_DYN 0x8000 /* allocate buffer in caller */ 114 #define ATH_DIAG_IN 0x4000 /* copy in parameters */ 115 #define ATH_DIAG_OUT 0x0000 /* copy out results (always) */ 116 #define ATH_DIAG_ID 0x0fff 117 u_int16_t ad_in_size; /* pack to fit, yech */ 118 caddr_t ad_in_data; 119 caddr_t ad_out_data; 120 u_int ad_out_size; 121 122 }; 123 #define SIOCGATHDIAG _IOWR('i', 138, struct ath_diag) 124 125 /* 126 * Radio capture format. 127 */ 128 #define ATH_RX_RADIOTAP_PRESENT ( \ 129 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 130 (1 << IEEE80211_RADIOTAP_RATE) | \ 131 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 132 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 133 (1 << IEEE80211_RADIOTAP_DB_ANTSIGNAL) | \ 134 0) 135 136 struct ath_rx_radiotap_header { 137 struct ieee80211_radiotap_header wr_ihdr; 138 u_int8_t wr_flags; /* XXX for padding */ 139 u_int8_t wr_rate; 140 u_int16_t wr_chan_freq; 141 u_int16_t wr_chan_flags; 142 u_int8_t wr_antenna; 143 u_int8_t wr_antsignal; 144 }; 145 146 #define ATH_TX_RADIOTAP_PRESENT ( \ 147 (1 << IEEE80211_RADIOTAP_FLAGS) | \ 148 (1 << IEEE80211_RADIOTAP_RATE) | \ 149 (1 << IEEE80211_RADIOTAP_CHANNEL) | \ 150 (1 << IEEE80211_RADIOTAP_DBM_TX_POWER) | \ 151 (1 << IEEE80211_RADIOTAP_ANTENNA) | \ 152 0) 153 154 struct ath_tx_radiotap_header { 155 struct ieee80211_radiotap_header wt_ihdr; 156 u_int8_t wt_flags; /* XXX for padding */ 157 u_int8_t wt_rate; 158 u_int16_t wt_chan_freq; 159 u_int16_t wt_chan_flags; 160 u_int8_t wt_txpower; 161 u_int8_t wt_antenna; 162 }; 163 164 #endif /* _DEV_ATH_ATHIOCTL_H */ 165