1 /*- 2 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer, 10 * without modification, immediately at the beginning of the file. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 #include <sys/cdefs.h> 28 __FBSDID("$FreeBSD$"); 29 30 #include <sys/param.h> 31 #include <sys/module.h> 32 #include <sys/systm.h> 33 #include <sys/kernel.h> 34 #include <sys/ata.h> 35 #include <sys/bus.h> 36 #include <sys/endian.h> 37 #include <sys/malloc.h> 38 #include <sys/lock.h> 39 #include <sys/mutex.h> 40 #include <sys/sema.h> 41 #include <sys/taskqueue.h> 42 #include <vm/uma.h> 43 #include <machine/stdarg.h> 44 #include <machine/resource.h> 45 #include <machine/bus.h> 46 #include <sys/rman.h> 47 #include <dev/pci/pcivar.h> 48 #include <dev/pci/pcireg.h> 49 #include <dev/ata/ata-all.h> 50 #include <dev/ata/ata-pci.h> 51 #include <ata_if.h> 52 53 /* local prototypes */ 54 static int ata_ite_chipinit(device_t dev); 55 static int ata_ite_ch_attach(device_t dev); 56 static int ata_ite_821x_setmode(device_t dev, int target, int mode); 57 static int ata_ite_8213_setmode(device_t dev, int target, int mode); 58 59 /* 60 * Integrated Technology Express Inc. (ITE) chipset support functions 61 */ 62 static int 63 ata_ite_probe(device_t dev) 64 { 65 struct ata_pci_controller *ctlr = device_get_softc(dev); 66 static const struct ata_chip_id ids[] = 67 {{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" }, 68 { ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 69 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 70 { 0, 0, 0, 0, 0, 0}}; 71 72 if (pci_get_vendor(dev) != ATA_ITE_ID) 73 return ENXIO; 74 75 if (!(ctlr->chip = ata_match_chip(dev, ids))) 76 return ENXIO; 77 78 ata_set_desc(dev); 79 ctlr->chipinit = ata_ite_chipinit; 80 return (BUS_PROBE_LOW_PRIORITY); 81 } 82 83 static int 84 ata_ite_chipinit(device_t dev) 85 { 86 struct ata_pci_controller *ctlr = device_get_softc(dev); 87 88 if (ata_setup_interrupt(dev, ata_generic_intr)) 89 return ENXIO; 90 91 if (ctlr->chip->chipid == ATA_IT8213F) { 92 /* the ITE 8213F only has one channel */ 93 ctlr->channels = 1; 94 95 ctlr->setmode = ata_ite_8213_setmode; 96 } 97 else { 98 /* set PCI mode and 66Mhz reference clock */ 99 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 100 101 /* set default active & recover timings */ 102 pci_write_config(dev, 0x54, 0x31, 1); 103 pci_write_config(dev, 0x56, 0x31, 1); 104 105 ctlr->setmode = ata_ite_821x_setmode; 106 /* No timing restrictions initally. */ 107 ctlr->chipset_data = NULL; 108 } 109 ctlr->ch_attach = ata_ite_ch_attach; 110 return (0); 111 } 112 113 static int 114 ata_ite_ch_attach(device_t dev) 115 { 116 struct ata_channel *ch = device_get_softc(dev); 117 int error; 118 119 error = ata_pci_ch_attach(dev); 120 ch->flags |= ATA_CHECKS_CABLE; 121 ch->flags |= ATA_NO_ATAPI_DMA; 122 return (error); 123 } 124 125 static int 126 ata_ite_821x_setmode(device_t dev, int target, int mode) 127 { 128 device_t parent = device_get_parent(dev); 129 struct ata_pci_controller *ctlr = device_get_softc(parent); 130 struct ata_channel *ch = device_get_softc(dev); 131 int devno = (ch->unit << 1) + target; 132 int piomode; 133 uint8_t *timings = (uint8_t*)(&ctlr->chipset_data); 134 static const uint8_t udmatiming[] = 135 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 136 static const uint8_t chtiming[] = 137 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 138 139 mode = min(mode, ctlr->chip->max_dma); 140 /* check the CBLID bits for 80 conductor cable detection */ 141 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 142 (pci_read_config(parent, 0x40, 2) & 143 (ch->unit ? (1<<3) : (1<<2)))) { 144 ata_print_cable(dev, "controller"); 145 mode = ATA_UDMA2; 146 } 147 if (mode >= ATA_UDMA0) { 148 /* enable UDMA mode */ 149 pci_write_config(parent, 0x50, 150 pci_read_config(parent, 0x50, 1) & 151 ~(1 << (devno + 3)), 1); 152 /* set UDMA timing */ 153 pci_write_config(parent, 154 0x56 + (ch->unit << 2) + target, 155 udmatiming[mode & ATA_MODE_MASK], 1); 156 piomode = ATA_PIO4; 157 } else { 158 /* disable UDMA mode */ 159 pci_write_config(parent, 0x50, 160 pci_read_config(parent, 0x50, 1) | 161 (1 << (devno + 3)), 1); 162 piomode = mode; 163 } 164 timings[devno] = chtiming[ata_mode2idx(piomode)]; 165 /* set active and recover timing (shared between master & slave) */ 166 pci_write_config(parent, 0x54 + (ch->unit << 2), 167 max(timings[ch->unit << 1], timings[(ch->unit << 1) + 1]), 1); 168 return (mode); 169 } 170 171 static int 172 ata_ite_8213_setmode(device_t dev, int target, int mode) 173 { 174 device_t parent = device_get_parent(dev); 175 struct ata_pci_controller *ctlr = device_get_softc(parent); 176 int piomode; 177 u_int16_t reg40 = pci_read_config(parent, 0x40, 2); 178 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 179 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 180 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 181 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 182 u_int16_t mask40 = 0, new40 = 0; 183 u_int8_t mask44 = 0, new44 = 0; 184 static const uint8_t timings[] = 185 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 186 static const uint8_t utimings[] = 187 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 188 189 mode = min(mode, ctlr->chip->max_dma); 190 191 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 192 !(reg54 & (0x10 << target))) { 193 ata_print_cable(dev, "controller"); 194 mode = ATA_UDMA2; 195 } 196 /* Enable/disable UDMA and set timings. */ 197 if (mode >= ATA_UDMA0) { 198 pci_write_config(parent, 0x48, reg48 | (0x0001 << target), 2); 199 pci_write_config(parent, 0x4a, 200 (reg4a & ~(0x3 << (target << 2))) | 201 (utimings[mode & ATA_MODE_MASK] << (target<<2)), 2); 202 piomode = ATA_PIO4; 203 } else { 204 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << target), 2); 205 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (target << 2))),2); 206 piomode = mode; 207 } 208 /* Set UDMA reference clock (33/66/133MHz). */ 209 reg54 &= ~(0x1001 << target); 210 if (mode >= ATA_UDMA5) 211 reg54 |= (0x1000 << target); 212 else if (mode >= ATA_UDMA3) 213 reg54 |= (0x1 << target); 214 pci_write_config(parent, 0x54, reg54, 2); 215 /* Allow PIO/WDMA timing controls. */ 216 reg40 &= 0xff00; 217 reg40 |= 0x4033; 218 /* Set PIO/WDMA timings. */ 219 if (target == 0) { 220 reg40 |= (ata_atapi(dev, target) ? 0x04 : 0x00); 221 mask40 = 0x3300; 222 new40 = timings[ata_mode2idx(piomode)] << 8; 223 } 224 else { 225 reg40 |= (ata_atapi(dev, target) ? 0x40 : 0x00); 226 mask44 = 0x0f; 227 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 228 (timings[ata_mode2idx(piomode)] & 0x03); 229 } 230 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 231 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 232 return (mode); 233 } 234 235 ATA_DECLARE_DRIVER(ata_ite); 236