1 /*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 1998 - 2008 Søren Schmidt <sos@FreeBSD.org> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer, 12 * without modification, immediately at the beginning of the file. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 18 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 19 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 20 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 21 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 22 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 26 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #include <sys/param.h> 30 #include <sys/module.h> 31 #include <sys/systm.h> 32 #include <sys/kernel.h> 33 #include <sys/ata.h> 34 #include <sys/bus.h> 35 #include <sys/endian.h> 36 #include <sys/malloc.h> 37 #include <sys/lock.h> 38 #include <sys/mutex.h> 39 #include <sys/sema.h> 40 #include <sys/taskqueue.h> 41 #include <vm/uma.h> 42 #include <machine/stdarg.h> 43 #include <machine/resource.h> 44 #include <machine/bus.h> 45 #include <sys/rman.h> 46 #include <dev/pci/pcivar.h> 47 #include <dev/pci/pcireg.h> 48 #include <dev/ata/ata-all.h> 49 #include <dev/ata/ata-pci.h> 50 #include <ata_if.h> 51 52 /* local prototypes */ 53 static int ata_ite_chipinit(device_t dev); 54 static int ata_ite_ch_attach(device_t dev); 55 static int ata_ite_821x_setmode(device_t dev, int target, int mode); 56 static int ata_ite_8213_setmode(device_t dev, int target, int mode); 57 58 /* 59 * Integrated Technology Express Inc. (ITE) chipset support functions 60 */ 61 static int 62 ata_ite_probe(device_t dev) 63 { 64 struct ata_pci_controller *ctlr = device_get_softc(dev); 65 static const struct ata_chip_id ids[] = 66 {{ ATA_IT8213F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8213F" }, 67 { ATA_IT8212F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8212F" }, 68 { ATA_IT8211F, 0x00, 0x00, 0x00, ATA_UDMA6, "IT8211F" }, 69 { 0, 0, 0, 0, 0, 0}}; 70 71 if (pci_get_vendor(dev) != ATA_ITE_ID) 72 return ENXIO; 73 74 if (!(ctlr->chip = ata_match_chip(dev, ids))) 75 return ENXIO; 76 77 ata_set_desc(dev); 78 ctlr->chipinit = ata_ite_chipinit; 79 return (BUS_PROBE_LOW_PRIORITY); 80 } 81 82 static int 83 ata_ite_chipinit(device_t dev) 84 { 85 struct ata_pci_controller *ctlr = device_get_softc(dev); 86 87 if (ata_setup_interrupt(dev, ata_generic_intr)) 88 return ENXIO; 89 90 if (ctlr->chip->chipid == ATA_IT8213F) { 91 /* the ITE 8213F only has one channel */ 92 ctlr->channels = 1; 93 94 ctlr->setmode = ata_ite_8213_setmode; 95 } 96 else { 97 /* set PCI mode and 66Mhz reference clock */ 98 pci_write_config(dev, 0x50, pci_read_config(dev, 0x50, 1) & ~0x83, 1); 99 100 /* set default active & recover timings */ 101 pci_write_config(dev, 0x54, 0x31, 1); 102 pci_write_config(dev, 0x56, 0x31, 1); 103 104 ctlr->setmode = ata_ite_821x_setmode; 105 /* No timing restrictions initially. */ 106 ctlr->chipset_data = NULL; 107 } 108 ctlr->ch_attach = ata_ite_ch_attach; 109 return (0); 110 } 111 112 static int 113 ata_ite_ch_attach(device_t dev) 114 { 115 struct ata_channel *ch = device_get_softc(dev); 116 int error; 117 118 error = ata_pci_ch_attach(dev); 119 ch->flags |= ATA_CHECKS_CABLE; 120 ch->flags |= ATA_NO_ATAPI_DMA; 121 return (error); 122 } 123 124 static int 125 ata_ite_821x_setmode(device_t dev, int target, int mode) 126 { 127 device_t parent = device_get_parent(dev); 128 struct ata_pci_controller *ctlr = device_get_softc(parent); 129 struct ata_channel *ch = device_get_softc(dev); 130 int devno = (ch->unit << 1) + target; 131 int piomode; 132 uint8_t *timings = (uint8_t*)(&ctlr->chipset_data); 133 static const uint8_t udmatiming[] = 134 { 0x44, 0x42, 0x31, 0x21, 0x11, 0xa2, 0x91 }; 135 static const uint8_t chtiming[] = 136 { 0xaa, 0xa3, 0xa1, 0x33, 0x31, 0x88, 0x32, 0x31 }; 137 138 mode = min(mode, ctlr->chip->max_dma); 139 /* check the CBLID bits for 80 conductor cable detection */ 140 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 141 (pci_read_config(parent, 0x40, 2) & 142 (ch->unit ? (1<<3) : (1<<2)))) { 143 ata_print_cable(dev, "controller"); 144 mode = ATA_UDMA2; 145 } 146 if (mode >= ATA_UDMA0) { 147 /* enable UDMA mode */ 148 pci_write_config(parent, 0x50, 149 pci_read_config(parent, 0x50, 1) & 150 ~(1 << (devno + 3)), 1); 151 /* set UDMA timing */ 152 pci_write_config(parent, 153 0x56 + (ch->unit << 2) + target, 154 udmatiming[mode & ATA_MODE_MASK], 1); 155 piomode = ATA_PIO4; 156 } else { 157 /* disable UDMA mode */ 158 pci_write_config(parent, 0x50, 159 pci_read_config(parent, 0x50, 1) | 160 (1 << (devno + 3)), 1); 161 piomode = mode; 162 } 163 timings[devno] = chtiming[ata_mode2idx(piomode)]; 164 /* set active and recover timing (shared between master & slave) */ 165 pci_write_config(parent, 0x54 + (ch->unit << 2), 166 max(timings[ch->unit << 1], timings[(ch->unit << 1) + 1]), 1); 167 return (mode); 168 } 169 170 static int 171 ata_ite_8213_setmode(device_t dev, int target, int mode) 172 { 173 device_t parent = device_get_parent(dev); 174 struct ata_pci_controller *ctlr = device_get_softc(parent); 175 int piomode; 176 u_int16_t reg40 = pci_read_config(parent, 0x40, 2); 177 u_int8_t reg44 = pci_read_config(parent, 0x44, 1); 178 u_int8_t reg48 = pci_read_config(parent, 0x48, 1); 179 u_int16_t reg4a = pci_read_config(parent, 0x4a, 2); 180 u_int16_t reg54 = pci_read_config(parent, 0x54, 2); 181 u_int16_t mask40 = 0, new40 = 0; 182 u_int8_t mask44 = 0, new44 = 0; 183 static const uint8_t timings[] = 184 { 0x00, 0x00, 0x10, 0x21, 0x23, 0x00, 0x21, 0x23 }; 185 static const uint8_t utimings[] = 186 { 0x00, 0x01, 0x02, 0x01, 0x02, 0x01, 0x02 }; 187 188 mode = min(mode, ctlr->chip->max_dma); 189 190 if (ata_dma_check_80pin && mode > ATA_UDMA2 && 191 !(reg54 & (0x10 << target))) { 192 ata_print_cable(dev, "controller"); 193 mode = ATA_UDMA2; 194 } 195 /* Enable/disable UDMA and set timings. */ 196 if (mode >= ATA_UDMA0) { 197 pci_write_config(parent, 0x48, reg48 | (0x0001 << target), 2); 198 pci_write_config(parent, 0x4a, 199 (reg4a & ~(0x3 << (target << 2))) | 200 (utimings[mode & ATA_MODE_MASK] << (target<<2)), 2); 201 piomode = ATA_PIO4; 202 } else { 203 pci_write_config(parent, 0x48, reg48 & ~(0x0001 << target), 2); 204 pci_write_config(parent, 0x4a, (reg4a & ~(0x3 << (target << 2))),2); 205 piomode = mode; 206 } 207 /* Set UDMA reference clock (33/66/133MHz). */ 208 reg54 &= ~(0x1001 << target); 209 if (mode >= ATA_UDMA5) 210 reg54 |= (0x1000 << target); 211 else if (mode >= ATA_UDMA3) 212 reg54 |= (0x1 << target); 213 pci_write_config(parent, 0x54, reg54, 2); 214 /* Allow PIO/WDMA timing controls. */ 215 reg40 &= 0xff00; 216 reg40 |= 0x4033; 217 /* Set PIO/WDMA timings. */ 218 if (target == 0) { 219 reg40 |= (ata_atapi(dev, target) ? 0x04 : 0x00); 220 mask40 = 0x3300; 221 new40 = timings[ata_mode2idx(piomode)] << 8; 222 } 223 else { 224 reg40 |= (ata_atapi(dev, target) ? 0x40 : 0x00); 225 mask44 = 0x0f; 226 new44 = ((timings[ata_mode2idx(piomode)] & 0x30) >> 2) | 227 (timings[ata_mode2idx(piomode)] & 0x03); 228 } 229 pci_write_config(parent, 0x40, (reg40 & ~mask40) | new40, 4); 230 pci_write_config(parent, 0x44, (reg44 & ~mask44) | new44, 1); 231 return (mode); 232 } 233 234 ATA_DECLARE_DRIVER(ata_ite); 235