1 /*-
2 * Atlantic 2 (AQC113/114/115/116) register definitions for aq(4).
3 *
4 * Register layout and field definitions adapted from the OpenBSD/NetBSD
5 * if_aq driver:
6 *
7 * Copyright (c) 2021 Jonathan Matthew <jonathan@d14n.org>
8 * Copyright (c) 2021 Mike Larkin <mlarkin@openbsd.org>
9 *
10 * Permission to use, copy, modify, and distribute this software for any
11 * purpose with or without fee is hereby granted, provided that the above
12 * copyright notice and this permission notice appear in all copies.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
15 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
16 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
17 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
18 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
19 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
20 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
21 */
22
23 #ifndef AQ2_HW_H
24 #define AQ2_HW_H
25
26 /* Atlantic 2 PCI device IDs (Aquantia/Marvell). */
27 #define AQ_DEVICE_ID_AQC113 0x04C0
28 #define AQ_DEVICE_ID_AQC113C 0x14C0
29 #define AQ_DEVICE_ID_AQC113CA 0x34C0
30 #define AQ_DEVICE_ID_AQC113CS 0x94C0
31 #define AQ_DEVICE_ID_AQC114CS 0x93C0
32 #define AQ_DEVICE_ID_AQC115C 0x12C0
33 #define AQ_DEVICE_ID_AQC116C 0x11C0
34
35 static __inline bool
aq_is_atlantic2(uint16_t device_id)36 aq_is_atlantic2(uint16_t device_id)
37 {
38 switch (device_id) {
39 case AQ_DEVICE_ID_AQC113:
40 case AQ_DEVICE_ID_AQC113C:
41 case AQ_DEVICE_ID_AQC113CA:
42 case AQ_DEVICE_ID_AQC113CS:
43 case AQ_DEVICE_ID_AQC114CS:
44 case AQ_DEVICE_ID_AQC115C:
45 case AQ_DEVICE_ID_AQC116C:
46 return (true);
47 default:
48 return (false);
49 }
50 }
51
52 /* Atlantic 2 host packet-buffer sizes (Atlantic 1 uses 160/320). */
53 #define AQ2_HW_TXBUF_MAX 128
54 #define AQ2_HW_RXBUF_MAX 192
55
56 /* A2 firmware handshake registers (host <-> MCP). */
57 #define AQ2_MIF_HOST_FINISHED_STATUS_WRITE_REG 0x0e00
58 #define AQ2_MIF_HOST_FINISHED_STATUS_READ_REG 0x0e04
59 #define AQ2_MIF_HOST_FINISHED_STATUS_ACK (1 << 0)
60
61 #define AQ2_MCP_HOST_REQ_INT_REG 0x0f00
62 #define AQ2_MCP_HOST_REQ_INT_READY (1 << 0)
63 #define AQ2_MCP_HOST_REQ_INT_SET_REG 0x0f04
64 #define AQ2_MCP_HOST_REQ_INT_CLR_REG 0x0f08
65
66 #define AQ2_MIF_BOOT_REG 0x3040
67 #define AQ2_MIF_BOOT_HOST_DATA_LOADED (1 << 16)
68 #define AQ2_MIF_BOOT_BOOT_STARTED (1 << 24)
69 #define AQ2_MIF_BOOT_CRASH_INIT (1 << 27)
70 #define AQ2_MIF_BOOT_BOOT_CODE_FAILED (1 << 28)
71 #define AQ2_MIF_BOOT_FW_INIT_FAILED (1 << 29)
72 #define AQ2_MIF_BOOT_FW_INIT_COMP_SUCCESS (1U << 31)
73 #define AQ2_MIF_BOOT_FAILED \
74 (AQ2_MIF_BOOT_CRASH_INIT | AQ2_MIF_BOOT_BOOT_CODE_FAILED | \
75 AQ2_MIF_BOOT_FW_INIT_FAILED)
76 #define AQ2_MIF_BOOT_COMPLETE \
77 (AQ2_MIF_BOOT_FAILED | AQ2_MIF_BOOT_FW_INIT_COMP_SUCCESS)
78
79 /* The ART semaphore is global CPU semaphore index 3. */
80 #define AQ2_ART_SEM_INDEX 3
81
82 /* Action Resolver Table (replaces Atlantic 1's discrete RPF filters). */
83 #define AQ2_ART_ACTION_ACT_SHIFT 8
84 #define AQ2_ART_ACTION_RSS 0x0080
85 #define AQ2_ART_ACTION_INDEX_SHIFT 2
86 #define AQ2_ART_ACTION_ENABLE 0x0001
87 #define AQ2_ART_ACTION(act, rss, idx, en) \
88 (((act) << AQ2_ART_ACTION_ACT_SHIFT) | \
89 ((rss) ? AQ2_ART_ACTION_RSS : 0) | \
90 ((idx) << AQ2_ART_ACTION_INDEX_SHIFT) | \
91 ((en) ? AQ2_ART_ACTION_ENABLE : 0))
92 #define AQ2_ART_ACTION_DROP AQ2_ART_ACTION(0, 0, 0, 1)
93 #define AQ2_ART_ACTION_DISABLE AQ2_ART_ACTION(0, 0, 0, 0)
94 #define AQ2_ART_ACTION_ASSIGN_QUEUE(q) AQ2_ART_ACTION(1, 0, (q), 1)
95 #define AQ2_ART_ACTION_ASSIGN_TC(tc) AQ2_ART_ACTION(1, 1, (tc), 1)
96
97 #define AQ2_RPF_TAG_PCP_MASK 0xe0000000
98 #define AQ2_RPF_TAG_PCP_SHIFT 29
99 #define AQ2_RPF_TAG_FLEX_MASK 0x18000000
100 #define AQ2_RPF_TAG_UNKNOWN_MASK 0x07000000
101 #define AQ2_RPF_TAG_L4_MASK 0x00e00000
102 #define AQ2_RPF_TAG_L3_V6_MASK 0x001c0000
103 #define AQ2_RPF_TAG_L3_V4_MASK 0x00038000
104 #define AQ2_RPF_TAG_UNTAG_MASK 0x00004000
105 #define AQ2_RPF_TAG_VLAN_MASK 0x00003c00
106 #define AQ2_RPF_TAG_ET_MASK 0x00000380
107 #define AQ2_RPF_TAG_ALLMC_MASK 0x00000040
108 #define AQ2_RPF_TAG_UC_MASK 0x0000002f
109
110 /* Logical ART row indices (before adding sc_art_filter_base_index). */
111 #define AQ2_RPF_INDEX_L2_PROMISC_OFF 0
112 #define AQ2_RPF_INDEX_VLAN_PROMISC_OFF 1
113 #define AQ2_RPF_INDEX_L3L4_USER 8
114 #define AQ2_RPF_INDEX_ET_PCP_USER 24
115 #define AQ2_RPF_INDEX_VLAN_USER 40
116 #define AQ2_RPF_INDEX_PCP_TO_TC 56
117
118 #define AQ2_RPF_L2BC_TAG_REG 0x50f0
119 #define AQ2_RPF_L2BC_TAG_MASK 0x0000003f
120
121 #define AQ2_RPF_NEW_CTRL_REG 0x5104
122 #define AQ2_RPF_NEW_CTRL_ENABLE (1 << 11)
123
124 #define AQ2_RPF_REDIR2_REG 0x54c8
125 #define AQ2_RPF_REDIR2_INDEX (1 << 12)
126 #define AQ2_RPF_REDIR2_HASHTYPE 0x000001FF
127 #define AQ2_RPF_REDIR2_HASHTYPE_NONE 0
128 #define AQ2_RPF_REDIR2_HASHTYPE_IP (1 << 0)
129 #define AQ2_RPF_REDIR2_HASHTYPE_TCP4 (1 << 1)
130 #define AQ2_RPF_REDIR2_HASHTYPE_UDP4 (1 << 2)
131 #define AQ2_RPF_REDIR2_HASHTYPE_IP6 (1 << 3)
132 #define AQ2_RPF_REDIR2_HASHTYPE_TCP6 (1 << 4)
133 #define AQ2_RPF_REDIR2_HASHTYPE_UDP6 (1 << 5)
134 #define AQ2_RPF_REDIR2_HASHTYPE_IP6EX (1 << 6)
135 #define AQ2_RPF_REDIR2_HASHTYPE_TCP6EX (1 << 7)
136 #define AQ2_RPF_REDIR2_HASHTYPE_UDP6EX (1 << 8)
137 #define AQ2_RPF_REDIR2_HASHTYPE_ALL 0x000001FF
138
139 #define AQ2_RX_Q_TC_MAP_REG(i) (0x5900 + (i) * 4)
140 #define AQ2_TX_Q_TC_MAP_REG(i) (0x799c + (i) * 4)
141
142 #define AQ2_RPF_RSS_REDIR_MAX 64
143 #define AQ2_RPF_RSS_REDIR_REG(tc, i) \
144 (0x6200 + (0x100 * ((tc) >> 2)) + (i) * 4)
145
146 #define AQ2_RPF_REC_TAB_ENABLE_REG 0x6ff0
147 #define AQ2_RPF_REC_TAB_ENABLE_MASK 0x0000ffff
148
149 #define AQ2_LAUNCHTIME_CTRL_REG 0x7a1c
150 #define AQ2_LAUNCHTIME_CTRL_RATIO 0x0000ff00
151 #define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_QUARTER 4
152 #define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_HALF 2
153 #define AQ2_LAUNCHTIME_CTRL_RATIO_SPEED_FULL 1
154
155 #define AQ2_HW_FPGA_VERSION_REG 0x00f4
156
157 #define AQ2_TX_INTR_MODERATION_CTL_REG(i) (0x7c28 + (i) * 0x40)
158 #define AQ2_TX_INTR_MODERATION_CTL_EN (1 << 1)
159 #define AQ2_TX_INTR_MODERATION_CTL_MIN 0x0000ff00
160 #define AQ2_TX_INTR_MODERATION_CTL_MAX 0x01ff0000
161
162 /* Firmware interface IN window (host -> MCP). */
163 #define AQ2_FW_INTERFACE_IN_MTU_REG 0x12000
164 #define AQ2_FW_INTERFACE_IN_MAC_ADDRESS_REG 0x12008
165
166 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_REG 0x12010
167 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE 0x0000000f
168 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_INVALID 0
169 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_ACTIVE 1
170 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_SLEEP_PROXY 2
171 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_LOWPOWER 3
172 #define AQ2_FW_INTERFACE_IN_LINK_CONTROL_MODE_SHUTDOWN 4
173
174 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_REG 0x12018
175 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_DOWNSHIFT (1 << 27)
176 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_TX (1 << 25)
177 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_PAUSE_RX (1 << 24)
178 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_10G (1 << 20)
179 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_5G (1 << 19)
180 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_2G5 (1 << 18)
181 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_1G (1 << 17)
182 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_EEE_100M (1 << 16)
183 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10G (1 << 15)
184 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N5G (1 << 14)
185 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_5G (1 << 13)
186 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_N2G5 (1 << 12)
187 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_2G5 (1 << 11)
188 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G (1 << 10)
189 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M (1 << 9)
190 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M (1 << 8)
191 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_1G_HD (1 << 7)
192 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_100M_HD (1 << 6)
193 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_RATE_10M_HD (1 << 5)
194 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_RENEGOTIATE (1 << 1)
195 #define AQ2_FW_INTERFACE_IN_LINK_OPTIONS_LINK_UP (1 << 0)
196
197 #define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_REG 0x12020
198 #define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_ENABLE (1 << 0)
199 #define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_TEMP 0x0000ff00 /* whole degC */
200 #define AQ2_FW_INTERFACE_IN_THERMAL_SHUTDOWN_TEMP_S 8
201
202 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_REG 0x12a58
203 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_QUEUE_OR_TC 0x00800000
204 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_RX_QUEUE_TC_INDEX 0x007c0000
205 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_MCAST_ACCEPT 0x00010000
206 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_QUEUE_OR_TC 0x00008000
207 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_RX_QUEUE_TC_INDEX 0x00007c00
208 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_BCAST_ACCEPT 0x00000100
209 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_QUEUE_OR_TC 0x00000080
210 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_RX_QUEUE_TX_INDEX 0x0000007c
211 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_MCAST 0x00000002
212 #define AQ2_FW_INTERFACE_IN_REQUEST_POLICY_PROMISC_ALL 0x00000001
213
214 /* Firmware interface OUT window (MCP -> host). */
215 #define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_REG 0x13000
216 #define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B 0xffff0000
217 #define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_B_S 16
218 #define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A 0x0000ffff
219 #define AQ2_FW_INTERFACE_OUT_TRANSACTION_ID_A_S 0
220
221 #define AQ2_FW_INTERFACE_OUT_VERSION_BUNDLE_REG 0x13004
222 #define AQ2_FW_INTERFACE_OUT_VERSION_MAC_REG 0x13008
223
224 #define AQ2_FW_INTERFACE_OUT_VERSION_PHY_REG 0x1300c
225 #define AQ2_FW_INTERFACE_OUT_VERSION_BUILD 0xffff0000
226 #define AQ2_FW_INTERFACE_OUT_VERSION_BUILD_S 16
227 #define AQ2_FW_INTERFACE_OUT_VERSION_MINOR 0x0000ff00
228 #define AQ2_FW_INTERFACE_OUT_VERSION_MINOR_S 8
229 #define AQ2_FW_INTERFACE_OUT_VERSION_MAJOR 0x000000ff
230 #define AQ2_FW_INTERFACE_OUT_VERSION_MAJOR_S 0
231
232 #define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_REG 0x13010
233 #define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER 0x0000000f
234 #define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_A0 0
235 #define AQ2_FW_INTERFACE_OUT_VERSION_IFACE_VER_B0 1
236
237 #define AQ2_FW_INTERFACE_OUT_PHY_HEALTH_MONITOR_REG 0x13620
238 #define AQ2_FW_INTERFACE_OUT_PHY_HEALTH_MONITOR_READY 0x00000001
239 #define AQ2_FW_INTERFACE_OUT_PHY_HEALTH_MONITOR_FAULT 0x00000002
240 #define AQ2_FW_INTERFACE_OUT_PHY_HEALTH_MONITOR_HOT 0x00000004
241 #define AQ2_FW_INTERFACE_OUT_PHY_TEMPERATURE 0x0000ff00
242 #define AQ2_FW_INTERFACE_OUT_PHY_TEMPERATURE_S 8
243
244 #define AQ2_FW_INTERFACE_OUT_PHY_FAULT_CODE_REG 0x13624
245 #define AQ2_FW_INTERFACE_OUT_PHY_FAULT_CODE 0x0000ffff
246
247 #define AQ2_FW_INTERFACE_OUT_STATS_REG 0x13700
248
249 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_REG 0x13014
250 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_DUPLEX (1 << 11)
251 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_EEE (1 << 10)
252 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_RX (1 << 9)
253 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_PAUSE_TX (1 << 8)
254 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE 0x000000f0
255 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_S 4
256 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10G 6
257 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_5G 5
258 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_2G5 4
259 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_1G 3
260 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_100M 2
261 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_10M 1
262 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_RATE_INVALID 0
263 #define AQ2_FW_INTERFACE_OUT_LINK_STATUS_STATE 0x0000000f
264
265 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS_REG 0x13774
266 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_BASE_INDEX 0x00ff0000
267 #define AQ2_FW_INTERFACE_OUT_FILTER_CAPS3_RESOLVER_BASE_INDEX_SHIFT 16
268
269 #define AQ2_RPF_ACT_ART_REQ_TAG_REG(i) (0x14000 + (i) * 0x10)
270 #define AQ2_RPF_ACT_ART_REQ_MASK_REG(i) (0x14004 + (i) * 0x10)
271 #define AQ2_RPF_ACT_ART_REQ_ACTION_REG(i) (0x14008 + (i) * 0x10)
272
273 /* Action-resolver table depth: 16 enable sections of 8 rows. */
274 #define AQ2_ART_TABLE_SIZE 128
275
276 /*
277 * L2 unicast filter MSW register (shared with Atlantic 1). Atlantic 2 sets
278 * the TAG field so unicast frames are classified into the resolver table.
279 */
280 #define AQ2_RPF_VLAN_FLR_TAG_REG(i) (0x5290 + (i) * 4)
281 #define AQ2_RPF_VLAN_FLR_TAG 0x0000F000
282 #define AQ2_RPF_VLAN_FLR_TAG_SHIFT 12
283
284 #define RPF_L2UC_MSW_REG(i) (0x5114 + (i) * 8)
285 #define RPF_L2UC_MSW_TAG 0x03c00000
286 #define RPF_L2UC_MSW_TAG_SHIFT 22
287
288 /*
289 * Tx packet-scheduler data-TC credit/weight (shared register, but the
290 * Atlantic 2 fields are wider than Atlantic 1's), and the Tx buffer control
291 * register whose randomized ring->TC map Atlantic 2 enables.
292 */
293 #define TPS_DATA_TCT_REG(i) (0x7110 + (i) * 4)
294 #define TPS2_DATA_TCT_CREDIT_MAX 0xffff0000
295 #define TPS2_DATA_TCT_CREDIT_MAX_SHIFT 16
296 #define TPS2_DATA_TCT_WEIGHT 0x00007fff
297 #define TPS2_DATA_TCT_WEIGHT_SHIFT 0
298
299 #define TPB_TX_BUF_REG 0x7900
300 #define TPB_TX_BUF_TC_Q_RAND_MAP_EN (1 << 9)
301 #define TPB_TX_BUF_TC_Q_RAND_MAP_EN_SHIFT 9
302
303 #endif /* AQ2_HW_H */
304