1 /*
2 * Copyright 2008-2012 Freescale Semiconductor Inc.
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions are met:
6 * * Redistributions of source code must retain the above copyright
7 * notice, this list of conditions and the following disclaimer.
8 * * Redistributions in binary form must reproduce the above copyright
9 * notice, this list of conditions and the following disclaimer in the
10 * documentation and/or other materials provided with the distribution.
11 * * Neither the name of Freescale Semiconductor nor the
12 * names of its contributors may be used to endorse or promote products
13 * derived from this software without specific prior written permission.
14 *
15 *
16 * ALTERNATIVELY, this software may be distributed under the terms of the
17 * GNU General Public License ("GPL") as published by the Free Software
18 * Foundation, either version 2 of that License or (at your option) any
19 * later version.
20 *
21 * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
22 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
23 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
24 * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
25 * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
26 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
28 * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
30 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 */
32
33
34 #include "error_ext.h"
35 #include "std_ext.h"
36 #include "fm_mac.h"
37 #include "memac.h"
38 #include "xx_ext.h"
39
40 #include "fm_common.h"
41 #include "memac_mii_acc.h"
42
43
44 /*****************************************************************************/
MEMAC_MII_WritePhyReg(t_Handle h_Memac,uint8_t phyAddr,uint8_t reg,uint16_t data)45 t_Error MEMAC_MII_WritePhyReg(t_Handle h_Memac,
46 uint8_t phyAddr,
47 uint8_t reg,
48 uint16_t data)
49 {
50 t_Memac *p_Memac = (t_Memac *)h_Memac;
51
52 SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
53 SANITY_CHECK_RETURN_ERROR(p_Memac->p_MiiMemMap, E_INVALID_HANDLE);
54
55 return (t_Error)fman_memac_mii_write_phy_reg(p_Memac->p_MiiMemMap,
56 phyAddr,
57 reg,
58 data,
59 (enum enet_speed)ENET_SPEED_FROM_MODE(p_Memac->enetMode));
60 }
61
62 /*****************************************************************************/
MEMAC_MII_ReadPhyReg(t_Handle h_Memac,uint8_t phyAddr,uint8_t reg,uint16_t * p_Data)63 t_Error MEMAC_MII_ReadPhyReg(t_Handle h_Memac,
64 uint8_t phyAddr,
65 uint8_t reg,
66 uint16_t *p_Data)
67 {
68 t_Memac *p_Memac = (t_Memac *)h_Memac;
69
70 SANITY_CHECK_RETURN_ERROR(p_Memac, E_INVALID_HANDLE);
71 SANITY_CHECK_RETURN_ERROR(p_Memac->p_MiiMemMap, E_INVALID_HANDLE);
72
73 return fman_memac_mii_read_phy_reg(p_Memac->p_MiiMemMap,
74 phyAddr,
75 reg,
76 p_Data,
77 (enum enet_speed)ENET_SPEED_FROM_MODE(p_Memac->enetMode));
78 }
79