1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (c) 2026 SpacemiT (Hangzhou) Technology Co. Ltd 4 * Copyright (c) 2026 Guodong Xu <guodong@riscstar.com> 5 */ 6 7#include <dt-bindings/clock/spacemit,k3-clocks.h> 8#include <dt-bindings/reset/spacemit,k3-resets.h> 9#include <dt-bindings/interrupt-controller/irq.h> 10 11/dts-v1/; 12 13/ { 14 #address-cells = <2>; 15 #size-cells = <2>; 16 model = "SpacemiT K3"; 17 compatible = "spacemit,k3"; 18 19 cpus: cpus { 20 #address-cells = <1>; 21 #size-cells = <0>; 22 timebase-frequency = <24000000>; 23 24 cpu_0: cpu@0 { 25 compatible = "spacemit,x100", "riscv"; 26 device_type = "cpu"; 27 reg = <0>; 28 riscv,isa-base = "rv64i"; 29 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 30 "sha", "shcounterenw", "shgatpa", "shtvala", 31 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 32 "smstateen", "ssaia", "ssccptr", "sscofpmf", 33 "sscounterenw", "ssnpm", "ssstateen", "sstc", 34 "sstvala", "sstvecd", "ssu64xl", "svade", 35 "svinval", "svnapot", "svpbmt", "za64rs", 36 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 37 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 38 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 39 "ziccamoa", "ziccif", "zicclsm", "zicntr", 40 "zicond", "zicsr", "zifencei", "zihintntl", 41 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 42 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 43 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 44 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 45 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 46 riscv,cbom-block-size = <64>; 47 riscv,cbop-block-size = <64>; 48 riscv,cboz-block-size = <64>; 49 i-cache-block-size = <64>; 50 i-cache-size = <65536>; 51 i-cache-sets = <256>; 52 d-cache-block-size = <64>; 53 d-cache-size = <65536>; 54 d-cache-sets = <256>; 55 next-level-cache = <&l2_cache0>; 56 mmu-type = "riscv,sv39"; 57 58 cpu0_intc: interrupt-controller { 59 compatible = "riscv,cpu-intc"; 60 #interrupt-cells = <1>; 61 interrupt-controller; 62 }; 63 }; 64 65 cpu_1: cpu@1 { 66 compatible = "spacemit,x100", "riscv"; 67 device_type = "cpu"; 68 reg = <1>; 69 riscv,isa-base = "rv64i"; 70 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 71 "sha", "shcounterenw", "shgatpa", "shtvala", 72 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 73 "smstateen", "ssaia", "ssccptr", "sscofpmf", 74 "sscounterenw", "ssnpm", "ssstateen", "sstc", 75 "sstvala", "sstvecd", "ssu64xl", "svade", 76 "svinval", "svnapot", "svpbmt", "za64rs", 77 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 78 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 79 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 80 "ziccamoa", "ziccif", "zicclsm", "zicntr", 81 "zicond", "zicsr", "zifencei", "zihintntl", 82 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 83 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 84 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 85 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 86 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 87 riscv,cbom-block-size = <64>; 88 riscv,cbop-block-size = <64>; 89 riscv,cboz-block-size = <64>; 90 i-cache-block-size = <64>; 91 i-cache-size = <65536>; 92 i-cache-sets = <256>; 93 d-cache-block-size = <64>; 94 d-cache-size = <65536>; 95 d-cache-sets = <256>; 96 next-level-cache = <&l2_cache0>; 97 mmu-type = "riscv,sv39"; 98 99 cpu1_intc: interrupt-controller { 100 compatible = "riscv,cpu-intc"; 101 #interrupt-cells = <1>; 102 interrupt-controller; 103 }; 104 }; 105 106 cpu_2: cpu@2 { 107 compatible = "spacemit,x100", "riscv"; 108 device_type = "cpu"; 109 reg = <2>; 110 riscv,isa-base = "rv64i"; 111 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 112 "sha", "shcounterenw", "shgatpa", "shtvala", 113 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 114 "smstateen", "ssaia", "ssccptr", "sscofpmf", 115 "sscounterenw", "ssnpm", "ssstateen", "sstc", 116 "sstvala", "sstvecd", "ssu64xl", "svade", 117 "svinval", "svnapot", "svpbmt", "za64rs", 118 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 119 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 120 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 121 "ziccamoa", "ziccif", "zicclsm", "zicntr", 122 "zicond", "zicsr", "zifencei", "zihintntl", 123 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 124 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 125 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 126 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 127 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 128 riscv,cbom-block-size = <64>; 129 riscv,cbop-block-size = <64>; 130 riscv,cboz-block-size = <64>; 131 i-cache-block-size = <64>; 132 i-cache-size = <65536>; 133 i-cache-sets = <256>; 134 d-cache-block-size = <64>; 135 d-cache-size = <65536>; 136 d-cache-sets = <256>; 137 next-level-cache = <&l2_cache0>; 138 mmu-type = "riscv,sv39"; 139 140 cpu2_intc: interrupt-controller { 141 compatible = "riscv,cpu-intc"; 142 #interrupt-cells = <1>; 143 interrupt-controller; 144 }; 145 }; 146 147 cpu_3: cpu@3 { 148 compatible = "spacemit,x100", "riscv"; 149 device_type = "cpu"; 150 reg = <3>; 151 riscv,isa-base = "rv64i"; 152 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 153 "sha", "shcounterenw", "shgatpa", "shtvala", 154 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 155 "smstateen", "ssaia", "ssccptr", "sscofpmf", 156 "sscounterenw", "ssnpm", "ssstateen", "sstc", 157 "sstvala", "sstvecd", "ssu64xl", "svade", 158 "svinval", "svnapot", "svpbmt", "za64rs", 159 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 160 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 161 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 162 "ziccamoa", "ziccif", "zicclsm", "zicntr", 163 "zicond", "zicsr", "zifencei", "zihintntl", 164 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 165 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 166 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 167 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 168 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 169 riscv,cbom-block-size = <64>; 170 riscv,cbop-block-size = <64>; 171 riscv,cboz-block-size = <64>; 172 i-cache-block-size = <64>; 173 i-cache-size = <65536>; 174 i-cache-sets = <256>; 175 d-cache-block-size = <64>; 176 d-cache-size = <65536>; 177 d-cache-sets = <256>; 178 next-level-cache = <&l2_cache0>; 179 mmu-type = "riscv,sv39"; 180 181 cpu3_intc: interrupt-controller { 182 compatible = "riscv,cpu-intc"; 183 #interrupt-cells = <1>; 184 interrupt-controller; 185 }; 186 }; 187 188 cpu_4: cpu@4 { 189 compatible = "spacemit,x100", "riscv"; 190 device_type = "cpu"; 191 reg = <4>; 192 riscv,isa-base = "rv64i"; 193 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 194 "sha", "shcounterenw", "shgatpa", "shtvala", 195 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 196 "smstateen", "ssaia", "ssccptr", "sscofpmf", 197 "sscounterenw", "ssnpm", "ssstateen", "sstc", 198 "sstvala", "sstvecd", "ssu64xl", "svade", 199 "svinval", "svnapot", "svpbmt", "za64rs", 200 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 201 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 202 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 203 "ziccamoa", "ziccif", "zicclsm", "zicntr", 204 "zicond", "zicsr", "zifencei", "zihintntl", 205 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 206 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 207 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 208 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 209 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 210 riscv,cbom-block-size = <64>; 211 riscv,cbop-block-size = <64>; 212 riscv,cboz-block-size = <64>; 213 i-cache-block-size = <64>; 214 i-cache-size = <65536>; 215 i-cache-sets = <256>; 216 d-cache-block-size = <64>; 217 d-cache-size = <65536>; 218 d-cache-sets = <256>; 219 next-level-cache = <&l2_cache1>; 220 mmu-type = "riscv,sv39"; 221 222 cpu4_intc: interrupt-controller { 223 compatible = "riscv,cpu-intc"; 224 #interrupt-cells = <1>; 225 interrupt-controller; 226 }; 227 }; 228 229 cpu_5: cpu@5 { 230 compatible = "spacemit,x100", "riscv"; 231 device_type = "cpu"; 232 reg = <5>; 233 riscv,isa-base = "rv64i"; 234 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 235 "sha", "shcounterenw", "shgatpa", "shtvala", 236 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 237 "smstateen", "ssaia", "ssccptr", "sscofpmf", 238 "sscounterenw", "ssnpm", "ssstateen", "sstc", 239 "sstvala", "sstvecd", "ssu64xl", "svade", 240 "svinval", "svnapot", "svpbmt", "za64rs", 241 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 242 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 243 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 244 "ziccamoa", "ziccif", "zicclsm", "zicntr", 245 "zicond", "zicsr", "zifencei", "zihintntl", 246 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 247 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 248 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 249 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 250 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 251 riscv,cbom-block-size = <64>; 252 riscv,cbop-block-size = <64>; 253 riscv,cboz-block-size = <64>; 254 i-cache-block-size = <64>; 255 i-cache-size = <65536>; 256 i-cache-sets = <256>; 257 d-cache-block-size = <64>; 258 d-cache-size = <65536>; 259 d-cache-sets = <256>; 260 next-level-cache = <&l2_cache1>; 261 mmu-type = "riscv,sv39"; 262 263 cpu5_intc: interrupt-controller { 264 compatible = "riscv,cpu-intc"; 265 #interrupt-cells = <1>; 266 interrupt-controller; 267 }; 268 }; 269 270 cpu_6: cpu@6 { 271 compatible = "spacemit,x100", "riscv"; 272 device_type = "cpu"; 273 reg = <6>; 274 riscv,isa-base = "rv64i"; 275 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 276 "sha", "shcounterenw", "shgatpa", "shtvala", 277 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 278 "smstateen", "ssaia", "ssccptr", "sscofpmf", 279 "sscounterenw", "ssnpm", "ssstateen", "sstc", 280 "sstvala", "sstvecd", "ssu64xl", "svade", 281 "svinval", "svnapot", "svpbmt", "za64rs", 282 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 283 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 284 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 285 "ziccamoa", "ziccif", "zicclsm", "zicntr", 286 "zicond", "zicsr", "zifencei", "zihintntl", 287 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 288 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 289 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 290 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 291 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 292 riscv,cbom-block-size = <64>; 293 riscv,cbop-block-size = <64>; 294 riscv,cboz-block-size = <64>; 295 i-cache-block-size = <64>; 296 i-cache-size = <65536>; 297 i-cache-sets = <256>; 298 d-cache-block-size = <64>; 299 d-cache-size = <65536>; 300 d-cache-sets = <256>; 301 next-level-cache = <&l2_cache1>; 302 mmu-type = "riscv,sv39"; 303 304 cpu6_intc: interrupt-controller { 305 compatible = "riscv,cpu-intc"; 306 #interrupt-cells = <1>; 307 interrupt-controller; 308 }; 309 }; 310 311 cpu_7: cpu@7 { 312 compatible = "spacemit,x100", "riscv"; 313 device_type = "cpu"; 314 reg = <7>; 315 riscv,isa-base = "rv64i"; 316 riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "b", "v", "h", 317 "sha", "shcounterenw", "shgatpa", "shtvala", 318 "shvsatpa", "shvstvala", "shvstvecd", "smaia", 319 "smstateen", "ssaia", "ssccptr", "sscofpmf", 320 "sscounterenw", "ssnpm", "ssstateen", "sstc", 321 "sstvala", "sstvecd", "ssu64xl", "svade", 322 "svinval", "svnapot", "svpbmt", "za64rs", 323 "zawrs", "zba", "zbb", "zbc", "zbs", "zca", 324 "zcb", "zcd", "zcmop", "zfa", "zfbfmin", 325 "zfh", "zfhmin", "zicbom", "zicbop", "zicboz", 326 "ziccamoa", "ziccif", "zicclsm", "zicntr", 327 "zicond", "zicsr", "zifencei", "zihintntl", 328 "zihintpause", "zihpm", "zimop", "zkt", "zvbb", 329 "zvbc", "zvfbfmin", "zvfbfwma", "zvfh", 330 "zvfhmin", "zvkb", "zvkg", "zvkn", "zvknc", 331 "zvkned", "zvkng", "zvknha", "zvknhb", "zvks", 332 "zvksc", "zvksed", "zvksg", "zvksh", "zvkt"; 333 riscv,cbom-block-size = <64>; 334 riscv,cbop-block-size = <64>; 335 riscv,cboz-block-size = <64>; 336 i-cache-block-size = <64>; 337 i-cache-size = <65536>; 338 i-cache-sets = <256>; 339 d-cache-block-size = <64>; 340 d-cache-size = <65536>; 341 d-cache-sets = <256>; 342 next-level-cache = <&l2_cache1>; 343 mmu-type = "riscv,sv39"; 344 345 cpu7_intc: interrupt-controller { 346 compatible = "riscv,cpu-intc"; 347 #interrupt-cells = <1>; 348 interrupt-controller; 349 }; 350 }; 351 352 l2_cache0: cache-controller-0 { 353 compatible = "cache"; 354 cache-block-size = <64>; 355 cache-level = <2>; 356 cache-size = <4194304>; 357 cache-sets = <4096>; 358 cache-unified; 359 }; 360 361 l2_cache1: cache-controller-1 { 362 compatible = "cache"; 363 cache-block-size = <64>; 364 cache-level = <2>; 365 cache-size = <4194304>; 366 cache-sets = <4096>; 367 cache-unified; 368 }; 369 370 cpu-map { 371 cluster0 { 372 core0 { 373 cpu = <&cpu_0>; 374 }; 375 core1 { 376 cpu = <&cpu_1>; 377 }; 378 core2 { 379 cpu = <&cpu_2>; 380 }; 381 core3 { 382 cpu = <&cpu_3>; 383 }; 384 }; 385 386 cluster1 { 387 core0 { 388 cpu = <&cpu_4>; 389 }; 390 core1 { 391 cpu = <&cpu_5>; 392 }; 393 core2 { 394 cpu = <&cpu_6>; 395 }; 396 core3 { 397 cpu = <&cpu_7>; 398 }; 399 }; 400 }; 401 }; 402 403 clocks { 404 vctcxo_1m: clock-1m { 405 compatible = "fixed-clock"; 406 clock-frequency = <1000000>; 407 clock-output-names = "vctcxo_1m"; 408 #clock-cells = <0>; 409 }; 410 411 vctcxo_24m: clock-24m { 412 compatible = "fixed-clock"; 413 clock-frequency = <24000000>; 414 clock-output-names = "vctcxo_24m"; 415 #clock-cells = <0>; 416 }; 417 418 vctcxo_3m: clock-3m { 419 compatible = "fixed-clock"; 420 clock-frequency = <3000000>; 421 clock-output-names = "vctcxo_3m"; 422 #clock-cells = <0>; 423 }; 424 425 osc_32k: clock-32k { 426 compatible = "fixed-clock"; 427 clock-frequency = <32000>; 428 clock-output-names = "osc_32k"; 429 #clock-cells = <0>; 430 }; 431 }; 432 433 soc: soc { 434 compatible = "simple-bus"; 435 interrupt-parent = <&saplic>; 436 #address-cells = <2>; 437 #size-cells = <2>; 438 dma-noncoherent; 439 ranges; 440 441 eth0: ethernet@cac80000 { 442 compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; 443 reg = <0x0 0xcac80000 0x0 0x2000>; 444 clocks = <&syscon_apmu CLK_APMU_EMAC0_BUS>, 445 <&syscon_apmu CLK_APMU_EMAC0_1588>, 446 <&syscon_apmu CLK_APMU_EMAC0_RGMII_TX>; 447 clock-names = "stmmaceth", "ptp_ref", "tx"; 448 interrupts = <131 IRQ_TYPE_LEVEL_HIGH>, 449 <276 IRQ_TYPE_LEVEL_HIGH>; 450 interrupt-names = "macirq", "eth_wake_irq"; 451 resets = <&syscon_apmu RESET_APMU_EMAC0>; 452 reset-names = "stmmaceth"; 453 rx-fifo-depth = <8192>; 454 tx-fifo-depth = <8192>; 455 snps,multicast-filter-bins = <64>; 456 snps,perfect-filter-entries = <32>; 457 snps,aal; 458 snps,tso; 459 snps,txpbl = <8>; 460 snps,rxpbl = <8>; 461 snps,force_sf_dma_mode; 462 snps,axi-config = <&gmac0_axi_setup>; 463 spacemit,apmu = <&syscon_apmu 0x3e4 0x3e8>; 464 status = "disabled"; 465 466 mdio { 467 compatible = "snps,dwmac-mdio"; 468 #address-cells = <1>; 469 #size-cells = <0>; 470 }; 471 472 gmac0_axi_setup: stmmac-axi-config { 473 snps,wr_osr_lmt = <0xf>; 474 snps,rd_osr_lmt = <0xf>; 475 /* max axi burst len is 256 */ 476 snps,blen = <256 128 64 32 16 0 0>; 477 }; 478 }; 479 480 eth1: ethernet@cac82000 { 481 compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; 482 reg = <0x0 0xcac82000 0x0 0x2000>; 483 clocks = <&syscon_apmu CLK_APMU_EMAC1_BUS>, 484 <&syscon_apmu CLK_APMU_EMAC1_1588>, 485 <&syscon_apmu CLK_APMU_EMAC1_RGMII_TX>; 486 clock-names = "stmmaceth", "ptp_ref", "tx"; 487 interrupts = <133 IRQ_TYPE_LEVEL_HIGH>, 488 <277 IRQ_TYPE_LEVEL_HIGH>; 489 interrupt-names = "macirq", "eth_wake_irq"; 490 resets = <&syscon_apmu RESET_APMU_EMAC1>; 491 reset-names = "stmmaceth"; 492 rx-fifo-depth = <8192>; 493 tx-fifo-depth = <8192>; 494 snps,multicast-filter-bins = <64>; 495 snps,perfect-filter-entries = <32>; 496 snps,aal; 497 snps,tso; 498 snps,txpbl = <8>; 499 snps,rxpbl = <8>; 500 snps,force_sf_dma_mode; 501 snps,axi-config = <&gmac1_axi_setup>; 502 spacemit,apmu = <&syscon_apmu 0x3ec 0x3f0>; 503 status = "disabled"; 504 505 mdio { 506 compatible = "snps,dwmac-mdio"; 507 #address-cells = <1>; 508 #size-cells = <0>; 509 }; 510 511 gmac1_axi_setup: stmmac-axi-config { 512 snps,wr_osr_lmt = <0xf>; 513 snps,rd_osr_lmt = <0xf>; 514 /* max axi burst len is 256 */ 515 snps,blen = <256 128 64 32 16 0 0>; 516 }; 517 }; 518 519 eth2: ethernet@cac8e000 { 520 compatible = "spacemit,k3-dwmac", "snps,dwmac-5.40a"; 521 reg = <0x0 0xcac8e000 0x0 0x2000>; 522 clocks = <&syscon_apmu CLK_APMU_EMAC2_BUS>, 523 <&syscon_apmu CLK_APMU_EMAC2_1588>, 524 <&syscon_apmu CLK_APMU_EMAC2_RGMII_TX>; 525 clock-names = "stmmaceth", "ptp_ref", "tx"; 526 interrupts = <130 IRQ_TYPE_LEVEL_HIGH>, 527 <278 IRQ_TYPE_LEVEL_HIGH>; 528 interrupt-names = "macirq", "eth_wake_irq"; 529 resets = <&syscon_apmu RESET_APMU_EMAC2>; 530 reset-names = "stmmaceth"; 531 rx-fifo-depth = <4096>; 532 tx-fifo-depth = <4096>; 533 snps,multicast-filter-bins = <64>; 534 snps,perfect-filter-entries = <32>; 535 snps,aal; 536 snps,tso; 537 snps,txpbl = <8>; 538 snps,rxpbl = <8>; 539 snps,force_sf_dma_mode; 540 snps,axi-config = <&gmac2_axi_setup>; 541 spacemit,apmu = <&syscon_apmu 0x248 0x24c>; 542 status = "disabled"; 543 544 mdio { 545 compatible = "snps,dwmac-mdio"; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 }; 549 550 gmac2_axi_setup: stmmac-axi-config { 551 snps,wr_osr_lmt = <0xf>; 552 snps,rd_osr_lmt = <0xf>; 553 /* max axi burst len is 256 */ 554 snps,blen = <256 128 64 32 16 0 0>; 555 }; 556 }; 557 558 i2c0: i2c@d4010800 { 559 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 560 reg = <0x0 0xd4010800 0x0 0x38>; 561 #address-cells = <1>; 562 #size-cells = <0>; 563 interrupts = <36 IRQ_TYPE_LEVEL_HIGH>; 564 clocks = <&syscon_apbc CLK_APBC_TWSI0>, 565 <&syscon_apbc CLK_APBC_TWSI0_BUS>; 566 clock-names = "func", "bus"; 567 clock-frequency = <400000>; 568 resets = <&syscon_apbc RESET_APBC_TWSI0>; 569 status = "disabled"; 570 }; 571 572 i2c1: i2c@d4011000 { 573 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 574 reg = <0x0 0xd4011000 0x0 0x38>; 575 #address-cells = <1>; 576 #size-cells = <0>; 577 interrupts = <37 IRQ_TYPE_LEVEL_HIGH>; 578 clocks = <&syscon_apbc CLK_APBC_TWSI1>, 579 <&syscon_apbc CLK_APBC_TWSI1_BUS>; 580 clock-names = "func", "bus"; 581 clock-frequency = <400000>; 582 resets = <&syscon_apbc RESET_APBC_TWSI1>; 583 status = "disabled"; 584 }; 585 586 i2c2: i2c@d4012000 { 587 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 588 reg = <0x0 0xd4012000 0x0 0x38>; 589 #address-cells = <1>; 590 #size-cells = <0>; 591 interrupts = <38 IRQ_TYPE_LEVEL_HIGH>; 592 clocks = <&syscon_apbc CLK_APBC_TWSI2>, 593 <&syscon_apbc CLK_APBC_TWSI2_BUS>; 594 clock-names = "func", "bus"; 595 clock-frequency = <400000>; 596 resets = <&syscon_apbc RESET_APBC_TWSI2>; 597 status = "disabled"; 598 }; 599 600 i2c4: i2c@d4012800 { 601 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 602 reg = <0x0 0xd4012800 0x0 0x38>; 603 #address-cells = <1>; 604 #size-cells = <0>; 605 interrupts = <40 IRQ_TYPE_LEVEL_HIGH>; 606 clocks = <&syscon_apbc CLK_APBC_TWSI4>, 607 <&syscon_apbc CLK_APBC_TWSI4_BUS>; 608 clock-names = "func", "bus"; 609 clock-frequency = <400000>; 610 resets = <&syscon_apbc RESET_APBC_TWSI4>; 611 status = "disabled"; 612 }; 613 614 i2c5: i2c@d4013800 { 615 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 616 reg = <0x0 0xd4013800 0x0 0x38>; 617 #address-cells = <1>; 618 #size-cells = <0>; 619 interrupts = <41 IRQ_TYPE_LEVEL_HIGH>; 620 clocks = <&syscon_apbc CLK_APBC_TWSI5>, 621 <&syscon_apbc CLK_APBC_TWSI5_BUS>; 622 clock-names = "func", "bus"; 623 clock-frequency = <400000>; 624 resets = <&syscon_apbc RESET_APBC_TWSI5>; 625 status = "disabled"; 626 }; 627 628 syscon_apbc: system-controller@d4015000 { 629 compatible = "spacemit,k3-syscon-apbc"; 630 reg = <0x0 0xd4015000 0x0 0x1000>; 631 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; 632 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; 633 #clock-cells = <1>; 634 #reset-cells = <1>; 635 }; 636 637 uart0: serial@d4017000 { 638 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 639 reg = <0x0 0xd4017000 0x0 0x100>; 640 reg-shift = <2>; 641 reg-io-width = <4>; 642 clocks = <&syscon_apbc CLK_APBC_UART0>, 643 <&syscon_apbc CLK_APBC_UART0_BUS>; 644 clock-names = "core", "bus"; 645 resets = <&syscon_apbc RESET_APBC_UART0>; 646 interrupts = <42 IRQ_TYPE_LEVEL_HIGH>; 647 status = "disabled"; 648 }; 649 650 uart2: serial@d4017100 { 651 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 652 reg = <0x0 0xd4017100 0x0 0x100>; 653 reg-shift = <2>; 654 reg-io-width = <4>; 655 clocks = <&syscon_apbc CLK_APBC_UART2>, 656 <&syscon_apbc CLK_APBC_UART2_BUS>; 657 clock-names = "core", "bus"; 658 resets = <&syscon_apbc RESET_APBC_UART2>; 659 interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; 660 status = "disabled"; 661 }; 662 663 uart3: serial@d4017200 { 664 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 665 reg = <0x0 0xd4017200 0x0 0x100>; 666 reg-shift = <2>; 667 reg-io-width = <4>; 668 clocks = <&syscon_apbc CLK_APBC_UART3>, 669 <&syscon_apbc CLK_APBC_UART3_BUS>; 670 clock-names = "core", "bus"; 671 resets = <&syscon_apbc RESET_APBC_UART3>; 672 interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; 673 status = "disabled"; 674 }; 675 676 uart4: serial@d4017300 { 677 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 678 reg = <0x0 0xd4017300 0x0 0x100>; 679 reg-shift = <2>; 680 reg-io-width = <4>; 681 clocks = <&syscon_apbc CLK_APBC_UART4>, 682 <&syscon_apbc CLK_APBC_UART4_BUS>; 683 clock-names = "core", "bus"; 684 resets = <&syscon_apbc RESET_APBC_UART4>; 685 interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; 686 status = "disabled"; 687 }; 688 689 uart5: serial@d4017400 { 690 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 691 reg = <0x0 0xd4017400 0x0 0x100>; 692 reg-shift = <2>; 693 reg-io-width = <4>; 694 clocks = <&syscon_apbc CLK_APBC_UART5>, 695 <&syscon_apbc CLK_APBC_UART5_BUS>; 696 clock-names = "core", "bus"; 697 resets = <&syscon_apbc RESET_APBC_UART5>; 698 interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; 699 status = "disabled"; 700 }; 701 702 uart6: serial@d4017500 { 703 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 704 reg = <0x0 0xd4017500 0x0 0x100>; 705 reg-shift = <2>; 706 reg-io-width = <4>; 707 clocks = <&syscon_apbc CLK_APBC_UART6>, 708 <&syscon_apbc CLK_APBC_UART6_BUS>; 709 clock-names = "core", "bus"; 710 resets = <&syscon_apbc RESET_APBC_UART6>; 711 interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; 712 status = "disabled"; 713 }; 714 715 uart7: serial@d4017600 { 716 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 717 reg = <0x0 0xd4017600 0x0 0x100>; 718 reg-shift = <2>; 719 reg-io-width = <4>; 720 clocks = <&syscon_apbc CLK_APBC_UART7>, 721 <&syscon_apbc CLK_APBC_UART7_BUS>; 722 clock-names = "core", "bus"; 723 resets = <&syscon_apbc RESET_APBC_UART7>; 724 interrupts = <49 IRQ_TYPE_LEVEL_HIGH>; 725 status = "disabled"; 726 }; 727 728 uart8: serial@d4017700 { 729 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 730 reg = <0x0 0xd4017700 0x0 0x100>; 731 reg-shift = <2>; 732 reg-io-width = <4>; 733 clocks = <&syscon_apbc CLK_APBC_UART8>, 734 <&syscon_apbc CLK_APBC_UART8_BUS>; 735 clock-names = "core", "bus"; 736 resets = <&syscon_apbc RESET_APBC_UART8>; 737 interrupts = <50 IRQ_TYPE_LEVEL_HIGH>; 738 status = "disabled"; 739 }; 740 741 uart9: serial@d4017800 { 742 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 743 reg = <0x0 0xd4017800 0x0 0x100>; 744 reg-shift = <2>; 745 reg-io-width = <4>; 746 clocks = <&syscon_apbc CLK_APBC_UART9>, 747 <&syscon_apbc CLK_APBC_UART9_BUS>; 748 clock-names = "core", "bus"; 749 resets = <&syscon_apbc RESET_APBC_UART9>; 750 interrupts = <51 IRQ_TYPE_LEVEL_HIGH>; 751 status = "disabled"; 752 }; 753 754 i2c6: i2c@d4018800 { 755 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 756 reg = <0x0 0xd4018800 0x0 0x38>; 757 #address-cells = <1>; 758 #size-cells = <0>; 759 interrupts = <70 IRQ_TYPE_LEVEL_HIGH>; 760 clocks = <&syscon_apbc CLK_APBC_TWSI6>, 761 <&syscon_apbc CLK_APBC_TWSI6_BUS>; 762 clock-names = "func", "bus"; 763 clock-frequency = <400000>; 764 resets = <&syscon_apbc RESET_APBC_TWSI6>; 765 status = "disabled"; 766 }; 767 768 gpio: gpio@d4019000 { 769 compatible = "spacemit,k3-gpio"; 770 reg = <0x0 0xd4019000 0x0 0x100>; 771 clocks = <&syscon_apbc CLK_APBC_GPIO>, 772 <&syscon_apbc CLK_APBC_GPIO_BUS>; 773 clock-names = "core", "bus"; 774 gpio-controller; 775 #gpio-cells = <3>; 776 interrupts = <58 IRQ_TYPE_LEVEL_HIGH>; 777 interrupt-parent = <&saplic>; 778 interrupt-controller; 779 #interrupt-cells = <3>; 780 gpio-ranges = <&pinctrl 0 0 0 32>, 781 <&pinctrl 1 0 32 32>, 782 <&pinctrl 2 0 64 32>, 783 <&pinctrl 3 0 96 32>; 784 }; 785 786 i2c8: i2c@d401d800 { 787 compatible = "spacemit,k3-i2c", "spacemit,k1-i2c"; 788 reg = <0x0 0xd401d800 0x0 0x38>; 789 #address-cells = <1>; 790 #size-cells = <0>; 791 interrupts = <19 IRQ_TYPE_LEVEL_HIGH>; 792 clocks = <&syscon_apbc CLK_APBC_TWSI8>, 793 <&syscon_apbc CLK_APBC_TWSI8_BUS>; 794 clock-names = "func", "bus"; 795 clock-frequency = <400000>; 796 resets = <&syscon_apbc RESET_APBC_TWSI8>; 797 status = "disabled"; 798 }; 799 800 pinctrl: pinctrl@d401e000 { 801 compatible = "spacemit,k3-pinctrl"; 802 reg = <0x0 0xd401e000 0x0 0x1000>; 803 clocks = <&syscon_apbc CLK_APBC_AIB>, 804 <&syscon_apbc CLK_APBC_AIB_BUS>; 805 clock-names = "func", "bus"; 806 }; 807 808 uart10: serial@d401f000 { 809 compatible = "spacemit,k3-uart", "intel,xscale-uart"; 810 reg = <0x0 0xd401f000 0x0 0x100>; 811 reg-shift = <2>; 812 reg-io-width = <4>; 813 clocks = <&syscon_apbc CLK_APBC_UART10>, 814 <&syscon_apbc CLK_APBC_UART10_BUS>; 815 clock-names = "core", "bus"; 816 resets = <&syscon_apbc RESET_APBC_UART10>; 817 interrupts = <281 IRQ_TYPE_LEVEL_HIGH>; 818 status = "disabled"; 819 }; 820 821 syscon_mpmu: system-controller@d4050000 { 822 compatible = "spacemit,k3-syscon-mpmu"; 823 reg = <0x0 0xd4050000 0x0 0x10000>; 824 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; 825 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; 826 #clock-cells = <1>; 827 #power-domain-cells = <1>; 828 #reset-cells = <1>; 829 }; 830 831 pll: clock-controller@d4090000 { 832 compatible = "spacemit,k3-pll"; 833 reg = <0x0 0xd4090000 0x0 0x10000>; 834 clocks = <&vctcxo_24m>; 835 spacemit,mpmu = <&syscon_mpmu>; 836 #clock-cells = <1>; 837 }; 838 839 syscon_apmu: system-controller@d4282800 { 840 compatible = "spacemit,k3-syscon-apmu"; 841 reg = <0x0 0xd4282800 0x0 0x400>; 842 clocks = <&osc_32k>, <&vctcxo_1m>, <&vctcxo_3m>, <&vctcxo_24m>; 843 clock-names = "osc", "vctcxo_1m", "vctcxo_3m", "vctcxo_24m"; 844 #clock-cells = <1>; 845 #power-domain-cells = <1>; 846 #reset-cells = <1>; 847 }; 848 849 syscon_dciu: system-controller@d8440000 { 850 compatible = "spacemit,k3-syscon-dciu"; 851 reg = <0x0 0xd8440000 0x0 0xc000>; 852 #clock-cells = <1>; 853 #reset-cells = <1>; 854 }; 855 856 simsic: interrupt-controller@e0400000 { 857 compatible = "spacemit,k3-imsics", "riscv,imsics"; 858 reg = <0x0 0xe0400000 0x0 0x200000>; 859 #interrupt-cells = <0>; 860 #msi-cells = <0>; 861 interrupt-controller; 862 interrupts-extended = <&cpu0_intc 9>, <&cpu1_intc 9>, 863 <&cpu2_intc 9>, <&cpu3_intc 9>, 864 <&cpu4_intc 9>, <&cpu5_intc 9>, 865 <&cpu6_intc 9>, <&cpu7_intc 9>; 866 msi-controller; 867 riscv,guest-index-bits = <6>; 868 riscv,hart-index-bits = <4>; 869 riscv,num-guest-ids = <511>; 870 riscv,num-ids = <511>; 871 }; 872 873 saplic: interrupt-controller@e0804000 { 874 compatible = "spacemit,k3-aplic", "riscv,aplic"; 875 reg = <0x0 0xe0804000 0x0 0x4000>; 876 #interrupt-cells = <2>; 877 interrupt-controller; 878 msi-parent = <&simsic>; 879 riscv,num-sources = <512>; 880 }; 881 882 clint: timer@e081c000 { 883 compatible = "spacemit,k3-clint", "sifive,clint0"; 884 reg = <0x0 0xe081c000 0x0 0x4000>; 885 interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>, 886 <&cpu1_intc 3>, <&cpu1_intc 7>, 887 <&cpu2_intc 3>, <&cpu2_intc 7>, 888 <&cpu3_intc 3>, <&cpu3_intc 7>, 889 <&cpu4_intc 3>, <&cpu4_intc 7>, 890 <&cpu5_intc 3>, <&cpu5_intc 7>, 891 <&cpu6_intc 3>, <&cpu6_intc 7>, 892 <&cpu7_intc 3>, <&cpu7_intc 7>; 893 }; 894 895 /* sec_i2c3: 0xf0614000, not available from Linux */ 896 897 mimsic: interrupt-controller@f1000000 { 898 compatible = "spacemit,k3-imsics", "riscv,imsics"; 899 reg = <0x0 0xf1000000 0x0 0x10000>; 900 #interrupt-cells = <0>; 901 #msi-cells = <0>; 902 interrupt-controller; 903 interrupts-extended = <&cpu0_intc 11>, <&cpu1_intc 11>, 904 <&cpu2_intc 11>, <&cpu3_intc 11>, 905 <&cpu4_intc 11>, <&cpu5_intc 11>, 906 <&cpu6_intc 11>, <&cpu7_intc 11>; 907 msi-controller; 908 riscv,guest-index-bits = <6>; 909 riscv,hart-index-bits = <4>; 910 riscv,num-guest-ids = <511>; 911 riscv,num-ids = <511>; 912 status = "reserved"; 913 }; 914 915 maplic: interrupt-controller@f1800000 { 916 compatible = "spacemit,k3-aplic", "riscv,aplic"; 917 reg = <0x0 0xf1800000 0x0 0x4000>; 918 #interrupt-cells = <2>; 919 interrupt-controller; 920 msi-parent = <&mimsic>; 921 riscv,children = <&saplic>; 922 riscv,delegation = <&saplic 1 512>; 923 riscv,num-sources = <512>; 924 status = "reserved"; 925 }; 926 }; 927}; 928