xref: /freebsd/sys/contrib/device-tree/src/riscv/microchip/mpfs-icicle-kit-common.dtsi (revision 69ed3df4f588860308677cda76cbcce1f19a54c9) 
1// SPDX-License-Identifier: (GPL-2.0 OR MIT)
2/* Copyright (c) 2025 Microchip Technology Inc */
3
4/dts-v1/;
5
6#include "mpfs-icicle-kit-fabric.dtsi"
7#include <dt-bindings/gpio/gpio.h>
8#include <dt-bindings/leds/common.h>
9
10/ {
11	aliases {
12		ethernet0 = &mac1;
13		serial0 = &mmuart0;
14		serial1 = &mmuart1;
15		serial2 = &mmuart2;
16		serial3 = &mmuart3;
17		serial4 = &mmuart4;
18	};
19
20	chosen {
21		stdout-path = "serial1:115200n8";
22	};
23
24	leds {
25		compatible = "gpio-leds";
26
27		led-1 {
28			gpios = <&gpio2 16 GPIO_ACTIVE_HIGH>;
29			color = <LED_COLOR_ID_RED>;
30			label = "led1";
31		};
32
33		led-2 {
34			gpios = <&gpio2 17 GPIO_ACTIVE_HIGH>;
35			color = <LED_COLOR_ID_RED>;
36			label = "led2";
37		};
38
39		led-3 {
40			gpios = <&gpio2 18 GPIO_ACTIVE_HIGH>;
41			color = <LED_COLOR_ID_AMBER>;
42			label = "led3";
43		};
44
45		led-4 {
46			gpios = <&gpio2 19 GPIO_ACTIVE_HIGH>;
47			color = <LED_COLOR_ID_AMBER>;
48			label = "led4";
49		};
50	};
51
52	ddrc_cache_lo: memory@80000000 {
53		device_type = "memory";
54		reg = <0x0 0x80000000 0x0 0x40000000>;
55	};
56
57	ddrc_cache_hi: memory@1040000000 {
58		device_type = "memory";
59		reg = <0x10 0x40000000 0x0 0x40000000>;
60	};
61
62	reserved-memory {
63		#address-cells = <2>;
64		#size-cells = <2>;
65		ranges;
66
67		hss_payload: region@bfc00000 {
68			reg = <0x0 0xbfc00000 0x0 0x400000>;
69			no-map;
70		};
71	};
72};
73
74&core_pwm0 {
75	status = "okay";
76};
77
78&gpio2 {
79	status = "okay";
80};
81
82&i2c0 {
83	status = "okay";
84};
85
86&i2c1 {
87	status = "okay";
88
89	power-monitor@10 {
90		compatible = "microchip,pac1934";
91		reg = <0x10>;
92
93		#address-cells = <1>;
94		#size-cells = <0>;
95
96		channel@1 {
97			reg = <0x1>;
98			shunt-resistor-micro-ohms = <10000>;
99			label = "VDDREG";
100		};
101
102		channel@2 {
103			reg = <0x2>;
104			shunt-resistor-micro-ohms = <10000>;
105			label = "VDDA25";
106		};
107
108		channel@3 {
109			reg = <0x3>;
110			shunt-resistor-micro-ohms = <10000>;
111			label = "VDD25";
112		};
113
114		channel@4 {
115			reg = <0x4>;
116			shunt-resistor-micro-ohms = <10000>;
117			label = "VDDA_REG";
118		};
119	};
120};
121
122&i2c2 {
123	status = "okay";
124};
125
126&ihc {
127	status = "okay";
128};
129
130&irqmux {
131	interrupt-map = <0 &plic 13>, <1 &plic 14>, <2 &plic 15>,
132			<3 &plic 16>, <4 &plic 17>, <5 &plic 18>,
133			<6 &plic 19>, <7 &plic 20>, <8 &plic 21>,
134			<9 &plic 22>, <10 &plic 23>, <11 &plic 24>,
135			<12 &plic 25>, <13 &plic 26>,
136
137			<32 &plic 27>, <33 &plic 28>, <34 &plic 29>,
138			<35 &plic 30>, <36 &plic 31>, <37 &plic 32>,
139			<38 &plic 33>, <39 &plic 34>, <40 &plic 35>,
140			<41 &plic 36>, <42 &plic 37>, <43 &plic 38>,
141			<44 &plic 39>, <45 &plic 40>, <46 &plic 41>,
142			<47 &plic 42>, <48 &plic 43>, <49 &plic 44>,
143			<50 &plic 45>, <51 &plic 46>, <52 &plic 47>,
144			<53 &plic 48>, <54 &plic 49>, <55 &plic 50>,
145
146			<64 &plic 53>, <65 &plic 53>, <66 &plic 53>,
147			<67 &plic 53>, <68 &plic 53>, <69 &plic 53>,
148			<70 &plic 53>, <71 &plic 53>, <72 &plic 53>,
149			<73 &plic 53>, <74 &plic 53>, <75 &plic 53>,
150			<76 &plic 53>, <77 &plic 53>, <78 &plic 53>,
151			<79 &plic 53>, <80 &plic 53>, <81 &plic 53>,
152			<82 &plic 53>, <83 &plic 53>, <84 &plic 53>,
153			<85 &plic 53>, <86 &plic 53>, <87 &plic 53>,
154			<88 &plic 53>, <89 &plic 53>, <90 &plic 53>,
155			<91 &plic 53>, <92 &plic 53>, <93 &plic 53>,
156			<94 &plic 53>, <95 &plic 53>;
157};
158
159&mac0 {
160	phy-mode = "sgmii";
161	phy-handle = <&phy0>;
162	status = "okay";
163};
164
165&mac1 {
166	phy-mode = "sgmii";
167	phy-handle = <&phy1>;
168	status = "okay";
169
170	phy1: ethernet-phy@9 {
171		reg = <9>;
172	};
173
174	phy0: ethernet-phy@8 {
175		reg = <8>;
176	};
177};
178
179&mbox {
180	status = "okay";
181};
182
183&mmc {
184	bus-width = <4>;
185	disable-wp;
186	cap-sd-highspeed;
187	cap-mmc-highspeed;
188	mmc-ddr-1_8v;
189	mmc-hs200-1_8v;
190	sd-uhs-sdr12;
191	sd-uhs-sdr25;
192	sd-uhs-sdr50;
193	sd-uhs-sdr104;
194	status = "okay";
195};
196
197&mmuart1 {
198	status = "okay";
199};
200
201&mmuart2 {
202	status = "okay";
203};
204
205&mmuart3 {
206	status = "okay";
207};
208
209&mmuart4 {
210	status = "okay";
211};
212
213&pcie {
214	status = "okay";
215};
216
217&qspi {
218	status = "okay";
219};
220
221&refclk {
222	clock-frequency = <125000000>;
223};
224
225&refclk_ccc {
226	clock-frequency = <50000000>;
227};
228
229&rtc {
230	status = "okay";
231};
232
233&spi0 {
234	status = "okay";
235};
236
237&spi1 {
238	status = "okay";
239};
240
241&syscontroller {
242	status = "okay";
243};
244
245&syscontroller_qspi {
246	/*
247	 * The flash *is* there, but Icicle kits that have engineering sample
248	 * silicon (write?) access to this flash to non-functional. The system
249	 * controller itself can actually access it, but the MSS cannot write
250	 * an image there. Instantiating a coreQSPI in the fabric & connecting
251	 * it to the flash instead should work though. Pre-production or later
252	 * silicon does not have this issue.
253	 */
254	status = "disabled";
255
256	sys_ctrl_flash: flash@0 { // MT25QL01GBBB8ESF-0SIT
257		compatible = "jedec,spi-nor";
258		#address-cells = <1>;
259		#size-cells = <1>;
260		spi-max-frequency = <20000000>;
261		spi-rx-bus-width = <1>;
262		reg = <0>;
263	};
264};
265
266&usb {
267	status = "okay";
268	dr_mode = "host";
269};
270