1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2022-2024 Texas Instruments Incorporated - https://www.ti.com/ 4 * 5 * EVM Board Schematics(j784s4): https://www.ti.com/lit/zip/sprr458 6 * EVM Board Schematics(j742s2): https://www.ti.com/lit/zip/SPAC001 7 */ 8 9#include <dt-bindings/phy/phy-cadence.h> 10 11/ { 12 chosen { 13 stdout-path = "serial2:115200n8"; 14 }; 15 16 aliases { 17 serial0 = &wkup_uart0; 18 serial1 = &mcu_uart0; 19 serial2 = &main_uart8; 20 mmc0 = &main_sdhci0; 21 mmc1 = &main_sdhci1; 22 i2c0 = &wkup_i2c0; 23 i2c3 = &main_i2c0; 24 ethernet0 = &mcu_cpsw_port1; 25 ethernet1 = &main_cpsw1_port1; 26 }; 27 28 reserved_memory: reserved-memory { 29 #address-cells = <2>; 30 #size-cells = <2>; 31 ranges; 32 33 secure_ddr: optee@9e800000 { 34 reg = <0x00 0x9e800000 0x00 0x01800000>; 35 no-map; 36 }; 37 38 mcu_r5fss0_core0_dma_memory_region: r5f-dma-memory@a0000000 { 39 compatible = "shared-dma-pool"; 40 reg = <0x00 0xa0000000 0x00 0x100000>; 41 no-map; 42 }; 43 44 mcu_r5fss0_core0_memory_region: r5f-memory@a0100000 { 45 compatible = "shared-dma-pool"; 46 reg = <0x00 0xa0100000 0x00 0xf00000>; 47 no-map; 48 }; 49 50 mcu_r5fss0_core1_dma_memory_region: r5f-dma-memory@a1000000 { 51 compatible = "shared-dma-pool"; 52 reg = <0x00 0xa1000000 0x00 0x100000>; 53 no-map; 54 }; 55 56 mcu_r5fss0_core1_memory_region: r5f-memory@a1100000 { 57 compatible = "shared-dma-pool"; 58 reg = <0x00 0xa1100000 0x00 0xf00000>; 59 no-map; 60 }; 61 62 main_r5fss0_core0_dma_memory_region: r5f-dma-memory@a2000000 { 63 compatible = "shared-dma-pool"; 64 reg = <0x00 0xa2000000 0x00 0x100000>; 65 no-map; 66 }; 67 68 main_r5fss0_core0_memory_region: r5f-memory@a2100000 { 69 compatible = "shared-dma-pool"; 70 reg = <0x00 0xa2100000 0x00 0xf00000>; 71 no-map; 72 }; 73 74 main_r5fss0_core1_dma_memory_region: r5f-dma-memory@a3000000 { 75 compatible = "shared-dma-pool"; 76 reg = <0x00 0xa3000000 0x00 0x100000>; 77 no-map; 78 }; 79 80 main_r5fss0_core1_memory_region: r5f-memory@a3100000 { 81 compatible = "shared-dma-pool"; 82 reg = <0x00 0xa3100000 0x00 0xf00000>; 83 no-map; 84 }; 85 86 main_r5fss1_core0_dma_memory_region: r5f-dma-memory@a4000000 { 87 compatible = "shared-dma-pool"; 88 reg = <0x00 0xa4000000 0x00 0x100000>; 89 no-map; 90 }; 91 92 main_r5fss1_core0_memory_region: r5f-memory@a4100000 { 93 compatible = "shared-dma-pool"; 94 reg = <0x00 0xa4100000 0x00 0xf00000>; 95 no-map; 96 }; 97 98 main_r5fss1_core1_dma_memory_region: r5f-dma-memory@a5000000 { 99 compatible = "shared-dma-pool"; 100 reg = <0x00 0xa5000000 0x00 0x100000>; 101 no-map; 102 }; 103 104 main_r5fss1_core1_memory_region: r5f-memory@a5100000 { 105 compatible = "shared-dma-pool"; 106 reg = <0x00 0xa5100000 0x00 0xf00000>; 107 no-map; 108 }; 109 110 main_r5fss2_core0_dma_memory_region: r5f-dma-memory@a6000000 { 111 compatible = "shared-dma-pool"; 112 reg = <0x00 0xa6000000 0x00 0x100000>; 113 no-map; 114 }; 115 116 main_r5fss2_core0_memory_region: r5f-memory@a6100000 { 117 compatible = "shared-dma-pool"; 118 reg = <0x00 0xa6100000 0x00 0xf00000>; 119 no-map; 120 }; 121 122 main_r5fss2_core1_dma_memory_region: r5f-dma-memory@a7000000 { 123 compatible = "shared-dma-pool"; 124 reg = <0x00 0xa7000000 0x00 0x100000>; 125 no-map; 126 }; 127 128 main_r5fss2_core1_memory_region: r5f-memory@a7100000 { 129 compatible = "shared-dma-pool"; 130 reg = <0x00 0xa7100000 0x00 0xf00000>; 131 no-map; 132 }; 133 134 c71_0_dma_memory_region: c71-dma-memory@a8000000 { 135 compatible = "shared-dma-pool"; 136 reg = <0x00 0xa8000000 0x00 0x100000>; 137 no-map; 138 }; 139 140 c71_0_memory_region: c71-memory@a8100000 { 141 compatible = "shared-dma-pool"; 142 reg = <0x00 0xa8100000 0x00 0xf00000>; 143 no-map; 144 }; 145 146 c71_1_dma_memory_region: c71-dma-memory@a9000000 { 147 compatible = "shared-dma-pool"; 148 reg = <0x00 0xa9000000 0x00 0x100000>; 149 no-map; 150 }; 151 152 c71_1_memory_region: c71-memory@a9100000 { 153 compatible = "shared-dma-pool"; 154 reg = <0x00 0xa9100000 0x00 0xf00000>; 155 no-map; 156 }; 157 158 c71_2_dma_memory_region: c71-dma-memory@aa000000 { 159 compatible = "shared-dma-pool"; 160 reg = <0x00 0xaa000000 0x00 0x100000>; 161 no-map; 162 }; 163 164 c71_2_memory_region: c71-memory@aa100000 { 165 compatible = "shared-dma-pool"; 166 reg = <0x00 0xaa100000 0x00 0xf00000>; 167 no-map; 168 }; 169 }; 170 171 evm_12v0: regulator-evm12v0 { 172 /* main supply */ 173 compatible = "regulator-fixed"; 174 regulator-name = "evm_12v0"; 175 regulator-min-microvolt = <12000000>; 176 regulator-max-microvolt = <12000000>; 177 regulator-always-on; 178 regulator-boot-on; 179 }; 180 181 vsys_3v3: regulator-vsys3v3 { 182 /* Output of LM5140 */ 183 compatible = "regulator-fixed"; 184 regulator-name = "vsys_3v3"; 185 regulator-min-microvolt = <3300000>; 186 regulator-max-microvolt = <3300000>; 187 vin-supply = <&evm_12v0>; 188 regulator-always-on; 189 regulator-boot-on; 190 }; 191 192 vsys_5v0: regulator-vsys5v0 { 193 /* Output of LM5140 */ 194 compatible = "regulator-fixed"; 195 regulator-name = "vsys_5v0"; 196 regulator-min-microvolt = <5000000>; 197 regulator-max-microvolt = <5000000>; 198 vin-supply = <&evm_12v0>; 199 regulator-always-on; 200 regulator-boot-on; 201 }; 202 203 vdd_mmc1: regulator-sd { 204 /* Output of TPS22918 */ 205 compatible = "regulator-fixed"; 206 regulator-name = "vdd_mmc1"; 207 regulator-min-microvolt = <3300000>; 208 regulator-max-microvolt = <3300000>; 209 regulator-boot-on; 210 enable-active-high; 211 vin-supply = <&vsys_3v3>; 212 gpio = <&exp2 2 GPIO_ACTIVE_HIGH>; 213 }; 214 215 vdd_sd_dv: regulator-TLV71033 { 216 /* Output of TLV71033 */ 217 compatible = "regulator-gpio"; 218 regulator-name = "tlv71033"; 219 pinctrl-names = "default"; 220 pinctrl-0 = <&vdd_sd_dv_pins_default>; 221 regulator-min-microvolt = <1800000>; 222 regulator-max-microvolt = <3300000>; 223 regulator-boot-on; 224 vin-supply = <&vsys_5v0>; 225 gpios = <&main_gpio0 8 GPIO_ACTIVE_HIGH>; 226 states = <1800000 0x0>, 227 <3300000 0x1>; 228 }; 229 230 dp0_pwr_3v3: regulator-dp0-prw { 231 compatible = "regulator-fixed"; 232 regulator-name = "dp0-pwr"; 233 regulator-min-microvolt = <3300000>; 234 regulator-max-microvolt = <3300000>; 235 gpio = <&exp4 0 GPIO_ACTIVE_HIGH>; 236 enable-active-high; 237 }; 238 239 dp0: connector-dp0 { 240 compatible = "dp-connector"; 241 label = "DP0"; 242 type = "full-size"; 243 dp-pwr-supply = <&dp0_pwr_3v3>; 244 245 port { 246 dp0_connector_in: endpoint { 247 remote-endpoint = <&dp0_out>; 248 }; 249 }; 250 }; 251 252 transceiver0: can-phy0 { 253 compatible = "ti,tcan1042"; 254 #phy-cells = <0>; 255 max-bitrate = <5000000>; 256 pinctrl-names = "default"; 257 pinctrl-0 = <&mcu_mcan0_gpio_pins_default>; 258 standby-gpios = <&wkup_gpio0 69 GPIO_ACTIVE_HIGH>; 259 }; 260 261 transceiver1: can-phy1 { 262 compatible = "ti,tcan1042"; 263 #phy-cells = <0>; 264 max-bitrate = <5000000>; 265 pinctrl-names = "default"; 266 pinctrl-0 = <&mcu_mcan1_gpio_pins_default>; 267 standby-gpios = <&wkup_gpio0 2 GPIO_ACTIVE_HIGH>; 268 }; 269 270 transceiver2: can-phy2 { 271 /* standby pin has been grounded by default */ 272 compatible = "ti,tcan1042"; 273 #phy-cells = <0>; 274 max-bitrate = <5000000>; 275 }; 276 277 transceiver3: can-phy3 { 278 compatible = "ti,tcan1042"; 279 #phy-cells = <0>; 280 max-bitrate = <5000000>; 281 standby-gpios = <&exp2 7 GPIO_ACTIVE_HIGH>; 282 mux-states = <&mux1 1>; 283 }; 284 285 mux1: mux-controller { 286 compatible = "gpio-mux"; 287 #mux-state-cells = <1>; 288 mux-gpios = <&exp2 14 GPIO_ACTIVE_HIGH>; 289 idle-state = <1>; 290 }; 291 292 codec_audio: sound { 293 compatible = "ti,j7200-cpb-audio"; 294 model = "j784s4-cpb"; 295 296 ti,cpb-mcasp = <&mcasp0>; 297 ti,cpb-codec = <&pcm3168a_1>; 298 299 clocks = <&k3_clks 265 0>, <&k3_clks 265 1>, 300 <&k3_clks 157 34>, <&k3_clks 157 63>; 301 clock-names = "cpb-mcasp-auxclk", "cpb-mcasp-auxclk-48000", 302 "cpb-codec-scki", "cpb-codec-scki-48000"; 303 }; 304}; 305 306&wkup_gpio0 { 307 status = "okay"; 308}; 309 310&main_pmx0 { 311 main_cpsw2g_default_pins: main-cpsw2g-default-pins { 312 pinctrl-single,pins = < 313 J784S4_IOPAD(0x0b8, PIN_INPUT, 6) /* (AC34) MCASP1_ACLKX.RGMII1_RD0 */ 314 J784S4_IOPAD(0x0a0, PIN_INPUT, 6) /* (AD34) MCASP0_AXR12.RGMII1_RD1 */ 315 J784S4_IOPAD(0x0a4, PIN_INPUT, 6) /* (AJ36) MCASP0_AXR13.RGMII1_RD2 */ 316 J784S4_IOPAD(0x0a8, PIN_INPUT, 6) /* (AF34) MCASP0_AXR14.RGMII1_RD3 */ 317 J784S4_IOPAD(0x0b0, PIN_INPUT, 6) /* (AL33) MCASP1_AXR3.RGMII1_RXC */ 318 J784S4_IOPAD(0x0ac, PIN_INPUT, 6) /* (AE34) MCASP0_AXR15.RGMII1_RX_CTL */ 319 J784S4_IOPAD(0x08c, PIN_INPUT, 6) /* (AE35) MCASP0_AXR7.RGMII1_TD0 */ 320 J784S4_IOPAD(0x090, PIN_INPUT, 6) /* (AC35) MCASP0_AXR8.RGMII1_TD1 */ 321 J784S4_IOPAD(0x094, PIN_INPUT, 6) /* (AG35) MCASP0_AXR9.RGMII1_TD2 */ 322 J784S4_IOPAD(0x098, PIN_INPUT, 6) /* (AH36) MCASP0_AXR10.RGMII1_TD3 */ 323 J784S4_IOPAD(0x0b4, PIN_INPUT, 6) /* (AL34) MCASP1_AXR4.RGMII1_TXC */ 324 J784S4_IOPAD(0x09c, PIN_INPUT, 6) /* (AF35) MCASP0_AXR11.RGMII1_TX_CTL */ 325 >; 326 }; 327 328 main_cpsw2g_mdio_default_pins: main-cpsw2g-mdio-default-pins { 329 pinctrl-single,pins = < 330 J784S4_IOPAD(0x0c0, PIN_INPUT, 6) /* (AD38) MCASP1_AXR0.MDIO0_MDC */ 331 J784S4_IOPAD(0x0bc, PIN_INPUT, 6) /* (AD33) MCASP1_AFSX.MDIO0_MDIO */ 332 >; 333 }; 334 335 main_uart8_pins_default: main-uart8-default-pins { 336 bootph-all; 337 pinctrl-single,pins = < 338 J784S4_IOPAD(0x040, PIN_INPUT, 14) /* (AF37) MCASP0_AXR0.UART8_CTSn */ 339 J784S4_IOPAD(0x044, PIN_OUTPUT, 14) /* (AG37) MCASP0_AXR1.UART8_RTSn */ 340 J784S4_IOPAD(0x0d0, PIN_INPUT, 11) /* (AP38) SPI0_CS1.UART8_RXD */ 341 J784S4_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AN38) SPI0_CLK.UART8_TXD */ 342 >; 343 }; 344 345 main_i2c0_pins_default: main-i2c0-default-pins { 346 pinctrl-single,pins = < 347 J784S4_IOPAD(0x0e0, PIN_INPUT_PULLUP, 0) /* (AN36) I2C0_SCL */ 348 J784S4_IOPAD(0x0e4, PIN_INPUT_PULLUP, 0) /* (AP37) I2C0_SDA */ 349 >; 350 }; 351 352 main_i2c5_pins_default: main-i2c5-default-pins { 353 pinctrl-single,pins = < 354 J784S4_IOPAD(0x01c, PIN_INPUT, 8) /* (AG34) MCAN15_TX.I2C5_SCL */ 355 J784S4_IOPAD(0x018, PIN_INPUT, 8) /* (AK36) MCAN14_RX.I2C5_SDA */ 356 >; 357 }; 358 359 main_mmc1_pins_default: main-mmc1-default-pins { 360 bootph-all; 361 pinctrl-single,pins = < 362 J784S4_IOPAD(0x104, PIN_INPUT, 0) /* (AB38) MMC1_CLK */ 363 J784S4_IOPAD(0x108, PIN_INPUT, 0) /* (AB36) MMC1_CMD */ 364 J784S4_IOPAD(0x100, PIN_INPUT, 0) /* (No Pin) MMC1_CLKLB */ 365 J784S4_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA33) MMC1_DAT0 */ 366 J784S4_IOPAD(0x0f8, PIN_INPUT, 0) /* (AB34) MMC1_DAT1 */ 367 J784S4_IOPAD(0x0f4, PIN_INPUT, 0) /* (AA32) MMC1_DAT2 */ 368 J784S4_IOPAD(0x0f0, PIN_INPUT, 0) /* (AC38) MMC1_DAT3 */ 369 J784S4_IOPAD(0x0e8, PIN_INPUT, 8) /* (AR38) TIMER_IO0.MMC1_SDCD */ 370 >; 371 }; 372 373 vdd_sd_dv_pins_default: vdd-sd-dv-default-pins { 374 pinctrl-single,pins = < 375 J784S4_IOPAD(0x020, PIN_INPUT, 7) /* (AJ35) MCAN15_RX.GPIO0_8 */ 376 >; 377 }; 378 379 dp0_pins_default: dp0-default-pins { 380 pinctrl-single,pins = < 381 J784S4_IOPAD(0x0cc, PIN_INPUT, 12) /* (AM37) SPI0_CS0.DP0_HPD */ 382 >; 383 }; 384 385 main_i2c4_pins_default: main-i2c4-default-pins { 386 pinctrl-single,pins = < 387 J784S4_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AG33) MCAN14_TX.I2C4_SCL */ 388 J784S4_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AH33) MCAN13_RX.I2C4_SDA */ 389 >; 390 }; 391 392 main_mcan4_pins_default: main-mcan4-default-pins { 393 pinctrl-single,pins = < 394 J784S4_IOPAD(0x088, PIN_INPUT, 0) /* (AF36) MCAN4_RX */ 395 J784S4_IOPAD(0x084, PIN_OUTPUT, 0) /* (AG38) MCAN4_TX */ 396 >; 397 }; 398 399 main_mcan16_pins_default: main-mcan16-default-pins { 400 pinctrl-single,pins = < 401 J784S4_IOPAD(0x028, PIN_INPUT, 0) /* (AE33) MCAN16_RX */ 402 J784S4_IOPAD(0x024, PIN_OUTPUT, 0) /* (AH34) MCAN16_TX */ 403 >; 404 }; 405 406 main_usbss0_pins_default: main-usbss0-default-pins { 407 bootph-all; 408 pinctrl-single,pins = < 409 J784S4_IOPAD(0x0ec, PIN_OUTPUT, 6) /* (AN37) TIMER_IO1.USB0_DRVVBUS */ 410 >; 411 }; 412 413 main_i2c3_pins_default: main-i2c3-default-pins { 414 pinctrl-single,pins = < 415 J784S4_IOPAD(0x064, PIN_INPUT, 13) /* (AF38) MCAN0_TX.I2C3_SCL */ 416 J784S4_IOPAD(0x060, PIN_INPUT, 13) /* (AE36) MCASP2_AXR1.I2C3_SDA */ 417 >; 418 }; 419 420 main_mcasp0_pins_default: main-mcasp0-default-pins { 421 pinctrl-single,pins = < 422 J784S4_IOPAD(0x038, PIN_OUTPUT_PULLDOWN, 1) /* (AK35) MCASP0_ACLKX */ 423 J784S4_IOPAD(0x03c, PIN_OUTPUT_PULLDOWN, 1) /* (AK38) MCASP0_AFSX */ 424 J784S4_IOPAD(0x07c, PIN_OUTPUT_PULLDOWN, 1) /* (AJ38) MCASP0_AXR3 */ 425 J784S4_IOPAD(0x080, PIN_INPUT_PULLDOWN, 1) /* (AK34) MCASP0_AXR4 */ 426 >; 427 }; 428 429 audio_ext_refclk1_pins_default: audio-ext-refclk1-default-pins { 430 pinctrl-single,pins = < 431 J784S4_IOPAD(0x078, PIN_OUTPUT, 1) /* (AH37) MCAN2_RX.AUDIO_EXT_REFCLK1 */ 432 >; 433 }; 434}; 435 436&wkup_pmx2 { 437 wkup_uart0_pins_default: wkup-uart0-default-pins { 438 bootph-all; 439 pinctrl-single,pins = < 440 J784S4_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (K35) WKUP_UART0_RXD */ 441 J784S4_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (K34) WKUP_UART0_TXD */ 442 >; 443 }; 444 445 wkup_i2c0_pins_default: wkup-i2c0-default-pins { 446 bootph-all; 447 pinctrl-single,pins = < 448 J784S4_WKUP_IOPAD(0x98, PIN_INPUT, 0) /* (N33) WKUP_I2C0_SCL */ 449 J784S4_WKUP_IOPAD(0x9c, PIN_INPUT, 0) /* (N35) WKUP_I2C0_SDA */ 450 >; 451 }; 452 453 mcu_uart0_pins_default: mcu-uart0-default-pins { 454 bootph-all; 455 pinctrl-single,pins = < 456 J784S4_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (H37) WKUP_GPIO0_14.MCU_UART0_CTSn */ 457 J784S4_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (K37) WKUP_GPIO0_15.MCU_UART0_RTSn */ 458 J784S4_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (K38) WKUP_GPIO0_13.MCU_UART0_RXD */ 459 J784S4_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (J37) WKUP_GPIO0_12.MCU_UART0_TXD */ 460 >; 461 }; 462 463 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 464 pinctrl-single,pins = < 465 J784S4_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (A35) MCU_RGMII1_RD0 */ 466 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B36) MCU_RGMII1_RD1 */ 467 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C36) MCU_RGMII1_RD2 */ 468 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D36) MCU_RGMII1_RD3 */ 469 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (B37) MCU_RGMII1_RXC */ 470 J784S4_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (C37) MCU_RGMII1_RX_CTL */ 471 J784S4_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (D37) MCU_RGMII1_TD0 */ 472 J784S4_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (D38) MCU_RGMII1_TD1 */ 473 J784S4_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E37) MCU_RGMII1_TD2 */ 474 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E38) MCU_RGMII1_TD3 */ 475 J784S4_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (E36) MCU_RGMII1_TXC */ 476 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (C38) MCU_RGMII1_TX_CTL */ 477 >; 478 }; 479 480 mcu_mdio_pins_default: mcu-mdio-default-pins { 481 pinctrl-single,pins = < 482 J784S4_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A36) MCU_MDIO0_MDC */ 483 J784S4_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (B35) MCU_MDIO0_MDIO */ 484 >; 485 }; 486 487 mcu_adc0_pins_default: mcu-adc0-default-pins { 488 pinctrl-single,pins = < 489 J784S4_WKUP_IOPAD(0x0cc, PIN_INPUT, 0) /* (P36) MCU_ADC0_AIN0 */ 490 J784S4_WKUP_IOPAD(0x0d0, PIN_INPUT, 0) /* (V36) MCU_ADC0_AIN1 */ 491 J784S4_WKUP_IOPAD(0x0d4, PIN_INPUT, 0) /* (T34) MCU_ADC0_AIN2 */ 492 J784S4_WKUP_IOPAD(0x0d8, PIN_INPUT, 0) /* (T36) MCU_ADC0_AIN3 */ 493 J784S4_WKUP_IOPAD(0x0dc, PIN_INPUT, 0) /* (P34) MCU_ADC0_AIN4 */ 494 J784S4_WKUP_IOPAD(0x0e0, PIN_INPUT, 0) /* (R37) MCU_ADC0_AIN5 */ 495 J784S4_WKUP_IOPAD(0x0e4, PIN_INPUT, 0) /* (R33) MCU_ADC0_AIN6 */ 496 J784S4_WKUP_IOPAD(0x0e8, PIN_INPUT, 0) /* (V38) MCU_ADC0_AIN7 */ 497 >; 498 }; 499 500 mcu_adc1_pins_default: mcu-adc1-default-pins { 501 pinctrl-single,pins = < 502 J784S4_WKUP_IOPAD(0x0ec, PIN_INPUT, 0) /* (Y38) MCU_ADC1_AIN0 */ 503 J784S4_WKUP_IOPAD(0x0f0, PIN_INPUT, 0) /* (Y34) MCU_ADC1_AIN1 */ 504 J784S4_WKUP_IOPAD(0x0f4, PIN_INPUT, 0) /* (V34) MCU_ADC1_AIN2 */ 505 J784S4_WKUP_IOPAD(0x0f8, PIN_INPUT, 0) /* (W37) MCU_ADC1_AIN3 */ 506 J784S4_WKUP_IOPAD(0x0fc, PIN_INPUT, 0) /* (AA37) MCU_ADC1_AIN4 */ 507 J784S4_WKUP_IOPAD(0x100, PIN_INPUT, 0) /* (W33) MCU_ADC1_AIN5 */ 508 J784S4_WKUP_IOPAD(0x104, PIN_INPUT, 0) /* (U33) MCU_ADC1_AIN6 */ 509 J784S4_WKUP_IOPAD(0x108, PIN_INPUT, 0) /* (Y36) MCU_ADC1_AIN7 */ 510 >; 511 }; 512 513 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 514 pinctrl-single,pins = < 515 J784S4_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (K33) MCU_MCAN0_TX */ 516 J784S4_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (F38) MCU_MCAN0_RX */ 517 >; 518 }; 519 520 mcu_mcan1_pins_default: mcu-mcan1-default-pins { 521 pinctrl-single,pins = < 522 J784S4_WKUP_IOPAD(0x068, PIN_OUTPUT, 0) /* (H35) WKUP_GPIO0_4.MCU_MCAN1_TX */ 523 J784S4_WKUP_IOPAD(0x06c, PIN_INPUT, 0) /* (K36) WKUP_GPIO0_5.MCU_MCAN1_RX */ 524 >; 525 }; 526 527 mcu_mcan0_gpio_pins_default: mcu-mcan0-gpio-default-pins { 528 pinctrl-single,pins = < 529 J784S4_WKUP_IOPAD(0x040, PIN_INPUT, 7) /* (J38) MCU_SPI0_D1.WKUP_GPIO0_69 */ 530 >; 531 }; 532 533 mcu_mcan1_gpio_pins_default: mcu-mcan1-gpio-default-pins { 534 pinctrl-single,pins = < 535 J784S4_WKUP_IOPAD(0x060, PIN_INPUT, 7) /* (J35) WKUP_GPIO0_2 */ 536 >; 537 }; 538}; 539 540&wkup_pmx1 { 541 status = "okay"; 542 543 pmic_irq_pins_default: pmic-irq-default-pins { 544 pinctrl-single,pins = < 545 /* (G33) MCU_OSPI1_CSn1.WKUP_GPIO0_39 */ 546 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 7) 547 >; 548 }; 549}; 550 551&wkup_pmx0 { 552 mcu_fss0_ospi0_pins_default: mcu-fss0-ospi0-default-pins { 553 bootph-all; 554 pinctrl-single,pins = < 555 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (E32) MCU_OSPI0_CLK */ 556 J784S4_WKUP_IOPAD(0x02c, PIN_OUTPUT, 0) /* (A32) MCU_OSPI0_CSn0 */ 557 J784S4_WKUP_IOPAD(0x00c, PIN_INPUT, 0) /* (B33) MCU_OSPI0_D0 */ 558 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (B32) MCU_OSPI0_D1 */ 559 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (C33) MCU_OSPI0_D2 */ 560 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (C35) MCU_OSPI0_D3 */ 561 J784S4_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D33) MCU_OSPI0_D4 */ 562 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D34) MCU_OSPI0_D5 */ 563 J784S4_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (E34) MCU_OSPI0_D6 */ 564 J784S4_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (E33) MCU_OSPI0_D7 */ 565 J784S4_WKUP_IOPAD(0x008, PIN_INPUT, 0) /* (C34) MCU_OSPI0_DQS */ 566 >; 567 }; 568}; 569 570&wkup_pmx1 { 571 mcu_fss0_ospi0_1_pins_default: mcu-fss0-ospi0-1-default-pins { 572 bootph-all; 573 pinctrl-single,pins = < 574 J784S4_WKUP_IOPAD(0x004, PIN_OUTPUT, 6) /* (C32) MCU_OSPI0_ECC_FAIL */ 575 J784S4_WKUP_IOPAD(0x000, PIN_OUTPUT, 6) /* (B34) MCU_OSPI0_RESET_OUT0 */ 576 >; 577 }; 578 579 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 580 bootph-all; 581 pinctrl-single,pins = < 582 J784S4_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (F32) MCU_OSPI1_CLK */ 583 J784S4_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (G32) MCU_OSPI1_CSn0 */ 584 J784S4_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (E35) MCU_OSPI1_D0 */ 585 J784S4_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (D31) MCU_OSPI1_D1 */ 586 J784S4_WKUP_IOPAD(0x01C, PIN_INPUT, 0) /* (G31) MCU_OSPI1_D2 */ 587 J784S4_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (F33) MCU_OSPI1_D3 */ 588 J784S4_WKUP_IOPAD(0x010, PIN_INPUT, 0) /* (F31) MCU_OSPI1_DQS */ 589 J784S4_WKUP_IOPAD(0x00C, PIN_INPUT, 0) /* (C31) MCU_OSPI1_LBCLKO */ 590 >; 591 }; 592}; 593 594&wkup_uart0 { 595 /* Firmware usage */ 596 status = "reserved"; 597 pinctrl-names = "default"; 598 pinctrl-0 = <&wkup_uart0_pins_default>; 599}; 600 601&wkup_i2c0 { 602 bootph-all; 603 status = "okay"; 604 pinctrl-names = "default"; 605 pinctrl-0 = <&wkup_i2c0_pins_default>; 606 clock-frequency = <400000>; 607 608 eeprom@50 { 609 /* CAV24C256WE-GT3 */ 610 compatible = "atmel,24c256"; 611 reg = <0x50>; 612 }; 613 614 tps659413: pmic@48 { 615 compatible = "ti,tps6594-q1"; 616 reg = <0x48>; 617 system-power-controller; 618 pinctrl-names = "default"; 619 pinctrl-0 = <&pmic_irq_pins_default>; 620 interrupt-parent = <&wkup_gpio0>; 621 interrupts = <39 IRQ_TYPE_EDGE_FALLING>; 622 gpio-controller; 623 #gpio-cells = <2>; 624 ti,primary-pmic; 625 buck12-supply = <&vsys_3v3>; 626 buck3-supply = <&vsys_3v3>; 627 buck4-supply = <&vsys_3v3>; 628 buck5-supply = <&vsys_3v3>; 629 ldo1-supply = <&vsys_3v3>; 630 ldo2-supply = <&vsys_3v3>; 631 ldo3-supply = <&vsys_3v3>; 632 ldo4-supply = <&vsys_3v3>; 633 634 regulators { 635 bucka12: buck12 { 636 regulator-name = "vdd_ddr_1v1"; 637 regulator-min-microvolt = <1100000>; 638 regulator-max-microvolt = <1100000>; 639 regulator-boot-on; 640 regulator-always-on; 641 bootph-all; 642 }; 643 644 bucka3: buck3 { 645 regulator-name = "vdd_ram_0v85"; 646 regulator-min-microvolt = <850000>; 647 regulator-max-microvolt = <850000>; 648 regulator-boot-on; 649 regulator-always-on; 650 bootph-all; 651 }; 652 653 bucka4: buck4 { 654 regulator-name = "vdd_io_1v8"; 655 regulator-min-microvolt = <1800000>; 656 regulator-max-microvolt = <1800000>; 657 regulator-boot-on; 658 regulator-always-on; 659 bootph-all; 660 }; 661 662 bucka5: buck5 { 663 regulator-name = "vdd_mcu_0v85"; 664 regulator-min-microvolt = <850000>; 665 regulator-max-microvolt = <850000>; 666 regulator-boot-on; 667 regulator-always-on; 668 bootph-all; 669 }; 670 671 ldoa1: ldo1 { 672 regulator-name = "vdd_mcuio_1v8"; 673 regulator-min-microvolt = <1800000>; 674 regulator-max-microvolt = <1800000>; 675 regulator-boot-on; 676 regulator-always-on; 677 bootph-all; 678 }; 679 680 ldoa2: ldo2 { 681 regulator-name = "vdd_mcuio_3v3"; 682 regulator-min-microvolt = <3300000>; 683 regulator-max-microvolt = <3300000>; 684 regulator-boot-on; 685 regulator-always-on; 686 bootph-all; 687 }; 688 689 ldoa3: ldo3 { 690 regulator-name = "vds_dll_0v8"; 691 regulator-min-microvolt = <800000>; 692 regulator-max-microvolt = <800000>; 693 regulator-boot-on; 694 regulator-always-on; 695 bootph-all; 696 }; 697 698 ldoa4: ldo4 { 699 regulator-name = "vda_mcu_1v8"; 700 regulator-min-microvolt = <1800000>; 701 regulator-max-microvolt = <1800000>; 702 regulator-boot-on; 703 regulator-always-on; 704 bootph-all; 705 }; 706 }; 707 }; 708 709 tps62873a: regulator@40 { 710 compatible = "ti,tps62873"; 711 reg = <0x40>; 712 bootph-pre-ram; 713 regulator-name = "VDD_CPU_AVS"; 714 regulator-min-microvolt = <750000>; 715 regulator-max-microvolt = <1330000>; 716 regulator-boot-on; 717 regulator-always-on; 718 }; 719 720 tps62873b: regulator@43 { 721 compatible = "ti,tps62873"; 722 reg = <0x43>; 723 regulator-name = "VDD_CORE_0V8"; 724 regulator-min-microvolt = <760000>; 725 regulator-max-microvolt = <840000>; 726 regulator-boot-on; 727 regulator-always-on; 728 }; 729}; 730 731&mcu_uart0 { 732 bootph-all; 733 status = "okay"; 734 pinctrl-names = "default"; 735 pinctrl-0 = <&mcu_uart0_pins_default>; 736}; 737 738&main_uart8 { 739 bootph-all; 740 status = "okay"; 741 pinctrl-names = "default"; 742 pinctrl-0 = <&main_uart8_pins_default>; 743}; 744 745&ufs_wrapper { 746 status = "okay"; 747}; 748 749&fss { 750 status = "okay"; 751}; 752 753&ospi0 { 754 status = "okay"; 755 pinctrl-names = "default"; 756 pinctrl-0 = <&mcu_fss0_ospi0_pins_default>, <&mcu_fss0_ospi0_1_pins_default>; 757 758 flash@0 { 759 compatible = "jedec,spi-nor"; 760 reg = <0x0>; 761 spi-tx-bus-width = <8>; 762 spi-rx-bus-width = <8>; 763 spi-max-frequency = <25000000>; 764 cdns,tshsl-ns = <60>; 765 cdns,tsd2d-ns = <60>; 766 cdns,tchsh-ns = <60>; 767 cdns,tslch-ns = <60>; 768 cdns,read-delay = <4>; 769 770 partitions { 771 compatible = "fixed-partitions"; 772 #address-cells = <1>; 773 #size-cells = <1>; 774 775 partition@0 { 776 label = "ospi.tiboot3"; 777 reg = <0x0 0x80000>; 778 }; 779 780 partition@80000 { 781 label = "ospi.tispl"; 782 reg = <0x80000 0x200000>; 783 }; 784 785 partition@280000 { 786 label = "ospi.u-boot"; 787 reg = <0x280000 0x400000>; 788 }; 789 790 partition@680000 { 791 label = "ospi.env"; 792 reg = <0x680000 0x40000>; 793 }; 794 795 partition@6c0000 { 796 label = "ospi.env.backup"; 797 reg = <0x6c0000 0x40000>; 798 }; 799 800 partition@800000 { 801 label = "ospi.rootfs"; 802 reg = <0x800000 0x37c0000>; 803 }; 804 805 partition@3fc0000 { 806 bootph-all; 807 label = "ospi.phypattern"; 808 reg = <0x3fc0000 0x40000>; 809 }; 810 }; 811 }; 812}; 813 814&ospi1 { 815 status = "okay"; 816 pinctrl-names = "default"; 817 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 818 819 flash@0 { 820 compatible = "jedec,spi-nor"; 821 reg = <0x0>; 822 spi-tx-bus-width = <1>; 823 spi-rx-bus-width = <4>; 824 spi-max-frequency = <40000000>; 825 cdns,tshsl-ns = <60>; 826 cdns,tsd2d-ns = <60>; 827 cdns,tchsh-ns = <60>; 828 cdns,tslch-ns = <60>; 829 cdns,read-delay = <2>; 830 831 partitions { 832 compatible = "fixed-partitions"; 833 #address-cells = <1>; 834 #size-cells = <1>; 835 836 partition@0 { 837 label = "qspi.tiboot3"; 838 reg = <0x0 0x80000>; 839 }; 840 841 partition@80000 { 842 label = "qspi.tispl"; 843 reg = <0x80000 0x200000>; 844 }; 845 846 partition@280000 { 847 label = "qspi.u-boot"; 848 reg = <0x280000 0x400000>; 849 }; 850 851 partition@680000 { 852 label = "qspi.env"; 853 reg = <0x680000 0x40000>; 854 }; 855 856 partition@6c0000 { 857 label = "qspi.env.backup"; 858 reg = <0x6c0000 0x40000>; 859 }; 860 861 partition@800000 { 862 label = "qspi.rootfs"; 863 reg = <0x800000 0x37c0000>; 864 }; 865 866 partition@3fc0000 { 867 bootph-all; 868 label = "qspi.phypattern"; 869 reg = <0x3fc0000 0x40000>; 870 }; 871 }; 872 873 }; 874}; 875 876&main_i2c0 { 877 status = "okay"; 878 pinctrl-names = "default"; 879 pinctrl-0 = <&main_i2c0_pins_default>; 880 881 clock-frequency = <400000>; 882 883 exp1: gpio@20 { 884 compatible = "ti,tca6416"; 885 reg = <0x20>; 886 gpio-controller; 887 #gpio-cells = <2>; 888 gpio-line-names = "PCIE1_2L_MODE_SEL", "PCIE1_4L_PERSTZ", "PCIE1_2L_RC_RSTZ", 889 "PCIE1_2L_EP_RST_EN", "PCIE0_4L_MODE_SEL", "PCIE0_4L_PERSTZ", 890 "PCIE0_4L_RC_RSTZ", "PCIE0_4L_EP_RST_EN", "PCIE1_4L_PRSNT#", 891 "PCIE0_4L_PRSNT#", "CDCI1_OE1/OE4", "CDCI1_OE2/OE3", 892 "AUDIO_MUX_SEL", "EXP_MUX2", "EXP_MUX3", "GESI_EXP_PHY_RSTZ"; 893 894 p12-hog { 895 /* P12 - AUDIO_MUX_SEL */ 896 gpio-hog; 897 gpios = <12 GPIO_ACTIVE_HIGH>; 898 output-low; 899 line-name = "AUDIO_MUX_SEL"; 900 }; 901 }; 902 903 exp2: gpio@22 { 904 compatible = "ti,tca6424"; 905 reg = <0x22>; 906 gpio-controller; 907 #gpio-cells = <2>; 908 gpio-line-names = "R_GPIO_RGMII1_RST", "ENET2_I2CMUX_SEL", "GPIO_USD_PWR_EN", 909 "USBC_PWR_EN", "USBC_MODE_SEL1", "USBC_MODE_SEL0", 910 "GPIO_LIN_EN", "R_CAN_STB", "CTRL_PM_I2C_OE#", 911 "ENET2_EXP_PWRDN", "ENET2_EXP_SPARE2", "CDCI2_RSTZ", 912 "USB2.0_MUX_SEL", "CANUART_MUX_SEL0", "CANUART_MUX2_SEL1", 913 "CANUART_MUX1_SEL1", "ENET1_EXP_PWRDN", "ENET1_EXP_RESETZ", 914 "ENET1_I2CMUX_SEL", "ENET1_EXP_SPARE2", "ENET2_EXP_RESETZ", 915 "USER_INPUT1", "USER_LED1", "USER_LED2"; 916 917 p13-hog { 918 /* P13 - CANUART_MUX_SEL0 */ 919 gpio-hog; 920 gpios = <13 GPIO_ACTIVE_HIGH>; 921 output-high; 922 line-name = "CANUART_MUX_SEL0"; 923 }; 924 925 p15-hog { 926 /* P15 - CANUART_MUX1_SEL1 */ 927 gpio-hog; 928 gpios = <15 GPIO_ACTIVE_HIGH>; 929 output-high; 930 line-name = "CANUART_MUX1_SEL1"; 931 }; 932 }; 933}; 934 935&main_i2c5 { 936 pinctrl-names = "default"; 937 pinctrl-0 = <&main_i2c5_pins_default>; 938 clock-frequency = <400000>; 939 status = "okay"; 940 941 exp5: gpio@20 { 942 compatible = "ti,tca6408"; 943 reg = <0x20>; 944 gpio-controller; 945 #gpio-cells = <2>; 946 gpio-line-names = "CSI2_EXP_RSTZ", "CSI2_EXP_A_GPIO0", 947 "CSI2_EXP_A_GPIO1", "CSI2_EXP_A_GPIO3", 948 "CSI2_EXP_B_GPIO1", "CSI2_EXP_B_GPIO2", 949 "CSI2_EXP_B_GPIO3", "CSI2_EXP_B_GPIO4"; 950 }; 951}; 952 953&main_sdhci0 { 954 bootph-all; 955 /* eMMC */ 956 status = "okay"; 957 non-removable; 958 ti,driver-strength-ohm = <50>; 959 disable-wp; 960}; 961 962&main_sdhci1 { 963 bootph-all; 964 /* SD card */ 965 status = "okay"; 966 pinctrl-0 = <&main_mmc1_pins_default>; 967 pinctrl-names = "default"; 968 disable-wp; 969 vmmc-supply = <&vdd_mmc1>; 970 vqmmc-supply = <&vdd_sd_dv>; 971}; 972 973&main_gpio0 { 974 status = "okay"; 975}; 976 977&mcu_cpsw { 978 status = "okay"; 979 pinctrl-names = "default"; 980 pinctrl-0 = <&mcu_cpsw_pins_default>; 981}; 982 983&davinci_mdio { 984 pinctrl-names = "default"; 985 pinctrl-0 = <&mcu_mdio_pins_default>; 986 987 mcu_phy0: ethernet-phy@0 { 988 reg = <0>; 989 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 990 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 991 ti,min-output-impedance; 992 }; 993}; 994 995&mcu_cpsw_port1 { 996 status = "okay"; 997 phy-mode = "rgmii-rxid"; 998 phy-handle = <&mcu_phy0>; 999}; 1000 1001&main_cpsw1 { 1002 pinctrl-names = "default"; 1003 pinctrl-0 = <&main_cpsw2g_default_pins>; 1004 status = "okay"; 1005}; 1006 1007&main_cpsw1_mdio { 1008 pinctrl-names = "default"; 1009 pinctrl-0 = <&main_cpsw2g_mdio_default_pins>; 1010 status = "okay"; 1011 1012 main_cpsw1_phy0: ethernet-phy@0 { 1013 reg = <0>; 1014 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 1015 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 1016 ti,min-output-impedance; 1017 }; 1018}; 1019 1020&main_cpsw1_port1 { 1021 phy-mode = "rgmii-rxid"; 1022 phy-handle = <&main_cpsw1_phy0>; 1023 status = "okay"; 1024}; 1025 1026&mailbox0_cluster0 { 1027 status = "okay"; 1028 interrupts = <436>; 1029 1030 mbox_mcu_r5fss0_core0: mbox-mcu-r5fss0-core0 { 1031 ti,mbox-rx = <0 0 0>; 1032 ti,mbox-tx = <1 0 0>; 1033 }; 1034 1035 mbox_mcu_r5fss0_core1: mbox-mcu-r5fss0-core1 { 1036 ti,mbox-rx = <2 0 0>; 1037 ti,mbox-tx = <3 0 0>; 1038 }; 1039}; 1040 1041&mailbox0_cluster1 { 1042 status = "okay"; 1043 interrupts = <432>; 1044 1045 mbox_main_r5fss0_core0: mbox-main-r5fss0-core0 { 1046 ti,mbox-rx = <0 0 0>; 1047 ti,mbox-tx = <1 0 0>; 1048 }; 1049 1050 mbox_main_r5fss0_core1: mbox-main-r5fss0-core1 { 1051 ti,mbox-rx = <2 0 0>; 1052 ti,mbox-tx = <3 0 0>; 1053 }; 1054}; 1055 1056&mailbox0_cluster2 { 1057 status = "okay"; 1058 interrupts = <428>; 1059 1060 mbox_main_r5fss1_core0: mbox-main-r5fss1-core0 { 1061 ti,mbox-rx = <0 0 0>; 1062 ti,mbox-tx = <1 0 0>; 1063 }; 1064 1065 mbox_main_r5fss1_core1: mbox-main-r5fss1-core1 { 1066 ti,mbox-rx = <2 0 0>; 1067 ti,mbox-tx = <3 0 0>; 1068 }; 1069}; 1070 1071&mailbox0_cluster3 { 1072 status = "okay"; 1073 interrupts = <424>; 1074 1075 mbox_main_r5fss2_core0: mbox-main-r5fss2-core0 { 1076 ti,mbox-rx = <0 0 0>; 1077 ti,mbox-tx = <1 0 0>; 1078 }; 1079 1080 mbox_main_r5fss2_core1: mbox-main-r5fss2-core1 { 1081 ti,mbox-rx = <2 0 0>; 1082 ti,mbox-tx = <3 0 0>; 1083 }; 1084}; 1085 1086&mailbox0_cluster4 { 1087 status = "okay"; 1088 interrupts = <420>; 1089 1090 mbox_c71_0: mbox-c71-0 { 1091 ti,mbox-rx = <0 0 0>; 1092 ti,mbox-tx = <1 0 0>; 1093 }; 1094 1095 mbox_c71_1: mbox-c71-1 { 1096 ti,mbox-rx = <2 0 0>; 1097 ti,mbox-tx = <3 0 0>; 1098 }; 1099}; 1100 1101&mailbox0_cluster5 { 1102 status = "okay"; 1103 interrupts = <416>; 1104 1105 mbox_c71_2: mbox-c71-2 { 1106 ti,mbox-rx = <0 0 0>; 1107 ti,mbox-tx = <1 0 0>; 1108 }; 1109}; 1110 1111&mcu_r5fss0_core0 { 1112 status = "okay"; 1113 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core0>; 1114 memory-region = <&mcu_r5fss0_core0_dma_memory_region>, 1115 <&mcu_r5fss0_core0_memory_region>; 1116}; 1117 1118&mcu_r5fss0_core1 { 1119 status = "okay"; 1120 mboxes = <&mailbox0_cluster0 &mbox_mcu_r5fss0_core1>; 1121 memory-region = <&mcu_r5fss0_core1_dma_memory_region>, 1122 <&mcu_r5fss0_core1_memory_region>; 1123}; 1124 1125&main_r5fss0 { 1126 ti,cluster-mode = <0>; 1127}; 1128 1129&main_r5fss1 { 1130 ti,cluster-mode = <0>; 1131}; 1132 1133&main_r5fss2 { 1134 ti,cluster-mode = <0>; 1135}; 1136 1137/* Timers are used by Remoteproc firmware */ 1138&main_timer0 { 1139 status = "reserved"; 1140}; 1141 1142&main_timer1 { 1143 status = "reserved"; 1144}; 1145 1146&main_timer2 { 1147 status = "reserved"; 1148}; 1149 1150&main_timer3 { 1151 status = "reserved"; 1152}; 1153 1154&main_timer4 { 1155 status = "reserved"; 1156}; 1157 1158&main_timer5 { 1159 status = "reserved"; 1160}; 1161 1162&main_timer6 { 1163 status = "reserved"; 1164}; 1165 1166&main_timer7 { 1167 status = "reserved"; 1168}; 1169 1170&main_timer8 { 1171 status = "reserved"; 1172}; 1173 1174&main_timer9 { 1175 status = "reserved"; 1176}; 1177 1178&main_r5fss0_core0 { 1179 status = "okay"; 1180 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core0>; 1181 memory-region = <&main_r5fss0_core0_dma_memory_region>, 1182 <&main_r5fss0_core0_memory_region>; 1183}; 1184 1185&main_r5fss0_core1 { 1186 status = "okay"; 1187 mboxes = <&mailbox0_cluster1 &mbox_main_r5fss0_core1>; 1188 memory-region = <&main_r5fss0_core1_dma_memory_region>, 1189 <&main_r5fss0_core1_memory_region>; 1190}; 1191 1192&main_r5fss1_core0 { 1193 status = "okay"; 1194 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core0>; 1195 memory-region = <&main_r5fss1_core0_dma_memory_region>, 1196 <&main_r5fss1_core0_memory_region>; 1197}; 1198 1199&main_r5fss1_core1 { 1200 status = "okay"; 1201 mboxes = <&mailbox0_cluster2 &mbox_main_r5fss1_core1>; 1202 memory-region = <&main_r5fss1_core1_dma_memory_region>, 1203 <&main_r5fss1_core1_memory_region>; 1204}; 1205 1206&main_r5fss2_core0 { 1207 status = "okay"; 1208 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core0>; 1209 memory-region = <&main_r5fss2_core0_dma_memory_region>, 1210 <&main_r5fss2_core0_memory_region>; 1211}; 1212 1213&main_r5fss2_core1 { 1214 status = "okay"; 1215 mboxes = <&mailbox0_cluster3 &mbox_main_r5fss2_core1>; 1216 memory-region = <&main_r5fss2_core1_dma_memory_region>, 1217 <&main_r5fss2_core1_memory_region>; 1218}; 1219 1220&c71_0 { 1221 status = "okay"; 1222 mboxes = <&mailbox0_cluster4 &mbox_c71_0>; 1223 memory-region = <&c71_0_dma_memory_region>, 1224 <&c71_0_memory_region>; 1225}; 1226 1227&c71_1 { 1228 status = "okay"; 1229 mboxes = <&mailbox0_cluster4 &mbox_c71_1>; 1230 memory-region = <&c71_1_dma_memory_region>, 1231 <&c71_1_memory_region>; 1232}; 1233 1234&c71_2 { 1235 status = "okay"; 1236 mboxes = <&mailbox0_cluster5 &mbox_c71_2>; 1237 memory-region = <&c71_2_dma_memory_region>, 1238 <&c71_2_memory_region>; 1239}; 1240 1241&tscadc0 { 1242 pinctrl-0 = <&mcu_adc0_pins_default>; 1243 pinctrl-names = "default"; 1244 status = "okay"; 1245 adc { 1246 ti,adc-channels = <0 1 2 3 4 5 6 7>; 1247 }; 1248}; 1249 1250&tscadc1 { 1251 pinctrl-0 = <&mcu_adc1_pins_default>; 1252 pinctrl-names = "default"; 1253 status = "okay"; 1254 adc { 1255 ti,adc-channels = <0 1 2 3 4 5 6 7>; 1256 }; 1257}; 1258 1259&serdes_refclk { 1260 status = "okay"; 1261 clock-frequency = <100000000>; 1262}; 1263 1264&dss { 1265 status = "okay"; 1266 assigned-clocks = <&k3_clks 218 2>, 1267 <&k3_clks 218 5>, 1268 <&k3_clks 218 14>, 1269 <&k3_clks 218 18>; 1270 assigned-clock-parents = <&k3_clks 218 3>, 1271 <&k3_clks 218 7>, 1272 <&k3_clks 218 16>, 1273 <&k3_clks 218 22>; 1274}; 1275 1276&serdes0 { 1277 status = "okay"; 1278 1279 serdes0_pcie1_link: phy@0 { 1280 reg = <0>; 1281 cdns,num-lanes = <2>; 1282 #phy-cells = <0>; 1283 cdns,phy-type = <PHY_TYPE_PCIE>; 1284 resets = <&serdes_wiz0 1>, <&serdes_wiz0 2>; 1285 }; 1286 1287 serdes0_usb_link: phy@3 { 1288 reg = <3>; 1289 cdns,num-lanes = <1>; 1290 #phy-cells = <0>; 1291 cdns,phy-type = <PHY_TYPE_USB3>; 1292 resets = <&serdes_wiz0 4>; 1293 }; 1294}; 1295 1296&serdes_wiz0 { 1297 status = "okay"; 1298}; 1299 1300&usb_serdes_mux { 1301 idle-states = <0>; /* USB0 to SERDES lane 3 */ 1302}; 1303 1304&usbss0 { 1305 status = "okay"; 1306 pinctrl-0 = <&main_usbss0_pins_default>; 1307 pinctrl-names = "default"; 1308 ti,vbus-divider; 1309}; 1310 1311&usb0 { 1312 dr_mode = "otg"; 1313 maximum-speed = "super-speed"; 1314 phys = <&serdes0_usb_link>; 1315 phy-names = "cdns3,usb3-phy"; 1316}; 1317 1318&serdes_wiz4 { 1319 status = "okay"; 1320}; 1321 1322&serdes4 { 1323 status = "okay"; 1324 serdes4_dp_link: phy@0 { 1325 reg = <0>; 1326 cdns,num-lanes = <4>; 1327 #phy-cells = <0>; 1328 cdns,phy-type = <PHY_TYPE_DP>; 1329 resets = <&serdes_wiz4 1>, <&serdes_wiz4 2>, 1330 <&serdes_wiz4 3>, <&serdes_wiz4 4>; 1331 }; 1332}; 1333 1334&mhdp { 1335 status = "okay"; 1336 pinctrl-names = "default"; 1337 pinctrl-0 = <&dp0_pins_default>; 1338 phys = <&serdes4_dp_link>; 1339 phy-names = "dpphy"; 1340}; 1341 1342&dss_ports { 1343 /* DP */ 1344 port { 1345 dpi0_out: endpoint { 1346 remote-endpoint = <&dp0_in>; 1347 }; 1348 }; 1349}; 1350 1351&main_i2c4 { 1352 status = "okay"; 1353 pinctrl-names = "default"; 1354 pinctrl-0 = <&main_i2c4_pins_default>; 1355 clock-frequency = <400000>; 1356 1357 exp4: gpio@20 { 1358 compatible = "ti,tca6408"; 1359 reg = <0x20>; 1360 gpio-controller; 1361 #gpio-cells = <2>; 1362 }; 1363}; 1364 1365&dp0_ports { 1366 port@0 { 1367 reg = <0>; 1368 1369 dp0_in: endpoint { 1370 remote-endpoint = <&dpi0_out>; 1371 }; 1372 }; 1373 1374 port@4 { 1375 reg = <4>; 1376 1377 dp0_out: endpoint { 1378 remote-endpoint = <&dp0_connector_in>; 1379 }; 1380 }; 1381}; 1382 1383&mcu_mcan0 { 1384 status = "okay"; 1385 pinctrl-names = "default"; 1386 pinctrl-0 = <&mcu_mcan0_pins_default>; 1387 phys = <&transceiver0>; 1388}; 1389 1390&mcu_mcan1 { 1391 status = "okay"; 1392 pinctrl-names = "default"; 1393 pinctrl-0 = <&mcu_mcan1_pins_default>; 1394 phys = <&transceiver1>; 1395}; 1396 1397&main_mcan16 { 1398 status = "okay"; 1399 pinctrl-names = "default"; 1400 pinctrl-0 = <&main_mcan16_pins_default>; 1401 phys = <&transceiver2>; 1402}; 1403 1404&main_mcan4 { 1405 status = "okay"; 1406 pinctrl-names = "default"; 1407 pinctrl-0 = <&main_mcan4_pins_default>; 1408 phys = <&transceiver3>; 1409}; 1410 1411&pcie1_rc { 1412 status = "okay"; 1413 clocks = <&k3_clks 333 0>, <&serdes0 CDNS_TORRENT_REFCLK_DRIVER>; 1414 clock-names = "fck", "pcie_refclk"; 1415 num-lanes = <2>; 1416 reset-gpios = <&exp1 2 GPIO_ACTIVE_HIGH>; 1417 phys = <&serdes0_pcie1_link>; 1418 phy-names = "pcie-phy"; 1419 ti,syscon-acspcie-proxy-ctrl = <&acspcie0_proxy_ctrl 0x1>; 1420}; 1421 1422&serdes1 { 1423 status = "okay"; 1424 1425 serdes1_pcie0_link: phy@0 { 1426 reg = <0>; 1427 cdns,num-lanes = <4>; 1428 #phy-cells = <0>; 1429 cdns,phy-type = <PHY_TYPE_PCIE>; 1430 resets = <&serdes_wiz1 1>, <&serdes_wiz1 2>, 1431 <&serdes_wiz1 3>, <&serdes_wiz1 4>; 1432 }; 1433}; 1434 1435&serdes_wiz1 { 1436 status = "okay"; 1437}; 1438 1439&pcie0_rc { 1440 status = "okay"; 1441 reset-gpios = <&exp1 6 GPIO_ACTIVE_HIGH>; 1442 phys = <&serdes1_pcie0_link>; 1443 phy-names = "pcie-phy"; 1444}; 1445 1446&k3_clks { 1447 /* Confiure AUDIO_EXT_REFCLK1 pin as output */ 1448 pinctrl-names = "default"; 1449 pinctrl-0 = <&audio_ext_refclk1_pins_default>; 1450}; 1451 1452&main_i2c3 { 1453 status = "okay"; 1454 pinctrl-names = "default"; 1455 pinctrl-0 = <&main_i2c3_pins_default>; 1456 clock-frequency = <400000>; 1457 1458 exp3: gpio@20 { 1459 compatible = "ti,tca6408"; 1460 reg = <0x20>; 1461 gpio-controller; 1462 #gpio-cells = <2>; 1463 }; 1464 1465 pcm3168a_1: audio-codec@44 { 1466 compatible = "ti,pcm3168a"; 1467 reg = <0x44>; 1468 #sound-dai-cells = <1>; 1469 reset-gpios = <&exp3 0 GPIO_ACTIVE_LOW>; 1470 clocks = <&audio_refclk1>; 1471 clock-names = "scki"; 1472 VDD1-supply = <&vsys_3v3>; 1473 VDD2-supply = <&vsys_3v3>; 1474 VCCAD1-supply = <&vsys_5v0>; 1475 VCCAD2-supply = <&vsys_5v0>; 1476 VCCDA1-supply = <&vsys_5v0>; 1477 VCCDA2-supply = <&vsys_5v0>; 1478 }; 1479}; 1480 1481&mcasp0 { 1482 status = "okay"; 1483 #sound-dai-cells = <0>; 1484 pinctrl-names = "default"; 1485 pinctrl-0 = <&main_mcasp0_pins_default>; 1486 op-mode = <0>; /* MCASP_IIS_MODE */ 1487 tdm-slots = <2>; 1488 auxclk-fs-ratio = <256>; 1489 serial-dir = < /* 0: INACTIVE, 1: TX, 2: RX */ 1490 0 0 0 1 1491 2 0 0 0 1492 0 0 0 0 1493 0 0 0 0 1494 >; 1495}; 1496