1// SPDX-License-Identifier: GPL-2.0-only OR MIT 2/* 3 * Copyright (C) 2025 PHYTEC Messtechnik GmbH 4 * Author: Dominik Haller <d.haller@phytec.de> 5 * 6 * https://www.phytec.eu/en/produkte/development-kits/phyboard-izar/ 7 */ 8 9/dts-v1/; 10 11#include <dt-bindings/leds/leds-pca9532.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include <dt-bindings/phy/phy-cadence.h> 14#include <dt-bindings/phy/phy.h> 15#include "k3-am68-phycore-som.dtsi" 16 17#include "k3-serdes.h" 18 19/ { 20 compatible = "phytec,am68-phyboard-izar", 21 "phytec,am68-phycore-som", "ti,j721s2"; 22 model = "PHYTEC phyBOARD-Izar-AM68x"; 23 24 aliases { 25 serial0 = &mcu_uart0; 26 serial1 = &main_uart1; 27 serial2 = &main_uart8; 28 serial3 = &main_uart2; 29 mmc1 = &main_sdhci1; 30 ethernet0 = &cpsw_port1; 31 }; 32 33 chosen { 34 stdout-path = &main_uart8; 35 }; 36 37 transceiver1: can-phy1 { 38 compatible = "ti,tcan1043"; 39 #phy-cells = <0>; 40 max-bitrate = <8000000>; 41 }; 42 43 transceiver2: can-phy2 { 44 compatible = "ti,tcan1043"; 45 #phy-cells = <0>; 46 max-bitrate = <8000000>; 47 }; 48 49 transceiver3: can-phy3 { 50 compatible = "ti,tcan1043"; 51 #phy-cells = <0>; 52 max-bitrate = <8000000>; 53 }; 54 55 transceiver4: can-phy4 { 56 compatible = "ti,tcan1043"; 57 #phy-cells = <0>; 58 max-bitrate = <8000000>; 59 }; 60 61 vcc_12v0: regulator-12v0 { 62 /* main supply */ 63 compatible = "regulator-fixed"; 64 regulator-name = "VCC_IN"; 65 regulator-min-microvolt = <12000000>; 66 regulator-max-microvolt = <12000000>; 67 regulator-always-on; 68 regulator-boot-on; 69 }; 70 71 vcc_1v8: regulator-vcc-1v8 { 72 /* Output of TLV7158P */ 73 compatible = "regulator-fixed"; 74 regulator-name = "VCC_1V8"; 75 regulator-min-microvolt = <1800000>; 76 regulator-max-microvolt = <1800000>; 77 regulator-always-on; 78 regulator-boot-on; 79 vin-supply = <&vcc_3v3>; 80 }; 81 82 vcc_3v3: regulator-vcc-3v3 { 83 /* Output of SiC431 */ 84 compatible = "regulator-fixed"; 85 regulator-name = "VCC_3V3"; 86 regulator-min-microvolt = <3300000>; 87 regulator-max-microvolt = <3300000>; 88 regulator-always-on; 89 regulator-boot-on; 90 vin-supply = <&vcc_5v0>; 91 }; 92 93 vcc_5v0: regulator-vcc-5v0 { 94 /* Output of LM5116 */ 95 compatible = "regulator-fixed"; 96 regulator-name = "VCC_5V0"; 97 regulator-min-microvolt = <5000000>; 98 regulator-max-microvolt = <5000000>; 99 regulator-always-on; 100 regulator-boot-on; 101 vin-supply = <&vcc_12v0>; 102 }; 103}; 104 105&main_pmx0 { 106 main_i2c2_pins_default: main-i2c2-default-pins { 107 pinctrl-single,pins = < 108 J721S2_IOPAD(0x04c, PIN_INPUT_PULLUP, 13) /* (V27) MCASP1_AXR1.I2C2_SCL */ 109 J721S2_IOPAD(0x050, PIN_INPUT_PULLUP, 13) /* (W27) MCASP1_AXR2.I2C2_SDA */ 110 >; 111 }; 112 113 main_i2c4_pins_default: main-i2c4-default-pins { 114 pinctrl-single,pins = < 115 J721S2_IOPAD(0x014, PIN_INPUT_PULLUP, 8) /* (AD25) MCAN14_TX.I2C4_SCL */ 116 J721S2_IOPAD(0x010, PIN_INPUT_PULLUP, 8) /* (AF28) MCAN13_RX.I2C4_SDA */ 117 >; 118 }; 119 120 main_i2c5_pins_default: main-i2c5-default-pins { 121 pinctrl-single,pins = < 122 J721S2_IOPAD(0x01c, PIN_INPUT_PULLUP, 8) /* (Y24) MCAN15_TX.I2C5_SCL */ 123 J721S2_IOPAD(0x018, PIN_INPUT_PULLUP, 8) /* (W23) MCAN14_RX.I2C5_SDA */ 124 >; 125 }; 126 127 main_gpio0_ioexp_intr_pins_default: main-gpio0-ioexp-intr-default-pins { 128 pinctrl-single,pins = < 129 J721S2_IOPAD(0x020, PIN_INPUT, 7) /* (AA23) MCAN15_RX.GPIO0_8 */ 130 >; 131 }; 132 133 main_mcan1_pins_default: main-mcan1-default-pins { 134 pinctrl-single,pins = < 135 J721S2_IOPAD(0x0c8, PIN_INPUT, 4) /* (AD28) EXT_REFCLK1.MCAN1_RX */ 136 J721S2_IOPAD(0x06c, PIN_OUTPUT, 0) /* (V26) MCAN1_TX */ 137 >; 138 }; 139 140 main_mcan13_pins_default: main-mcan13-default-pins { 141 pinctrl-single,pins = < 142 J721S2_IOPAD(0x0ec, PIN_INPUT, 9) /* (AG25) TIMER_IO1.MCAN13_RX */ 143 J721S2_IOPAD(0x00c, PIN_OUTPUT, 0) /* (AE28) MCAN13_TX */ 144 >; 145 }; 146 147 main_mcan16_pins_default: main-mcan16-default-pins { 148 pinctrl-single,pins = < 149 J721S2_IOPAD(0x028, PIN_INPUT, 0) /* (AB24) MCAN16_RX */ 150 J721S2_IOPAD(0x024, PIN_OUTPUT, 0) /* (Y28) MCAN16_TX */ 151 >; 152 }; 153 154 main_mmc1_pins_default: main-mmc1-default-pins { 155 pinctrl-single,pins = < 156 J721S2_IOPAD(0x104, PIN_INPUT, 0) /* (P23) MMC1_CLK */ 157 J721S2_IOPAD(0x108, PIN_INPUT, 0) /* (N24) MMC1_CMD */ 158 J721S2_IOPAD(0x100, PIN_INPUT, 0) /* (###) MMC1_CLKLB */ 159 J721S2_IOPAD(0x0fc, PIN_INPUT, 0) /* (M23) MMC1_DAT0 */ 160 J721S2_IOPAD(0x0f8, PIN_INPUT, 0) /* (P24) MMC1_DAT1 */ 161 J721S2_IOPAD(0x0f4, PIN_INPUT, 0) /* (R24) MMC1_DAT2 */ 162 J721S2_IOPAD(0x0f0, PIN_INPUT, 0) /* (R22) MMC1_DAT3 */ 163 J721S2_IOPAD(0x0e8, PIN_INPUT, 8) /* (AE25) TIMER_IO0.MMC1_SDCD */ 164 >; 165 bootph-all; 166 }; 167 168 main_spi6_pins_default: main-spi6-default-pins { 169 pinctrl-single,pins = < 170 J721S2_IOPAD(0x030, PIN_INPUT, 8) /* (T26) GPIO0_12.SPI6_CLK */ 171 J721S2_IOPAD(0x080, PIN_INPUT, 8) /* (U26) MCASP0_AXR4.SPI6_CS2 */ 172 J721S2_IOPAD(0x0c4, PIN_OUTPUT, 8) /* (AB26) ECAP0_IN_APWM_OUT.SPI6_D0 */ 173 J721S2_IOPAD(0x074, PIN_INPUT, 8) /* (R28) MCAN2_TX.SPI6_D1 */ 174 J721S2_IOPAD(0x0dc, PIN_OUTPUT, 7) /* (AH26) SPI0_D1.GPIO0_55 */ 175 >; 176 }; 177 178 main_uart1_pins_default: main-uart1-default-pins { 179 pinctrl-single,pins = < 180 J721S2_IOPAD(0x05c, PIN_INPUT, 11) /* (AA26) MCASP2_AXR0.UART1_CTSn */ 181 J721S2_IOPAD(0x060, PIN_OUTPUT, 11) /* (AC27) MCASP2_AXR1.UART1_RTSn */ 182 J721S2_IOPAD(0x054, PIN_INPUT, 11) /* (Y27) MCASP2_ACLKX.UART1_RXD */ 183 J721S2_IOPAD(0x058, PIN_OUTPUT, 11) /* (AA27) MCASP2_AFSX.UART1_TXD */ 184 >; 185 }; 186 187 main_uart2_pins_default: main-uart2-default-pins { 188 pinctrl-single,pins = < 189 J721S2_IOPAD(0x0d8, PIN_INPUT, 11) /* (AG26) SPI0_D0.UART2_RXD */ 190 J721S2_IOPAD(0x068, PIN_OUTPUT, 11) /* (U28) MCAN0_RX.UART2_TXD */ 191 >; 192 }; 193 194 main_uart8_pins_default: main-uart8-default-pins { 195 pinctrl-single,pins = < 196 J721S2_IOPAD(0x0d0, PIN_INPUT, 11) /* (AF26) SPI0_CS1.UART8_RXD */ 197 J721S2_IOPAD(0x0d4, PIN_OUTPUT, 11) /* (AH27) SPI0_CLK.UART8_TXD */ 198 >; 199 bootph-all; 200 }; 201}; 202 203&wkup_pmx1 { 204 mcu_fss0_ospi1_pins_default: mcu-fss0-ospi1-default-pins { 205 pinctrl-single,pins = < 206 J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (A19) MCU_OSPI1_CLK */ 207 J721S2_WKUP_IOPAD(0x024, PIN_OUTPUT, 0) /* (D20) MCU_OSPI1_CSn0 */ 208 J721S2_WKUP_IOPAD(0x014, PIN_INPUT, 0) /* (D21) MCU_OSPI1_D0 */ 209 J721S2_WKUP_IOPAD(0x018, PIN_INPUT, 0) /* (G20) MCU_OSPI1_D1 */ 210 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (C20) MCU_OSPI1_D2 */ 211 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (A20) MCU_OSPI1_D3 */ 212 >; 213 }; 214}; 215 216&wkup_pmx2 { 217 mcu_cpsw_pins_default: mcu-cpsw-default-pins { 218 pinctrl-single,pins = < 219 J721S2_WKUP_IOPAD(0x02c, PIN_INPUT, 0) /* (B22) MCU_RGMII1_RD0 */ 220 J721S2_WKUP_IOPAD(0x028, PIN_INPUT, 0) /* (B21) MCU_RGMII1_RD1 */ 221 J721S2_WKUP_IOPAD(0x024, PIN_INPUT, 0) /* (C22) MCU_RGMII1_RD2 */ 222 J721S2_WKUP_IOPAD(0x020, PIN_INPUT, 0) /* (D23) MCU_RGMII1_RD3 */ 223 J721S2_WKUP_IOPAD(0x01c, PIN_INPUT, 0) /* (D22) MCU_RGMII1_RXC */ 224 J721S2_WKUP_IOPAD(0x004, PIN_INPUT, 0) /* (E23) MCU_RGMII1_RX_CTL */ 225 J721S2_WKUP_IOPAD(0x014, PIN_OUTPUT, 0) /* (F23) MCU_RGMII1_TD0 */ 226 J721S2_WKUP_IOPAD(0x010, PIN_OUTPUT, 0) /* (G22) MCU_RGMII1_TD1 */ 227 J721S2_WKUP_IOPAD(0x00c, PIN_OUTPUT, 0) /* (E21) MCU_RGMII1_TD2 */ 228 J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RGMII1_TD3 */ 229 J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ 230 J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ 231 >; 232 }; 233 234 mcu_i2c1_pins_default: mcu-i2c1-default-pins { 235 pinctrl-single,pins = < 236 J721S2_WKUP_IOPAD(0x078, PIN_INPUT_PULLUP, 0) /* (F24) WKUP_GPIO0_8.MCU_I2C1_SCL */ 237 J721S2_WKUP_IOPAD(0x07c, PIN_INPUT_PULLUP, 0) /* (H26) WKUP_GPIO0_9.MCU_I2C1_SDA */ 238 >; 239 }; 240 241 mcu_mcan0_pins_default: mcu-mcan0-default-pins { 242 pinctrl-single,pins = < 243 J721S2_WKUP_IOPAD(0x054, PIN_INPUT, 0) /* (E28) MCU_MCAN0_RX */ 244 J721S2_WKUP_IOPAD(0x050, PIN_OUTPUT, 0) /* (E27) MCU_MCAN0_TX */ 245 >; 246 }; 247 248 mcu_mdio_pins_default: mcu-mdio-default-pins { 249 pinctrl-single,pins = < 250 J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ 251 J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ 252 >; 253 }; 254 255 mcu_spi0_pins_default: mcu-spi0-default-pins { 256 pinctrl-single,pins = < 257 J721S2_WKUP_IOPAD(0x038, PIN_INPUT, 0) /* (B27) MCU_SPI0_CLK */ 258 J721S2_WKUP_IOPAD(0x044, PIN_INPUT, 0) /* (B26) MCU_SPI0_CS0 */ 259 J721S2_WKUP_IOPAD(0x068, PIN_INPUT, 2) /* (C23) WKUP_GPIO0_4.MCU_SPI0_CS3 */ 260 J721S2_WKUP_IOPAD(0x03c, PIN_INPUT, 0) /* (D24) MCU_SPI0_D0 */ 261 J721S2_WKUP_IOPAD(0x040, PIN_INPUT, 0) /* (B25) MCU_SPI0_D1 */ 262 >; 263 }; 264 265 mcu_uart0_pins_default: mcu-uart0-default-pins { 266 pinctrl-single,pins = < 267 J721S2_WKUP_IOPAD(0x090, PIN_INPUT, 0) /* (B24) WKUP_GPIO0_14.MCU_UART0_CTSn */ 268 J721S2_WKUP_IOPAD(0x094, PIN_OUTPUT, 0) /* (D25) WKUP_GPIO0_15.MCU_UART0_RTSn */ 269 J721S2_WKUP_IOPAD(0x08c, PIN_INPUT, 0) /* (C24) WKUP_GPIO0_13.MCU_UART0_RXD */ 270 J721S2_WKUP_IOPAD(0x088, PIN_OUTPUT, 0) /* (C25) WKUP_GPIO0_12.MCU_UART0_TXD */ 271 >; 272 }; 273 274 wkup_uart0_pins_default: wkup-uart0-default-pins { 275 pinctrl-single,pins = < 276 J721S2_WKUP_IOPAD(0x048, PIN_INPUT, 0) /* (D28) WKUP_UART0_RXD */ 277 J721S2_WKUP_IOPAD(0x04c, PIN_OUTPUT, 0) /* (D27) WKUP_UART0_TXD */ 278 >; 279 bootph-all; 280 }; 281}; 282 283&cpsw_port1 { 284 phy-mode = "rgmii-rxid"; 285 phy-handle = <&phy0>; 286}; 287 288&davinci_mdio { 289 pinctrl-names = "default"; 290 pinctrl-0 = <&mcu_mdio_pins_default>; 291 292 phy0: ethernet-phy@0 { 293 reg = <0>; 294 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 295 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 296 ti,min-output-impedance; 297 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 298 }; 299}; 300 301&i2c_som_rtc { 302 trickle-resistor-ohms = <3000>; 303}; 304 305&main_i2c2 { 306 pinctrl-names = "default"; 307 pinctrl-0 = <&main_i2c2_pins_default>; 308 status = "okay"; 309 310 exp1: gpio@20 { 311 compatible = "nxp,pca9672"; 312 reg = <0x20>; 313 gpio-controller; 314 #gpio-cells = <2>; 315 gpio-line-names = "HALF/nFULL_EN", "RS485/nRS232_EN", "MCU_ETH_nRESET", "", 316 "PCIe_nRESET", "USB2.0-Hub_nRESET", "USB3.0-Hub_nRESET", "PEB_AV_BL_EN"; 317 interrupt-parent = <&main_gpio0>; 318 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 319 interrupt-controller; 320 #interrupt-cells = <2>; 321 }; 322 323 exp2: gpio@22 { 324 compatible = "ti,tca6424"; 325 reg = <0x22>; 326 gpio-controller; 327 #gpio-cells = <2>; 328 gpio-line-names = "RPI_GPIO4", "RPI_GPIO5", "RPI_GPIO6", "RPI_GPIO19", 329 "RPI_GPIO20", "RPI_GPIO21", "RPI_GPIO22", "RPI_GPIO23", 330 "RPI_GPIO24", "RPI_GPIO25", "RPI_GPIO26", "RPI_GPIO20", 331 "LVDS_BL_nEN", "LVDS_REG_nEN", "CSI_CAM0_nRESET", "CSI_CAM1_nRESET", 332 "CSI0_CTRL1", "CSI0_CTRL2", "CSI0_CTRL3", "CSI0_CTRL4", 333 "CSI1_CTRL1", "CSI1_CTRL2", "CSI1_CTRL3", "CSI1_CTRL4"; 334 interrupt-parent = <&main_gpio0>; 335 interrupts = <8 IRQ_TYPE_EDGE_FALLING>; 336 interrupt-controller; 337 #interrupt-cells = <2>; 338 pinctrl-names = "default"; 339 pinctrl-0 = <&main_gpio0_ioexp_intr_pins_default>; 340 }; 341}; 342 343/* CSI0 + RPI */ 344&main_i2c4 { 345 pinctrl-names = "default"; 346 pinctrl-0 = <&main_i2c4_pins_default>; 347}; 348 349/* CSI1 + PCIe */ 350&main_i2c5 { 351 pinctrl-names = "default"; 352 pinctrl-0 = <&main_i2c5_pins_default>; 353}; 354 355&main_mcan1 { 356 pinctrl-names = "default"; 357 pinctrl-0 = <&main_mcan1_pins_default>; 358 phys = <&transceiver1>; 359 status = "okay"; 360}; 361 362&main_mcan13 { 363 pinctrl-names = "default"; 364 pinctrl-0 = <&main_mcan13_pins_default>; 365 phys = <&transceiver2>; 366 status = "okay"; 367}; 368 369&main_mcan16 { 370 pinctrl-names = "default"; 371 pinctrl-0 = <&main_mcan16_pins_default>; 372 phys = <&transceiver3>; 373 status = "okay"; 374}; 375 376/* SD-Card */ 377&main_sdhci1 { 378 pinctrl-0 = <&main_mmc1_pins_default>; 379 pinctrl-names = "default"; 380 disable-wp; 381 vmmc-supply = <&vcc_3v3>; 382 status = "okay"; 383}; 384 385&main_spi6 { 386 pinctrl-names = "default"; 387 pinctrl-0 = <&main_spi6_pins_default>; 388 cs-gpios = <&main_gpio0 55 GPIO_ACTIVE_LOW>; 389 ti,spi-num-cs = <1>; 390 ti,pindir-d0-out-d1-in; 391 status = "okay"; 392 393 tpm@0 { 394 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 395 reg = <0>; 396 spi-max-frequency = <10000000>; 397 }; 398}; 399 400&main_uart1 { 401 pinctrl-names = "default"; 402 pinctrl-0 = <&main_uart1_pins_default>; 403 uart-has-rtscts; 404 status = "okay"; 405}; 406 407&main_uart2 { 408 pinctrl-names = "default"; 409 pinctrl-0 = <&main_uart2_pins_default>; 410 status = "okay"; 411}; 412 413&main_uart8 { 414 pinctrl-names = "default"; 415 pinctrl-0 = <&main_uart8_pins_default>; 416 /* Shared with TFA on this platform */ 417 power-domains = <&k3_pds 357 TI_SCI_PD_SHARED>; 418 bootph-all; 419 status = "okay"; 420}; 421 422&mcu_cpsw { 423 pinctrl-names = "default"; 424 pinctrl-0 = <&mcu_cpsw_pins_default>; 425}; 426 427&mcu_i2c1 { 428 pinctrl-names = "default"; 429 pinctrl-0 = <&mcu_i2c1_pins_default>; 430 status = "okay"; 431}; 432 433&mcu_mcan0 { 434 pinctrl-names = "default"; 435 pinctrl-0 = <&mcu_mcan0_pins_default>; 436 phys = <&transceiver4>; 437 status = "okay"; 438}; 439 440/* RPI-Header */ 441&mcu_spi0 { 442 pinctrl-names = "default"; 443 pinctrl-0 = <&mcu_spi0_pins_default>; 444}; 445 446/* RPI-Header */ 447&mcu_uart0 { 448 pinctrl-names = "default"; 449 pinctrl-0 = <&mcu_uart0_pins_default>; 450 uart-has-rtscts; 451 status = "okay"; 452}; 453 454&ospi1 { 455 pinctrl-names = "default"; 456 pinctrl-0 = <&mcu_fss0_ospi1_pins_default>; 457 status = "okay"; 458 459 flash@0 { 460 compatible = "jedec,spi-nor"; 461 reg = <0x0>; 462 spi-tx-bus-width = <4>; 463 spi-rx-bus-width = <4>; 464 spi-max-frequency = <40000000>; 465 cdns,tshsl-ns = <60>; 466 cdns,tsd2d-ns = <60>; 467 cdns,tchsh-ns = <60>; 468 cdns,tslch-ns = <60>; 469 cdns,read-delay = <2>; 470 }; 471}; 472 473&pcie1_rc { 474 num-lanes = <1>; 475 phys = <&serdes0_pcie_link>; 476 phy-names = "pcie-phy"; 477 reset-gpios = <&exp1 4 GPIO_ACTIVE_HIGH>; 478 status = "okay"; 479}; 480 481&serdes_ln_ctrl { 482 idle-states = <J721S2_SERDES0_LANE0_PCIE1_LANE0>, <J721S2_SERDES0_LANE1_USB>, 483 <J721S2_SERDES0_LANE2_EDP_LANE2>, <J721S2_SERDES0_LANE3_EDP_LANE3>; 484}; 485 486&serdes_refclk { 487 clock-frequency = <100000000>; 488}; 489 490&serdes0 { 491 status = "okay"; 492 493 serdes0_pcie_link: phy@0 { 494 reg = <0>; 495 cdns,num-lanes = <1>; 496 #phy-cells = <0>; 497 resets = <&serdes_wiz0 1>; 498 cdns,phy-type = <PHY_TYPE_PCIE>; 499 }; 500 501 serdes0_usb_link: phy@1 { 502 reg = <1>; 503 cdns,num-lanes = <1>; 504 #phy-cells = <0>; 505 resets = <&serdes_wiz0 2>; 506 cdns,phy-type = <PHY_TYPE_USB3>; 507 }; 508}; 509 510&tscadc0 { 511 status = "okay"; 512 513 adc { 514 ti,adc-channels = <0 1 2 3 4 5 6 7>; 515 }; 516}; 517 518&tscadc1 { 519 status = "okay"; 520 521 adc { 522 ti,adc-channels = <3 4 5 6 7>; 523 }; 524}; 525 526&usbss0 { 527 ti,vbus-divider; 528 status = "okay"; 529}; 530 531&usb0 { 532 dr_mode = "host"; 533 phys = <&serdes0_usb_link>; 534 phy-names = "cdns3,usb3-phy"; 535}; 536 537&usb_serdes_mux { 538 idle-states = <1>; /* USB0 to SERDES lane 1 */ 539}; 540 541&wkup_i2c0 { 542 eeprom@57 { 543 compatible = "atmel,24c32"; 544 reg = <0x57>; 545 pagesize = <32>; 546 }; 547 548 led-controller@62 { 549 compatible = "nxp,pca9533"; 550 reg = <0x62>; 551 552 led-1 { 553 label = "user-led1"; 554 type = <PCA9532_TYPE_LED>; 555 }; 556 557 led-2 { 558 label = "user-led2"; 559 type = <PCA9532_TYPE_LED>; 560 }; 561 562 led-3 { 563 label = "user-led3"; 564 type = <PCA9532_TYPE_LED>; 565 }; 566 }; 567}; 568 569/* Shared with TIFS */ 570&wkup_uart0 { 571 pinctrl-names = "default"; 572 pinctrl-0 = <&wkup_uart0_pins_default>; 573 bootph-all; 574 status = "reserved"; 575}; 576