1// SPDX-License-Identifier: GPL-2.0-only or MIT 2/* 3 * Device Tree file for the AM62L3 SoC family (Dual Core A53) 4 * Copyright (C) 2025 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 * Technical Reference Manual: https://www.ti.com/lit/pdf/sprujb4 7 */ 8 9/dts-v1/; 10 11#include "k3-am62l.dtsi" 12 13/ { 14 cpus { 15 #address-cells = <1>; 16 #size-cells = <0>; 17 18 cpu-map { 19 cluster0: cluster0 { 20 core0 { 21 cpu = <&cpu0>; 22 }; 23 24 core1 { 25 cpu = <&cpu1>; 26 }; 27 }; 28 }; 29 30 cpu0: cpu@0 { 31 compatible = "arm,cortex-a53"; 32 reg = <0x000>; 33 device_type = "cpu"; 34 enable-method = "psci"; 35 i-cache-size = <0x8000>; 36 i-cache-line-size = <64>; 37 i-cache-sets = <256>; 38 d-cache-size = <0x8000>; 39 d-cache-line-size = <64>; 40 d-cache-sets = <128>; 41 next-level-cache = <&l2_0>; 42 operating-points-v2 = <&a53_opp_table>; 43 clocks = <&scmi_clk 356>; 44 }; 45 46 cpu1: cpu@1 { 47 compatible = "arm,cortex-a53"; 48 reg = <0x001>; 49 device_type = "cpu"; 50 enable-method = "psci"; 51 i-cache-size = <0x8000>; 52 i-cache-line-size = <64>; 53 i-cache-sets = <256>; 54 d-cache-size = <0x8000>; 55 d-cache-line-size = <64>; 56 d-cache-sets = <128>; 57 next-level-cache = <&l2_0>; 58 operating-points-v2 = <&a53_opp_table>; 59 clocks = <&scmi_clk 357>; 60 }; 61 }; 62 63 l2_0: l2-cache0 { 64 compatible = "cache"; 65 cache-unified; 66 cache-level = <2>; 67 cache-size = <0x40000>; 68 cache-line-size = <64>; 69 cache-sets = <256>; 70 }; 71 72 a53_opp_table: opp-table { 73 compatible = "operating-points-v2-ti-cpu"; 74 opp-shared; 75 syscon = <&opp_efuse_table>; 76 77 opp-200000000 { 78 opp-hz = /bits/ 64 <200000000>; 79 opp-supported-hw = <0x01 0x0003>; 80 clock-latency-ns = <6000000>; 81 }; 82 83 opp-400000000 { 84 opp-hz = /bits/ 64 <400000000>; 85 opp-supported-hw = <0x01 0x0003>; 86 clock-latency-ns = <6000000>; 87 }; 88 89 opp-600000000 { 90 opp-hz = /bits/ 64 <600000000>; 91 opp-supported-hw = <0x01 0x0003>; 92 clock-latency-ns = <6000000>; 93 }; 94 95 opp-800000000 { 96 opp-hz = /bits/ 64 <800000000>; 97 opp-supported-hw = <0x01 0x0003>; 98 clock-latency-ns = <6000000>; 99 }; 100 101 opp-1000000000 { 102 opp-hz = /bits/ 64 <1000000000>; 103 opp-supported-hw = <0x01 0x0002>; 104 clock-latency-ns = <6000000>; 105 }; 106 107 opp-1250000000 { 108 opp-hz = /bits/ 64 <1250000000>; 109 opp-supported-hw = <0x01 0x0002>; 110 clock-latency-ns = <6000000>; 111 opp-suspend; 112 }; 113 }; 114}; 115