1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/N2H SoC 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g087-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/* The IRQ_NS lines start at offset 16 in the ICU interrupt space */ 12#define RZN2H_IRQ0 16 13#define RZN2H_IRQ1 17 14#define RZN2H_IRQ2 18 15#define RZN2H_IRQ3 19 16#define RZN2H_IRQ4 20 17#define RZN2H_IRQ5 21 18#define RZN2H_IRQ6 22 19#define RZN2H_IRQ7 23 20#define RZN2H_IRQ8 24 21#define RZN2H_IRQ9 25 22#define RZN2H_IRQ10 26 23#define RZN2H_IRQ11 27 24#define RZN2H_IRQ12 28 25#define RZN2H_IRQ13 29 26#define RZN2H_IRQ14 30 27#define RZN2H_IRQ15 31 28 29/ { 30 compatible = "renesas,r9a09g087"; 31 #address-cells = <2>; 32 #size-cells = <2>; 33 interrupt-parent = <&gic>; 34 35 cluster0_opp: opp-table-0 { 36 compatible = "operating-points-v2"; 37 38 opp-600000000 { 39 opp-hz = /bits/ 64 <600000000>; 40 }; 41 opp-1200000000 { 42 opp-hz = /bits/ 64 <1200000000>; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 compatible = "arm,cortex-a55"; 52 reg = <0>; 53 device_type = "cpu"; 54 next-level-cache = <&L3_CA55>; 55 enable-method = "psci"; 56 clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C0>; 57 #cooling-cells = <2>; 58 operating-points-v2 = <&cluster0_opp>; 59 }; 60 61 cpu1: cpu@100 { 62 compatible = "arm,cortex-a55"; 63 reg = <0x100>; 64 device_type = "cpu"; 65 next-level-cache = <&L3_CA55>; 66 enable-method = "psci"; 67 clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C1>; 68 #cooling-cells = <2>; 69 operating-points-v2 = <&cluster0_opp>; 70 }; 71 72 cpu2: cpu@200 { 73 compatible = "arm,cortex-a55"; 74 reg = <0x200>; 75 device_type = "cpu"; 76 next-level-cache = <&L3_CA55>; 77 enable-method = "psci"; 78 clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C2>; 79 #cooling-cells = <2>; 80 operating-points-v2 = <&cluster0_opp>; 81 }; 82 83 cpu3: cpu@300 { 84 compatible = "arm,cortex-a55"; 85 reg = <0x300>; 86 device_type = "cpu"; 87 next-level-cache = <&L3_CA55>; 88 enable-method = "psci"; 89 clocks = <&cpg CPG_CORE R9A09G087_CLK_CA55C3>; 90 #cooling-cells = <2>; 91 operating-points-v2 = <&cluster0_opp>; 92 }; 93 94 L3_CA55: cache-controller-0 { 95 compatible = "cache"; 96 cache-unified; 97 cache-size = <0x100000>; 98 cache-level = <3>; 99 }; 100 }; 101 102 extal_clk: extal { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 /* This value must be overridden by the board */ 106 clock-frequency = <0>; 107 }; 108 109 pmu { 110 compatible = "arm,cortex-a55-pmu"; 111 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 112 }; 113 114 psci { 115 compatible = "arm,psci-1.0", "arm,psci-0.2"; 116 method = "smc"; 117 }; 118 119 soc: soc { 120 compatible = "simple-bus"; 121 #address-cells = <2>; 122 #size-cells = <2>; 123 ranges; 124 125 sci0: serial@80005000 { 126 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 127 reg = <0 0x80005000 0 0x400>; 128 interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>, 130 <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>, 131 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>; 132 interrupt-names = "eri", "rxi", "txi", "tei"; 133 clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 134 clock-names = "operation", "bus"; 135 power-domains = <&cpg>; 136 status = "disabled"; 137 }; 138 139 sci1: serial@80005400 { 140 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 141 reg = <0 0x80005400 0 0x400>; 142 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>, 144 <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>, 145 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 146 interrupt-names = "eri", "rxi", "txi", "tei"; 147 clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 148 clock-names = "operation", "bus"; 149 power-domains = <&cpg>; 150 status = "disabled"; 151 }; 152 153 sci2: serial@80005800 { 154 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 155 reg = <0 0x80005800 0 0x400>; 156 interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>, 158 <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>, 159 <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 160 interrupt-names = "eri", "rxi", "txi", "tei"; 161 clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 162 clock-names = "operation", "bus"; 163 power-domains = <&cpg>; 164 status = "disabled"; 165 }; 166 167 sci3: serial@80005c00 { 168 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 169 reg = <0 0x80005c00 0 0x400>; 170 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, 172 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 173 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 174 interrupt-names = "eri", "rxi", "txi", "tei"; 175 clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 176 clock-names = "operation", "bus"; 177 power-domains = <&cpg>; 178 status = "disabled"; 179 }; 180 181 sci4: serial@80006000 { 182 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 183 reg = <0 0x80006000 0 0x400>; 184 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>, 186 <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>, 187 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 188 interrupt-names = "eri", "rxi", "txi", "tei"; 189 clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 190 clock-names = "operation", "bus"; 191 power-domains = <&cpg>; 192 status = "disabled"; 193 }; 194 195 sci5: serial@81005000 { 196 compatible = "renesas,r9a09g087-rsci", "renesas,r9a09g077-rsci"; 197 reg = <0 0x81005000 0 0x400>; 198 interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>, 200 <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>, 201 <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; 202 interrupt-names = "eri", "rxi", "txi", "tei"; 203 clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 204 clock-names = "operation", "bus"; 205 power-domains = <&cpg>; 206 status = "disabled"; 207 }; 208 209 rspi0: spi@80007000 { 210 compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; 211 reg = <0x0 0x80007000 0x0 0x400>; 212 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 638 IRQ_TYPE_EDGE_RISING>, 215 <GIC_SPI 634 IRQ_TYPE_EDGE_RISING>, 216 <GIC_SPI 635 IRQ_TYPE_EDGE_RISING>; 217 interrupt-names = "idle", "error", "end", "rx", "tx"; 218 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, 219 <&cpg CPG_MOD 104>; 220 clock-names = "pclk", "pclkspi"; 221 dmas = <&dmac0 0x267a>, <&dmac0 0x267b>, 222 <&dmac1 0x267a>, <&dmac1 0x267b>, 223 <&dmac2 0x267a>, <&dmac2 0x267b>; 224 dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; 225 power-domains = <&cpg>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 status = "disabled"; 229 }; 230 231 rspi1: spi@80007400 { 232 compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; 233 reg = <0x0 0x80007400 0x0 0x400>; 234 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 643 IRQ_TYPE_EDGE_RISING>, 237 <GIC_SPI 639 IRQ_TYPE_EDGE_RISING>, 238 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>; 239 interrupt-names = "idle", "error", "end", "rx", "tx"; 240 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, 241 <&cpg CPG_MOD 105>; 242 clock-names = "pclk", "pclkspi"; 243 dmas = <&dmac0 0x267f>, <&dmac0 0x2680>, 244 <&dmac1 0x267f>, <&dmac1 0x2680>, 245 <&dmac2 0x267f>, <&dmac2 0x2680>; 246 dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; 247 power-domains = <&cpg>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 status = "disabled"; 251 }; 252 253 rspi2: spi@80007800 { 254 compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; 255 reg = <0x0 0x80007800 0x0 0x400>; 256 interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 648 IRQ_TYPE_EDGE_RISING>, 259 <GIC_SPI 644 IRQ_TYPE_EDGE_RISING>, 260 <GIC_SPI 645 IRQ_TYPE_EDGE_RISING>; 261 interrupt-names = "idle", "error", "end", "rx", "tx"; 262 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, 263 <&cpg CPG_MOD 106>; 264 clock-names = "pclk", "pclkspi"; 265 dmas = <&dmac0 0x2684>, <&dmac0 0x2685>, 266 <&dmac1 0x2684>, <&dmac1 0x2685>, 267 <&dmac2 0x2684>, <&dmac2 0x2685>; 268 dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; 269 power-domains = <&cpg>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 status = "disabled"; 273 }; 274 275 rspi3: spi@81007000 { 276 compatible = "renesas,r9a09g087-rspi", "renesas,r9a09g077-rspi"; 277 reg = <0x0 0x81007000 0x0 0x400>; 278 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 653 IRQ_TYPE_EDGE_RISING>, 281 <GIC_SPI 649 IRQ_TYPE_EDGE_RISING>, 282 <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; 283 interrupt-names = "idle", "error", "end", "rx", "tx"; 284 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>, 285 <&cpg CPG_MOD 602>; 286 clock-names = "pclk", "pclkspi"; 287 dmas = <&dmac0 0x2689>, <&dmac0 0x268a>, 288 <&dmac1 0x2689>, <&dmac1 0x268a>, 289 <&dmac2 0x2689>, <&dmac2 0x268a>; 290 dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; 291 power-domains = <&cpg>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 status = "disabled"; 295 }; 296 297 canfd: can@80040000 { 298 compatible = "renesas,r9a09g087-canfd", "renesas,r9a09g077-canfd"; 299 reg = <0 0x80040000 0 0x20000>; 300 interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>; 308 interrupt-names = "g_err", "g_recc", 309 "ch0_err", "ch0_rec", "ch0_trx", 310 "ch1_err", "ch1_rec", "ch1_trx"; 311 clocks = <&cpg CPG_MOD 310>, 312 <&cpg CPG_CORE R9A09G087_CLK_PCLKH>, 313 <&cpg CPG_CORE R9A09G087_PCLKCAN>; 314 clock-names = "fck", "ram_clk", "can_clk"; 315 assigned-clocks = <&cpg CPG_CORE R9A09G087_PCLKCAN>; 316 assigned-clock-rates = <80000000>; 317 power-domains = <&cpg>; 318 status = "disabled"; 319 320 channel0 { 321 status = "disabled"; 322 }; 323 channel1 { 324 status = "disabled"; 325 }; 326 }; 327 328 wdt0: watchdog@80082000 { 329 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 330 reg = <0 0x80082000 0 0x400>, 331 <0 0x81295100 0 0x04>; 332 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 333 clock-names = "pclk"; 334 power-domains = <&cpg>; 335 status = "disabled"; 336 }; 337 338 wdt1: watchdog@80082400 { 339 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 340 reg = <0 0x80082400 0 0x400>, 341 <0 0x81295104 0 0x04>; 342 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 343 clock-names = "pclk"; 344 power-domains = <&cpg>; 345 status = "disabled"; 346 }; 347 348 wdt2: watchdog@80082800 { 349 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 350 reg = <0 0x80082800 0 0x400>, 351 <0 0x81295108 0 0x04>; 352 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 353 clock-names = "pclk"; 354 power-domains = <&cpg>; 355 status = "disabled"; 356 }; 357 358 wdt3: watchdog@80082c00 { 359 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 360 reg = <0 0x80082c00 0 0x400>, 361 <0 0x8129510c 0 0x04>; 362 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 363 clock-names = "pclk"; 364 power-domains = <&cpg>; 365 status = "disabled"; 366 }; 367 368 wdt4: watchdog@80083000 { 369 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 370 reg = <0 0x80083000 0 0x400>, 371 <0 0x81295110 0 0x04>; 372 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 373 clock-names = "pclk"; 374 power-domains = <&cpg>; 375 status = "disabled"; 376 }; 377 378 wdt5: watchdog@80083400 { 379 compatible = "renesas,r9a09g087-wdt", "renesas,r9a09g077-wdt"; 380 reg = <0 0x80083400 0 0x400>, 381 <0 0x81295114 0 0x04>; 382 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>; 383 clock-names = "pclk"; 384 power-domains = <&cpg>; 385 status = "disabled"; 386 }; 387 388 tsu: thermal@80086000 { 389 compatible = "renesas,r9a09g087-tsu", "renesas,r9a09g077-tsu"; 390 reg = <0 0x80086000 0 0x1000>; 391 interrupts = <GIC_SPI 713 IRQ_TYPE_EDGE_RISING>, 392 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>; 393 interrupt-names = "adi", "adcmpi"; 394 clocks = <&cpg CPG_MOD 307>; 395 power-domains = <&cpg>; 396 #thermal-sensor-cells = <0>; 397 }; 398 399 i2c0: i2c@80088000 { 400 compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; 401 reg = <0 0x80088000 0 0x400>; 402 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>, 404 <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>, 405 <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>; 406 interrupt-names = "eei", "rxi", "txi", "tei"; 407 clocks = <&cpg CPG_MOD 100>; 408 power-domains = <&cpg>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 status = "disabled"; 412 }; 413 414 i2c1: i2c@80088400 { 415 compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; 416 reg = <0 0x80088400 0 0x400>; 417 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>; 421 interrupt-names = "eei", "rxi", "txi", "tei"; 422 clocks = <&cpg CPG_MOD 101>; 423 power-domains = <&cpg>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 status = "disabled"; 427 }; 428 429 i2c2: i2c@81008000 { 430 compatible = "renesas,riic-r9a09g087", "renesas,riic-r9a09g077"; 431 reg = <0 0x81008000 0 0x400>; 432 interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>, 434 <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 435 <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>; 436 interrupt-names = "eei", "rxi", "txi", "tei"; 437 clocks = <&cpg CPG_MOD 601>; 438 power-domains = <&cpg>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 status = "disabled"; 442 }; 443 444 dmac0: dma-controller@800c0000 { 445 compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac"; 446 reg = <0 0x800c0000 0 0x1000>; 447 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 448 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 449 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 450 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 451 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 452 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 453 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 454 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 455 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 456 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 457 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 458 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 459 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 460 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 461 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 462 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 463 interrupt-names = "ch0", "ch1", "ch2", "ch3", 464 "ch4", "ch5", "ch6", "ch7", 465 "ch8", "ch9", "ch10", "ch11", 466 "ch12", "ch13", "ch14", "ch15"; 467 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>; 468 power-domains = <&cpg>; 469 #dma-cells = <1>; 470 dma-channels = <16>; 471 renesas,icu = <&icu 0>; 472 }; 473 474 dmac1: dma-controller@800c1000 { 475 compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac"; 476 reg = <0 0x800c1000 0 0x1000>; 477 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 478 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 479 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 480 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 481 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 482 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 483 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 484 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 485 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, 486 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 487 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 488 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 489 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 490 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 491 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 492 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>; 493 interrupt-names = "ch0", "ch1", "ch2", "ch3", 494 "ch4", "ch5", "ch6", "ch7", 495 "ch8", "ch9", "ch10", "ch11", 496 "ch12", "ch13", "ch14", "ch15"; 497 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>; 498 power-domains = <&cpg>; 499 #dma-cells = <1>; 500 dma-channels = <16>; 501 renesas,icu = <&icu 1>; 502 }; 503 504 dmac2: dma-controller@800c2000 { 505 compatible = "renesas,r9a09g087-dmac", "renesas,r9a09g077-dmac"; 506 reg = <0 0x800c2000 0 0x1000>; 507 interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, 508 <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, 509 <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 510 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 511 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, 512 <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, 513 <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, 514 <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, 515 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, 516 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 517 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 518 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 519 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 520 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 521 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 522 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>; 523 interrupt-names = "ch0", "ch1", "ch2", "ch3", 524 "ch4", "ch5", "ch6", "ch7", 525 "ch8", "ch9", "ch10", "ch11", 526 "ch12", "ch13", "ch14", "ch15"; 527 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKH>; 528 power-domains = <&cpg>; 529 #dma-cells = <1>; 530 dma-channels = <16>; 531 renesas,icu = <&icu 2>; 532 }; 533 534 gmac0: ethernet@80100000 { 535 compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", 536 "snps,dwmac-5.20"; 537 reg = <0 0x80100000 0 0x10000>; 538 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 556 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 557 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 558 "rx-queue-0", "rx-queue-1", "rx-queue-2", 559 "rx-queue-3", "rx-queue-4", "rx-queue-5", 560 "rx-queue-6", "rx-queue-7", "tx-queue-0", 561 "tx-queue-1", "tx-queue-2", "tx-queue-3", 562 "tx-queue-4", "tx-queue-5", "tx-queue-6", 563 "tx-queue-7"; 564 clocks = <&cpg CPG_MOD 400>, 565 <&cpg CPG_CORE R9A09G087_CLK_PCLKH>, 566 <&cpg CPG_CORE R9A09G087_ETCLKB>; 567 clock-names = "stmmaceth", "pclk", "tx"; 568 resets = <&cpg 400>, <&cpg 401>; 569 reset-names = "stmmaceth", "ahb"; 570 power-domains = <&cpg>; 571 snps,multicast-filter-bins = <256>; 572 snps,perfect-filter-entries = <32>; 573 rx-fifo-depth = <8192>; 574 tx-fifo-depth = <8192>; 575 snps,fixed-burst; 576 snps,no-pbl-x8; 577 snps,force_thresh_dma_mode; 578 snps,axi-config = <&stmmac_axi_setup>; 579 snps,mtl-rx-config = <&mtl_rx_setup0>; 580 snps,mtl-tx-config = <&mtl_tx_setup0>; 581 snps,txpbl = <16>; 582 snps,rxpbl = <16>; 583 status = "disabled"; 584 585 mdio0: mdio { 586 compatible = "snps,dwmac-mdio"; 587 #address-cells = <1>; 588 #size-cells = <0>; 589 }; 590 591 mtl_rx_setup0: rx-queues-config { 592 snps,rx-queues-to-use = <8>; 593 snps,rx-sched-sp; 594 595 queue0 { 596 snps,dcb-algorithm; 597 snps,priority = <0x1>; 598 snps,map-to-dma-channel = <0>; 599 }; 600 601 queue1 { 602 snps,dcb-algorithm; 603 snps,priority = <0x2>; 604 snps,map-to-dma-channel = <1>; 605 }; 606 607 queue2 { 608 snps,dcb-algorithm; 609 snps,priority = <0x4>; 610 snps,map-to-dma-channel = <2>; 611 }; 612 613 queue3 { 614 snps,dcb-algorithm; 615 snps,priority = <0x8>; 616 snps,map-to-dma-channel = <3>; 617 }; 618 619 queue4 { 620 snps,dcb-algorithm; 621 snps,priority = <0x10>; 622 snps,map-to-dma-channel = <4>; 623 }; 624 625 queue5 { 626 snps,dcb-algorithm; 627 snps,priority = <0x20>; 628 snps,map-to-dma-channel = <5>; 629 }; 630 631 queue6 { 632 snps,dcb-algorithm; 633 snps,priority = <0x40>; 634 snps,map-to-dma-channel = <6>; 635 }; 636 637 queue7 { 638 snps,dcb-algorithm; 639 snps,priority = <0x80>; 640 snps,map-to-dma-channel = <7>; 641 }; 642 }; 643 644 mtl_tx_setup0: tx-queues-config { 645 snps,tx-queues-to-use = <8>; 646 647 queue0 { 648 snps,dcb-algorithm; 649 }; 650 651 queue1 { 652 snps,dcb-algorithm; 653 }; 654 655 queue2 { 656 snps,dcb-algorithm; 657 }; 658 659 queue3 { 660 snps,dcb-algorithm; 661 }; 662 663 queue4 { 664 snps,dcb-algorithm; 665 }; 666 667 queue5 { 668 snps,dcb-algorithm; 669 }; 670 671 queue6 { 672 snps,dcb-algorithm; 673 }; 674 675 queue7 { 676 snps,dcb-algorithm; 677 }; 678 }; 679 }; 680 681 gmac1: ethernet@92000000 { 682 compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", 683 "snps,dwmac-5.20"; 684 reg = <0 0x92000000 0 0x10000>; 685 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, 702 <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 703 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>; 704 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 705 "rx-queue-0", "rx-queue-1", "rx-queue-2", 706 "rx-queue-3", "rx-queue-4", "rx-queue-5", 707 "rx-queue-6", "rx-queue-7", "tx-queue-0", 708 "tx-queue-1", "tx-queue-2", "tx-queue-3", 709 "tx-queue-4", "tx-queue-5", "tx-queue-6", 710 "tx-queue-7"; 711 clocks = <&cpg CPG_MOD 416>, 712 <&cpg CPG_CORE R9A09G087_CLK_PCLKAH>, 713 <&cpg CPG_CORE R9A09G087_ETCLKB>; 714 clock-names = "stmmaceth", "pclk", "tx"; 715 resets = <&cpg 416>, <&cpg 417>; 716 reset-names = "stmmaceth", "ahb"; 717 power-domains = <&cpg>; 718 snps,multicast-filter-bins = <256>; 719 snps,perfect-filter-entries = <32>; 720 rx-fifo-depth = <8192>; 721 tx-fifo-depth = <8192>; 722 snps,fixed-burst; 723 snps,no-pbl-x8; 724 snps,force_thresh_dma_mode; 725 snps,axi-config = <&stmmac_axi_setup>; 726 snps,mtl-rx-config = <&mtl_rx_setup1>; 727 snps,mtl-tx-config = <&mtl_tx_setup1>; 728 snps,txpbl = <16>; 729 snps,rxpbl = <16>; 730 status = "disabled"; 731 732 mdio1: mdio { 733 compatible = "snps,dwmac-mdio"; 734 #address-cells = <1>; 735 #size-cells = <0>; 736 }; 737 738 mtl_rx_setup1: rx-queues-config { 739 snps,rx-queues-to-use = <8>; 740 snps,rx-sched-sp; 741 742 queue0 { 743 snps,dcb-algorithm; 744 snps,priority = <0x1>; 745 snps,map-to-dma-channel = <0>; 746 }; 747 748 queue1 { 749 snps,dcb-algorithm; 750 snps,priority = <0x2>; 751 snps,map-to-dma-channel = <1>; 752 }; 753 754 queue2 { 755 snps,dcb-algorithm; 756 snps,priority = <0x4>; 757 snps,map-to-dma-channel = <2>; 758 }; 759 760 queue3 { 761 snps,dcb-algorithm; 762 snps,priority = <0x8>; 763 snps,map-to-dma-channel = <3>; 764 }; 765 766 queue4 { 767 snps,dcb-algorithm; 768 snps,priority = <0x10>; 769 snps,map-to-dma-channel = <4>; 770 }; 771 772 queue5 { 773 snps,dcb-algorithm; 774 snps,priority = <0x20>; 775 snps,map-to-dma-channel = <5>; 776 }; 777 778 queue6 { 779 snps,dcb-algorithm; 780 snps,priority = <0x40>; 781 snps,map-to-dma-channel = <6>; 782 }; 783 784 queue7 { 785 snps,dcb-algorithm; 786 snps,priority = <0x80>; 787 snps,map-to-dma-channel = <7>; 788 }; 789 }; 790 791 mtl_tx_setup1: tx-queues-config { 792 snps,tx-queues-to-use = <8>; 793 794 queue0 { 795 snps,dcb-algorithm; 796 }; 797 798 queue1 { 799 snps,dcb-algorithm; 800 }; 801 802 queue2 { 803 snps,dcb-algorithm; 804 }; 805 806 queue3 { 807 snps,dcb-algorithm; 808 }; 809 810 queue4 { 811 snps,dcb-algorithm; 812 }; 813 814 queue5 { 815 snps,dcb-algorithm; 816 }; 817 818 queue6 { 819 snps,dcb-algorithm; 820 }; 821 822 queue7 { 823 snps,dcb-algorithm; 824 }; 825 }; 826 }; 827 828 gmac2: ethernet@92010000 { 829 compatible = "renesas,r9a09g087-gbeth", "renesas,r9a09g077-gbeth", 830 "snps,dwmac-5.20"; 831 reg = <0 0x92010000 0 0x10000>; 832 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 848 <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 849 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>, 850 <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; 851 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 852 "rx-queue-0", "rx-queue-1", "rx-queue-2", 853 "rx-queue-3", "rx-queue-4", "rx-queue-5", 854 "rx-queue-6", "rx-queue-7", "tx-queue-0", 855 "tx-queue-1", "tx-queue-2", "tx-queue-3", 856 "tx-queue-4", "tx-queue-5", "tx-queue-6", 857 "tx-queue-7"; 858 clocks = <&cpg CPG_MOD 417>, 859 <&cpg CPG_CORE R9A09G087_CLK_PCLKAH>, 860 <&cpg CPG_CORE R9A09G087_ETCLKB>; 861 clock-names = "stmmaceth", "pclk", "tx"; 862 resets = <&cpg 418>, <&cpg 419>; 863 reset-names = "stmmaceth", "ahb"; 864 power-domains = <&cpg>; 865 snps,multicast-filter-bins = <256>; 866 snps,perfect-filter-entries = <32>; 867 rx-fifo-depth = <8192>; 868 tx-fifo-depth = <8192>; 869 snps,fixed-burst; 870 snps,no-pbl-x8; 871 snps,force_thresh_dma_mode; 872 snps,axi-config = <&stmmac_axi_setup>; 873 snps,mtl-rx-config = <&mtl_rx_setup2>; 874 snps,mtl-tx-config = <&mtl_tx_setup2>; 875 snps,txpbl = <16>; 876 snps,rxpbl = <16>; 877 status = "disabled"; 878 879 mdio2: mdio { 880 compatible = "snps,dwmac-mdio"; 881 #address-cells = <1>; 882 #size-cells = <0>; 883 }; 884 885 mtl_rx_setup2: rx-queues-config { 886 snps,rx-queues-to-use = <8>; 887 snps,rx-sched-sp; 888 889 queue0 { 890 snps,dcb-algorithm; 891 snps,priority = <0x1>; 892 snps,map-to-dma-channel = <0>; 893 }; 894 895 queue1 { 896 snps,dcb-algorithm; 897 snps,priority = <0x2>; 898 snps,map-to-dma-channel = <1>; 899 }; 900 901 queue2 { 902 snps,dcb-algorithm; 903 snps,priority = <0x4>; 904 snps,map-to-dma-channel = <2>; 905 }; 906 907 queue3 { 908 snps,dcb-algorithm; 909 snps,priority = <0x8>; 910 snps,map-to-dma-channel = <3>; 911 }; 912 913 queue4 { 914 snps,dcb-algorithm; 915 snps,priority = <0x10>; 916 snps,map-to-dma-channel = <4>; 917 }; 918 919 queue5 { 920 snps,dcb-algorithm; 921 snps,priority = <0x20>; 922 snps,map-to-dma-channel = <5>; 923 }; 924 925 queue6 { 926 snps,dcb-algorithm; 927 snps,priority = <0x40>; 928 snps,map-to-dma-channel = <6>; 929 }; 930 931 queue7 { 932 snps,dcb-algorithm; 933 snps,priority = <0x80>; 934 snps,map-to-dma-channel = <7>; 935 }; 936 }; 937 938 mtl_tx_setup2: tx-queues-config { 939 snps,tx-queues-to-use = <8>; 940 941 queue0 { 942 snps,dcb-algorithm; 943 }; 944 945 queue1 { 946 snps,dcb-algorithm; 947 }; 948 949 queue2 { 950 snps,dcb-algorithm; 951 }; 952 953 queue3 { 954 snps,dcb-algorithm; 955 }; 956 957 queue4 { 958 snps,dcb-algorithm; 959 }; 960 961 queue5 { 962 snps,dcb-algorithm; 963 }; 964 965 queue6 { 966 snps,dcb-algorithm; 967 }; 968 969 queue7 { 970 snps,dcb-algorithm; 971 }; 972 }; 973 }; 974 975 ethss: ethss@80110000 { 976 compatible = "renesas,r9a09g087-miic", "renesas,r9a09g077-miic"; 977 reg = <0 0x80110000 0 0x10000>; 978 clocks = <&cpg CPG_CORE R9A09G087_ETCLKE>, 979 <&cpg CPG_CORE R9A09G087_ETCLKB>, 980 <&cpg CPG_CORE R9A09G087_ETCLKD>, 981 <&cpg CPG_MOD 403>; 982 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; 983 resets = <&cpg 405>, <&cpg 406>; 984 reset-names = "rst", "crst"; 985 power-domains = <&cpg>; 986 status = "disabled"; 987 988 #address-cells = <1>; 989 #size-cells = <0>; 990 991 mii_conv0: mii-conv@0 { 992 reg = <0>; 993 status = "disabled"; 994 }; 995 996 mii_conv1: mii-conv@1 { 997 reg = <1>; 998 status = "disabled"; 999 }; 1000 1001 mii_conv2: mii-conv@2 { 1002 reg = <2>; 1003 status = "disabled"; 1004 }; 1005 1006 mii_conv3: mii-conv@3 { 1007 reg = <3>; 1008 status = "disabled"; 1009 }; 1010 }; 1011 1012 cpg: clock-controller@80280000 { 1013 compatible = "renesas,r9a09g087-cpg-mssr"; 1014 reg = <0 0x80280000 0 0x10000>, 1015 <0 0x81280000 0 0x10000>; 1016 clocks = <&extal_clk>; 1017 clock-names = "extal"; 1018 #clock-cells = <2>; 1019 #reset-cells = <1>; 1020 #power-domain-cells = <0>; 1021 }; 1022 1023 icu: interrupt-controller@802a0000 { 1024 compatible = "renesas,r9a09g087-icu", "renesas,r9a09g077-icu"; 1025 reg = <0 0x802a0000 0 0x10000>, 1026 <0 0x812a0000 0 0x10000>; 1027 #interrupt-cells = <2>; 1028 #address-cells = <0>; 1029 interrupt-controller; 1030 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>, 1031 <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>, 1032 <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, 1033 <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 1034 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>, 1035 <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>, 1036 <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>, 1037 <GIC_SPI 7 IRQ_TYPE_EDGE_RISING>, 1038 <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>, 1039 <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>, 1040 <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>, 1041 <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>, 1042 <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>, 1043 <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>, 1044 <GIC_SPI 14 IRQ_TYPE_EDGE_RISING>, 1045 <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>, 1046 <GIC_SPI 16 IRQ_TYPE_EDGE_RISING>, 1047 <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>, 1048 <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>, 1049 <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 1050 <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>, 1051 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 1052 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>, 1053 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>, 1054 <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1055 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 1056 <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 1057 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 1058 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 1059 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, 1060 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 1061 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 1062 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, 1063 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, 1064 <GIC_SPI 408 IRQ_TYPE_EDGE_RISING>, 1065 <GIC_SPI 409 IRQ_TYPE_EDGE_RISING>, 1066 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, 1067 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, 1068 <GIC_SPI 412 IRQ_TYPE_EDGE_RISING>, 1069 <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>, 1070 <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>, 1071 <GIC_SPI 415 IRQ_TYPE_EDGE_RISING>, 1072 <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>, 1073 <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>, 1074 <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>; 1075 interrupt-names = "intcpu0", "intcpu1", "intcpu2", 1076 "intcpu3", "intcpu4", "intcpu5", 1077 "intcpu6", "intcpu7", "intcpu8", 1078 "intcpu9", "intcpu10", "intcpu11", 1079 "intcpu12", "intcpu13", "intcpu14", 1080 "intcpu15", 1081 "irq0", "irq1", "irq2", "irq3", 1082 "irq4", "irq5", "irq6", "irq7", 1083 "irq8", "irq9", "irq10", "irq11", 1084 "irq12", "irq13", "irq14", "irq15", 1085 "sei", 1086 "ca55-err0", "ca55-err1", 1087 "cr520-err0", "cr520-err1", 1088 "cr521-err0", "cr521-err1", 1089 "peri-err0", "peri-err1", 1090 "dsmif-err0", "dsmif-err1", 1091 "encif-err0", "encif-err1"; 1092 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 1093 power-domains = <&cpg>; 1094 }; 1095 1096 pinctrl: pinctrl@802c0000 { 1097 compatible = "renesas,r9a09g087-pinctrl"; 1098 reg = <0 0x802c0000 0 0x10000>, 1099 <0 0x812c0000 0 0x10000>, 1100 <0 0x802b0000 0 0x10000>; 1101 reg-names = "nsr", "srs", "srn"; 1102 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKM>; 1103 gpio-controller; 1104 #gpio-cells = <2>; 1105 gpio-ranges = <&pinctrl 0 0 280>; 1106 #interrupt-cells = <2>; 1107 interrupt-controller; 1108 interrupt-parent = <&icu>; 1109 power-domains = <&cpg>; 1110 }; 1111 1112 gic: interrupt-controller@83000000 { 1113 compatible = "arm,gic-v3"; 1114 reg = <0x0 0x83000000 0 0x40000>, 1115 <0x0 0x83040000 0 0x160000>; 1116 #interrupt-cells = <3>; 1117 #address-cells = <0>; 1118 interrupt-controller; 1119 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1120 }; 1121 1122 adc0: adc@90014000 { 1123 compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc"; 1124 reg = <0 0x90014000 0 0x400>; 1125 interrupts = <GIC_SPI 698 IRQ_TYPE_EDGE_RISING>, 1126 <GIC_SPI 699 IRQ_TYPE_EDGE_RISING>, 1127 <GIC_SPI 700 IRQ_TYPE_EDGE_RISING>, 1128 <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, 1129 <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, 1130 <GIC_SPI 851 IRQ_TYPE_EDGE_RISING>, 1131 <GIC_SPI 852 IRQ_TYPE_EDGE_RISING>; 1132 interrupt-names = "adi", "gbadi", "gcadi", 1133 "cmpai", "cmpbi", "wcmpm", "wcmpum"; 1134 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, 1135 <&cpg CPG_MOD 206>; 1136 clock-names = "adclk", "pclk"; 1137 power-domains = <&cpg>; 1138 #address-cells = <1>; 1139 #size-cells = <0>; 1140 #io-channel-cells = <1>; 1141 status = "disabled"; 1142 }; 1143 1144 adc1: adc@90014400 { 1145 compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc"; 1146 reg = <0 0x90014400 0 0x400>; 1147 interrupts = <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>, 1148 <GIC_SPI 704 IRQ_TYPE_EDGE_RISING>, 1149 <GIC_SPI 705 IRQ_TYPE_EDGE_RISING>, 1150 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 1151 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 1152 <GIC_SPI 853 IRQ_TYPE_EDGE_RISING>, 1153 <GIC_SPI 854 IRQ_TYPE_EDGE_RISING>; 1154 interrupt-names = "adi", "gbadi", "gcadi", 1155 "cmpai", "cmpbi", "wcmpm", "wcmpum"; 1156 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, 1157 <&cpg CPG_MOD 207>; 1158 clock-names = "adclk", "pclk"; 1159 power-domains = <&cpg>; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 #io-channel-cells = <1>; 1163 status = "disabled"; 1164 }; 1165 1166 adc2: adc@80008000 { 1167 compatible = "renesas,r9a09g087-adc", "renesas,r9a09g077-adc"; 1168 reg = <0 0x80008000 0 0x400>; 1169 interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>, 1170 <GIC_SPI 709 IRQ_TYPE_EDGE_RISING>, 1171 <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>, 1172 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 1174 <GIC_SPI 855 IRQ_TYPE_EDGE_RISING>, 1175 <GIC_SPI 856 IRQ_TYPE_EDGE_RISING>; 1176 interrupt-names = "adi", "gbadi", "gcadi", 1177 "cmpai", "cmpbi", "wcmpm", "wcmpum"; 1178 clocks = <&cpg CPG_CORE R9A09G087_CLK_PCLKL>, 1179 <&cpg CPG_MOD 225>; 1180 clock-names = "adclk", "pclk"; 1181 power-domains = <&cpg>; 1182 #address-cells = <1>; 1183 #size-cells = <0>; 1184 #io-channel-cells = <1>; 1185 status = "disabled"; 1186 }; 1187 1188 ohci: usb@92040000 { 1189 compatible = "generic-ohci"; 1190 reg = <0 0x92040000 0 0x100>; 1191 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1192 clocks = <&cpg CPG_MOD 408>; 1193 phys = <&usb2_phy 1>; 1194 phy-names = "usb"; 1195 power-domains = <&cpg>; 1196 status = "disabled"; 1197 }; 1198 1199 ehci: usb@92040100 { 1200 compatible = "generic-ehci"; 1201 reg = <0 0x92040100 0 0x100>; 1202 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1203 clocks = <&cpg CPG_MOD 408>; 1204 phys = <&usb2_phy 2>; 1205 phy-names = "usb"; 1206 companion = <&ohci>; 1207 power-domains = <&cpg>; 1208 status = "disabled"; 1209 }; 1210 1211 usb2_phy: usb-phy@92040200 { 1212 compatible = "renesas,usb2-phy-r9a09g087", "renesas,usb2-phy-r9a09g077"; 1213 reg = <0 0x92040200 0 0x700>; 1214 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1215 clocks = <&cpg CPG_MOD 408>, 1216 <&cpg CPG_CORE R9A09G087_USB_CLK>; 1217 #phy-cells = <1>; 1218 power-domains = <&cpg>; 1219 status = "disabled"; 1220 }; 1221 1222 hsusb: usb@92041000 { 1223 compatible = "renesas,usbhs-r9a09g087", "renesas,usbhs-r9a09g077"; 1224 reg = <0 0x92041000 0 0x1000>; 1225 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, 1226 <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1227 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1228 clocks = <&cpg CPG_MOD 408>; 1229 phys = <&usb2_phy 3>; 1230 phy-names = "usb"; 1231 power-domains = <&cpg>; 1232 status = "disabled"; 1233 }; 1234 1235 sdhi0: mmc@92080000 { 1236 compatible = "renesas,sdhi-r9a09g087", 1237 "renesas,sdhi-r9a09g057"; 1238 reg = <0x0 0x92080000 0 0x10000>; 1239 interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1240 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 1241 clocks = <&cpg CPG_MOD 1212>, 1242 <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>; 1243 clock-names = "aclk", "clkh"; 1244 power-domains = <&cpg>; 1245 status = "disabled"; 1246 1247 sdhi0_vqmmc: vqmmc-regulator { 1248 regulator-name = "SDHI0-VQMMC"; 1249 regulator-min-microvolt = <1800000>; 1250 regulator-max-microvolt = <3300000>; 1251 status = "disabled"; 1252 }; 1253 }; 1254 1255 sdhi1: mmc@92090000 { 1256 compatible = "renesas,sdhi-r9a09g087", 1257 "renesas,sdhi-r9a09g057"; 1258 reg = <0x0 0x92090000 0 0x10000>; 1259 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1260 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1261 clocks = <&cpg CPG_MOD 1213>, 1262 <&cpg CPG_CORE R9A09G087_SDHI_CLKHS>; 1263 clock-names = "aclk", "clkh"; 1264 power-domains = <&cpg>; 1265 status = "disabled"; 1266 1267 sdhi1_vqmmc: vqmmc-regulator { 1268 regulator-name = "SDHI1-VQMMC"; 1269 regulator-min-microvolt = <1800000>; 1270 regulator-max-microvolt = <3300000>; 1271 status = "disabled"; 1272 }; 1273 }; 1274 }; 1275 1276 stmmac_axi_setup: stmmac-axi-config { 1277 snps,lpi_en; 1278 snps,wr_osr_lmt = <0xf>; 1279 snps,rd_osr_lmt = <0xf>; 1280 snps,blen = <16 8 4 0 0 0 0>; 1281 }; 1282 1283 thermal-zones { 1284 cpu-thermal { 1285 polling-delay = <1000>; 1286 polling-delay-passive = <250>; 1287 thermal-sensors = <&tsu>; 1288 1289 cooling-maps { 1290 map0 { 1291 trip = <&target>; 1292 cooling-device = <&cpu0 0 1>, <&cpu1 0 1>, 1293 <&cpu2 0 1>, <&cpu3 0 1>; 1294 contribution = <1024>; 1295 }; 1296 }; 1297 1298 trips { 1299 target: trip-point { 1300 temperature = <95000>; 1301 hysteresis = <1000>; 1302 type = "passive"; 1303 }; 1304 1305 sensor_crit: sensor-crit { 1306 temperature = <120000>; 1307 hysteresis = <1000>; 1308 type = "critical"; 1309 }; 1310 }; 1311 }; 1312 }; 1313 1314 timer { 1315 compatible = "arm,armv8-timer"; 1316 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1317 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1318 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1319 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1320 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1321 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 1322 }; 1323}; 1324