1// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) 2/* 3 * Device Tree Source for the RZ/T2H SoC 4 * 5 * Copyright (C) 2025 Renesas Electronics Corp. 6 */ 7 8#include <dt-bindings/clock/renesas,r9a09g077-cpg-mssr.h> 9#include <dt-bindings/interrupt-controller/arm-gic.h> 10 11/* The IRQ_NS lines start at offset 16 in the ICU interrupt space */ 12#define RZT2H_IRQ0 16 13#define RZT2H_IRQ1 17 14#define RZT2H_IRQ2 18 15#define RZT2H_IRQ3 19 16#define RZT2H_IRQ4 20 17#define RZT2H_IRQ5 21 18#define RZT2H_IRQ6 22 19#define RZT2H_IRQ7 23 20#define RZT2H_IRQ8 24 21#define RZT2H_IRQ9 25 22#define RZT2H_IRQ10 26 23#define RZT2H_IRQ11 27 24#define RZT2H_IRQ12 28 25#define RZT2H_IRQ13 29 26#define RZT2H_IRQ14 30 27#define RZT2H_IRQ15 31 28 29/ { 30 compatible = "renesas,r9a09g077"; 31 #address-cells = <2>; 32 #size-cells = <2>; 33 interrupt-parent = <&gic>; 34 35 cluster0_opp: opp-table-0 { 36 compatible = "operating-points-v2"; 37 38 opp-600000000 { 39 opp-hz = /bits/ 64 <600000000>; 40 }; 41 opp-1200000000 { 42 opp-hz = /bits/ 64 <1200000000>; 43 }; 44 }; 45 46 cpus { 47 #address-cells = <1>; 48 #size-cells = <0>; 49 50 cpu0: cpu@0 { 51 compatible = "arm,cortex-a55"; 52 reg = <0>; 53 device_type = "cpu"; 54 next-level-cache = <&L3_CA55>; 55 enable-method = "psci"; 56 clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C0>; 57 #cooling-cells = <2>; 58 operating-points-v2 = <&cluster0_opp>; 59 }; 60 61 cpu1: cpu@100 { 62 compatible = "arm,cortex-a55"; 63 reg = <0x100>; 64 device_type = "cpu"; 65 next-level-cache = <&L3_CA55>; 66 enable-method = "psci"; 67 clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C1>; 68 #cooling-cells = <2>; 69 operating-points-v2 = <&cluster0_opp>; 70 }; 71 72 cpu2: cpu@200 { 73 compatible = "arm,cortex-a55"; 74 reg = <0x200>; 75 device_type = "cpu"; 76 next-level-cache = <&L3_CA55>; 77 enable-method = "psci"; 78 clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C2>; 79 #cooling-cells = <2>; 80 operating-points-v2 = <&cluster0_opp>; 81 }; 82 83 cpu3: cpu@300 { 84 compatible = "arm,cortex-a55"; 85 reg = <0x300>; 86 device_type = "cpu"; 87 next-level-cache = <&L3_CA55>; 88 enable-method = "psci"; 89 clocks = <&cpg CPG_CORE R9A09G077_CLK_CA55C3>; 90 #cooling-cells = <2>; 91 operating-points-v2 = <&cluster0_opp>; 92 }; 93 94 L3_CA55: cache-controller-0 { 95 compatible = "cache"; 96 cache-unified; 97 cache-size = <0x100000>; 98 cache-level = <3>; 99 }; 100 }; 101 102 extal_clk: extal { 103 compatible = "fixed-clock"; 104 #clock-cells = <0>; 105 /* This value must be overridden by the board */ 106 clock-frequency = <0>; 107 }; 108 109 pmu { 110 compatible = "arm,cortex-a55-pmu"; 111 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 112 }; 113 114 psci { 115 compatible = "arm,psci-1.0", "arm,psci-0.2"; 116 method = "smc"; 117 }; 118 119 soc: soc { 120 compatible = "simple-bus"; 121 #address-cells = <2>; 122 #size-cells = <2>; 123 ranges; 124 125 sci0: serial@80005000 { 126 compatible = "renesas,r9a09g077-rsci"; 127 reg = <0 0x80005000 0 0x400>; 128 interrupts = <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 129 <GIC_SPI 591 IRQ_TYPE_EDGE_RISING>, 130 <GIC_SPI 592 IRQ_TYPE_EDGE_RISING>, 131 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>; 132 interrupt-names = "eri", "rxi", "txi", "tei"; 133 clocks = <&cpg CPG_MOD 8>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 134 clock-names = "operation", "bus"; 135 power-domains = <&cpg>; 136 status = "disabled"; 137 }; 138 139 sci1: serial@80005400 { 140 compatible = "renesas,r9a09g077-rsci"; 141 reg = <0 0x80005400 0 0x400>; 142 interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 143 <GIC_SPI 595 IRQ_TYPE_EDGE_RISING>, 144 <GIC_SPI 596 IRQ_TYPE_EDGE_RISING>, 145 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>; 146 interrupt-names = "eri", "rxi", "txi", "tei"; 147 clocks = <&cpg CPG_MOD 9>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 148 clock-names = "operation", "bus"; 149 power-domains = <&cpg>; 150 status = "disabled"; 151 }; 152 153 sci2: serial@80005800 { 154 compatible = "renesas,r9a09g077-rsci"; 155 reg = <0 0x80005800 0 0x400>; 156 interrupts = <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 157 <GIC_SPI 599 IRQ_TYPE_EDGE_RISING>, 158 <GIC_SPI 600 IRQ_TYPE_EDGE_RISING>, 159 <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 160 interrupt-names = "eri", "rxi", "txi", "tei"; 161 clocks = <&cpg CPG_MOD 10>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 162 clock-names = "operation", "bus"; 163 power-domains = <&cpg>; 164 status = "disabled"; 165 }; 166 167 sci3: serial@80005c00 { 168 compatible = "renesas,r9a09g077-rsci"; 169 reg = <0 0x80005c00 0 0x400>; 170 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>, 171 <GIC_SPI 603 IRQ_TYPE_EDGE_RISING>, 172 <GIC_SPI 604 IRQ_TYPE_EDGE_RISING>, 173 <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 174 interrupt-names = "eri", "rxi", "txi", "tei"; 175 clocks = <&cpg CPG_MOD 11>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 176 clock-names = "operation", "bus"; 177 power-domains = <&cpg>; 178 status = "disabled"; 179 }; 180 181 sci4: serial@80006000 { 182 compatible = "renesas,r9a09g077-rsci"; 183 reg = <0 0x80006000 0 0x400>; 184 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>, 185 <GIC_SPI 607 IRQ_TYPE_EDGE_RISING>, 186 <GIC_SPI 608 IRQ_TYPE_EDGE_RISING>, 187 <GIC_SPI 609 IRQ_TYPE_LEVEL_HIGH>; 188 interrupt-names = "eri", "rxi", "txi", "tei"; 189 clocks = <&cpg CPG_MOD 12>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 190 clock-names = "operation", "bus"; 191 power-domains = <&cpg>; 192 status = "disabled"; 193 }; 194 195 sci5: serial@81005000 { 196 compatible = "renesas,r9a09g077-rsci"; 197 reg = <0 0x81005000 0 0x400>; 198 interrupts = <GIC_SPI 610 IRQ_TYPE_LEVEL_HIGH>, 199 <GIC_SPI 611 IRQ_TYPE_EDGE_RISING>, 200 <GIC_SPI 612 IRQ_TYPE_EDGE_RISING>, 201 <GIC_SPI 613 IRQ_TYPE_LEVEL_HIGH>; 202 interrupt-names = "eri", "rxi", "txi", "tei"; 203 clocks = <&cpg CPG_MOD 600>, <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 204 clock-names = "operation", "bus"; 205 power-domains = <&cpg>; 206 status = "disabled"; 207 }; 208 209 rspi0: spi@80007000 { 210 compatible = "renesas,r9a09g077-rspi"; 211 reg = <0x0 0x80007000 0x0 0x400>; 212 interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH>, 213 <GIC_SPI 637 IRQ_TYPE_LEVEL_HIGH>, 214 <GIC_SPI 638 IRQ_TYPE_EDGE_RISING>, 215 <GIC_SPI 634 IRQ_TYPE_EDGE_RISING>, 216 <GIC_SPI 635 IRQ_TYPE_EDGE_RISING>; 217 interrupt-names = "idle", "error", "end", "rx", "tx"; 218 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, 219 <&cpg CPG_MOD 104>; 220 clock-names = "pclk", "pclkspi"; 221 dmas = <&dmac0 0x267a>, <&dmac0 0x267b>, 222 <&dmac1 0x267a>, <&dmac1 0x267b>, 223 <&dmac2 0x267a>, <&dmac2 0x267b>; 224 dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; 225 power-domains = <&cpg>; 226 #address-cells = <1>; 227 #size-cells = <0>; 228 status = "disabled"; 229 }; 230 231 rspi1: spi@80007400 { 232 compatible = "renesas,r9a09g077-rspi"; 233 reg = <0x0 0x80007400 0x0 0x400>; 234 interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH>, 235 <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH>, 236 <GIC_SPI 643 IRQ_TYPE_EDGE_RISING>, 237 <GIC_SPI 639 IRQ_TYPE_EDGE_RISING>, 238 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>; 239 interrupt-names = "idle", "error", "end", "rx", "tx"; 240 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, 241 <&cpg CPG_MOD 105>; 242 clock-names = "pclk", "pclkspi"; 243 dmas = <&dmac0 0x267f>, <&dmac0 0x2680>, 244 <&dmac1 0x267f>, <&dmac1 0x2680>, 245 <&dmac2 0x267f>, <&dmac2 0x2680>; 246 dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; 247 power-domains = <&cpg>; 248 #address-cells = <1>; 249 #size-cells = <0>; 250 status = "disabled"; 251 }; 252 253 rspi2: spi@80007800 { 254 compatible = "renesas,r9a09g077-rspi"; 255 reg = <0x0 0x80007800 0x0 0x400>; 256 interrupts = <GIC_SPI 646 IRQ_TYPE_LEVEL_HIGH>, 257 <GIC_SPI 647 IRQ_TYPE_LEVEL_HIGH>, 258 <GIC_SPI 648 IRQ_TYPE_EDGE_RISING>, 259 <GIC_SPI 644 IRQ_TYPE_EDGE_RISING>, 260 <GIC_SPI 645 IRQ_TYPE_EDGE_RISING>; 261 interrupt-names = "idle", "error", "end", "rx", "tx"; 262 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, 263 <&cpg CPG_MOD 106>; 264 clock-names = "pclk", "pclkspi"; 265 dmas = <&dmac0 0x2684>, <&dmac0 0x2685>, 266 <&dmac1 0x2684>, <&dmac1 0x2685>, 267 <&dmac2 0x2684>, <&dmac2 0x2685>; 268 dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; 269 power-domains = <&cpg>; 270 #address-cells = <1>; 271 #size-cells = <0>; 272 status = "disabled"; 273 }; 274 275 rspi3: spi@81007000 { 276 compatible = "renesas,r9a09g077-rspi"; 277 reg = <0x0 0x81007000 0x0 0x400>; 278 interrupts = <GIC_SPI 651 IRQ_TYPE_LEVEL_HIGH>, 279 <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 280 <GIC_SPI 653 IRQ_TYPE_EDGE_RISING>, 281 <GIC_SPI 649 IRQ_TYPE_EDGE_RISING>, 282 <GIC_SPI 650 IRQ_TYPE_EDGE_RISING>; 283 interrupt-names = "idle", "error", "end", "rx", "tx"; 284 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>, 285 <&cpg CPG_MOD 602>; 286 clock-names = "pclk", "pclkspi"; 287 dmas = <&dmac0 0x2689>, <&dmac0 0x268a>, 288 <&dmac1 0x2689>, <&dmac1 0x268a>, 289 <&dmac2 0x2689>, <&dmac2 0x268a>; 290 dma-names = "rx", "tx", "rx", "tx", "rx", "tx"; 291 power-domains = <&cpg>; 292 #address-cells = <1>; 293 #size-cells = <0>; 294 status = "disabled"; 295 }; 296 297 canfd: can@80040000 { 298 compatible = "renesas,r9a09g077-canfd"; 299 reg = <0 0x80040000 0 0x20000>; 300 interrupts = <GIC_SPI 633 IRQ_TYPE_LEVEL_HIGH>, 301 <GIC_SPI 632 IRQ_TYPE_LEVEL_HIGH>, 302 <GIC_SPI 627 IRQ_TYPE_LEVEL_HIGH>, 303 <GIC_SPI 628 IRQ_TYPE_LEVEL_HIGH>, 304 <GIC_SPI 626 IRQ_TYPE_LEVEL_HIGH>, 305 <GIC_SPI 630 IRQ_TYPE_LEVEL_HIGH>, 306 <GIC_SPI 631 IRQ_TYPE_LEVEL_HIGH>, 307 <GIC_SPI 629 IRQ_TYPE_LEVEL_HIGH>; 308 interrupt-names = "g_err", "g_recc", 309 "ch0_err", "ch0_rec", "ch0_trx", 310 "ch1_err", "ch1_rec", "ch1_trx"; 311 clocks = <&cpg CPG_MOD 310>, 312 <&cpg CPG_CORE R9A09G077_CLK_PCLKH>, 313 <&cpg CPG_CORE R9A09G077_PCLKCAN>; 314 clock-names = "fck", "ram_clk", "can_clk"; 315 assigned-clocks = <&cpg CPG_CORE R9A09G077_PCLKCAN>; 316 assigned-clock-rates = <80000000>; 317 power-domains = <&cpg>; 318 status = "disabled"; 319 320 channel0 { 321 status = "disabled"; 322 }; 323 channel1 { 324 status = "disabled"; 325 }; 326 }; 327 328 wdt0: watchdog@80082000 { 329 compatible = "renesas,r9a09g077-wdt"; 330 reg = <0 0x80082000 0 0x400>, 331 <0 0x81295100 0 0x04>; 332 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; 333 clock-names = "pclk"; 334 power-domains = <&cpg>; 335 status = "disabled"; 336 }; 337 338 wdt1: watchdog@80082400 { 339 compatible = "renesas,r9a09g077-wdt"; 340 reg = <0 0x80082400 0 0x400>, 341 <0 0x81295104 0 0x04>; 342 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; 343 clock-names = "pclk"; 344 power-domains = <&cpg>; 345 status = "disabled"; 346 }; 347 348 wdt2: watchdog@80082800 { 349 compatible = "renesas,r9a09g077-wdt"; 350 reg = <0 0x80082800 0 0x400>, 351 <0 0x81295108 0 0x04>; 352 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; 353 clock-names = "pclk"; 354 power-domains = <&cpg>; 355 status = "disabled"; 356 }; 357 358 wdt3: watchdog@80082c00 { 359 compatible = "renesas,r9a09g077-wdt"; 360 reg = <0 0x80082c00 0 0x400>, 361 <0 0x8129510c 0 0x04>; 362 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; 363 clock-names = "pclk"; 364 power-domains = <&cpg>; 365 status = "disabled"; 366 }; 367 368 wdt4: watchdog@80083000 { 369 compatible = "renesas,r9a09g077-wdt"; 370 reg = <0 0x80083000 0 0x400>, 371 <0 0x81295110 0 0x04>; 372 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; 373 clock-names = "pclk"; 374 power-domains = <&cpg>; 375 status = "disabled"; 376 }; 377 378 wdt5: watchdog@80083400 { 379 compatible = "renesas,r9a09g077-wdt"; 380 reg = <0 0x80083400 0 0x400>, 381 <0 0x81295114 0 0x04>; 382 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>; 383 clock-names = "pclk"; 384 power-domains = <&cpg>; 385 status = "disabled"; 386 }; 387 388 tsu: thermal@80086000 { 389 compatible = "renesas,r9a09g077-tsu"; 390 reg = <0 0x80086000 0 0x1000>; 391 interrupts = <GIC_SPI 713 IRQ_TYPE_EDGE_RISING>, 392 <GIC_SPI 714 IRQ_TYPE_LEVEL_HIGH>; 393 interrupt-names = "adi", "adcmpi"; 394 clocks = <&cpg CPG_MOD 307>; 395 power-domains = <&cpg>; 396 #thermal-sensor-cells = <0>; 397 }; 398 399 i2c0: i2c@80088000 { 400 compatible = "renesas,riic-r9a09g077"; 401 reg = <0 0x80088000 0 0x400>; 402 interrupts = <GIC_SPI 614 IRQ_TYPE_LEVEL_HIGH>, 403 <GIC_SPI 615 IRQ_TYPE_EDGE_RISING>, 404 <GIC_SPI 616 IRQ_TYPE_EDGE_RISING>, 405 <GIC_SPI 617 IRQ_TYPE_LEVEL_HIGH>; 406 interrupt-names = "eei", "rxi", "txi", "tei"; 407 clocks = <&cpg CPG_MOD 100>; 408 power-domains = <&cpg>; 409 #address-cells = <1>; 410 #size-cells = <0>; 411 status = "disabled"; 412 }; 413 414 i2c1: i2c@80088400 { 415 compatible = "renesas,riic-r9a09g077"; 416 reg = <0 0x80088400 0 0x400>; 417 interrupts = <GIC_SPI 618 IRQ_TYPE_LEVEL_HIGH>, 418 <GIC_SPI 619 IRQ_TYPE_EDGE_RISING>, 419 <GIC_SPI 620 IRQ_TYPE_EDGE_RISING>, 420 <GIC_SPI 621 IRQ_TYPE_LEVEL_HIGH>; 421 interrupt-names = "eei", "rxi", "txi", "tei"; 422 clocks = <&cpg CPG_MOD 101>; 423 power-domains = <&cpg>; 424 #address-cells = <1>; 425 #size-cells = <0>; 426 status = "disabled"; 427 }; 428 429 i2c2: i2c@81008000 { 430 compatible = "renesas,riic-r9a09g077"; 431 reg = <0 0x81008000 0 0x400>; 432 interrupts = <GIC_SPI 622 IRQ_TYPE_LEVEL_HIGH>, 433 <GIC_SPI 623 IRQ_TYPE_EDGE_RISING>, 434 <GIC_SPI 624 IRQ_TYPE_EDGE_RISING>, 435 <GIC_SPI 625 IRQ_TYPE_LEVEL_HIGH>; 436 interrupt-names = "eei", "rxi", "txi", "tei"; 437 clocks = <&cpg CPG_MOD 601>; 438 power-domains = <&cpg>; 439 #address-cells = <1>; 440 #size-cells = <0>; 441 status = "disabled"; 442 }; 443 444 dmac0: dma-controller@800c0000 { 445 compatible = "renesas,r9a09g077-dmac"; 446 reg = <0 0x800c0000 0 0x1000>; 447 interrupts = <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>, 448 <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>, 449 <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>, 450 <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>, 451 <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>, 452 <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>, 453 <GIC_SPI 38 IRQ_TYPE_EDGE_RISING>, 454 <GIC_SPI 39 IRQ_TYPE_EDGE_RISING>, 455 <GIC_SPI 40 IRQ_TYPE_EDGE_RISING>, 456 <GIC_SPI 41 IRQ_TYPE_EDGE_RISING>, 457 <GIC_SPI 42 IRQ_TYPE_EDGE_RISING>, 458 <GIC_SPI 43 IRQ_TYPE_EDGE_RISING>, 459 <GIC_SPI 44 IRQ_TYPE_EDGE_RISING>, 460 <GIC_SPI 45 IRQ_TYPE_EDGE_RISING>, 461 <GIC_SPI 46 IRQ_TYPE_EDGE_RISING>, 462 <GIC_SPI 47 IRQ_TYPE_EDGE_RISING>; 463 interrupt-names = "ch0", "ch1", "ch2", "ch3", 464 "ch4", "ch5", "ch6", "ch7", 465 "ch8", "ch9", "ch10", "ch11", 466 "ch12", "ch13", "ch14", "ch15"; 467 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>; 468 power-domains = <&cpg>; 469 #dma-cells = <1>; 470 dma-channels = <16>; 471 renesas,icu = <&icu 0>; 472 }; 473 474 dmac1: dma-controller@800c1000 { 475 compatible = "renesas,r9a09g077-dmac"; 476 reg = <0 0x800c1000 0 0x1000>; 477 interrupts = <GIC_SPI 48 IRQ_TYPE_EDGE_RISING>, 478 <GIC_SPI 49 IRQ_TYPE_EDGE_RISING>, 479 <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>, 480 <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>, 481 <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>, 482 <GIC_SPI 53 IRQ_TYPE_EDGE_RISING>, 483 <GIC_SPI 54 IRQ_TYPE_EDGE_RISING>, 484 <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>, 485 <GIC_SPI 56 IRQ_TYPE_EDGE_RISING>, 486 <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>, 487 <GIC_SPI 58 IRQ_TYPE_EDGE_RISING>, 488 <GIC_SPI 59 IRQ_TYPE_EDGE_RISING>, 489 <GIC_SPI 60 IRQ_TYPE_EDGE_RISING>, 490 <GIC_SPI 61 IRQ_TYPE_EDGE_RISING>, 491 <GIC_SPI 62 IRQ_TYPE_EDGE_RISING>, 492 <GIC_SPI 63 IRQ_TYPE_EDGE_RISING>; 493 interrupt-names = "ch0", "ch1", "ch2", "ch3", 494 "ch4", "ch5", "ch6", "ch7", 495 "ch8", "ch9", "ch10", "ch11", 496 "ch12", "ch13", "ch14", "ch15"; 497 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>; 498 power-domains = <&cpg>; 499 #dma-cells = <1>; 500 dma-channels = <16>; 501 renesas,icu = <&icu 1>; 502 }; 503 504 dmac2: dma-controller@800c2000 { 505 compatible = "renesas,r9a09g077-dmac"; 506 reg = <0 0x800c2000 0 0x1000>; 507 interrupts = <GIC_SPI 64 IRQ_TYPE_EDGE_RISING>, 508 <GIC_SPI 65 IRQ_TYPE_EDGE_RISING>, 509 <GIC_SPI 66 IRQ_TYPE_EDGE_RISING>, 510 <GIC_SPI 67 IRQ_TYPE_EDGE_RISING>, 511 <GIC_SPI 68 IRQ_TYPE_EDGE_RISING>, 512 <GIC_SPI 69 IRQ_TYPE_EDGE_RISING>, 513 <GIC_SPI 70 IRQ_TYPE_EDGE_RISING>, 514 <GIC_SPI 71 IRQ_TYPE_EDGE_RISING>, 515 <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>, 516 <GIC_SPI 73 IRQ_TYPE_EDGE_RISING>, 517 <GIC_SPI 74 IRQ_TYPE_EDGE_RISING>, 518 <GIC_SPI 75 IRQ_TYPE_EDGE_RISING>, 519 <GIC_SPI 76 IRQ_TYPE_EDGE_RISING>, 520 <GIC_SPI 77 IRQ_TYPE_EDGE_RISING>, 521 <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>, 522 <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>; 523 interrupt-names = "ch0", "ch1", "ch2", "ch3", 524 "ch4", "ch5", "ch6", "ch7", 525 "ch8", "ch9", "ch10", "ch11", 526 "ch12", "ch13", "ch14", "ch15"; 527 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKH>; 528 power-domains = <&cpg>; 529 #dma-cells = <1>; 530 dma-channels = <16>; 531 renesas,icu = <&icu 2>; 532 }; 533 534 gmac0: ethernet@80100000 { 535 compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; 536 reg = <0 0x80100000 0 0x10000>; 537 interrupts = <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 549 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>, 550 <GIC_SPI 503 IRQ_TYPE_LEVEL_HIGH>, 551 <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 552 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 553 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 554 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 555 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 556 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 557 "rx-queue-0", "rx-queue-1", "rx-queue-2", 558 "rx-queue-3", "rx-queue-4", "rx-queue-5", 559 "rx-queue-6", "rx-queue-7", "tx-queue-0", 560 "tx-queue-1", "tx-queue-2", "tx-queue-3", 561 "tx-queue-4", "tx-queue-5", "tx-queue-6", 562 "tx-queue-7"; 563 clocks = <&cpg CPG_MOD 400>, 564 <&cpg CPG_CORE R9A09G077_CLK_PCLKH>, 565 <&cpg CPG_CORE R9A09G077_ETCLKB>; 566 clock-names = "stmmaceth", "pclk", "tx"; 567 resets = <&cpg 400>, <&cpg 401>; 568 reset-names = "stmmaceth", "ahb"; 569 power-domains = <&cpg>; 570 snps,multicast-filter-bins = <256>; 571 snps,perfect-filter-entries = <32>; 572 rx-fifo-depth = <8192>; 573 tx-fifo-depth = <8192>; 574 snps,fixed-burst; 575 snps,no-pbl-x8; 576 snps,force_thresh_dma_mode; 577 snps,axi-config = <&stmmac_axi_setup>; 578 snps,mtl-rx-config = <&mtl_rx_setup0>; 579 snps,mtl-tx-config = <&mtl_tx_setup0>; 580 snps,txpbl = <16>; 581 snps,rxpbl = <16>; 582 status = "disabled"; 583 584 mdio0: mdio { 585 compatible = "snps,dwmac-mdio"; 586 #address-cells = <1>; 587 #size-cells = <0>; 588 }; 589 590 mtl_rx_setup0: rx-queues-config { 591 snps,rx-queues-to-use = <8>; 592 snps,rx-sched-sp; 593 594 queue0 { 595 snps,dcb-algorithm; 596 snps,priority = <0x1>; 597 snps,map-to-dma-channel = <0>; 598 }; 599 600 queue1 { 601 snps,dcb-algorithm; 602 snps,priority = <0x2>; 603 snps,map-to-dma-channel = <1>; 604 }; 605 606 queue2 { 607 snps,dcb-algorithm; 608 snps,priority = <0x4>; 609 snps,map-to-dma-channel = <2>; 610 }; 611 612 queue3 { 613 snps,dcb-algorithm; 614 snps,priority = <0x8>; 615 snps,map-to-dma-channel = <3>; 616 }; 617 618 queue4 { 619 snps,dcb-algorithm; 620 snps,priority = <0x10>; 621 snps,map-to-dma-channel = <4>; 622 }; 623 624 queue5 { 625 snps,dcb-algorithm; 626 snps,priority = <0x20>; 627 snps,map-to-dma-channel = <5>; 628 }; 629 630 queue6 { 631 snps,dcb-algorithm; 632 snps,priority = <0x40>; 633 snps,map-to-dma-channel = <6>; 634 }; 635 636 queue7 { 637 snps,dcb-algorithm; 638 snps,priority = <0x80>; 639 snps,map-to-dma-channel = <7>; 640 }; 641 }; 642 643 mtl_tx_setup0: tx-queues-config { 644 snps,tx-queues-to-use = <8>; 645 646 queue0 { 647 snps,dcb-algorithm; 648 }; 649 650 queue1 { 651 snps,dcb-algorithm; 652 }; 653 654 queue2 { 655 snps,dcb-algorithm; 656 }; 657 658 queue3 { 659 snps,dcb-algorithm; 660 }; 661 662 queue4 { 663 snps,dcb-algorithm; 664 }; 665 666 queue5 { 667 snps,dcb-algorithm; 668 }; 669 670 queue6 { 671 snps,dcb-algorithm; 672 }; 673 674 queue7 { 675 snps,dcb-algorithm; 676 }; 677 }; 678 }; 679 680 gmac1: ethernet@92000000 { 681 compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; 682 reg = <0 0x92000000 0 0x10000>; 683 interrupts = <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH>, 685 <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH>, 686 <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH>, 687 <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH>, 688 <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>, 689 <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH>, 690 <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH>, 691 <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>, 692 <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH>, 693 <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH>, 694 <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH>, 695 <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH>, 696 <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH>, 697 <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH>, 698 <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH>, 699 <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH>, 700 <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH>, 701 <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH>; 702 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 703 "rx-queue-0", "rx-queue-1", "rx-queue-2", 704 "rx-queue-3", "rx-queue-4", "rx-queue-5", 705 "rx-queue-6", "rx-queue-7", "tx-queue-0", 706 "tx-queue-1", "tx-queue-2", "tx-queue-3", 707 "tx-queue-4", "tx-queue-5", "tx-queue-6", 708 "tx-queue-7"; 709 clocks = <&cpg CPG_MOD 416>, 710 <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>, 711 <&cpg CPG_CORE R9A09G077_ETCLKB>; 712 clock-names = "stmmaceth", "pclk", "tx"; 713 resets = <&cpg 416>, <&cpg 417>; 714 reset-names = "stmmaceth", "ahb"; 715 power-domains = <&cpg>; 716 snps,multicast-filter-bins = <256>; 717 snps,perfect-filter-entries = <32>; 718 rx-fifo-depth = <8192>; 719 tx-fifo-depth = <8192>; 720 snps,fixed-burst; 721 snps,no-pbl-x8; 722 snps,force_thresh_dma_mode; 723 snps,axi-config = <&stmmac_axi_setup>; 724 snps,mtl-rx-config = <&mtl_rx_setup1>; 725 snps,mtl-tx-config = <&mtl_tx_setup1>; 726 snps,txpbl = <16>; 727 snps,rxpbl = <16>; 728 status = "disabled"; 729 730 mdio1: mdio { 731 compatible = "snps,dwmac-mdio"; 732 #address-cells = <1>; 733 #size-cells = <0>; 734 }; 735 736 mtl_rx_setup1: rx-queues-config { 737 snps,rx-queues-to-use = <8>; 738 snps,rx-sched-sp; 739 740 queue0 { 741 snps,dcb-algorithm; 742 snps,priority = <0x1>; 743 snps,map-to-dma-channel = <0>; 744 }; 745 746 queue1 { 747 snps,dcb-algorithm; 748 snps,priority = <0x2>; 749 snps,map-to-dma-channel = <1>; 750 }; 751 752 queue2 { 753 snps,dcb-algorithm; 754 snps,priority = <0x4>; 755 snps,map-to-dma-channel = <2>; 756 }; 757 758 queue3 { 759 snps,dcb-algorithm; 760 snps,priority = <0x8>; 761 snps,map-to-dma-channel = <3>; 762 }; 763 764 queue4 { 765 snps,dcb-algorithm; 766 snps,priority = <0x10>; 767 snps,map-to-dma-channel = <4>; 768 }; 769 770 queue5 { 771 snps,dcb-algorithm; 772 snps,priority = <0x20>; 773 snps,map-to-dma-channel = <5>; 774 }; 775 776 queue6 { 777 snps,dcb-algorithm; 778 snps,priority = <0x40>; 779 snps,map-to-dma-channel = <6>; 780 }; 781 782 queue7 { 783 snps,dcb-algorithm; 784 snps,priority = <0x80>; 785 snps,map-to-dma-channel = <7>; 786 }; 787 }; 788 789 mtl_tx_setup1: tx-queues-config { 790 snps,tx-queues-to-use = <8>; 791 792 queue0 { 793 snps,dcb-algorithm; 794 }; 795 796 queue1 { 797 snps,dcb-algorithm; 798 }; 799 800 queue2 { 801 snps,dcb-algorithm; 802 }; 803 804 queue3 { 805 snps,dcb-algorithm; 806 }; 807 808 queue4 { 809 snps,dcb-algorithm; 810 }; 811 812 queue5 { 813 snps,dcb-algorithm; 814 }; 815 816 queue6 { 817 snps,dcb-algorithm; 818 }; 819 820 queue7 { 821 snps,dcb-algorithm; 822 }; 823 }; 824 }; 825 826 gmac2: ethernet@92010000 { 827 compatible = "renesas,r9a09g077-gbeth", "snps,dwmac-5.20"; 828 reg = <0 0x92010000 0 0x10000>; 829 interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>, 830 <GIC_SPI 538 IRQ_TYPE_LEVEL_HIGH>, 831 <GIC_SPI 537 IRQ_TYPE_LEVEL_HIGH>, 832 <GIC_SPI 547 IRQ_TYPE_LEVEL_HIGH>, 833 <GIC_SPI 548 IRQ_TYPE_LEVEL_HIGH>, 834 <GIC_SPI 549 IRQ_TYPE_LEVEL_HIGH>, 835 <GIC_SPI 550 IRQ_TYPE_LEVEL_HIGH>, 836 <GIC_SPI 551 IRQ_TYPE_LEVEL_HIGH>, 837 <GIC_SPI 552 IRQ_TYPE_LEVEL_HIGH>, 838 <GIC_SPI 553 IRQ_TYPE_LEVEL_HIGH>, 839 <GIC_SPI 554 IRQ_TYPE_LEVEL_HIGH>, 840 <GIC_SPI 539 IRQ_TYPE_LEVEL_HIGH>, 841 <GIC_SPI 540 IRQ_TYPE_LEVEL_HIGH>, 842 <GIC_SPI 541 IRQ_TYPE_LEVEL_HIGH>, 843 <GIC_SPI 542 IRQ_TYPE_LEVEL_HIGH>, 844 <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 845 <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 846 <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>, 847 <GIC_SPI 546 IRQ_TYPE_LEVEL_HIGH>; 848 interrupt-names = "macirq", "eth_wake_irq", "eth_lpi", 849 "rx-queue-0", "rx-queue-1", "rx-queue-2", 850 "rx-queue-3", "rx-queue-4", "rx-queue-5", 851 "rx-queue-6", "rx-queue-7", "tx-queue-0", 852 "tx-queue-1", "tx-queue-2", "tx-queue-3", 853 "tx-queue-4", "tx-queue-5", "tx-queue-6", 854 "tx-queue-7"; 855 clocks = <&cpg CPG_MOD 417>, 856 <&cpg CPG_CORE R9A09G077_CLK_PCLKAH>, 857 <&cpg CPG_CORE R9A09G077_ETCLKB>; 858 clock-names = "stmmaceth", "pclk", "tx"; 859 resets = <&cpg 418>, <&cpg 419>; 860 reset-names = "stmmaceth", "ahb"; 861 power-domains = <&cpg>; 862 snps,multicast-filter-bins = <256>; 863 snps,perfect-filter-entries = <32>; 864 rx-fifo-depth = <8192>; 865 tx-fifo-depth = <8192>; 866 snps,fixed-burst; 867 snps,no-pbl-x8; 868 snps,force_thresh_dma_mode; 869 snps,axi-config = <&stmmac_axi_setup>; 870 snps,mtl-rx-config = <&mtl_rx_setup2>; 871 snps,mtl-tx-config = <&mtl_tx_setup2>; 872 snps,txpbl = <16>; 873 snps,rxpbl = <16>; 874 status = "disabled"; 875 876 mdio2: mdio { 877 compatible = "snps,dwmac-mdio"; 878 #address-cells = <1>; 879 #size-cells = <0>; 880 }; 881 882 mtl_rx_setup2: rx-queues-config { 883 snps,rx-queues-to-use = <8>; 884 snps,rx-sched-sp; 885 886 queue0 { 887 snps,dcb-algorithm; 888 snps,priority = <0x1>; 889 snps,map-to-dma-channel = <0>; 890 }; 891 892 queue1 { 893 snps,dcb-algorithm; 894 snps,priority = <0x2>; 895 snps,map-to-dma-channel = <1>; 896 }; 897 898 queue2 { 899 snps,dcb-algorithm; 900 snps,priority = <0x4>; 901 snps,map-to-dma-channel = <2>; 902 }; 903 904 queue3 { 905 snps,dcb-algorithm; 906 snps,priority = <0x8>; 907 snps,map-to-dma-channel = <3>; 908 }; 909 910 queue4 { 911 snps,dcb-algorithm; 912 snps,priority = <0x10>; 913 snps,map-to-dma-channel = <4>; 914 }; 915 916 queue5 { 917 snps,dcb-algorithm; 918 snps,priority = <0x20>; 919 snps,map-to-dma-channel = <5>; 920 }; 921 922 queue6 { 923 snps,dcb-algorithm; 924 snps,priority = <0x40>; 925 snps,map-to-dma-channel = <6>; 926 }; 927 928 queue7 { 929 snps,dcb-algorithm; 930 snps,priority = <0x80>; 931 snps,map-to-dma-channel = <7>; 932 }; 933 }; 934 935 mtl_tx_setup2: tx-queues-config { 936 snps,tx-queues-to-use = <8>; 937 938 queue0 { 939 snps,dcb-algorithm; 940 }; 941 942 queue1 { 943 snps,dcb-algorithm; 944 }; 945 946 queue2 { 947 snps,dcb-algorithm; 948 }; 949 950 queue3 { 951 snps,dcb-algorithm; 952 }; 953 954 queue4 { 955 snps,dcb-algorithm; 956 }; 957 958 queue5 { 959 snps,dcb-algorithm; 960 }; 961 962 queue6 { 963 snps,dcb-algorithm; 964 }; 965 966 queue7 { 967 snps,dcb-algorithm; 968 }; 969 }; 970 }; 971 972 ethss: ethss@80110000 { 973 compatible = "renesas,r9a09g077-miic"; 974 reg = <0 0x80110000 0 0x10000>; 975 clocks = <&cpg CPG_CORE R9A09G077_ETCLKE>, 976 <&cpg CPG_CORE R9A09G077_ETCLKB>, 977 <&cpg CPG_CORE R9A09G077_ETCLKD>, 978 <&cpg CPG_MOD 403>; 979 clock-names = "mii_ref", "rgmii_ref", "rmii_ref", "hclk"; 980 resets = <&cpg 405>, <&cpg 406>; 981 reset-names = "rst", "crst"; 982 power-domains = <&cpg>; 983 status = "disabled"; 984 985 #address-cells = <1>; 986 #size-cells = <0>; 987 988 mii_conv0: mii-conv@0 { 989 reg = <0>; 990 status = "disabled"; 991 }; 992 993 mii_conv1: mii-conv@1 { 994 reg = <1>; 995 status = "disabled"; 996 }; 997 998 mii_conv2: mii-conv@2 { 999 reg = <2>; 1000 status = "disabled"; 1001 }; 1002 1003 mii_conv3: mii-conv@3 { 1004 reg = <3>; 1005 status = "disabled"; 1006 }; 1007 }; 1008 1009 cpg: clock-controller@80280000 { 1010 compatible = "renesas,r9a09g077-cpg-mssr"; 1011 reg = <0 0x80280000 0 0x10000>, 1012 <0 0x81280000 0 0x10000>; 1013 clocks = <&extal_clk>; 1014 clock-names = "extal"; 1015 #clock-cells = <2>; 1016 #reset-cells = <1>; 1017 #power-domain-cells = <0>; 1018 }; 1019 1020 icu: interrupt-controller@802a0000 { 1021 compatible = "renesas,r9a09g077-icu"; 1022 reg = <0 0x802a0000 0 0x10000>, 1023 <0 0x812a0000 0 0x10000>; 1024 #interrupt-cells = <2>; 1025 #address-cells = <0>; 1026 interrupt-controller; 1027 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>, 1028 <GIC_SPI 1 IRQ_TYPE_EDGE_RISING>, 1029 <GIC_SPI 2 IRQ_TYPE_EDGE_RISING>, 1030 <GIC_SPI 3 IRQ_TYPE_EDGE_RISING>, 1031 <GIC_SPI 4 IRQ_TYPE_EDGE_RISING>, 1032 <GIC_SPI 5 IRQ_TYPE_EDGE_RISING>, 1033 <GIC_SPI 6 IRQ_TYPE_EDGE_RISING>, 1034 <GIC_SPI 7 IRQ_TYPE_EDGE_RISING>, 1035 <GIC_SPI 8 IRQ_TYPE_EDGE_RISING>, 1036 <GIC_SPI 9 IRQ_TYPE_EDGE_RISING>, 1037 <GIC_SPI 10 IRQ_TYPE_EDGE_RISING>, 1038 <GIC_SPI 11 IRQ_TYPE_EDGE_RISING>, 1039 <GIC_SPI 12 IRQ_TYPE_EDGE_RISING>, 1040 <GIC_SPI 13 IRQ_TYPE_EDGE_RISING>, 1041 <GIC_SPI 14 IRQ_TYPE_EDGE_RISING>, 1042 <GIC_SPI 15 IRQ_TYPE_EDGE_RISING>, 1043 <GIC_SPI 16 IRQ_TYPE_EDGE_RISING>, 1044 <GIC_SPI 17 IRQ_TYPE_EDGE_RISING>, 1045 <GIC_SPI 18 IRQ_TYPE_EDGE_RISING>, 1046 <GIC_SPI 19 IRQ_TYPE_EDGE_RISING>, 1047 <GIC_SPI 20 IRQ_TYPE_EDGE_RISING>, 1048 <GIC_SPI 21 IRQ_TYPE_EDGE_RISING>, 1049 <GIC_SPI 22 IRQ_TYPE_EDGE_RISING>, 1050 <GIC_SPI 23 IRQ_TYPE_EDGE_RISING>, 1051 <GIC_SPI 24 IRQ_TYPE_EDGE_RISING>, 1052 <GIC_SPI 25 IRQ_TYPE_EDGE_RISING>, 1053 <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>, 1054 <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>, 1055 <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>, 1056 <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>, 1057 <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>, 1058 <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>, 1059 <GIC_SPI 406 IRQ_TYPE_EDGE_RISING>, 1060 <GIC_SPI 407 IRQ_TYPE_EDGE_RISING>, 1061 <GIC_SPI 408 IRQ_TYPE_EDGE_RISING>, 1062 <GIC_SPI 409 IRQ_TYPE_EDGE_RISING>, 1063 <GIC_SPI 410 IRQ_TYPE_EDGE_RISING>, 1064 <GIC_SPI 411 IRQ_TYPE_EDGE_RISING>, 1065 <GIC_SPI 412 IRQ_TYPE_EDGE_RISING>, 1066 <GIC_SPI 413 IRQ_TYPE_EDGE_RISING>, 1067 <GIC_SPI 414 IRQ_TYPE_EDGE_RISING>, 1068 <GIC_SPI 415 IRQ_TYPE_EDGE_RISING>, 1069 <GIC_SPI 416 IRQ_TYPE_EDGE_RISING>, 1070 <GIC_SPI 417 IRQ_TYPE_EDGE_RISING>, 1071 <GIC_SPI 418 IRQ_TYPE_EDGE_RISING>; 1072 interrupt-names = "intcpu0", "intcpu1", "intcpu2", 1073 "intcpu3", "intcpu4", "intcpu5", 1074 "intcpu6", "intcpu7", "intcpu8", 1075 "intcpu9", "intcpu10", "intcpu11", 1076 "intcpu12", "intcpu13", "intcpu14", 1077 "intcpu15", 1078 "irq0", "irq1", "irq2", "irq3", 1079 "irq4", "irq5", "irq6", "irq7", 1080 "irq8", "irq9", "irq10", "irq11", 1081 "irq12", "irq13", "irq14", "irq15", 1082 "sei", 1083 "ca55-err0", "ca55-err1", 1084 "cr520-err0", "cr520-err1", 1085 "cr521-err0", "cr521-err1", 1086 "peri-err0", "peri-err1", 1087 "dsmif-err0", "dsmif-err1", 1088 "encif-err0", "encif-err1"; 1089 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 1090 power-domains = <&cpg>; 1091 }; 1092 1093 pinctrl: pinctrl@802c0000 { 1094 compatible = "renesas,r9a09g077-pinctrl"; 1095 reg = <0 0x802c0000 0 0x10000>, 1096 <0 0x812c0000 0 0x10000>, 1097 <0 0x802b0000 0 0x10000>; 1098 reg-names = "nsr", "srs", "srn"; 1099 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKM>; 1100 gpio-controller; 1101 #gpio-cells = <2>; 1102 gpio-ranges = <&pinctrl 0 0 288>; 1103 #interrupt-cells = <2>; 1104 interrupt-controller; 1105 interrupt-parent = <&icu>; 1106 power-domains = <&cpg>; 1107 }; 1108 1109 gic: interrupt-controller@83000000 { 1110 compatible = "arm,gic-v3"; 1111 reg = <0x0 0x83000000 0 0x40000>, 1112 <0x0 0x83040000 0 0x160000>; 1113 #interrupt-cells = <3>; 1114 #address-cells = <0>; 1115 interrupt-controller; 1116 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 1117 }; 1118 1119 adc0: adc@90014000 { 1120 compatible = "renesas,r9a09g077-adc"; 1121 reg = <0 0x90014000 0 0x400>; 1122 interrupts = <GIC_SPI 698 IRQ_TYPE_EDGE_RISING>, 1123 <GIC_SPI 699 IRQ_TYPE_EDGE_RISING>, 1124 <GIC_SPI 700 IRQ_TYPE_EDGE_RISING>, 1125 <GIC_SPI 701 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 851 IRQ_TYPE_EDGE_RISING>, 1128 <GIC_SPI 852 IRQ_TYPE_EDGE_RISING>; 1129 interrupt-names = "adi", "gbadi", "gcadi", 1130 "cmpai", "cmpbi", "wcmpm", "wcmpum"; 1131 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, 1132 <&cpg CPG_MOD 206>; 1133 clock-names = "adclk", "pclk"; 1134 power-domains = <&cpg>; 1135 #address-cells = <1>; 1136 #size-cells = <0>; 1137 #io-channel-cells = <1>; 1138 status = "disabled"; 1139 }; 1140 1141 adc1: adc@90014400 { 1142 compatible = "renesas,r9a09g077-adc"; 1143 reg = <0 0x90014400 0 0x400>; 1144 interrupts = <GIC_SPI 703 IRQ_TYPE_EDGE_RISING>, 1145 <GIC_SPI 704 IRQ_TYPE_EDGE_RISING>, 1146 <GIC_SPI 705 IRQ_TYPE_EDGE_RISING>, 1147 <GIC_SPI 706 IRQ_TYPE_LEVEL_HIGH>, 1148 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 1149 <GIC_SPI 853 IRQ_TYPE_EDGE_RISING>, 1150 <GIC_SPI 854 IRQ_TYPE_EDGE_RISING>; 1151 interrupt-names = "adi", "gbadi", "gcadi", 1152 "cmpai", "cmpbi", "wcmpm", "wcmpum"; 1153 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, 1154 <&cpg CPG_MOD 207>; 1155 clock-names = "adclk", "pclk"; 1156 power-domains = <&cpg>; 1157 #address-cells = <1>; 1158 #size-cells = <0>; 1159 #io-channel-cells = <1>; 1160 status = "disabled"; 1161 }; 1162 1163 adc2: adc@80008000 { 1164 compatible = "renesas,r9a09g077-adc"; 1165 reg = <0 0x80008000 0 0x400>; 1166 interrupts = <GIC_SPI 708 IRQ_TYPE_EDGE_RISING>, 1167 <GIC_SPI 709 IRQ_TYPE_EDGE_RISING>, 1168 <GIC_SPI 710 IRQ_TYPE_EDGE_RISING>, 1169 <GIC_SPI 711 IRQ_TYPE_LEVEL_HIGH>, 1170 <GIC_SPI 712 IRQ_TYPE_LEVEL_HIGH>, 1171 <GIC_SPI 855 IRQ_TYPE_EDGE_RISING>, 1172 <GIC_SPI 856 IRQ_TYPE_EDGE_RISING>; 1173 interrupt-names = "adi", "gbadi", "gcadi", 1174 "cmpai", "cmpbi", "wcmpm", "wcmpum"; 1175 clocks = <&cpg CPG_CORE R9A09G077_CLK_PCLKL>, 1176 <&cpg CPG_MOD 225>; 1177 clock-names = "adclk", "pclk"; 1178 power-domains = <&cpg>; 1179 #address-cells = <1>; 1180 #size-cells = <0>; 1181 #io-channel-cells = <1>; 1182 status = "disabled"; 1183 }; 1184 1185 ohci: usb@92040000 { 1186 compatible = "generic-ohci"; 1187 reg = <0 0x92040000 0 0x100>; 1188 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1189 clocks = <&cpg CPG_MOD 408>; 1190 phys = <&usb2_phy 1>; 1191 phy-names = "usb"; 1192 power-domains = <&cpg>; 1193 status = "disabled"; 1194 }; 1195 1196 ehci: usb@92040100 { 1197 compatible = "generic-ehci"; 1198 reg = <0 0x92040100 0 0x100>; 1199 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1200 clocks = <&cpg CPG_MOD 408>; 1201 phys = <&usb2_phy 2>; 1202 phy-names = "usb"; 1203 companion = <&ohci>; 1204 power-domains = <&cpg>; 1205 status = "disabled"; 1206 }; 1207 1208 usb2_phy: usb-phy@92040200 { 1209 compatible = "renesas,usb2-phy-r9a09g077"; 1210 reg = <0 0x92040200 0 0x700>; 1211 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1212 clocks = <&cpg CPG_MOD 408>, 1213 <&cpg CPG_CORE R9A09G077_USB_CLK>; 1214 #phy-cells = <1>; 1215 power-domains = <&cpg>; 1216 status = "disabled"; 1217 }; 1218 1219 hsusb: usb@92041000 { 1220 compatible = "renesas,usbhs-r9a09g077"; 1221 reg = <0 0x92041000 0 0x1000>; 1222 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>, 1223 <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1224 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>; 1225 clocks = <&cpg CPG_MOD 408>; 1226 phys = <&usb2_phy 3>; 1227 phy-names = "usb"; 1228 power-domains = <&cpg>; 1229 status = "disabled"; 1230 }; 1231 1232 sdhi0: mmc@92080000 { 1233 compatible = "renesas,sdhi-r9a09g077", 1234 "renesas,sdhi-r9a09g057"; 1235 reg = <0x0 0x92080000 0 0x10000>; 1236 interrupts = <GIC_SPI 782 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 783 IRQ_TYPE_LEVEL_HIGH>; 1238 clocks = <&cpg CPG_MOD 1212>, 1239 <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>; 1240 clock-names = "aclk", "clkh"; 1241 power-domains = <&cpg>; 1242 status = "disabled"; 1243 1244 sdhi0_vqmmc: vqmmc-regulator { 1245 regulator-name = "SDHI0-VQMMC"; 1246 regulator-min-microvolt = <1800000>; 1247 regulator-max-microvolt = <3300000>; 1248 status = "disabled"; 1249 }; 1250 }; 1251 1252 sdhi1: mmc@92090000 { 1253 compatible = "renesas,sdhi-r9a09g077", 1254 "renesas,sdhi-r9a09g057"; 1255 reg = <0x0 0x92090000 0 0x10000>; 1256 interrupts = <GIC_SPI 784 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 785 IRQ_TYPE_LEVEL_HIGH>; 1258 clocks = <&cpg CPG_MOD 1213>, 1259 <&cpg CPG_CORE R9A09G077_SDHI_CLKHS>; 1260 clock-names = "aclk", "clkh"; 1261 power-domains = <&cpg>; 1262 status = "disabled"; 1263 1264 sdhi1_vqmmc: vqmmc-regulator { 1265 regulator-name = "SDHI1-VQMMC"; 1266 regulator-min-microvolt = <1800000>; 1267 regulator-max-microvolt = <3300000>; 1268 status = "disabled"; 1269 }; 1270 }; 1271 }; 1272 1273 stmmac_axi_setup: stmmac-axi-config { 1274 snps,lpi_en; 1275 snps,wr_osr_lmt = <0xf>; 1276 snps,rd_osr_lmt = <0xf>; 1277 snps,blen = <16 8 4 0 0 0 0>; 1278 }; 1279 1280 thermal-zones { 1281 cpu-thermal { 1282 polling-delay = <1000>; 1283 polling-delay-passive = <250>; 1284 thermal-sensors = <&tsu>; 1285 1286 cooling-maps { 1287 map0 { 1288 trip = <&target>; 1289 cooling-device = <&cpu0 0 1>, <&cpu1 0 1>, 1290 <&cpu2 0 1>, <&cpu3 0 1>; 1291 contribution = <1024>; 1292 }; 1293 }; 1294 1295 trips { 1296 target: trip-point { 1297 temperature = <95000>; 1298 hysteresis = <1000>; 1299 type = "passive"; 1300 }; 1301 1302 sensor_crit: sensor-crit { 1303 temperature = <120000>; 1304 hysteresis = <1000>; 1305 type = "critical"; 1306 }; 1307 }; 1308 }; 1309 }; 1310 1311 timer { 1312 compatible = "arm,armv8-timer"; 1313 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1314 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1315 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1316 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>, 1317 <GIC_PPI 12 IRQ_TYPE_LEVEL_LOW>; 1318 interrupt-names = "sec-phys", "phys", "virt", "hyp-phys", "hyp-virt"; 1319 }; 1320}; 1321