1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) 2025 Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 6/* X1P42100 is heavily based on hamoa, with some meaningful differences */ 7#include "hamoa.dtsi" 8 9/delete-node/ &bwmon_cluster0; 10/delete-node/ &cluster_pd2; 11/delete-node/ &cpu_map_cluster2; 12/delete-node/ &cpu8; 13/delete-node/ &cpu9; 14/delete-node/ &cpu10; 15/delete-node/ &cpu11; 16/delete-node/ &cpu_pd8; 17/delete-node/ &cpu_pd9; 18/delete-node/ &cpu_pd10; 19/delete-node/ &cpu_pd11; 20/delete-node/ &gpu_opp_table; 21/delete-node/ &gpu_speed_bin; 22/delete-node/ &pcie3_phy; 23/delete-node/ &thermal_aoss3; 24/delete-node/ &thermal_cpu2_0_btm; 25/delete-node/ &thermal_cpu2_0_top; 26/delete-node/ &thermal_cpu2_1_btm; 27/delete-node/ &thermal_cpu2_1_top; 28/delete-node/ &thermal_cpu2_2_btm; 29/delete-node/ &thermal_cpu2_2_top; 30/delete-node/ &thermal_cpu2_3_btm; 31/delete-node/ &thermal_cpu2_3_top; 32/delete-node/ &thermal_cpuss2_btm; 33/delete-node/ &thermal_cpuss2_top; 34/delete-node/ &thermal_gpuss_4; 35/delete-node/ &thermal_gpuss_5; 36/delete-node/ &thermal_gpuss_6; 37/delete-node/ &thermal_gpuss_7; 38 39&gcc { 40 compatible = "qcom,x1p42100-gcc", "qcom,x1e80100-gcc"; 41}; 42 43&gmu { 44 compatible = "qcom,adreno-gmu-x145.0", "qcom,adreno-gmu"; 45}; 46 47&gpu { 48 compatible = "qcom,adreno-43030c00", "qcom,adreno"; 49 50 nvmem-cells = <&gpu_speed_bin>; 51 nvmem-cell-names = "speed_bin"; 52 53 gpu_opp_table: opp-table { 54 compatible = "operating-points-v2-adreno", "operating-points-v2"; 55 56 opp-1400000000 { 57 opp-hz = /bits/ 64 <1400000000>; 58 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 59 opp-peak-kBps = <16500000>; 60 qcom,opp-acd-level = <0xa8295ffd>; 61 opp-supported-hw = <0x3>; 62 }; 63 64 opp-1250000000 { 65 opp-hz = /bits/ 64 <1250000000>; 66 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 67 opp-peak-kBps = <16500000>; 68 qcom,opp-acd-level = <0x882a5ffd>; 69 opp-supported-hw = <0x7>; 70 }; 71 72 opp-1107000000 { 73 opp-hz = /bits/ 64 <1107000000>; 74 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 75 opp-peak-kBps = <16500000>; 76 qcom,opp-acd-level = <0x882a5ffd>; 77 opp-supported-hw = <0xf>; 78 }; 79 80 opp-1014000000 { 81 opp-hz = /bits/ 64 <1014000000>; 82 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 83 opp-peak-kBps = <14398438>; 84 qcom,opp-acd-level = <0xa82a5ffd>; 85 opp-supported-hw = <0xf>; 86 }; 87 88 opp-940000000 { 89 opp-hz = /bits/ 64 <940000000>; 90 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 91 opp-peak-kBps = <14398438>; 92 qcom,opp-acd-level = <0xa82a5ffd>; 93 opp-supported-hw = <0xf>; 94 }; 95 96 opp-825000000 { 97 opp-hz = /bits/ 64 <825000000>; 98 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 99 opp-peak-kBps = <12449219>; 100 qcom,opp-acd-level = <0x882b5ffd>; 101 opp-supported-hw = <0xf>; 102 }; 103 104 opp-720000000 { 105 opp-hz = /bits/ 64 <720000000>; 106 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 107 opp-peak-kBps = <10687500>; 108 qcom,opp-acd-level = <0xa82c5ffd>; 109 opp-supported-hw = <0xf>; 110 }; 111 112 opp-666000000-0 { 113 opp-hz = /bits/ 64 <666000000>; 114 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 115 opp-peak-kBps = <8171875>; 116 qcom,opp-acd-level = <0xa82d5ffd>; 117 opp-supported-hw = <0xf>; 118 }; 119 120 /* Only applicable for SKUs which has 666Mhz as Fmax */ 121 opp-666000000-1 { 122 opp-hz = /bits/ 64 <666000000>; 123 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 124 opp-peak-kBps = <16500000>; 125 qcom,opp-acd-level = <0xa82d5ffd>; 126 opp-supported-hw = <0x10>; 127 }; 128 129 opp-550000000 { 130 opp-hz = /bits/ 64 <550000000>; 131 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 132 opp-peak-kBps = <6074219>; 133 qcom,opp-acd-level = <0x882e5ffd>; 134 opp-supported-hw = <0x1f>; 135 }; 136 137 opp-380000000 { 138 opp-hz = /bits/ 64 <380000000>; 139 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 140 opp-peak-kBps = <3000000>; 141 qcom,opp-acd-level = <0xc82f5ffd>; 142 opp-supported-hw = <0x1f>; 143 }; 144 145 opp-280000000 { 146 opp-hz = /bits/ 64 <280000000>; 147 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 148 opp-peak-kBps = <2136719>; 149 qcom,opp-acd-level = <0xc82f5ffd>; 150 opp-supported-hw = <0x1f>; 151 }; 152 }; 153 154}; 155 156&gpucc { 157 compatible = "qcom,x1p42100-gpucc"; 158}; 159 160/* PCIe3 has half the lanes compared to X1E80100 */ 161&pcie3 { 162 num-lanes = <4>; 163}; 164 165&pcie6a_phy { 166 compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; 167}; 168 169&qfprom { 170 gpu_speed_bin: gpu-speed-bin@119 { 171 reg = <0x119 0x2>; 172 bits = <7 9>; 173 }; 174}; 175 176&soc { 177 /* The PCIe3 PHY on X1P42100 uses a different IP block */ 178 pcie3_phy: phy@1bd4000 { 179 compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy"; 180 reg = <0x0 0x01bd4000 0x0 0x2000>, 181 <0x0 0x01bd6000 0x0 0x2000>; 182 183 clocks = <&gcc GCC_PCIE_3_PHY_AUX_CLK>, 184 <&gcc GCC_PCIE_3_CFG_AHB_CLK>, 185 <&tcsr TCSR_PCIE_8L_CLKREF_EN>, 186 <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>, 187 <&gcc GCC_PCIE_3_PIPE_CLK>, 188 <&gcc GCC_PCIE_3_PIPEDIV2_CLK>; 189 clock-names = "aux", 190 "cfg_ahb", 191 "ref", 192 "rchng", 193 "pipe", 194 "pipediv2"; 195 196 resets = <&gcc GCC_PCIE_3_PHY_BCR>, 197 <&gcc GCC_PCIE_3_NOCSR_COM_PHY_BCR>; 198 reset-names = "phy", 199 "phy_nocsr"; 200 201 assigned-clocks = <&gcc GCC_PCIE_3_PHY_RCHNG_CLK>; 202 assigned-clock-rates = <100000000>; 203 204 power-domains = <&gcc GCC_PCIE_3_PHY_GDSC>; 205 206 #clock-cells = <0>; 207 clock-output-names = "pcie3_pipe_clk"; 208 209 #phy-cells = <0>; 210 211 status = "disabled"; 212 }; 213}; 214 215&thermal_camera0 { 216 thermal-sensors = <&tsens2 9>; 217}; 218 219&thermal_camera1 { 220 thermal-sensors = <&tsens2 10>; 221}; 222 223&thermal_gpuss_0 { 224 thermal-sensors = <&tsens2 5>; 225}; 226 227&thermal_gpuss_1 { 228 thermal-sensors = <&tsens2 6>; 229}; 230 231&thermal_gpuss_2 { 232 thermal-sensors = <&tsens2 7>; 233}; 234 235&thermal_gpuss_3 { 236 thermal-sensors = <&tsens2 8>; 237}; 238 239&thermal_nsp0 { 240 thermal-sensors = <&tsens2 1>; 241}; 242 243&thermal_nsp1 { 244 thermal-sensors = <&tsens2 2>; 245}; 246 247&thermal_nsp2 { 248 thermal-sensors = <&tsens2 3>; 249}; 250 251&thermal_nsp3 { 252 thermal-sensors = <&tsens2 4>; 253}; 254 255/* While physically present, this controller is left unconfigured and unused */ 256&tsens3 { 257 status = "disabled"; 258}; 259