1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * sc7280 SoC device tree source 4 * 5 * Copyright (c) 2020-2021, The Linux Foundation. All rights reserved. 6 */ 7#include <dt-bindings/clock/qcom,camcc-sc7280.h> 8#include <dt-bindings/clock/qcom,dispcc-sc7280.h> 9#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 10#include <dt-bindings/clock/qcom,gcc-sc7280.h> 11#include <dt-bindings/clock/qcom,gpucc-sc7280.h> 12#include <dt-bindings/clock/qcom,lpassaudiocc-sc7280.h> 13#include <dt-bindings/clock/qcom,lpasscorecc-sc7280.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/clock/qcom,videocc-sc7280.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/firmware/qcom,scm.h> 18#include <dt-bindings/gpio/gpio.h> 19#include <dt-bindings/interconnect/qcom,icc.h> 20#include <dt-bindings/interconnect/qcom,osm-l3.h> 21#include <dt-bindings/interconnect/qcom,sc7280.h> 22#include <dt-bindings/interrupt-controller/arm-gic.h> 23#include <dt-bindings/mailbox/qcom-ipcc.h> 24#include <dt-bindings/phy/phy-qcom-qmp.h> 25#include <dt-bindings/power/qcom-rpmpd.h> 26#include <dt-bindings/reset/qcom,sdm845-aoss.h> 27#include <dt-bindings/reset/qcom,sdm845-pdc.h> 28#include <dt-bindings/soc/qcom,apr.h> 29#include <dt-bindings/soc/qcom,rpmh-rsc.h> 30#include <dt-bindings/sound/qcom,lpass.h> 31#include <dt-bindings/sound/qcom,q6afe.h> 32#include <dt-bindings/sound/qcom,q6asm.h> 33#include <dt-bindings/thermal/thermal.h> 34 35/ { 36 interrupt-parent = <&intc>; 37 38 #address-cells = <2>; 39 #size-cells = <2>; 40 41 chosen { }; 42 43 aliases { 44 i2c0 = &i2c0; 45 i2c1 = &i2c1; 46 i2c2 = &i2c2; 47 i2c3 = &i2c3; 48 i2c4 = &i2c4; 49 i2c5 = &i2c5; 50 i2c6 = &i2c6; 51 i2c7 = &i2c7; 52 i2c8 = &i2c8; 53 i2c9 = &i2c9; 54 i2c10 = &i2c10; 55 i2c11 = &i2c11; 56 i2c12 = &i2c12; 57 i2c13 = &i2c13; 58 i2c14 = &i2c14; 59 i2c15 = &i2c15; 60 mmc1 = &sdhc_1; 61 mmc2 = &sdhc_2; 62 spi0 = &spi0; 63 spi1 = &spi1; 64 spi2 = &spi2; 65 spi3 = &spi3; 66 spi4 = &spi4; 67 spi5 = &spi5; 68 spi6 = &spi6; 69 spi7 = &spi7; 70 spi8 = &spi8; 71 spi9 = &spi9; 72 spi10 = &spi10; 73 spi11 = &spi11; 74 spi12 = &spi12; 75 spi13 = &spi13; 76 spi14 = &spi14; 77 spi15 = &spi15; 78 }; 79 80 clocks { 81 xo_board: xo-board { 82 compatible = "fixed-clock"; 83 clock-frequency = <76800000>; 84 #clock-cells = <0>; 85 }; 86 87 sleep_clk: sleep-clk { 88 compatible = "fixed-clock"; 89 clock-frequency = <32764>; 90 #clock-cells = <0>; 91 }; 92 }; 93 94 reserved-memory { 95 #address-cells = <2>; 96 #size-cells = <2>; 97 ranges; 98 99 wlan_ce_mem: wlan-ce@4cd000 { 100 no-map; 101 reg = <0x0 0x004cd000 0x0 0x1000>; 102 }; 103 104 hyp_mem: hyp@80000000 { 105 reg = <0x0 0x80000000 0x0 0x600000>; 106 no-map; 107 }; 108 109 xbl_mem: xbl@80600000 { 110 reg = <0x0 0x80600000 0x0 0x200000>; 111 no-map; 112 }; 113 114 aop_mem: aop@80800000 { 115 reg = <0x0 0x80800000 0x0 0x60000>; 116 no-map; 117 }; 118 119 aop_cmd_db_mem: aop-cmd-db@80860000 { 120 reg = <0x0 0x80860000 0x0 0x20000>; 121 compatible = "qcom,cmd-db"; 122 no-map; 123 }; 124 125 reserved_xbl_uefi_log: xbl-uefi-res@80880000 { 126 reg = <0x0 0x80884000 0x0 0x10000>; 127 no-map; 128 }; 129 130 sec_apps_mem: sec-apps@808ff000 { 131 reg = <0x0 0x808ff000 0x0 0x1000>; 132 no-map; 133 }; 134 135 smem_mem: smem@80900000 { 136 reg = <0x0 0x80900000 0x0 0x200000>; 137 no-map; 138 }; 139 140 cpucp_mem: cpucp@80b00000 { 141 no-map; 142 reg = <0x0 0x80b00000 0x0 0x100000>; 143 }; 144 145 wlan_fw_mem: wlan-fw@80c00000 { 146 reg = <0x0 0x80c00000 0x0 0xc00000>; 147 no-map; 148 }; 149 150 adsp_mem: adsp@86700000 { 151 reg = <0x0 0x86700000 0x0 0x2800000>; 152 no-map; 153 }; 154 155 video_mem: video@8b200000 { 156 reg = <0x0 0x8b200000 0x0 0x500000>; 157 no-map; 158 }; 159 160 cdsp_mem: cdsp@88f00000 { 161 reg = <0x0 0x88f00000 0x0 0x1e00000>; 162 no-map; 163 }; 164 165 ipa_fw_mem: ipa-fw@8b700000 { 166 reg = <0 0x8b700000 0 0x10000>; 167 no-map; 168 }; 169 170 gpu_zap_mem: zap@8b71a000 { 171 reg = <0 0x8b71a000 0 0x2000>; 172 no-map; 173 }; 174 175 mpss_mem: mpss@8b800000 { 176 reg = <0x0 0x8b800000 0x0 0xf600000>; 177 no-map; 178 }; 179 180 wpss_mem: wpss@9ae00000 { 181 reg = <0x0 0x9ae00000 0x0 0x1900000>; 182 no-map; 183 }; 184 185 rmtfs_mem: rmtfs@9c900000 { 186 compatible = "qcom,rmtfs-mem"; 187 reg = <0x0 0x9c900000 0x0 0x280000>; 188 no-map; 189 190 qcom,client-id = <1>; 191 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 192 }; 193 194 adsp_rpc_remote_heap_mem: adsp-rpc-remote-heap@9cb80000 { 195 reg = <0x0 0x9cb80000 0x0 0x800000>; 196 no-map; 197 }; 198 }; 199 200 cpus { 201 #address-cells = <2>; 202 #size-cells = <0>; 203 204 cpu0: cpu@0 { 205 device_type = "cpu"; 206 compatible = "qcom,kryo"; 207 reg = <0x0 0x0>; 208 clocks = <&cpufreq_hw 0>; 209 enable-method = "psci"; 210 power-domains = <&cpu_pd0>; 211 power-domain-names = "psci"; 212 next-level-cache = <&l2_0>; 213 operating-points-v2 = <&cpu0_opp_table>; 214 capacity-dmips-mhz = <1024>; 215 dynamic-power-coefficient = <100>; 216 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 217 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 218 qcom,freq-domain = <&cpufreq_hw 0>; 219 #cooling-cells = <2>; 220 l2_0: l2-cache { 221 compatible = "cache"; 222 cache-level = <2>; 223 cache-unified; 224 next-level-cache = <&l3_0>; 225 l3_0: l3-cache { 226 compatible = "cache"; 227 cache-level = <3>; 228 cache-unified; 229 }; 230 }; 231 }; 232 233 cpu1: cpu@100 { 234 device_type = "cpu"; 235 compatible = "qcom,kryo"; 236 reg = <0x0 0x100>; 237 clocks = <&cpufreq_hw 0>; 238 enable-method = "psci"; 239 power-domains = <&cpu_pd1>; 240 power-domain-names = "psci"; 241 next-level-cache = <&l2_100>; 242 operating-points-v2 = <&cpu0_opp_table>; 243 capacity-dmips-mhz = <1024>; 244 dynamic-power-coefficient = <100>; 245 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 246 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 247 qcom,freq-domain = <&cpufreq_hw 0>; 248 #cooling-cells = <2>; 249 l2_100: l2-cache { 250 compatible = "cache"; 251 cache-level = <2>; 252 cache-unified; 253 next-level-cache = <&l3_0>; 254 }; 255 }; 256 257 cpu2: cpu@200 { 258 device_type = "cpu"; 259 compatible = "qcom,kryo"; 260 reg = <0x0 0x200>; 261 clocks = <&cpufreq_hw 0>; 262 enable-method = "psci"; 263 power-domains = <&cpu_pd2>; 264 power-domain-names = "psci"; 265 next-level-cache = <&l2_200>; 266 operating-points-v2 = <&cpu0_opp_table>; 267 capacity-dmips-mhz = <1024>; 268 dynamic-power-coefficient = <100>; 269 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 270 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 271 qcom,freq-domain = <&cpufreq_hw 0>; 272 #cooling-cells = <2>; 273 l2_200: l2-cache { 274 compatible = "cache"; 275 cache-level = <2>; 276 cache-unified; 277 next-level-cache = <&l3_0>; 278 }; 279 }; 280 281 cpu3: cpu@300 { 282 device_type = "cpu"; 283 compatible = "qcom,kryo"; 284 reg = <0x0 0x300>; 285 clocks = <&cpufreq_hw 0>; 286 enable-method = "psci"; 287 power-domains = <&cpu_pd3>; 288 power-domain-names = "psci"; 289 next-level-cache = <&l2_300>; 290 operating-points-v2 = <&cpu0_opp_table>; 291 capacity-dmips-mhz = <1024>; 292 dynamic-power-coefficient = <100>; 293 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 294 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 295 qcom,freq-domain = <&cpufreq_hw 0>; 296 #cooling-cells = <2>; 297 l2_300: l2-cache { 298 compatible = "cache"; 299 cache-level = <2>; 300 cache-unified; 301 next-level-cache = <&l3_0>; 302 }; 303 }; 304 305 cpu4: cpu@400 { 306 device_type = "cpu"; 307 compatible = "qcom,kryo"; 308 reg = <0x0 0x400>; 309 clocks = <&cpufreq_hw 1>; 310 enable-method = "psci"; 311 power-domains = <&cpu_pd4>; 312 power-domain-names = "psci"; 313 next-level-cache = <&l2_400>; 314 operating-points-v2 = <&cpu4_opp_table>; 315 capacity-dmips-mhz = <1946>; 316 dynamic-power-coefficient = <520>; 317 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 318 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 319 qcom,freq-domain = <&cpufreq_hw 1>; 320 #cooling-cells = <2>; 321 l2_400: l2-cache { 322 compatible = "cache"; 323 cache-level = <2>; 324 cache-unified; 325 next-level-cache = <&l3_0>; 326 }; 327 }; 328 329 cpu5: cpu@500 { 330 device_type = "cpu"; 331 compatible = "qcom,kryo"; 332 reg = <0x0 0x500>; 333 clocks = <&cpufreq_hw 1>; 334 enable-method = "psci"; 335 power-domains = <&cpu_pd5>; 336 power-domain-names = "psci"; 337 next-level-cache = <&l2_500>; 338 operating-points-v2 = <&cpu4_opp_table>; 339 capacity-dmips-mhz = <1946>; 340 dynamic-power-coefficient = <520>; 341 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 342 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 343 qcom,freq-domain = <&cpufreq_hw 1>; 344 #cooling-cells = <2>; 345 l2_500: l2-cache { 346 compatible = "cache"; 347 cache-level = <2>; 348 cache-unified; 349 next-level-cache = <&l3_0>; 350 }; 351 }; 352 353 cpu6: cpu@600 { 354 device_type = "cpu"; 355 compatible = "qcom,kryo"; 356 reg = <0x0 0x600>; 357 clocks = <&cpufreq_hw 1>; 358 enable-method = "psci"; 359 power-domains = <&cpu_pd6>; 360 power-domain-names = "psci"; 361 next-level-cache = <&l2_600>; 362 operating-points-v2 = <&cpu4_opp_table>; 363 capacity-dmips-mhz = <1946>; 364 dynamic-power-coefficient = <520>; 365 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 366 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 367 qcom,freq-domain = <&cpufreq_hw 1>; 368 #cooling-cells = <2>; 369 l2_600: l2-cache { 370 compatible = "cache"; 371 cache-level = <2>; 372 cache-unified; 373 next-level-cache = <&l3_0>; 374 }; 375 }; 376 377 cpu7: cpu@700 { 378 device_type = "cpu"; 379 compatible = "qcom,kryo"; 380 reg = <0x0 0x700>; 381 clocks = <&cpufreq_hw 2>; 382 enable-method = "psci"; 383 power-domains = <&cpu_pd7>; 384 power-domain-names = "psci"; 385 next-level-cache = <&l2_700>; 386 operating-points-v2 = <&cpu7_opp_table>; 387 capacity-dmips-mhz = <1985>; 388 dynamic-power-coefficient = <552>; 389 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &mc_virt SLAVE_EBI1 3>, 390 <&epss_l3 MASTER_EPSS_L3_APPS &epss_l3 SLAVE_EPSS_L3_SHARED>; 391 qcom,freq-domain = <&cpufreq_hw 2>; 392 #cooling-cells = <2>; 393 l2_700: l2-cache { 394 compatible = "cache"; 395 cache-level = <2>; 396 cache-unified; 397 next-level-cache = <&l3_0>; 398 }; 399 }; 400 401 cpu-map { 402 cluster0 { 403 core0 { 404 cpu = <&cpu0>; 405 }; 406 407 core1 { 408 cpu = <&cpu1>; 409 }; 410 411 core2 { 412 cpu = <&cpu2>; 413 }; 414 415 core3 { 416 cpu = <&cpu3>; 417 }; 418 419 core4 { 420 cpu = <&cpu4>; 421 }; 422 423 core5 { 424 cpu = <&cpu5>; 425 }; 426 427 core6 { 428 cpu = <&cpu6>; 429 }; 430 431 core7 { 432 cpu = <&cpu7>; 433 }; 434 }; 435 }; 436 437 idle-states { 438 entry-method = "psci"; 439 440 little_cpu_sleep_0: cpu-sleep-0-0 { 441 compatible = "arm,idle-state"; 442 idle-state-name = "little-power-down"; 443 arm,psci-suspend-param = <0x40000003>; 444 entry-latency-us = <549>; 445 exit-latency-us = <901>; 446 min-residency-us = <1774>; 447 local-timer-stop; 448 }; 449 450 little_cpu_sleep_1: cpu-sleep-0-1 { 451 compatible = "arm,idle-state"; 452 idle-state-name = "little-rail-power-down"; 453 arm,psci-suspend-param = <0x40000004>; 454 entry-latency-us = <702>; 455 exit-latency-us = <915>; 456 min-residency-us = <4001>; 457 local-timer-stop; 458 }; 459 460 big_cpu_sleep_0: cpu-sleep-1-0 { 461 compatible = "arm,idle-state"; 462 idle-state-name = "big-power-down"; 463 arm,psci-suspend-param = <0x40000003>; 464 entry-latency-us = <523>; 465 exit-latency-us = <1244>; 466 min-residency-us = <2207>; 467 local-timer-stop; 468 }; 469 470 big_cpu_sleep_1: cpu-sleep-1-1 { 471 compatible = "arm,idle-state"; 472 idle-state-name = "big-rail-power-down"; 473 arm,psci-suspend-param = <0x40000004>; 474 entry-latency-us = <526>; 475 exit-latency-us = <1854>; 476 min-residency-us = <5555>; 477 local-timer-stop; 478 }; 479 }; 480 481 domain_idle_states: domain-idle-states { 482 cluster_sleep_apss_off: cluster-sleep-0 { 483 compatible = "domain-idle-state"; 484 arm,psci-suspend-param = <0x41000044>; 485 entry-latency-us = <2752>; 486 exit-latency-us = <3048>; 487 min-residency-us = <6118>; 488 }; 489 490 cluster_sleep_cx_ret: cluster-sleep-1 { 491 compatible = "domain-idle-state"; 492 arm,psci-suspend-param = <0x41001344>; 493 entry-latency-us = <3263>; 494 exit-latency-us = <4562>; 495 min-residency-us = <8467>; 496 }; 497 498 cluster_sleep_llcc_off: cluster-sleep-2 { 499 compatible = "domain-idle-state"; 500 arm,psci-suspend-param = <0x4100b344>; 501 entry-latency-us = <3638>; 502 exit-latency-us = <6562>; 503 min-residency-us = <9826>; 504 }; 505 }; 506 }; 507 508 cpu0_opp_table: opp-table-cpu0 { 509 compatible = "operating-points-v2"; 510 opp-shared; 511 512 cpu0_opp_300mhz: opp-300000000 { 513 opp-hz = /bits/ 64 <300000000>; 514 opp-peak-kBps = <800000 9600000>; 515 }; 516 517 cpu0_opp_691mhz: opp-691200000 { 518 opp-hz = /bits/ 64 <691200000>; 519 opp-peak-kBps = <800000 17817600>; 520 }; 521 522 cpu0_opp_806mhz: opp-806400000 { 523 opp-hz = /bits/ 64 <806400000>; 524 opp-peak-kBps = <800000 20889600>; 525 }; 526 527 cpu0_opp_941mhz: opp-940800000 { 528 opp-hz = /bits/ 64 <940800000>; 529 opp-peak-kBps = <1804000 24576000>; 530 }; 531 532 cpu0_opp_1152mhz: opp-1152000000 { 533 opp-hz = /bits/ 64 <1152000000>; 534 opp-peak-kBps = <2188000 27033600>; 535 }; 536 537 cpu0_opp_1325mhz: opp-1324800000 { 538 opp-hz = /bits/ 64 <1324800000>; 539 opp-peak-kBps = <2188000 33792000>; 540 }; 541 542 cpu0_opp_1517mhz: opp-1516800000 { 543 opp-hz = /bits/ 64 <1516800000>; 544 opp-peak-kBps = <3072000 38092800>; 545 }; 546 547 cpu0_opp_1651mhz: opp-1651200000 { 548 opp-hz = /bits/ 64 <1651200000>; 549 opp-peak-kBps = <3072000 41779200>; 550 }; 551 552 cpu0_opp_1805mhz: opp-1804800000 { 553 opp-hz = /bits/ 64 <1804800000>; 554 opp-peak-kBps = <4068000 48537600>; 555 }; 556 557 cpu0_opp_1958mhz: opp-1958400000 { 558 opp-hz = /bits/ 64 <1958400000>; 559 opp-peak-kBps = <4068000 48537600>; 560 }; 561 562 cpu0_opp_2016mhz: opp-2016000000 { 563 opp-hz = /bits/ 64 <2016000000>; 564 opp-peak-kBps = <6220000 48537600>; 565 }; 566 }; 567 568 cpu4_opp_table: opp-table-cpu4 { 569 compatible = "operating-points-v2"; 570 opp-shared; 571 572 cpu4_opp_691mhz: opp-691200000 { 573 opp-hz = /bits/ 64 <691200000>; 574 opp-peak-kBps = <1804000 9600000>; 575 }; 576 577 cpu4_opp_941mhz: opp-940800000 { 578 opp-hz = /bits/ 64 <940800000>; 579 opp-peak-kBps = <2188000 17817600>; 580 }; 581 582 cpu4_opp_1229mhz: opp-1228800000 { 583 opp-hz = /bits/ 64 <1228800000>; 584 opp-peak-kBps = <4068000 24576000>; 585 }; 586 587 cpu4_opp_1344mhz: opp-1344000000 { 588 opp-hz = /bits/ 64 <1344000000>; 589 opp-peak-kBps = <4068000 24576000>; 590 }; 591 592 cpu4_opp_1517mhz: opp-1516800000 { 593 opp-hz = /bits/ 64 <1516800000>; 594 opp-peak-kBps = <4068000 24576000>; 595 }; 596 597 cpu4_opp_1651mhz: opp-1651200000 { 598 opp-hz = /bits/ 64 <1651200000>; 599 opp-peak-kBps = <6220000 38092800>; 600 }; 601 602 cpu4_opp_1901mhz: opp-1900800000 { 603 opp-hz = /bits/ 64 <1900800000>; 604 opp-peak-kBps = <6220000 44851200>; 605 }; 606 607 cpu4_opp_2054mhz: opp-2054400000 { 608 opp-hz = /bits/ 64 <2054400000>; 609 opp-peak-kBps = <6220000 44851200>; 610 }; 611 612 cpu4_opp_2112mhz: opp-2112000000 { 613 opp-hz = /bits/ 64 <2112000000>; 614 opp-peak-kBps = <6220000 44851200>; 615 }; 616 617 cpu4_opp_2131mhz: opp-2131200000 { 618 opp-hz = /bits/ 64 <2131200000>; 619 opp-peak-kBps = <6220000 44851200>; 620 }; 621 622 cpu4_opp_2208mhz: opp-2208000000 { 623 opp-hz = /bits/ 64 <2208000000>; 624 opp-peak-kBps = <6220000 44851200>; 625 }; 626 627 cpu4_opp_2400mhz: opp-2400000000 { 628 opp-hz = /bits/ 64 <2400000000>; 629 opp-peak-kBps = <12787200 48537600>; 630 }; 631 632 cpu4_opp_2611mhz: opp-2611200000 { 633 opp-hz = /bits/ 64 <2611200000>; 634 opp-peak-kBps = <12787200 48537600>; 635 }; 636 }; 637 638 cpu7_opp_table: opp-table-cpu7 { 639 compatible = "operating-points-v2"; 640 opp-shared; 641 642 cpu7_opp_806mhz: opp-806400000 { 643 opp-hz = /bits/ 64 <806400000>; 644 opp-peak-kBps = <1804000 9600000>; 645 }; 646 647 cpu7_opp_1056mhz: opp-1056000000 { 648 opp-hz = /bits/ 64 <1056000000>; 649 opp-peak-kBps = <2188000 17817600>; 650 }; 651 652 cpu7_opp_1325mhz: opp-1324800000 { 653 opp-hz = /bits/ 64 <1324800000>; 654 opp-peak-kBps = <4068000 24576000>; 655 }; 656 657 cpu7_opp_1517mhz: opp-1516800000 { 658 opp-hz = /bits/ 64 <1516800000>; 659 opp-peak-kBps = <4068000 24576000>; 660 }; 661 662 cpu7_opp_1766mhz: opp-1766400000 { 663 opp-hz = /bits/ 64 <1766400000>; 664 opp-peak-kBps = <6220000 38092800>; 665 }; 666 667 cpu7_opp_1862mhz: opp-1862400000 { 668 opp-hz = /bits/ 64 <1862400000>; 669 opp-peak-kBps = <6220000 38092800>; 670 }; 671 672 cpu7_opp_2035mhz: opp-2035200000 { 673 opp-hz = /bits/ 64 <2035200000>; 674 opp-peak-kBps = <6220000 38092800>; 675 }; 676 677 cpu7_opp_2112mhz: opp-2112000000 { 678 opp-hz = /bits/ 64 <2112000000>; 679 opp-peak-kBps = <6220000 44851200>; 680 }; 681 682 cpu7_opp_2208mhz: opp-2208000000 { 683 opp-hz = /bits/ 64 <2208000000>; 684 opp-peak-kBps = <6220000 44851200>; 685 }; 686 687 cpu7_opp_2381mhz: opp-2380800000 { 688 opp-hz = /bits/ 64 <2380800000>; 689 opp-peak-kBps = <6832000 44851200>; 690 }; 691 692 cpu7_opp_2400mhz: opp-2400000000 { 693 opp-hz = /bits/ 64 <2400000000>; 694 opp-peak-kBps = <12787200 48537600>; 695 }; 696 697 cpu7_opp_2515mhz: opp-2515200000 { 698 opp-hz = /bits/ 64 <2515200000>; 699 opp-peak-kBps = <12787200 48537600>; 700 }; 701 702 cpu7_opp_2707mhz: opp-2707200000 { 703 opp-hz = /bits/ 64 <2707200000>; 704 opp-peak-kBps = <12787200 48537600>; 705 }; 706 707 cpu7_opp_3014mhz: opp-3014400000 { 708 opp-hz = /bits/ 64 <3014400000>; 709 opp-peak-kBps = <12787200 48537600>; 710 }; 711 }; 712 713 memory@80000000 { 714 device_type = "memory"; 715 /* We expect the bootloader to fill in the size */ 716 reg = <0 0x80000000 0 0>; 717 }; 718 719 firmware { 720 scm: scm { 721 compatible = "qcom,scm-sc7280", "qcom,scm"; 722 qcom,dload-mode = <&tcsr_2 0x13000>; 723 }; 724 }; 725 726 clk_virt: interconnect { 727 compatible = "qcom,sc7280-clk-virt"; 728 #interconnect-cells = <2>; 729 qcom,bcm-voters = <&apps_bcm_voter>; 730 }; 731 732 smem { 733 compatible = "qcom,smem"; 734 memory-region = <&smem_mem>; 735 hwlocks = <&tcsr_mutex 3>; 736 }; 737 738 smp2p-adsp { 739 compatible = "qcom,smp2p"; 740 qcom,smem = <443>, <429>; 741 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 742 IPCC_MPROC_SIGNAL_SMP2P 743 IRQ_TYPE_EDGE_RISING>; 744 mboxes = <&ipcc IPCC_CLIENT_LPASS 745 IPCC_MPROC_SIGNAL_SMP2P>; 746 747 qcom,local-pid = <0>; 748 qcom,remote-pid = <2>; 749 750 adsp_smp2p_out: master-kernel { 751 qcom,entry-name = "master-kernel"; 752 #qcom,smem-state-cells = <1>; 753 }; 754 755 adsp_smp2p_in: slave-kernel { 756 qcom,entry-name = "slave-kernel"; 757 interrupt-controller; 758 #interrupt-cells = <2>; 759 }; 760 }; 761 762 smp2p-cdsp { 763 compatible = "qcom,smp2p"; 764 qcom,smem = <94>, <432>; 765 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 766 IPCC_MPROC_SIGNAL_SMP2P 767 IRQ_TYPE_EDGE_RISING>; 768 mboxes = <&ipcc IPCC_CLIENT_CDSP 769 IPCC_MPROC_SIGNAL_SMP2P>; 770 771 qcom,local-pid = <0>; 772 qcom,remote-pid = <5>; 773 774 cdsp_smp2p_out: master-kernel { 775 qcom,entry-name = "master-kernel"; 776 #qcom,smem-state-cells = <1>; 777 }; 778 779 cdsp_smp2p_in: slave-kernel { 780 qcom,entry-name = "slave-kernel"; 781 interrupt-controller; 782 #interrupt-cells = <2>; 783 }; 784 }; 785 786 smp2p-mpss { 787 compatible = "qcom,smp2p"; 788 qcom,smem = <435>, <428>; 789 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 790 IPCC_MPROC_SIGNAL_SMP2P 791 IRQ_TYPE_EDGE_RISING>; 792 mboxes = <&ipcc IPCC_CLIENT_MPSS 793 IPCC_MPROC_SIGNAL_SMP2P>; 794 795 qcom,local-pid = <0>; 796 qcom,remote-pid = <1>; 797 798 modem_smp2p_out: master-kernel { 799 qcom,entry-name = "master-kernel"; 800 #qcom,smem-state-cells = <1>; 801 }; 802 803 modem_smp2p_in: slave-kernel { 804 qcom,entry-name = "slave-kernel"; 805 interrupt-controller; 806 #interrupt-cells = <2>; 807 }; 808 809 ipa_smp2p_out: ipa-ap-to-modem { 810 qcom,entry-name = "ipa"; 811 #qcom,smem-state-cells = <1>; 812 }; 813 814 ipa_smp2p_in: ipa-modem-to-ap { 815 qcom,entry-name = "ipa"; 816 interrupt-controller; 817 #interrupt-cells = <2>; 818 }; 819 }; 820 821 smp2p-wpss { 822 compatible = "qcom,smp2p"; 823 qcom,smem = <617>, <616>; 824 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 825 IPCC_MPROC_SIGNAL_SMP2P 826 IRQ_TYPE_EDGE_RISING>; 827 mboxes = <&ipcc IPCC_CLIENT_WPSS 828 IPCC_MPROC_SIGNAL_SMP2P>; 829 830 qcom,local-pid = <0>; 831 qcom,remote-pid = <13>; 832 833 wpss_smp2p_out: master-kernel { 834 qcom,entry-name = "master-kernel"; 835 #qcom,smem-state-cells = <1>; 836 }; 837 838 wpss_smp2p_in: slave-kernel { 839 qcom,entry-name = "slave-kernel"; 840 interrupt-controller; 841 #interrupt-cells = <2>; 842 }; 843 844 wlan_smp2p_out: wlan-ap-to-wpss { 845 qcom,entry-name = "wlan"; 846 #qcom,smem-state-cells = <1>; 847 }; 848 849 wlan_smp2p_in: wlan-wpss-to-ap { 850 qcom,entry-name = "wlan"; 851 interrupt-controller; 852 #interrupt-cells = <2>; 853 }; 854 }; 855 856 pmu-a55 { 857 compatible = "arm,cortex-a55-pmu"; 858 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 859 }; 860 861 pmu-a78 { 862 compatible = "arm,cortex-a78-pmu"; 863 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 864 }; 865 866 psci { 867 compatible = "arm,psci-1.0"; 868 method = "smc"; 869 870 cpu_pd0: power-domain-cpu0 { 871 #power-domain-cells = <0>; 872 power-domains = <&cluster_pd>; 873 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 874 }; 875 876 cpu_pd1: power-domain-cpu1 { 877 #power-domain-cells = <0>; 878 power-domains = <&cluster_pd>; 879 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 880 }; 881 882 cpu_pd2: power-domain-cpu2 { 883 #power-domain-cells = <0>; 884 power-domains = <&cluster_pd>; 885 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 886 }; 887 888 cpu_pd3: power-domain-cpu3 { 889 #power-domain-cells = <0>; 890 power-domains = <&cluster_pd>; 891 domain-idle-states = <&little_cpu_sleep_0 &little_cpu_sleep_1>; 892 }; 893 894 cpu_pd4: power-domain-cpu4 { 895 #power-domain-cells = <0>; 896 power-domains = <&cluster_pd>; 897 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 898 }; 899 900 cpu_pd5: power-domain-cpu5 { 901 #power-domain-cells = <0>; 902 power-domains = <&cluster_pd>; 903 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 904 }; 905 906 cpu_pd6: power-domain-cpu6 { 907 #power-domain-cells = <0>; 908 power-domains = <&cluster_pd>; 909 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 910 }; 911 912 cpu_pd7: power-domain-cpu7 { 913 #power-domain-cells = <0>; 914 power-domains = <&cluster_pd>; 915 domain-idle-states = <&big_cpu_sleep_0 &big_cpu_sleep_1>; 916 }; 917 918 cluster_pd: power-domain-cluster { 919 #power-domain-cells = <0>; 920 domain-idle-states = <&cluster_sleep_apss_off &cluster_sleep_cx_ret &cluster_sleep_llcc_off>; 921 }; 922 }; 923 924 qspi_opp_table: opp-table-qspi { 925 compatible = "operating-points-v2"; 926 927 opp-75000000 { 928 opp-hz = /bits/ 64 <75000000>; 929 required-opps = <&rpmhpd_opp_low_svs>; 930 }; 931 932 opp-150000000 { 933 opp-hz = /bits/ 64 <150000000>; 934 required-opps = <&rpmhpd_opp_svs>; 935 }; 936 937 opp-200000000 { 938 opp-hz = /bits/ 64 <200000000>; 939 required-opps = <&rpmhpd_opp_svs_l1>; 940 }; 941 942 opp-300000000 { 943 opp-hz = /bits/ 64 <300000000>; 944 required-opps = <&rpmhpd_opp_nom>; 945 }; 946 }; 947 948 qup_opp_table: opp-table-qup { 949 compatible = "operating-points-v2"; 950 951 opp-75000000 { 952 opp-hz = /bits/ 64 <75000000>; 953 required-opps = <&rpmhpd_opp_low_svs>; 954 }; 955 956 opp-100000000 { 957 opp-hz = /bits/ 64 <100000000>; 958 required-opps = <&rpmhpd_opp_svs>; 959 }; 960 961 opp-128000000 { 962 opp-hz = /bits/ 64 <128000000>; 963 required-opps = <&rpmhpd_opp_nom>; 964 }; 965 }; 966 967 soc: soc@0 { 968 #address-cells = <2>; 969 #size-cells = <2>; 970 ranges = <0 0 0 0 0x10 0>; 971 dma-ranges = <0 0 0 0 0x10 0>; 972 compatible = "simple-bus"; 973 974 gcc: clock-controller@100000 { 975 compatible = "qcom,gcc-sc7280"; 976 reg = <0 0x00100000 0 0x1f0000>; 977 clocks = <&rpmhcc RPMH_CXO_CLK>, 978 <&rpmhcc RPMH_CXO_CLK_A>, <&sleep_clk>, 979 <0>, <&pcie1_phy>, 980 <&ufs_mem_phy 0>, <&ufs_mem_phy 1>, <&ufs_mem_phy 2>, 981 <&usb_1_qmpphy QMP_USB43DP_USB3_PIPE_CLK>; 982 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk", 983 "pcie_0_pipe_clk", "pcie_1_pipe_clk", 984 "ufs_phy_rx_symbol_0_clk", "ufs_phy_rx_symbol_1_clk", 985 "ufs_phy_tx_symbol_0_clk", 986 "usb3_phy_wrapper_gcc_usb30_pipe_clk"; 987 #clock-cells = <1>; 988 #reset-cells = <1>; 989 #power-domain-cells = <1>; 990 power-domains = <&rpmhpd SC7280_CX>; 991 }; 992 993 ipcc: mailbox@408000 { 994 compatible = "qcom,sc7280-ipcc", "qcom,ipcc"; 995 reg = <0 0x00408000 0 0x1000>; 996 interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>; 997 interrupt-controller; 998 #interrupt-cells = <3>; 999 #mbox-cells = <2>; 1000 }; 1001 1002 qfprom: efuse@784000 { 1003 compatible = "qcom,sc7280-qfprom", "qcom,qfprom"; 1004 reg = <0 0x00784000 0 0xa20>, 1005 <0 0x00780000 0 0xa20>, 1006 <0 0x00782000 0 0x120>, 1007 <0 0x00786000 0 0x1fff>; 1008 clocks = <&gcc GCC_SEC_CTRL_CLK_SRC>; 1009 clock-names = "core"; 1010 power-domains = <&rpmhpd SC7280_MX>; 1011 #address-cells = <1>; 1012 #size-cells = <1>; 1013 1014 gpu_speed_bin: gpu-speed-bin@1e9 { 1015 reg = <0x1e9 0x2>; 1016 bits = <5 8>; 1017 }; 1018 }; 1019 1020 sdhc_1: mmc@7c4000 { 1021 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 1022 pinctrl-names = "default", "sleep"; 1023 pinctrl-0 = <&sdc1_clk>, <&sdc1_cmd>, <&sdc1_data>, <&sdc1_rclk>; 1024 pinctrl-1 = <&sdc1_clk_sleep>, <&sdc1_cmd_sleep>, <&sdc1_data_sleep>, <&sdc1_rclk_sleep>; 1025 status = "disabled"; 1026 1027 reg = <0 0x007c4000 0 0x1000>, 1028 <0 0x007c5000 0 0x1000>; 1029 reg-names = "hc", "cqhci"; 1030 1031 iommus = <&apps_smmu 0xc0 0x0>; 1032 interrupts = <GIC_SPI 652 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH>; 1034 interrupt-names = "hc_irq", "pwr_irq"; 1035 1036 clocks = <&gcc GCC_SDCC1_AHB_CLK>, 1037 <&gcc GCC_SDCC1_APPS_CLK>, 1038 <&rpmhcc RPMH_CXO_CLK>; 1039 clock-names = "iface", "core", "xo"; 1040 interconnects = <&aggre1_noc MASTER_SDCC_1 0 &mc_virt SLAVE_EBI1 0>, 1041 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_1 0>; 1042 interconnect-names = "sdhc-ddr","cpu-sdhc"; 1043 power-domains = <&rpmhpd SC7280_CX>; 1044 operating-points-v2 = <&sdhc1_opp_table>; 1045 1046 bus-width = <8>; 1047 supports-cqe; 1048 dma-coherent; 1049 1050 qcom,dll-config = <0x0007642c>; 1051 qcom,ddr-config = <0x80040868>; 1052 1053 mmc-ddr-1_8v; 1054 mmc-hs200-1_8v; 1055 mmc-hs400-1_8v; 1056 mmc-hs400-enhanced-strobe; 1057 1058 resets = <&gcc GCC_SDCC1_BCR>; 1059 1060 sdhc1_opp_table: opp-table { 1061 compatible = "operating-points-v2"; 1062 1063 opp-100000000 { 1064 opp-hz = /bits/ 64 <100000000>; 1065 required-opps = <&rpmhpd_opp_low_svs>; 1066 opp-peak-kBps = <1800000 400000>; 1067 opp-avg-kBps = <100000 0>; 1068 }; 1069 1070 opp-384000000 { 1071 opp-hz = /bits/ 64 <384000000>; 1072 required-opps = <&rpmhpd_opp_nom>; 1073 opp-peak-kBps = <5400000 1600000>; 1074 opp-avg-kBps = <390000 0>; 1075 }; 1076 }; 1077 }; 1078 1079 gpi_dma0: dma-controller@900000 { 1080 #dma-cells = <3>; 1081 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1082 reg = <0 0x00900000 0 0x60000>; 1083 interrupts = <GIC_SPI 244 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 245 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 247 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 248 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 249 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 250 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1095 dma-channels = <12>; 1096 dma-channel-mask = <0x7f>; 1097 iommus = <&apps_smmu 0x0136 0x0>; 1098 status = "disabled"; 1099 }; 1100 1101 qupv3_id_0: geniqup@9c0000 { 1102 compatible = "qcom,geni-se-qup"; 1103 reg = <0 0x009c0000 0 0x2000>; 1104 clocks = <&gcc GCC_QUPV3_WRAP_0_M_AHB_CLK>, 1105 <&gcc GCC_QUPV3_WRAP_0_S_AHB_CLK>; 1106 clock-names = "m-ahb", "s-ahb"; 1107 #address-cells = <2>; 1108 #size-cells = <2>; 1109 ranges; 1110 iommus = <&apps_smmu 0x123 0x0>; 1111 status = "disabled"; 1112 1113 i2c0: i2c@980000 { 1114 compatible = "qcom,geni-i2c"; 1115 reg = <0 0x00980000 0 0x4000>; 1116 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1117 clock-names = "se"; 1118 pinctrl-names = "default"; 1119 pinctrl-0 = <&qup_i2c0_data_clk>; 1120 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1121 #address-cells = <1>; 1122 #size-cells = <0>; 1123 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1124 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1125 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1126 interconnect-names = "qup-core", "qup-config", 1127 "qup-memory"; 1128 power-domains = <&rpmhpd SC7280_CX>; 1129 required-opps = <&rpmhpd_opp_low_svs>; 1130 dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>, 1131 <&gpi_dma0 1 0 QCOM_GPI_I2C>; 1132 dma-names = "tx", "rx"; 1133 status = "disabled"; 1134 }; 1135 1136 spi0: spi@980000 { 1137 compatible = "qcom,geni-spi"; 1138 reg = <0 0x00980000 0 0x4000>; 1139 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1140 clock-names = "se"; 1141 pinctrl-names = "default"; 1142 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1143 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1144 #address-cells = <1>; 1145 #size-cells = <0>; 1146 power-domains = <&rpmhpd SC7280_CX>; 1147 operating-points-v2 = <&qup_opp_table>; 1148 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1149 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1150 interconnect-names = "qup-core", "qup-config"; 1151 dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>, 1152 <&gpi_dma0 1 0 QCOM_GPI_SPI>; 1153 dma-names = "tx", "rx"; 1154 status = "disabled"; 1155 }; 1156 1157 uart0: serial@980000 { 1158 compatible = "qcom,geni-uart"; 1159 reg = <0 0x00980000 0 0x4000>; 1160 clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>; 1161 clock-names = "se"; 1162 pinctrl-names = "default"; 1163 pinctrl-0 = <&qup_uart0_cts>, <&qup_uart0_rts>, <&qup_uart0_tx>, <&qup_uart0_rx>; 1164 interrupts = <GIC_SPI 601 IRQ_TYPE_LEVEL_HIGH>; 1165 power-domains = <&rpmhpd SC7280_CX>; 1166 operating-points-v2 = <&qup_opp_table>; 1167 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1168 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1169 interconnect-names = "qup-core", "qup-config"; 1170 status = "disabled"; 1171 }; 1172 1173 i2c1: i2c@984000 { 1174 compatible = "qcom,geni-i2c"; 1175 reg = <0 0x00984000 0 0x4000>; 1176 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1177 clock-names = "se"; 1178 pinctrl-names = "default"; 1179 pinctrl-0 = <&qup_i2c1_data_clk>; 1180 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1181 #address-cells = <1>; 1182 #size-cells = <0>; 1183 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1184 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1185 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1186 interconnect-names = "qup-core", "qup-config", 1187 "qup-memory"; 1188 power-domains = <&rpmhpd SC7280_CX>; 1189 required-opps = <&rpmhpd_opp_low_svs>; 1190 dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>, 1191 <&gpi_dma0 1 1 QCOM_GPI_I2C>; 1192 dma-names = "tx", "rx"; 1193 status = "disabled"; 1194 }; 1195 1196 spi1: spi@984000 { 1197 compatible = "qcom,geni-spi"; 1198 reg = <0 0x00984000 0 0x4000>; 1199 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1200 clock-names = "se"; 1201 pinctrl-names = "default"; 1202 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1203 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1204 #address-cells = <1>; 1205 #size-cells = <0>; 1206 power-domains = <&rpmhpd SC7280_CX>; 1207 operating-points-v2 = <&qup_opp_table>; 1208 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1209 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1210 interconnect-names = "qup-core", "qup-config"; 1211 dmas = <&gpi_dma0 0 1 QCOM_GPI_SPI>, 1212 <&gpi_dma0 1 1 QCOM_GPI_SPI>; 1213 dma-names = "tx", "rx"; 1214 status = "disabled"; 1215 }; 1216 1217 uart1: serial@984000 { 1218 compatible = "qcom,geni-uart"; 1219 reg = <0 0x00984000 0 0x4000>; 1220 clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>; 1221 clock-names = "se"; 1222 pinctrl-names = "default"; 1223 pinctrl-0 = <&qup_uart1_cts>, <&qup_uart1_rts>, <&qup_uart1_tx>, <&qup_uart1_rx>; 1224 interrupts = <GIC_SPI 602 IRQ_TYPE_LEVEL_HIGH>; 1225 power-domains = <&rpmhpd SC7280_CX>; 1226 operating-points-v2 = <&qup_opp_table>; 1227 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1228 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1229 interconnect-names = "qup-core", "qup-config"; 1230 status = "disabled"; 1231 }; 1232 1233 i2c2: i2c@988000 { 1234 compatible = "qcom,geni-i2c"; 1235 reg = <0 0x00988000 0 0x4000>; 1236 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1237 clock-names = "se"; 1238 pinctrl-names = "default"; 1239 pinctrl-0 = <&qup_i2c2_data_clk>; 1240 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1241 #address-cells = <1>; 1242 #size-cells = <0>; 1243 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1244 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1245 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1246 interconnect-names = "qup-core", "qup-config", 1247 "qup-memory"; 1248 power-domains = <&rpmhpd SC7280_CX>; 1249 required-opps = <&rpmhpd_opp_low_svs>; 1250 dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>, 1251 <&gpi_dma0 1 2 QCOM_GPI_I2C>; 1252 dma-names = "tx", "rx"; 1253 status = "disabled"; 1254 }; 1255 1256 spi2: spi@988000 { 1257 compatible = "qcom,geni-spi"; 1258 reg = <0 0x00988000 0 0x4000>; 1259 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1260 clock-names = "se"; 1261 pinctrl-names = "default"; 1262 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1263 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1264 #address-cells = <1>; 1265 #size-cells = <0>; 1266 power-domains = <&rpmhpd SC7280_CX>; 1267 operating-points-v2 = <&qup_opp_table>; 1268 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1269 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1270 interconnect-names = "qup-core", "qup-config"; 1271 dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>, 1272 <&gpi_dma0 1 2 QCOM_GPI_SPI>; 1273 dma-names = "tx", "rx"; 1274 status = "disabled"; 1275 }; 1276 1277 uart2: serial@988000 { 1278 compatible = "qcom,geni-uart"; 1279 reg = <0 0x00988000 0 0x4000>; 1280 clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>; 1281 clock-names = "se"; 1282 pinctrl-names = "default"; 1283 pinctrl-0 = <&qup_uart2_cts>, <&qup_uart2_rts>, <&qup_uart2_tx>, <&qup_uart2_rx>; 1284 interrupts = <GIC_SPI 603 IRQ_TYPE_LEVEL_HIGH>; 1285 power-domains = <&rpmhpd SC7280_CX>; 1286 operating-points-v2 = <&qup_opp_table>; 1287 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1288 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1289 interconnect-names = "qup-core", "qup-config"; 1290 status = "disabled"; 1291 }; 1292 1293 i2c3: i2c@98c000 { 1294 compatible = "qcom,geni-i2c"; 1295 reg = <0 0x0098c000 0 0x4000>; 1296 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1297 clock-names = "se"; 1298 pinctrl-names = "default"; 1299 pinctrl-0 = <&qup_i2c3_data_clk>; 1300 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1301 #address-cells = <1>; 1302 #size-cells = <0>; 1303 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1304 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1305 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1306 interconnect-names = "qup-core", "qup-config", 1307 "qup-memory"; 1308 power-domains = <&rpmhpd SC7280_CX>; 1309 required-opps = <&rpmhpd_opp_low_svs>; 1310 dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>, 1311 <&gpi_dma0 1 3 QCOM_GPI_I2C>; 1312 dma-names = "tx", "rx"; 1313 status = "disabled"; 1314 }; 1315 1316 spi3: spi@98c000 { 1317 compatible = "qcom,geni-spi"; 1318 reg = <0 0x0098c000 0 0x4000>; 1319 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1320 clock-names = "se"; 1321 pinctrl-names = "default"; 1322 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1323 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1324 #address-cells = <1>; 1325 #size-cells = <0>; 1326 power-domains = <&rpmhpd SC7280_CX>; 1327 operating-points-v2 = <&qup_opp_table>; 1328 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1329 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1330 interconnect-names = "qup-core", "qup-config"; 1331 dmas = <&gpi_dma0 0 3 QCOM_GPI_SPI>, 1332 <&gpi_dma0 1 3 QCOM_GPI_SPI>; 1333 dma-names = "tx", "rx"; 1334 status = "disabled"; 1335 }; 1336 1337 uart3: serial@98c000 { 1338 compatible = "qcom,geni-uart"; 1339 reg = <0 0x0098c000 0 0x4000>; 1340 clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>; 1341 clock-names = "se"; 1342 pinctrl-names = "default"; 1343 pinctrl-0 = <&qup_uart3_cts>, <&qup_uart3_rts>, <&qup_uart3_tx>, <&qup_uart3_rx>; 1344 interrupts = <GIC_SPI 604 IRQ_TYPE_LEVEL_HIGH>; 1345 power-domains = <&rpmhpd SC7280_CX>; 1346 operating-points-v2 = <&qup_opp_table>; 1347 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1348 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1349 interconnect-names = "qup-core", "qup-config"; 1350 status = "disabled"; 1351 }; 1352 1353 i2c4: i2c@990000 { 1354 compatible = "qcom,geni-i2c"; 1355 reg = <0 0x00990000 0 0x4000>; 1356 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1357 clock-names = "se"; 1358 pinctrl-names = "default"; 1359 pinctrl-0 = <&qup_i2c4_data_clk>; 1360 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1364 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1365 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1366 interconnect-names = "qup-core", "qup-config", 1367 "qup-memory"; 1368 power-domains = <&rpmhpd SC7280_CX>; 1369 required-opps = <&rpmhpd_opp_low_svs>; 1370 dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>, 1371 <&gpi_dma0 1 4 QCOM_GPI_I2C>; 1372 dma-names = "tx", "rx"; 1373 status = "disabled"; 1374 }; 1375 1376 spi4: spi@990000 { 1377 compatible = "qcom,geni-spi"; 1378 reg = <0 0x00990000 0 0x4000>; 1379 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1380 clock-names = "se"; 1381 pinctrl-names = "default"; 1382 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1383 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1384 #address-cells = <1>; 1385 #size-cells = <0>; 1386 power-domains = <&rpmhpd SC7280_CX>; 1387 operating-points-v2 = <&qup_opp_table>; 1388 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1389 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1390 interconnect-names = "qup-core", "qup-config"; 1391 dmas = <&gpi_dma0 0 4 QCOM_GPI_SPI>, 1392 <&gpi_dma0 1 4 QCOM_GPI_SPI>; 1393 dma-names = "tx", "rx"; 1394 status = "disabled"; 1395 }; 1396 1397 uart4: serial@990000 { 1398 compatible = "qcom,geni-uart"; 1399 reg = <0 0x00990000 0 0x4000>; 1400 clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>; 1401 clock-names = "se"; 1402 pinctrl-names = "default"; 1403 pinctrl-0 = <&qup_uart4_cts>, <&qup_uart4_rts>, <&qup_uart4_tx>, <&qup_uart4_rx>; 1404 interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL_HIGH>; 1405 power-domains = <&rpmhpd SC7280_CX>; 1406 operating-points-v2 = <&qup_opp_table>; 1407 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1408 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1409 interconnect-names = "qup-core", "qup-config"; 1410 status = "disabled"; 1411 }; 1412 1413 i2c5: i2c@994000 { 1414 compatible = "qcom,geni-i2c"; 1415 reg = <0 0x00994000 0 0x4000>; 1416 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1417 clock-names = "se"; 1418 pinctrl-names = "default"; 1419 pinctrl-0 = <&qup_i2c5_data_clk>; 1420 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1421 #address-cells = <1>; 1422 #size-cells = <0>; 1423 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1424 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1425 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1426 interconnect-names = "qup-core", "qup-config", 1427 "qup-memory"; 1428 power-domains = <&rpmhpd SC7280_CX>; 1429 required-opps = <&rpmhpd_opp_low_svs>; 1430 dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>, 1431 <&gpi_dma0 1 5 QCOM_GPI_I2C>; 1432 dma-names = "tx", "rx"; 1433 status = "disabled"; 1434 }; 1435 1436 spi5: spi@994000 { 1437 compatible = "qcom,geni-spi"; 1438 reg = <0 0x00994000 0 0x4000>; 1439 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1440 clock-names = "se"; 1441 pinctrl-names = "default"; 1442 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1443 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1444 #address-cells = <1>; 1445 #size-cells = <0>; 1446 power-domains = <&rpmhpd SC7280_CX>; 1447 operating-points-v2 = <&qup_opp_table>; 1448 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1449 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1450 interconnect-names = "qup-core", "qup-config"; 1451 dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>, 1452 <&gpi_dma0 1 5 QCOM_GPI_SPI>; 1453 dma-names = "tx", "rx"; 1454 status = "disabled"; 1455 }; 1456 1457 uart5: serial@994000 { 1458 compatible = "qcom,geni-debug-uart"; 1459 reg = <0 0x00994000 0 0x4000>; 1460 clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>; 1461 clock-names = "se"; 1462 pinctrl-names = "default"; 1463 pinctrl-0 = <&qup_uart5_tx>, <&qup_uart5_rx>; 1464 interrupts = <GIC_SPI 606 IRQ_TYPE_LEVEL_HIGH>; 1465 power-domains = <&rpmhpd SC7280_CX>; 1466 operating-points-v2 = <&qup_opp_table>; 1467 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1468 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1469 interconnect-names = "qup-core", "qup-config"; 1470 status = "disabled"; 1471 }; 1472 1473 i2c6: i2c@998000 { 1474 compatible = "qcom,geni-i2c"; 1475 reg = <0 0x00998000 0 0x4000>; 1476 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1477 clock-names = "se"; 1478 pinctrl-names = "default"; 1479 pinctrl-0 = <&qup_i2c6_data_clk>; 1480 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1481 #address-cells = <1>; 1482 #size-cells = <0>; 1483 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1484 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1485 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1486 interconnect-names = "qup-core", "qup-config", 1487 "qup-memory"; 1488 power-domains = <&rpmhpd SC7280_CX>; 1489 required-opps = <&rpmhpd_opp_low_svs>; 1490 dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>, 1491 <&gpi_dma0 1 6 QCOM_GPI_I2C>; 1492 dma-names = "tx", "rx"; 1493 status = "disabled"; 1494 }; 1495 1496 spi6: spi@998000 { 1497 compatible = "qcom,geni-spi"; 1498 reg = <0 0x00998000 0 0x4000>; 1499 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1500 clock-names = "se"; 1501 pinctrl-names = "default"; 1502 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1503 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1504 #address-cells = <1>; 1505 #size-cells = <0>; 1506 power-domains = <&rpmhpd SC7280_CX>; 1507 operating-points-v2 = <&qup_opp_table>; 1508 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1509 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1510 interconnect-names = "qup-core", "qup-config"; 1511 dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>, 1512 <&gpi_dma0 1 6 QCOM_GPI_SPI>; 1513 dma-names = "tx", "rx"; 1514 status = "disabled"; 1515 }; 1516 1517 uart6: serial@998000 { 1518 compatible = "qcom,geni-uart"; 1519 reg = <0 0x00998000 0 0x4000>; 1520 clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>; 1521 clock-names = "se"; 1522 pinctrl-names = "default"; 1523 pinctrl-0 = <&qup_uart6_cts>, <&qup_uart6_rts>, <&qup_uart6_tx>, <&qup_uart6_rx>; 1524 interrupts = <GIC_SPI 607 IRQ_TYPE_LEVEL_HIGH>; 1525 power-domains = <&rpmhpd SC7280_CX>; 1526 operating-points-v2 = <&qup_opp_table>; 1527 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1528 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1529 interconnect-names = "qup-core", "qup-config"; 1530 status = "disabled"; 1531 }; 1532 1533 i2c7: i2c@99c000 { 1534 compatible = "qcom,geni-i2c"; 1535 reg = <0 0x0099c000 0 0x4000>; 1536 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1537 clock-names = "se"; 1538 pinctrl-names = "default"; 1539 pinctrl-0 = <&qup_i2c7_data_clk>; 1540 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1541 #address-cells = <1>; 1542 #size-cells = <0>; 1543 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1544 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>, 1545 <&aggre1_noc MASTER_QUP_0 0 &mc_virt SLAVE_EBI1 0>; 1546 interconnect-names = "qup-core", "qup-config", 1547 "qup-memory"; 1548 power-domains = <&rpmhpd SC7280_CX>; 1549 required-opps = <&rpmhpd_opp_low_svs>; 1550 dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>, 1551 <&gpi_dma0 1 7 QCOM_GPI_I2C>; 1552 dma-names = "tx", "rx"; 1553 status = "disabled"; 1554 }; 1555 1556 spi7: spi@99c000 { 1557 compatible = "qcom,geni-spi"; 1558 reg = <0 0x0099c000 0 0x4000>; 1559 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1560 clock-names = "se"; 1561 pinctrl-names = "default"; 1562 pinctrl-0 = <&qup_spi7_data_clk>, <&qup_spi7_cs>; 1563 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1564 #address-cells = <1>; 1565 #size-cells = <0>; 1566 power-domains = <&rpmhpd SC7280_CX>; 1567 operating-points-v2 = <&qup_opp_table>; 1568 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1569 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1570 interconnect-names = "qup-core", "qup-config"; 1571 dmas = <&gpi_dma0 0 7 QCOM_GPI_SPI>, 1572 <&gpi_dma0 1 7 QCOM_GPI_SPI>; 1573 dma-names = "tx", "rx"; 1574 status = "disabled"; 1575 }; 1576 1577 uart7: serial@99c000 { 1578 compatible = "qcom,geni-uart"; 1579 reg = <0 0x0099c000 0 0x4000>; 1580 clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>; 1581 clock-names = "se"; 1582 pinctrl-names = "default"; 1583 pinctrl-0 = <&qup_uart7_cts>, <&qup_uart7_rts>, <&qup_uart7_tx>, <&qup_uart7_rx>; 1584 interrupts = <GIC_SPI 608 IRQ_TYPE_LEVEL_HIGH>; 1585 power-domains = <&rpmhpd SC7280_CX>; 1586 operating-points-v2 = <&qup_opp_table>; 1587 interconnects = <&clk_virt MASTER_QUP_CORE_0 0 &clk_virt SLAVE_QUP_CORE_0 0>, 1588 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_0 0>; 1589 interconnect-names = "qup-core", "qup-config"; 1590 status = "disabled"; 1591 }; 1592 }; 1593 1594 gpi_dma1: dma-controller@a00000 { 1595 #dma-cells = <3>; 1596 compatible = "qcom,sc7280-gpi-dma", "qcom,sm6350-gpi-dma"; 1597 reg = <0 0x00a00000 0 0x60000>; 1598 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 284 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 293 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 294 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 296 IRQ_TYPE_LEVEL_HIGH>, 1608 <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH>, 1609 <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH>; 1610 dma-channels = <12>; 1611 dma-channel-mask = <0x1e>; 1612 iommus = <&apps_smmu 0x56 0x0>; 1613 status = "disabled"; 1614 }; 1615 1616 qupv3_id_1: geniqup@ac0000 { 1617 compatible = "qcom,geni-se-qup"; 1618 reg = <0 0x00ac0000 0 0x2000>; 1619 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AHB_CLK>, 1620 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1621 clock-names = "m-ahb", "s-ahb"; 1622 #address-cells = <2>; 1623 #size-cells = <2>; 1624 ranges; 1625 iommus = <&apps_smmu 0x43 0x0>; 1626 status = "disabled"; 1627 1628 i2c8: i2c@a80000 { 1629 compatible = "qcom,geni-i2c"; 1630 reg = <0 0x00a80000 0 0x4000>; 1631 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1632 clock-names = "se"; 1633 pinctrl-names = "default"; 1634 pinctrl-0 = <&qup_i2c8_data_clk>; 1635 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1636 #address-cells = <1>; 1637 #size-cells = <0>; 1638 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1639 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1640 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1641 interconnect-names = "qup-core", "qup-config", 1642 "qup-memory"; 1643 power-domains = <&rpmhpd SC7280_CX>; 1644 required-opps = <&rpmhpd_opp_low_svs>; 1645 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1646 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1647 dma-names = "tx", "rx"; 1648 status = "disabled"; 1649 }; 1650 1651 spi8: spi@a80000 { 1652 compatible = "qcom,geni-spi"; 1653 reg = <0 0x00a80000 0 0x4000>; 1654 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1655 clock-names = "se"; 1656 pinctrl-names = "default"; 1657 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 1658 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1659 #address-cells = <1>; 1660 #size-cells = <0>; 1661 power-domains = <&rpmhpd SC7280_CX>; 1662 operating-points-v2 = <&qup_opp_table>; 1663 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1664 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1665 interconnect-names = "qup-core", "qup-config"; 1666 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1667 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1668 dma-names = "tx", "rx"; 1669 status = "disabled"; 1670 }; 1671 1672 uart8: serial@a80000 { 1673 compatible = "qcom,geni-uart"; 1674 reg = <0 0x00a80000 0 0x4000>; 1675 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1676 clock-names = "se"; 1677 pinctrl-names = "default"; 1678 pinctrl-0 = <&qup_uart8_cts>, <&qup_uart8_rts>, <&qup_uart8_tx>, <&qup_uart8_rx>; 1679 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 1680 power-domains = <&rpmhpd SC7280_CX>; 1681 operating-points-v2 = <&qup_opp_table>; 1682 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1683 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1684 interconnect-names = "qup-core", "qup-config"; 1685 status = "disabled"; 1686 }; 1687 1688 i2c9: i2c@a84000 { 1689 compatible = "qcom,geni-i2c"; 1690 reg = <0 0x00a84000 0 0x4000>; 1691 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1692 clock-names = "se"; 1693 pinctrl-names = "default"; 1694 pinctrl-0 = <&qup_i2c9_data_clk>; 1695 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1696 #address-cells = <1>; 1697 #size-cells = <0>; 1698 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1699 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1700 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1701 interconnect-names = "qup-core", "qup-config", 1702 "qup-memory"; 1703 power-domains = <&rpmhpd SC7280_CX>; 1704 required-opps = <&rpmhpd_opp_low_svs>; 1705 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1706 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1707 dma-names = "tx", "rx"; 1708 status = "disabled"; 1709 }; 1710 1711 spi9: spi@a84000 { 1712 compatible = "qcom,geni-spi"; 1713 reg = <0 0x00a84000 0 0x4000>; 1714 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1715 clock-names = "se"; 1716 pinctrl-names = "default"; 1717 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 1718 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1719 #address-cells = <1>; 1720 #size-cells = <0>; 1721 power-domains = <&rpmhpd SC7280_CX>; 1722 operating-points-v2 = <&qup_opp_table>; 1723 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1724 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1725 interconnect-names = "qup-core", "qup-config"; 1726 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1727 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1728 dma-names = "tx", "rx"; 1729 status = "disabled"; 1730 }; 1731 1732 uart9: serial@a84000 { 1733 compatible = "qcom,geni-uart"; 1734 reg = <0 0x00a84000 0 0x4000>; 1735 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1736 clock-names = "se"; 1737 pinctrl-names = "default"; 1738 pinctrl-0 = <&qup_uart9_cts>, <&qup_uart9_rts>, <&qup_uart9_tx>, <&qup_uart9_rx>; 1739 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 1740 power-domains = <&rpmhpd SC7280_CX>; 1741 operating-points-v2 = <&qup_opp_table>; 1742 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1743 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1744 interconnect-names = "qup-core", "qup-config"; 1745 status = "disabled"; 1746 }; 1747 1748 i2c10: i2c@a88000 { 1749 compatible = "qcom,geni-i2c"; 1750 reg = <0 0x00a88000 0 0x4000>; 1751 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1752 clock-names = "se"; 1753 pinctrl-names = "default"; 1754 pinctrl-0 = <&qup_i2c10_data_clk>; 1755 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1756 #address-cells = <1>; 1757 #size-cells = <0>; 1758 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1759 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1760 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1761 interconnect-names = "qup-core", "qup-config", 1762 "qup-memory"; 1763 power-domains = <&rpmhpd SC7280_CX>; 1764 required-opps = <&rpmhpd_opp_low_svs>; 1765 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1766 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1767 dma-names = "tx", "rx"; 1768 status = "disabled"; 1769 }; 1770 1771 spi10: spi@a88000 { 1772 compatible = "qcom,geni-spi"; 1773 reg = <0 0x00a88000 0 0x4000>; 1774 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1775 clock-names = "se"; 1776 pinctrl-names = "default"; 1777 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 1778 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1779 #address-cells = <1>; 1780 #size-cells = <0>; 1781 power-domains = <&rpmhpd SC7280_CX>; 1782 operating-points-v2 = <&qup_opp_table>; 1783 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1784 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1785 interconnect-names = "qup-core", "qup-config"; 1786 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1787 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1788 dma-names = "tx", "rx"; 1789 status = "disabled"; 1790 }; 1791 1792 uart10: serial@a88000 { 1793 compatible = "qcom,geni-uart"; 1794 reg = <0 0x00a88000 0 0x4000>; 1795 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1796 clock-names = "se"; 1797 pinctrl-names = "default"; 1798 pinctrl-0 = <&qup_uart10_cts>, <&qup_uart10_rts>, <&qup_uart10_tx>, <&qup_uart10_rx>; 1799 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 1800 power-domains = <&rpmhpd SC7280_CX>; 1801 operating-points-v2 = <&qup_opp_table>; 1802 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1803 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1804 interconnect-names = "qup-core", "qup-config"; 1805 status = "disabled"; 1806 }; 1807 1808 i2c11: i2c@a8c000 { 1809 compatible = "qcom,geni-i2c"; 1810 reg = <0 0x00a8c000 0 0x4000>; 1811 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1812 clock-names = "se"; 1813 pinctrl-names = "default"; 1814 pinctrl-0 = <&qup_i2c11_data_clk>; 1815 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1816 #address-cells = <1>; 1817 #size-cells = <0>; 1818 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1819 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1820 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1821 interconnect-names = "qup-core", "qup-config", 1822 "qup-memory"; 1823 power-domains = <&rpmhpd SC7280_CX>; 1824 required-opps = <&rpmhpd_opp_low_svs>; 1825 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1826 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1827 dma-names = "tx", "rx"; 1828 status = "disabled"; 1829 }; 1830 1831 spi11: spi@a8c000 { 1832 compatible = "qcom,geni-spi"; 1833 reg = <0 0x00a8c000 0 0x4000>; 1834 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1835 clock-names = "se"; 1836 pinctrl-names = "default"; 1837 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 1838 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1839 #address-cells = <1>; 1840 #size-cells = <0>; 1841 power-domains = <&rpmhpd SC7280_CX>; 1842 operating-points-v2 = <&qup_opp_table>; 1843 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1844 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1845 interconnect-names = "qup-core", "qup-config"; 1846 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1847 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1848 dma-names = "tx", "rx"; 1849 status = "disabled"; 1850 }; 1851 1852 uart11: serial@a8c000 { 1853 compatible = "qcom,geni-uart"; 1854 reg = <0 0x00a8c000 0 0x4000>; 1855 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1856 clock-names = "se"; 1857 pinctrl-names = "default"; 1858 pinctrl-0 = <&qup_uart11_cts>, <&qup_uart11_rts>, <&qup_uart11_tx>, <&qup_uart11_rx>; 1859 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 1860 power-domains = <&rpmhpd SC7280_CX>; 1861 operating-points-v2 = <&qup_opp_table>; 1862 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1863 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1864 interconnect-names = "qup-core", "qup-config"; 1865 status = "disabled"; 1866 }; 1867 1868 i2c12: i2c@a90000 { 1869 compatible = "qcom,geni-i2c"; 1870 reg = <0 0x00a90000 0 0x4000>; 1871 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1872 clock-names = "se"; 1873 pinctrl-names = "default"; 1874 pinctrl-0 = <&qup_i2c12_data_clk>; 1875 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1876 #address-cells = <1>; 1877 #size-cells = <0>; 1878 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1879 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1880 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1881 interconnect-names = "qup-core", "qup-config", 1882 "qup-memory"; 1883 power-domains = <&rpmhpd SC7280_CX>; 1884 required-opps = <&rpmhpd_opp_low_svs>; 1885 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1886 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1887 dma-names = "tx", "rx"; 1888 status = "disabled"; 1889 }; 1890 1891 spi12: spi@a90000 { 1892 compatible = "qcom,geni-spi"; 1893 reg = <0 0x00a90000 0 0x4000>; 1894 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1895 clock-names = "se"; 1896 pinctrl-names = "default"; 1897 pinctrl-0 = <&qup_spi12_data_clk>, <&qup_spi12_cs>; 1898 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1899 #address-cells = <1>; 1900 #size-cells = <0>; 1901 power-domains = <&rpmhpd SC7280_CX>; 1902 operating-points-v2 = <&qup_opp_table>; 1903 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1904 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1905 interconnect-names = "qup-core", "qup-config"; 1906 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1907 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1908 dma-names = "tx", "rx"; 1909 status = "disabled"; 1910 }; 1911 1912 uart12: serial@a90000 { 1913 compatible = "qcom,geni-uart"; 1914 reg = <0 0x00a90000 0 0x4000>; 1915 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1916 clock-names = "se"; 1917 pinctrl-names = "default"; 1918 pinctrl-0 = <&qup_uart12_cts>, <&qup_uart12_rts>, <&qup_uart12_tx>, <&qup_uart12_rx>; 1919 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 1920 power-domains = <&rpmhpd SC7280_CX>; 1921 operating-points-v2 = <&qup_opp_table>; 1922 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1923 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1924 interconnect-names = "qup-core", "qup-config"; 1925 status = "disabled"; 1926 }; 1927 1928 i2c13: i2c@a94000 { 1929 compatible = "qcom,geni-i2c"; 1930 reg = <0 0x00a94000 0 0x4000>; 1931 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1932 clock-names = "se"; 1933 pinctrl-names = "default"; 1934 pinctrl-0 = <&qup_i2c13_data_clk>; 1935 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1936 #address-cells = <1>; 1937 #size-cells = <0>; 1938 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1939 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 1940 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 1941 interconnect-names = "qup-core", "qup-config", 1942 "qup-memory"; 1943 power-domains = <&rpmhpd SC7280_CX>; 1944 required-opps = <&rpmhpd_opp_low_svs>; 1945 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1946 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1947 dma-names = "tx", "rx"; 1948 status = "disabled"; 1949 }; 1950 1951 spi13: spi@a94000 { 1952 compatible = "qcom,geni-spi"; 1953 reg = <0 0x00a94000 0 0x4000>; 1954 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1955 clock-names = "se"; 1956 pinctrl-names = "default"; 1957 pinctrl-0 = <&qup_spi13_data_clk>, <&qup_spi13_cs>; 1958 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1959 #address-cells = <1>; 1960 #size-cells = <0>; 1961 power-domains = <&rpmhpd SC7280_CX>; 1962 operating-points-v2 = <&qup_opp_table>; 1963 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1964 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1965 interconnect-names = "qup-core", "qup-config"; 1966 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1967 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1968 dma-names = "tx", "rx"; 1969 status = "disabled"; 1970 }; 1971 1972 uart13: serial@a94000 { 1973 compatible = "qcom,geni-uart"; 1974 reg = <0 0x00a94000 0 0x4000>; 1975 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1976 clock-names = "se"; 1977 pinctrl-names = "default"; 1978 pinctrl-0 = <&qup_uart13_cts>, <&qup_uart13_rts>, <&qup_uart13_tx>, <&qup_uart13_rx>; 1979 interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH>; 1980 power-domains = <&rpmhpd SC7280_CX>; 1981 operating-points-v2 = <&qup_opp_table>; 1982 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1983 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 1984 interconnect-names = "qup-core", "qup-config"; 1985 status = "disabled"; 1986 }; 1987 1988 i2c14: i2c@a98000 { 1989 compatible = "qcom,geni-i2c"; 1990 reg = <0 0x00a98000 0 0x4000>; 1991 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1992 clock-names = "se"; 1993 pinctrl-names = "default"; 1994 pinctrl-0 = <&qup_i2c14_data_clk>; 1995 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 1996 #address-cells = <1>; 1997 #size-cells = <0>; 1998 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 1999 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 2000 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2001 interconnect-names = "qup-core", "qup-config", 2002 "qup-memory"; 2003 power-domains = <&rpmhpd SC7280_CX>; 2004 required-opps = <&rpmhpd_opp_low_svs>; 2005 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 2006 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 2007 dma-names = "tx", "rx"; 2008 status = "disabled"; 2009 }; 2010 2011 spi14: spi@a98000 { 2012 compatible = "qcom,geni-spi"; 2013 reg = <0 0x00a98000 0 0x4000>; 2014 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2015 clock-names = "se"; 2016 pinctrl-names = "default"; 2017 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 2018 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2019 #address-cells = <1>; 2020 #size-cells = <0>; 2021 power-domains = <&rpmhpd SC7280_CX>; 2022 operating-points-v2 = <&qup_opp_table>; 2023 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2024 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2025 interconnect-names = "qup-core", "qup-config"; 2026 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 2027 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 2028 dma-names = "tx", "rx"; 2029 status = "disabled"; 2030 }; 2031 2032 uart14: serial@a98000 { 2033 compatible = "qcom,geni-uart"; 2034 reg = <0 0x00a98000 0 0x4000>; 2035 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 2036 clock-names = "se"; 2037 pinctrl-names = "default"; 2038 pinctrl-0 = <&qup_uart14_cts>, <&qup_uart14_rts>, <&qup_uart14_tx>, <&qup_uart14_rx>; 2039 interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; 2040 power-domains = <&rpmhpd SC7280_CX>; 2041 operating-points-v2 = <&qup_opp_table>; 2042 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2043 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2044 interconnect-names = "qup-core", "qup-config"; 2045 status = "disabled"; 2046 }; 2047 2048 i2c15: i2c@a9c000 { 2049 compatible = "qcom,geni-i2c"; 2050 reg = <0 0x00a9c000 0 0x4000>; 2051 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2052 clock-names = "se"; 2053 pinctrl-names = "default"; 2054 pinctrl-0 = <&qup_i2c15_data_clk>; 2055 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2056 #address-cells = <1>; 2057 #size-cells = <0>; 2058 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2059 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>, 2060 <&aggre2_noc MASTER_QUP_1 0 &mc_virt SLAVE_EBI1 0>; 2061 interconnect-names = "qup-core", "qup-config", 2062 "qup-memory"; 2063 power-domains = <&rpmhpd SC7280_CX>; 2064 required-opps = <&rpmhpd_opp_low_svs>; 2065 dmas = <&gpi_dma1 0 7 QCOM_GPI_I2C>, 2066 <&gpi_dma1 1 7 QCOM_GPI_I2C>; 2067 dma-names = "tx", "rx"; 2068 status = "disabled"; 2069 }; 2070 2071 spi15: spi@a9c000 { 2072 compatible = "qcom,geni-spi"; 2073 reg = <0 0x00a9c000 0 0x4000>; 2074 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2075 clock-names = "se"; 2076 pinctrl-names = "default"; 2077 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 2078 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2079 #address-cells = <1>; 2080 #size-cells = <0>; 2081 power-domains = <&rpmhpd SC7280_CX>; 2082 operating-points-v2 = <&qup_opp_table>; 2083 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2084 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2085 interconnect-names = "qup-core", "qup-config"; 2086 dmas = <&gpi_dma1 0 7 QCOM_GPI_SPI>, 2087 <&gpi_dma1 1 7 QCOM_GPI_SPI>; 2088 dma-names = "tx", "rx"; 2089 status = "disabled"; 2090 }; 2091 2092 uart15: serial@a9c000 { 2093 compatible = "qcom,geni-uart"; 2094 reg = <0 0x00a9c000 0 0x4000>; 2095 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 2096 clock-names = "se"; 2097 pinctrl-names = "default"; 2098 pinctrl-0 = <&qup_uart15_cts>, <&qup_uart15_rts>, <&qup_uart15_tx>, <&qup_uart15_rx>; 2099 interrupts = <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; 2100 power-domains = <&rpmhpd SC7280_CX>; 2101 operating-points-v2 = <&qup_opp_table>; 2102 interconnects = <&clk_virt MASTER_QUP_CORE_1 0 &clk_virt SLAVE_QUP_CORE_1 0>, 2103 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_QUP_1 0>; 2104 interconnect-names = "qup-core", "qup-config"; 2105 status = "disabled"; 2106 }; 2107 }; 2108 2109 rng: rng@10d3000 { 2110 compatible = "qcom,sc7280-trng", "qcom,trng"; 2111 reg = <0 0x010d3000 0 0x1000>; 2112 }; 2113 2114 cnoc2: interconnect@1500000 { 2115 reg = <0 0x01500000 0 0x1000>; 2116 compatible = "qcom,sc7280-cnoc2"; 2117 #interconnect-cells = <2>; 2118 qcom,bcm-voters = <&apps_bcm_voter>; 2119 }; 2120 2121 cnoc3: interconnect@1502000 { 2122 reg = <0 0x01502000 0 0x1000>; 2123 compatible = "qcom,sc7280-cnoc3"; 2124 #interconnect-cells = <2>; 2125 qcom,bcm-voters = <&apps_bcm_voter>; 2126 }; 2127 2128 mc_virt: interconnect@1580000 { 2129 reg = <0 0x01580000 0 0x4>; 2130 compatible = "qcom,sc7280-mc-virt"; 2131 #interconnect-cells = <2>; 2132 qcom,bcm-voters = <&apps_bcm_voter>; 2133 }; 2134 2135 system_noc: interconnect@1680000 { 2136 reg = <0 0x01680000 0 0x15480>; 2137 compatible = "qcom,sc7280-system-noc"; 2138 #interconnect-cells = <2>; 2139 qcom,bcm-voters = <&apps_bcm_voter>; 2140 }; 2141 2142 aggre1_noc: interconnect@16e0000 { 2143 compatible = "qcom,sc7280-aggre1-noc"; 2144 reg = <0 0x016e0000 0 0x1c080>; 2145 #interconnect-cells = <2>; 2146 qcom,bcm-voters = <&apps_bcm_voter>; 2147 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2148 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 2149 }; 2150 2151 aggre2_noc: interconnect@1700000 { 2152 reg = <0 0x01700000 0 0x2b080>; 2153 compatible = "qcom,sc7280-aggre2-noc"; 2154 #interconnect-cells = <2>; 2155 qcom,bcm-voters = <&apps_bcm_voter>; 2156 clocks = <&rpmhcc RPMH_IPA_CLK>; 2157 }; 2158 2159 mmss_noc: interconnect@1740000 { 2160 reg = <0 0x01740000 0 0x1e080>; 2161 compatible = "qcom,sc7280-mmss-noc"; 2162 #interconnect-cells = <2>; 2163 qcom,bcm-voters = <&apps_bcm_voter>; 2164 }; 2165 2166 wifi: wifi@17a10040 { 2167 compatible = "qcom,wcn6750-wifi"; 2168 reg = <0 0x17a10040 0 0x0>; 2169 iommus = <&apps_smmu 0x1c00 0x1>; 2170 interrupts = <GIC_SPI 768 IRQ_TYPE_EDGE_RISING>, 2171 <GIC_SPI 769 IRQ_TYPE_EDGE_RISING>, 2172 <GIC_SPI 770 IRQ_TYPE_EDGE_RISING>, 2173 <GIC_SPI 771 IRQ_TYPE_EDGE_RISING>, 2174 <GIC_SPI 772 IRQ_TYPE_EDGE_RISING>, 2175 <GIC_SPI 773 IRQ_TYPE_EDGE_RISING>, 2176 <GIC_SPI 774 IRQ_TYPE_EDGE_RISING>, 2177 <GIC_SPI 775 IRQ_TYPE_EDGE_RISING>, 2178 <GIC_SPI 776 IRQ_TYPE_EDGE_RISING>, 2179 <GIC_SPI 777 IRQ_TYPE_EDGE_RISING>, 2180 <GIC_SPI 778 IRQ_TYPE_EDGE_RISING>, 2181 <GIC_SPI 779 IRQ_TYPE_EDGE_RISING>, 2182 <GIC_SPI 780 IRQ_TYPE_EDGE_RISING>, 2183 <GIC_SPI 781 IRQ_TYPE_EDGE_RISING>, 2184 <GIC_SPI 782 IRQ_TYPE_EDGE_RISING>, 2185 <GIC_SPI 783 IRQ_TYPE_EDGE_RISING>, 2186 <GIC_SPI 784 IRQ_TYPE_EDGE_RISING>, 2187 <GIC_SPI 785 IRQ_TYPE_EDGE_RISING>, 2188 <GIC_SPI 786 IRQ_TYPE_EDGE_RISING>, 2189 <GIC_SPI 787 IRQ_TYPE_EDGE_RISING>, 2190 <GIC_SPI 788 IRQ_TYPE_EDGE_RISING>, 2191 <GIC_SPI 789 IRQ_TYPE_EDGE_RISING>, 2192 <GIC_SPI 790 IRQ_TYPE_EDGE_RISING>, 2193 <GIC_SPI 791 IRQ_TYPE_EDGE_RISING>, 2194 <GIC_SPI 792 IRQ_TYPE_EDGE_RISING>, 2195 <GIC_SPI 793 IRQ_TYPE_EDGE_RISING>, 2196 <GIC_SPI 794 IRQ_TYPE_EDGE_RISING>, 2197 <GIC_SPI 795 IRQ_TYPE_EDGE_RISING>, 2198 <GIC_SPI 796 IRQ_TYPE_EDGE_RISING>, 2199 <GIC_SPI 797 IRQ_TYPE_EDGE_RISING>, 2200 <GIC_SPI 798 IRQ_TYPE_EDGE_RISING>, 2201 <GIC_SPI 799 IRQ_TYPE_EDGE_RISING>; 2202 qcom,rproc = <&remoteproc_wpss>; 2203 memory-region = <&wlan_fw_mem>, <&wlan_ce_mem>; 2204 status = "disabled"; 2205 qcom,smem-states = <&wlan_smp2p_out 0>; 2206 qcom,smem-state-names = "wlan-smp2p-out"; 2207 }; 2208 2209 pcie0: pcie@1c00000 { 2210 compatible = "qcom,pcie-sc7280"; 2211 reg = <0 0x01c00000 0 0x3000>, 2212 <0 0x60000000 0 0xf1d>, 2213 <0 0x60000f20 0 0xa8>, 2214 <0 0x60001000 0 0x1000>, 2215 <0 0x60100000 0 0x100000>, 2216 <0 0x01c03000 0 0x1000>; 2217 reg-names = "parf", "dbi", "elbi", "atu", "config", "mhi"; 2218 device_type = "pci"; 2219 linux,pci-domain = <0>; 2220 bus-range = <0x00 0xff>; 2221 num-lanes = <1>; 2222 2223 #address-cells = <3>; 2224 #size-cells = <2>; 2225 2226 ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>, 2227 <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0x3d00000>; 2228 2229 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2230 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2231 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2232 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2233 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2234 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2235 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2236 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2237 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2238 interrupt-names = "msi0", 2239 "msi1", 2240 "msi2", 2241 "msi3", 2242 "msi4", 2243 "msi5", 2244 "msi6", 2245 "msi7", 2246 "global"; 2247 #interrupt-cells = <1>; 2248 interrupt-map-mask = <0 0 0 0x7>; 2249 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 2250 <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 2251 <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 2252 <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; 2253 2254 clocks = <&gcc GCC_PCIE_0_PIPE_CLK>, 2255 <&gcc GCC_PCIE_0_PIPE_CLK_SRC>, 2256 <&pcie0_phy>, 2257 <&rpmhcc RPMH_CXO_CLK>, 2258 <&gcc GCC_PCIE_0_AUX_CLK>, 2259 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2260 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2261 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2262 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2263 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2264 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2265 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2266 <&gcc GCC_AGGRE_NOC_PCIE_0_AXI_CLK>; 2267 clock-names = "pipe", 2268 "pipe_mux", 2269 "phy_pipe", 2270 "ref", 2271 "aux", 2272 "cfg", 2273 "bus_master", 2274 "bus_slave", 2275 "slave_q2a", 2276 "tbu", 2277 "ddrss_sf_tbu", 2278 "aggre0", 2279 "aggre1"; 2280 2281 iommu-map = <0x0 &apps_smmu 0x1c00 0x1>, 2282 <0x100 &apps_smmu 0x1c01 0x1>; 2283 2284 resets = <&gcc GCC_PCIE_0_BCR>; 2285 reset-names = "pci"; 2286 2287 power-domains = <&gcc GCC_PCIE_0_GDSC>; 2288 2289 phys = <&pcie0_phy>; 2290 phy-names = "pciephy"; 2291 2292 pinctrl-names = "default"; 2293 pinctrl-0 = <&pcie0_clkreq_n>; 2294 dma-coherent; 2295 2296 status = "disabled"; 2297 2298 pcie0_port: pcie@0 { 2299 device_type = "pci"; 2300 reg = <0x0 0x0 0x0 0x0 0x0>; 2301 bus-range = <0x01 0xff>; 2302 2303 #address-cells = <3>; 2304 #size-cells = <2>; 2305 ranges; 2306 }; 2307 }; 2308 2309 pcie0_phy: phy@1c06000 { 2310 compatible = "qcom,sm8250-qmp-gen3x1-pcie-phy"; 2311 reg = <0 0x01c06000 0 0x1000>; 2312 2313 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2314 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2315 <&gcc GCC_PCIE_CLKREF_EN>, 2316 <&gcc GCC_PCIE0_PHY_RCHNG_CLK>, 2317 <&gcc GCC_PCIE_0_PIPE_CLK>; 2318 clock-names = "aux", 2319 "cfg_ahb", 2320 "ref", 2321 "refgen", 2322 "pipe"; 2323 2324 clock-output-names = "pcie_0_pipe_clk"; 2325 #clock-cells = <0>; 2326 2327 #phy-cells = <0>; 2328 2329 resets = <&gcc GCC_PCIE_0_PHY_BCR>; 2330 reset-names = "phy"; 2331 2332 assigned-clocks = <&gcc GCC_PCIE0_PHY_RCHNG_CLK>; 2333 assigned-clock-rates = <100000000>; 2334 2335 status = "disabled"; 2336 }; 2337 2338 pcie1: pcie@1c08000 { 2339 compatible = "qcom,pcie-sc7280"; 2340 reg = <0 0x01c08000 0 0x3000>, 2341 <0 0x40000000 0 0xf1d>, 2342 <0 0x40000f20 0 0xa8>, 2343 <0 0x40001000 0 0x1000>, 2344 <0 0x40100000 0 0x100000>; 2345 2346 reg-names = "parf", "dbi", "elbi", "atu", "config"; 2347 device_type = "pci"; 2348 linux,pci-domain = <1>; 2349 bus-range = <0x00 0xff>; 2350 num-lanes = <2>; 2351 2352 #address-cells = <3>; 2353 #size-cells = <2>; 2354 2355 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2356 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x1fd00000>; 2357 2358 interrupts = <GIC_SPI 307 IRQ_TYPE_LEVEL_HIGH>, 2359 <GIC_SPI 308 IRQ_TYPE_LEVEL_HIGH>, 2360 <GIC_SPI 309 IRQ_TYPE_LEVEL_HIGH>, 2361 <GIC_SPI 312 IRQ_TYPE_LEVEL_HIGH>, 2362 <GIC_SPI 313 IRQ_TYPE_LEVEL_HIGH>, 2363 <GIC_SPI 314 IRQ_TYPE_LEVEL_HIGH>, 2364 <GIC_SPI 374 IRQ_TYPE_LEVEL_HIGH>, 2365 <GIC_SPI 375 IRQ_TYPE_LEVEL_HIGH>, 2366 <GIC_SPI 306 IRQ_TYPE_LEVEL_HIGH>; 2367 interrupt-names = "msi0", 2368 "msi1", 2369 "msi2", 2370 "msi3", 2371 "msi4", 2372 "msi5", 2373 "msi6", 2374 "msi7", 2375 "global"; 2376 #interrupt-cells = <1>; 2377 interrupt-map-mask = <0 0 0 0x7>; 2378 interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 434 IRQ_TYPE_LEVEL_HIGH>, 2379 <0 0 0 2 &intc 0 0 GIC_SPI 435 IRQ_TYPE_LEVEL_HIGH>, 2380 <0 0 0 3 &intc 0 0 GIC_SPI 438 IRQ_TYPE_LEVEL_HIGH>, 2381 <0 0 0 4 &intc 0 0 GIC_SPI 439 IRQ_TYPE_LEVEL_HIGH>; 2382 2383 clocks = <&gcc GCC_PCIE_1_PIPE_CLK>, 2384 <&gcc GCC_PCIE_1_PIPE_CLK_SRC>, 2385 <&pcie1_phy>, 2386 <&rpmhcc RPMH_CXO_CLK>, 2387 <&gcc GCC_PCIE_1_AUX_CLK>, 2388 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2389 <&gcc GCC_PCIE_1_MSTR_AXI_CLK>, 2390 <&gcc GCC_PCIE_1_SLV_AXI_CLK>, 2391 <&gcc GCC_PCIE_1_SLV_Q2A_AXI_CLK>, 2392 <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>, 2393 <&gcc GCC_DDRSS_PCIE_SF_CLK>, 2394 <&gcc GCC_AGGRE_NOC_PCIE_CENTER_SF_AXI_CLK>, 2395 <&gcc GCC_AGGRE_NOC_PCIE_1_AXI_CLK>; 2396 2397 clock-names = "pipe", 2398 "pipe_mux", 2399 "phy_pipe", 2400 "ref", 2401 "aux", 2402 "cfg", 2403 "bus_master", 2404 "bus_slave", 2405 "slave_q2a", 2406 "tbu", 2407 "ddrss_sf_tbu", 2408 "aggre0", 2409 "aggre1"; 2410 2411 assigned-clocks = <&gcc GCC_PCIE_1_AUX_CLK>; 2412 assigned-clock-rates = <19200000>; 2413 2414 resets = <&gcc GCC_PCIE_1_BCR>; 2415 reset-names = "pci"; 2416 2417 power-domains = <&gcc GCC_PCIE_1_GDSC>; 2418 2419 phys = <&pcie1_phy>; 2420 phy-names = "pciephy"; 2421 2422 pinctrl-names = "default"; 2423 pinctrl-0 = <&pcie1_clkreq_n>; 2424 2425 dma-coherent; 2426 2427 iommu-map = <0x0 &apps_smmu 0x1c80 0x1>, 2428 <0x100 &apps_smmu 0x1c81 0x1>; 2429 2430 status = "disabled"; 2431 2432 pcie1_port0: pcie@0 { 2433 device_type = "pci"; 2434 reg = <0x0 0x0 0x0 0x0 0x0>; 2435 bus-range = <0x01 0xff>; 2436 2437 #address-cells = <3>; 2438 #size-cells = <2>; 2439 ranges; 2440 }; 2441 }; 2442 2443 pcie1_phy: phy@1c0e000 { 2444 compatible = "qcom,sm8250-qmp-gen3x2-pcie-phy"; 2445 reg = <0 0x01c0e000 0 0x1000>; 2446 clocks = <&gcc GCC_PCIE_1_AUX_CLK>, 2447 <&gcc GCC_PCIE_1_CFG_AHB_CLK>, 2448 <&rpmhcc RPMH_CXO_CLK>, 2449 <&gcc GCC_PCIE1_PHY_RCHNG_CLK>, 2450 <&gcc GCC_PCIE_1_PIPE_CLK>; 2451 clock-names = "aux", 2452 "cfg_ahb", 2453 "ref", 2454 "refgen", 2455 "pipe"; 2456 2457 clock-output-names = "pcie_1_pipe_clk"; 2458 #clock-cells = <0>; 2459 2460 #phy-cells = <0>; 2461 2462 resets = <&gcc GCC_PCIE_1_PHY_BCR>; 2463 reset-names = "phy"; 2464 2465 assigned-clocks = <&gcc GCC_PCIE1_PHY_RCHNG_CLK>; 2466 assigned-clock-rates = <100000000>; 2467 2468 status = "disabled"; 2469 }; 2470 2471 ufs_mem_hc: ufshc@1d84000 { 2472 compatible = "qcom,sc7280-ufshc", "qcom,ufshc", 2473 "jedec,ufs-2.0"; 2474 reg = <0x0 0x01d84000 0x0 0x3000>; 2475 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2476 phys = <&ufs_mem_phy>; 2477 phy-names = "ufsphy"; 2478 lanes-per-direction = <2>; 2479 #reset-cells = <1>; 2480 resets = <&gcc GCC_UFS_PHY_BCR>; 2481 reset-names = "rst"; 2482 2483 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2484 required-opps = <&rpmhpd_opp_nom>; 2485 2486 iommus = <&apps_smmu 0x80 0x0>; 2487 dma-coherent; 2488 2489 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2490 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2491 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 2492 &cnoc2 SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ALWAYS>; 2493 interconnect-names = "ufs-ddr", "cpu-ufs"; 2494 2495 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2496 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2497 <&gcc GCC_UFS_PHY_AHB_CLK>, 2498 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2499 <&rpmhcc RPMH_CXO_CLK>, 2500 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2501 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2502 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2503 clock-names = "core_clk", 2504 "bus_aggr_clk", 2505 "iface_clk", 2506 "core_clk_unipro", 2507 "ref_clk", 2508 "tx_lane0_sync_clk", 2509 "rx_lane0_sync_clk", 2510 "rx_lane1_sync_clk"; 2511 2512 operating-points-v2 = <&ufs_opp_table>; 2513 2514 qcom,ice = <&ice>; 2515 2516 status = "disabled"; 2517 2518 ufs_opp_table: opp-table { 2519 compatible = "operating-points-v2"; 2520 2521 opp-75000000 { 2522 opp-hz = /bits/ 64 <75000000>, 2523 /bits/ 64 <0>, 2524 /bits/ 64 <0>, 2525 /bits/ 64 <75000000>, 2526 /bits/ 64 <0>, 2527 /bits/ 64 <0>, 2528 /bits/ 64 <0>, 2529 /bits/ 64 <0>; 2530 required-opps = <&rpmhpd_opp_low_svs>; 2531 }; 2532 2533 opp-150000000 { 2534 opp-hz = /bits/ 64 <150000000>, 2535 /bits/ 64 <0>, 2536 /bits/ 64 <0>, 2537 /bits/ 64 <150000000>, 2538 /bits/ 64 <0>, 2539 /bits/ 64 <0>, 2540 /bits/ 64 <0>, 2541 /bits/ 64 <0>; 2542 required-opps = <&rpmhpd_opp_svs>; 2543 }; 2544 2545 opp-300000000 { 2546 opp-hz = /bits/ 64 <300000000>, 2547 /bits/ 64 <0>, 2548 /bits/ 64 <0>, 2549 /bits/ 64 <300000000>, 2550 /bits/ 64 <0>, 2551 /bits/ 64 <0>, 2552 /bits/ 64 <0>, 2553 /bits/ 64 <0>; 2554 required-opps = <&rpmhpd_opp_nom>; 2555 }; 2556 }; 2557 }; 2558 2559 ufs_mem_phy: phy@1d87000 { 2560 compatible = "qcom,sc7280-qmp-ufs-phy"; 2561 reg = <0x0 0x01d87000 0x0 0xe00>; 2562 clocks = <&rpmhcc RPMH_CXO_CLK>, 2563 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2564 <&gcc GCC_UFS_1_CLKREF_EN>; 2565 clock-names = "ref", "ref_aux", "qref"; 2566 2567 power-domains = <&rpmhpd SC7280_MX>; 2568 2569 resets = <&ufs_mem_hc 0>; 2570 reset-names = "ufsphy"; 2571 2572 #clock-cells = <1>; 2573 #phy-cells = <0>; 2574 2575 status = "disabled"; 2576 }; 2577 2578 ice: crypto@1d88000 { 2579 compatible = "qcom,sc7280-inline-crypto-engine", 2580 "qcom,inline-crypto-engine"; 2581 reg = <0 0x01d88000 0 0x8000>; 2582 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2583 }; 2584 2585 cryptobam: dma-controller@1dc4000 { 2586 compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0"; 2587 reg = <0x0 0x01dc4000 0x0 0x28000>; 2588 interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; 2589 #dma-cells = <1>; 2590 iommus = <&apps_smmu 0x4e4 0x0011>, 2591 <&apps_smmu 0x4e6 0x0011>; 2592 qcom,ee = <0>; 2593 qcom,controlled-remotely; 2594 num-channels = <16>; 2595 qcom,num-ees = <4>; 2596 }; 2597 2598 crypto: crypto@1dfa000 { 2599 compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce"; 2600 reg = <0x0 0x01dfa000 0x0 0x6000>; 2601 dmas = <&cryptobam 4>, <&cryptobam 5>; 2602 dma-names = "rx", "tx"; 2603 iommus = <&apps_smmu 0x4e4 0x0011>, 2604 <&apps_smmu 0x4e4 0x0011>; 2605 interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>; 2606 interconnect-names = "memory"; 2607 }; 2608 2609 ipa: ipa@1e40000 { 2610 compatible = "qcom,sc7280-ipa"; 2611 2612 iommus = <&apps_smmu 0x480 0x0>, 2613 <&apps_smmu 0x482 0x0>; 2614 reg = <0 0x01e40000 0 0x8000>, 2615 <0 0x01e50000 0 0x4ad0>, 2616 <0 0x01e04000 0 0x23000>; 2617 reg-names = "ipa-reg", 2618 "ipa-shared", 2619 "gsi"; 2620 2621 interrupts-extended = <&intc GIC_SPI 654 IRQ_TYPE_EDGE_RISING>, 2622 <&intc GIC_SPI 432 IRQ_TYPE_LEVEL_HIGH>, 2623 <&ipa_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 2624 <&ipa_smp2p_in 1 IRQ_TYPE_EDGE_RISING>; 2625 interrupt-names = "ipa", 2626 "gsi", 2627 "ipa-clock-query", 2628 "ipa-setup-ready"; 2629 2630 clocks = <&rpmhcc RPMH_IPA_CLK>; 2631 clock-names = "core"; 2632 2633 interconnects = <&aggre2_noc MASTER_IPA 0 &mc_virt SLAVE_EBI1 0>, 2634 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_IPA_CFG 0>; 2635 interconnect-names = "memory", 2636 "config"; 2637 2638 qcom,qmp = <&aoss_qmp>; 2639 2640 qcom,smem-states = <&ipa_smp2p_out 0>, 2641 <&ipa_smp2p_out 1>; 2642 qcom,smem-state-names = "ipa-clock-enabled-valid", 2643 "ipa-clock-enabled"; 2644 2645 sram = <&ipa_modem_tables>; 2646 2647 status = "disabled"; 2648 }; 2649 2650 tcsr_mutex: hwlock@1f40000 { 2651 compatible = "qcom,tcsr-mutex"; 2652 reg = <0 0x01f40000 0 0x20000>; 2653 #hwlock-cells = <1>; 2654 }; 2655 2656 tcsr_1: syscon@1f60000 { 2657 compatible = "qcom,sc7280-tcsr", "syscon"; 2658 reg = <0 0x01f60000 0 0x20000>; 2659 }; 2660 2661 tcsr_2: syscon@1fc0000 { 2662 compatible = "qcom,sc7280-tcsr", "syscon"; 2663 reg = <0 0x01fc0000 0 0x30000>; 2664 }; 2665 2666 lpasscc: lpasscc@3000000 { 2667 compatible = "qcom,sc7280-lpasscc"; 2668 reg = <0 0x03000000 0 0x40>, 2669 <0 0x03c04000 0 0x4>; 2670 reg-names = "qdsp6ss", "top_cc"; 2671 clocks = <&gcc GCC_CFG_NOC_LPASS_CLK>; 2672 clock-names = "iface"; 2673 #clock-cells = <1>; 2674 status = "reserved"; /* Owned by ADSP firmware */ 2675 }; 2676 2677 lpass_rx_macro: codec@3200000 { 2678 compatible = "qcom,sc7280-lpass-rx-macro"; 2679 reg = <0 0x03200000 0 0x1000>; 2680 2681 pinctrl-names = "default"; 2682 pinctrl-0 = <&lpass_rx_swr_clk>, <&lpass_rx_swr_data>; 2683 2684 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2685 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2686 <&lpass_va_macro>; 2687 clock-names = "mclk", "npl", "fsgen"; 2688 2689 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2690 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2691 power-domain-names = "macro", "dcodec"; 2692 2693 #clock-cells = <0>; 2694 #sound-dai-cells = <1>; 2695 2696 status = "disabled"; 2697 }; 2698 2699 swr0: soundwire@3210000 { 2700 compatible = "qcom,soundwire-v1.6.0"; 2701 reg = <0 0x03210000 0 0x2000>; 2702 2703 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2704 clocks = <&lpass_rx_macro>; 2705 clock-names = "iface"; 2706 2707 qcom,din-ports = <0>; 2708 qcom,dout-ports = <5>; 2709 2710 resets = <&lpass_audiocc LPASS_AUDIO_SWR_RX_CGCR>; 2711 reset-names = "swr_audio_cgcr"; 2712 2713 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff>; 2714 qcom,ports-sinterval-low = /bits/ 8 <0x03 0x3f 0x1f 0x03 0x03>; 2715 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x01>; 2716 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00>; 2717 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00>; 2718 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff>; 2719 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff>; 2720 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff>; 2721 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00>; 2722 2723 #sound-dai-cells = <1>; 2724 #address-cells = <2>; 2725 #size-cells = <0>; 2726 2727 status = "disabled"; 2728 }; 2729 2730 lpass_tx_macro: codec@3220000 { 2731 compatible = "qcom,sc7280-lpass-tx-macro"; 2732 reg = <0 0x03220000 0 0x1000>; 2733 2734 pinctrl-names = "default"; 2735 pinctrl-0 = <&lpass_tx_swr_clk>, <&lpass_tx_swr_data>; 2736 2737 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2738 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2739 <&lpass_va_macro>; 2740 clock-names = "mclk", "npl", "fsgen"; 2741 2742 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2743 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2744 power-domain-names = "macro", "dcodec"; 2745 2746 #clock-cells = <0>; 2747 #sound-dai-cells = <1>; 2748 2749 status = "disabled"; 2750 }; 2751 2752 swr1: soundwire@3230000 { 2753 compatible = "qcom,soundwire-v1.6.0"; 2754 reg = <0 0x03230000 0 0x2000>; 2755 2756 interrupts-extended = <&intc GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 2757 <&pdc 130 IRQ_TYPE_LEVEL_HIGH>; 2758 clocks = <&lpass_tx_macro>; 2759 clock-names = "iface"; 2760 2761 qcom,din-ports = <3>; 2762 qcom,dout-ports = <0>; 2763 2764 resets = <&lpass_audiocc LPASS_AUDIO_SWR_TX_CGCR>; 2765 reset-names = "swr_audio_cgcr"; 2766 2767 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x03 0x03>; 2768 qcom,ports-offset1 = /bits/ 8 <0x01 0x00 0x02>; 2769 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00>; 2770 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff>; 2771 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff>; 2772 qcom,ports-word-length = /bits/ 8 <0xff 0x00 0xff>; 2773 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff>; 2774 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff>; 2775 qcom,ports-lane-control = /bits/ 8 <0x00 0x01 0x00>; 2776 2777 #sound-dai-cells = <1>; 2778 #address-cells = <2>; 2779 #size-cells = <0>; 2780 2781 status = "disabled"; 2782 }; 2783 2784 lpass_wsa_macro: codec@3240000 { 2785 compatible = "qcom,sc7280-lpass-wsa-macro"; 2786 reg = <0x0 0x03240000 0x0 0x1000>; 2787 2788 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>, 2789 <&lpass_aon LPASS_AON_CC_TX_MCLK_2X_CLK>, 2790 <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2791 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2792 <&lpass_va_macro>; 2793 clock-names = "mclk", 2794 "npl", 2795 "macro", 2796 "dcodec", 2797 "fsgen"; 2798 2799 pinctrl-0 = <&lpass_wsa_swr_clk>, <&lpass_wsa_swr_data>; 2800 pinctrl-names = "default"; 2801 2802 #clock-cells = <0>; 2803 clock-output-names = "mclk"; 2804 #sound-dai-cells = <1>; 2805 2806 status = "disabled"; 2807 }; 2808 2809 swr2: soundwire@3250000 { 2810 compatible = "qcom,soundwire-v1.6.0"; 2811 reg = <0x0 0x03250000 0x0 0x2000>; 2812 2813 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2814 clocks = <&lpass_wsa_macro>; 2815 clock-names = "iface"; 2816 2817 resets = <&lpass_audiocc LPASS_AUDIO_SWR_WSA_CGCR>; 2818 reset-names = "swr_audio_cgcr"; 2819 2820 qcom,din-ports = <2>; 2821 qcom,dout-ports = <6>; 2822 2823 qcom,ports-sinterval-low = /bits/ 8 <0x07 0x1f 0x3f 0x07 2824 0x1f 0x3f 0x0f 0x0f>; 2825 qcom,ports-offset1 = /bits/ 8 <0x01 0x02 0x0c 0x06 0x12 0x0d 0x07 0x0a>; 2826 qcom,ports-offset2 = /bits/ 8 <0xff 0x00 0x1f 0xff 0x00 0x1f 0x00 0x00>; 2827 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2828 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2829 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2830 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0x01 0xff 0xff 0x01 2831 0xff 0xff>; 2832 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 2833 0xff 0xff>; 2834 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 2835 0xff 0xff>; 2836 2837 #address-cells = <2>; 2838 #size-cells = <0>; 2839 #sound-dai-cells = <1>; 2840 2841 status = "disabled"; 2842 }; 2843 2844 lpass_audiocc: clock-controller@3300000 { 2845 compatible = "qcom,sc7280-lpassaudiocc"; 2846 reg = <0 0x03300000 0 0x30000>, 2847 <0 0x032a9000 0 0x1000>; 2848 clocks = <&rpmhcc RPMH_CXO_CLK>, 2849 <&lpass_aon LPASS_AON_CC_MAIN_RCG_CLK_SRC>; 2850 clock-names = "bi_tcxo", "lpass_aon_cc_main_rcg_clk_src"; 2851 power-domains = <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2852 #clock-cells = <1>; 2853 #power-domain-cells = <1>; 2854 #reset-cells = <1>; 2855 }; 2856 2857 lpass_va_macro: codec@3370000 { 2858 compatible = "qcom,sc7280-lpass-va-macro"; 2859 reg = <0 0x03370000 0 0x1000>; 2860 2861 clocks = <&lpass_aon LPASS_AON_CC_TX_MCLK_CLK>; 2862 clock-names = "mclk"; 2863 2864 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>, 2865 <&lpass_aon LPASS_AON_CC_LPASS_AUDIO_HM_GDSC>; 2866 power-domain-names = "macro", "dcodec"; 2867 2868 #clock-cells = <0>; 2869 #sound-dai-cells = <1>; 2870 2871 status = "disabled"; 2872 }; 2873 2874 lpass_aon: clock-controller@3380000 { 2875 compatible = "qcom,sc7280-lpassaoncc"; 2876 reg = <0 0x03380000 0 0x30000>; 2877 clocks = <&rpmhcc RPMH_CXO_CLK>, 2878 <&rpmhcc RPMH_CXO_CLK_A>, 2879 <&lpass_core LPASS_CORE_CC_CORE_CLK>; 2880 clock-names = "bi_tcxo", "bi_tcxo_ao", "iface"; 2881 #clock-cells = <1>; 2882 #power-domain-cells = <1>; 2883 status = "reserved"; /* Owned by ADSP firmware */ 2884 }; 2885 2886 lpass_core: clock-controller@3900000 { 2887 compatible = "qcom,sc7280-lpasscorecc"; 2888 reg = <0 0x03900000 0 0x50000>; 2889 clocks = <&rpmhcc RPMH_CXO_CLK>; 2890 clock-names = "bi_tcxo"; 2891 power-domains = <&lpass_hm LPASS_CORE_CC_LPASS_CORE_HM_GDSC>; 2892 #clock-cells = <1>; 2893 #power-domain-cells = <1>; 2894 status = "reserved"; /* Owned by ADSP firmware */ 2895 }; 2896 2897 lpass_cpu: audio@3987000 { 2898 compatible = "qcom,sc7280-lpass-cpu"; 2899 2900 reg = <0 0x03987000 0 0x68000>, 2901 <0 0x03b00000 0 0x29000>, 2902 <0 0x03260000 0 0xc000>, 2903 <0 0x03280000 0 0x29000>, 2904 <0 0x03340000 0 0x29000>, 2905 <0 0x0336c000 0 0x3000>; 2906 reg-names = "lpass-hdmiif", 2907 "lpass-lpaif", 2908 "lpass-rxtx-cdc-dma-lpm", 2909 "lpass-rxtx-lpaif", 2910 "lpass-va-lpaif", 2911 "lpass-va-cdc-dma-lpm"; 2912 2913 iommus = <&apps_smmu 0x1820 0>, 2914 <&apps_smmu 0x1821 0>, 2915 <&apps_smmu 0x1832 0>; 2916 2917 power-domains = <&rpmhpd SC7280_LCX>; 2918 power-domain-names = "lcx"; 2919 required-opps = <&rpmhpd_opp_nom>; 2920 2921 clocks = <&lpass_aon LPASS_AON_CC_AUDIO_HM_H_CLK>, 2922 <&lpass_core LPASS_CORE_CC_EXT_MCLK0_CLK>, 2923 <&lpass_core LPASS_CORE_CC_SYSNOC_MPORT_CORE_CLK>, 2924 <&lpass_core LPASS_CORE_CC_EXT_IF0_IBIT_CLK>, 2925 <&lpass_core LPASS_CORE_CC_EXT_IF1_IBIT_CLK>, 2926 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM_CLK>, 2927 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM0_CLK>, 2928 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM1_CLK>, 2929 <&lpass_audiocc LPASS_AUDIO_CC_CODEC_MEM2_CLK>, 2930 <&lpass_aon LPASS_AON_CC_VA_MEM0_CLK>; 2931 clock-names = "aon_cc_audio_hm_h", 2932 "audio_cc_ext_mclk0", 2933 "core_cc_sysnoc_mport_core", 2934 "core_cc_ext_if0_ibit", 2935 "core_cc_ext_if1_ibit", 2936 "audio_cc_codec_mem", 2937 "audio_cc_codec_mem0", 2938 "audio_cc_codec_mem1", 2939 "audio_cc_codec_mem2", 2940 "aon_cc_va_mem0"; 2941 2942 #sound-dai-cells = <1>; 2943 #address-cells = <1>; 2944 #size-cells = <0>; 2945 2946 interrupts = <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, 2947 <GIC_SPI 268 IRQ_TYPE_LEVEL_HIGH>, 2948 <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 2949 <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 2950 interrupt-names = "lpass-irq-lpaif", 2951 "lpass-irq-hdmi", 2952 "lpass-irq-vaif", 2953 "lpass-irq-rxtxif"; 2954 2955 status = "disabled"; 2956 }; 2957 2958 slimbam: dma-controller@3a84000 { 2959 compatible = "qcom,bam-v1.7.0"; 2960 reg = <0 0x03a84000 0 0x20000>; 2961 interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>; 2962 #dma-cells = <1>; 2963 qcom,controlled-remotely; 2964 num-channels = <31>; 2965 qcom,ee = <1>; 2966 qcom,num-ees = <2>; 2967 iommus = <&apps_smmu 0x1826 0x0>; 2968 status = "disabled"; 2969 }; 2970 2971 slim: slim-ngd@3ac0000 { 2972 compatible = "qcom,slim-ngd-v1.5.0"; 2973 reg = <0 0x03ac0000 0 0x2c000>; 2974 interrupts = <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>; 2975 dmas = <&slimbam 3>, <&slimbam 4>; 2976 dma-names = "rx", "tx"; 2977 iommus = <&apps_smmu 0x1826 0x0>; 2978 #address-cells = <1>; 2979 #size-cells = <0>; 2980 status = "disabled"; 2981 }; 2982 2983 lpass_hm: clock-controller@3c00000 { 2984 compatible = "qcom,sc7280-lpasshm"; 2985 reg = <0 0x03c00000 0 0x28>; 2986 clocks = <&rpmhcc RPMH_CXO_CLK>; 2987 clock-names = "bi_tcxo"; 2988 #clock-cells = <1>; 2989 #power-domain-cells = <1>; 2990 status = "reserved"; /* Owned by ADSP firmware */ 2991 }; 2992 2993 lpass_ag_noc: interconnect@3c40000 { 2994 reg = <0 0x03c40000 0 0xf080>; 2995 compatible = "qcom,sc7280-lpass-ag-noc"; 2996 #interconnect-cells = <2>; 2997 qcom,bcm-voters = <&apps_bcm_voter>; 2998 }; 2999 3000 lpass_tlmm: pinctrl@33c0000 { 3001 compatible = "qcom,sc7280-lpass-lpi-pinctrl"; 3002 reg = <0 0x033c0000 0x0 0x20000>, 3003 <0 0x03550000 0x0 0x10000>; 3004 3005 clocks = <&q6afecc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 3006 <&q6afecc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 3007 clock-names = "core", "audio"; 3008 3009 gpio-controller; 3010 #gpio-cells = <2>; 3011 gpio-ranges = <&lpass_tlmm 0 0 15>; 3012 3013 lpass_dmic01_clk: dmic01-clk-state { 3014 pins = "gpio6"; 3015 function = "dmic1_clk"; 3016 drive-strength = <8>; 3017 bias-disable; 3018 }; 3019 3020 lpass_dmic01_data: dmic01-data-state { 3021 pins = "gpio7"; 3022 function = "dmic1_data"; 3023 drive-strength = <8>; 3024 bias-pull-down; 3025 }; 3026 3027 lpass_dmic23_clk: dmic23-clk-state { 3028 pins = "gpio8"; 3029 function = "dmic2_clk"; 3030 drive-strength = <8>; 3031 bias-disable; 3032 }; 3033 3034 lpass_dmic23_data: dmic23-data-state { 3035 pins = "gpio9"; 3036 function = "dmic2_data"; 3037 drive-strength = <8>; 3038 bias-pull-down; 3039 }; 3040 3041 lpass_i2s1_active: i2s1-active-state { 3042 clk-pins { 3043 pins = "gpio6"; 3044 function = "i2s1_clk"; 3045 drive-strength = <8>; 3046 bias-disable; 3047 output-high; 3048 }; 3049 3050 ws-pins { 3051 pins = "gpio7"; 3052 function = "i2s1_ws"; 3053 drive-strength = <8>; 3054 bias-disable; 3055 output-high; 3056 }; 3057 3058 data-pins { 3059 pins = "gpio8", "gpio9"; 3060 function = "i2s1_data"; 3061 drive-strength = <8>; 3062 bias-disable; 3063 output-high; 3064 }; 3065 }; 3066 3067 lpass_i2s1_sleep: i2s1-sleep-state { 3068 clk-pins { 3069 pins = "gpio6"; 3070 function = "i2s1_clk"; 3071 drive-strength = <2>; 3072 bias-pull-down; 3073 input-enable; 3074 }; 3075 3076 ws-pins { 3077 pins = "gpio7"; 3078 function = "i2s1_ws"; 3079 drive-strength = <2>; 3080 bias-pull-down; 3081 input-enable; 3082 }; 3083 3084 data-pins { 3085 pins = "gpio8", "gpio9"; 3086 function = "i2s1_data"; 3087 drive-strength = <2>; 3088 bias-pull-down; 3089 input-enable; 3090 }; 3091 }; 3092 3093 lpass_i2s2_active: i2s2-active-state { 3094 clk-pins { 3095 pins = "gpio10"; 3096 function = "i2s2_clk"; 3097 drive-strength = <8>; 3098 bias-disable; 3099 output-high; 3100 }; 3101 3102 ws-pins { 3103 pins = "gpio11"; 3104 function = "i2s2_ws"; 3105 drive-strength = <8>; 3106 bias-disable; 3107 output-high; 3108 }; 3109 3110 data-pins { 3111 pins = "gpio12", "gpio13"; 3112 function = "i2s2_data"; 3113 drive-strength = <8>; 3114 bias-disable; 3115 output-high; 3116 }; 3117 }; 3118 3119 lpass_i2s2_sleep: i2s2-sleep-state { 3120 clk-pins { 3121 pins = "gpio10"; 3122 function = "i2s2_clk"; 3123 drive-strength = <2>; 3124 bias-pull-down; 3125 input-enable; 3126 }; 3127 3128 ws-pins { 3129 pins = "gpio11"; 3130 function = "i2s2_ws"; 3131 drive-strength = <2>; 3132 bias-pull-down; 3133 input-enable; 3134 }; 3135 3136 data-pins { 3137 pins = "gpio12", "gpio13"; 3138 function = "i2s2_data"; 3139 drive-strength = <2>; 3140 bias-pull-down; 3141 input-enable; 3142 }; 3143 }; 3144 3145 lpass_rx_swr_clk: rx-swr-clk-state { 3146 pins = "gpio3"; 3147 function = "swr_rx_clk"; 3148 drive-strength = <2>; 3149 slew-rate = <1>; 3150 bias-disable; 3151 }; 3152 3153 lpass_rx_swr_data: rx-swr-data-state { 3154 pins = "gpio4", "gpio5"; 3155 function = "swr_rx_data"; 3156 drive-strength = <2>; 3157 slew-rate = <1>; 3158 bias-bus-hold; 3159 }; 3160 3161 lpass_tx_swr_clk: tx-swr-clk-state { 3162 pins = "gpio0"; 3163 function = "swr_tx_clk"; 3164 drive-strength = <2>; 3165 slew-rate = <1>; 3166 bias-disable; 3167 }; 3168 3169 lpass_tx_swr_data: tx-swr-data-state { 3170 pins = "gpio1", "gpio2", "gpio14"; 3171 function = "swr_tx_data"; 3172 drive-strength = <2>; 3173 slew-rate = <1>; 3174 bias-bus-hold; 3175 }; 3176 3177 lpass_wsa_swr_clk: wsa-swr-clk-state { 3178 pins = "gpio10"; 3179 function = "wsa_swr_clk"; 3180 drive-strength = <2>; 3181 slew-rate = <1>; 3182 bias-disable; 3183 }; 3184 3185 lpass_wsa_swr_data: wsa-swr-data-state { 3186 pins = "gpio11"; 3187 function = "wsa_swr_data"; 3188 drive-strength = <2>; 3189 slew-rate = <1>; 3190 bias-bus-hold; 3191 }; 3192 }; 3193 3194 gpu: gpu@3d00000 { 3195 compatible = "qcom,adreno-635.0", "qcom,adreno"; 3196 reg = <0 0x03d00000 0 0x40000>, 3197 <0 0x03d9e000 0 0x1000>, 3198 <0 0x03d61000 0 0x800>; 3199 reg-names = "kgsl_3d0_reg_memory", 3200 "cx_mem", 3201 "cx_dbgc"; 3202 interrupts = <GIC_SPI 300 IRQ_TYPE_LEVEL_HIGH>; 3203 iommus = <&adreno_smmu 0 0x400>, 3204 <&adreno_smmu 1 0x400>; 3205 operating-points-v2 = <&gpu_opp_table>; 3206 qcom,gmu = <&gmu>; 3207 interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>; 3208 interconnect-names = "gfx-mem"; 3209 #cooling-cells = <2>; 3210 3211 nvmem-cells = <&gpu_speed_bin>; 3212 nvmem-cell-names = "speed_bin"; 3213 3214 status = "disabled"; 3215 3216 gpu_zap_shader: zap-shader { 3217 memory-region = <&gpu_zap_mem>; 3218 }; 3219 3220 gpu_opp_table: opp-table { 3221 compatible = "operating-points-v2"; 3222 3223 opp-315000000 { 3224 opp-hz = /bits/ 64 <315000000>; 3225 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 3226 opp-peak-kBps = <1804000>; 3227 opp-supported-hw = <0x17>; 3228 }; 3229 3230 opp-450000000 { 3231 opp-hz = /bits/ 64 <450000000>; 3232 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 3233 opp-peak-kBps = <4068000>; 3234 opp-supported-hw = <0x17>; 3235 }; 3236 3237 /* Only applicable for SKUs which has 550Mhz as Fmax */ 3238 opp-550000000-0 { 3239 opp-hz = /bits/ 64 <550000000>; 3240 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3241 opp-peak-kBps = <8368000>; 3242 opp-supported-hw = <0x01>; 3243 }; 3244 3245 opp-550000000-1 { 3246 opp-hz = /bits/ 64 <550000000>; 3247 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 3248 opp-peak-kBps = <6832000>; 3249 opp-supported-hw = <0x16>; 3250 }; 3251 3252 opp-608000000 { 3253 opp-hz = /bits/ 64 <608000000>; 3254 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 3255 opp-peak-kBps = <8368000>; 3256 opp-supported-hw = <0x16>; 3257 }; 3258 3259 opp-700000000 { 3260 opp-hz = /bits/ 64 <700000000>; 3261 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 3262 opp-peak-kBps = <8532000>; 3263 opp-supported-hw = <0x06>; 3264 }; 3265 3266 opp-812000000 { 3267 opp-hz = /bits/ 64 <812000000>; 3268 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 3269 opp-peak-kBps = <8532000>; 3270 opp-supported-hw = <0x06>; 3271 }; 3272 3273 opp-840000000 { 3274 opp-hz = /bits/ 64 <840000000>; 3275 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 3276 opp-peak-kBps = <8532000>; 3277 opp-supported-hw = <0x02>; 3278 }; 3279 3280 opp-900000000 { 3281 opp-hz = /bits/ 64 <900000000>; 3282 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 3283 opp-peak-kBps = <8532000>; 3284 opp-supported-hw = <0x02>; 3285 }; 3286 }; 3287 }; 3288 3289 gmu: gmu@3d6a000 { 3290 compatible = "qcom,adreno-gmu-635.0", "qcom,adreno-gmu"; 3291 reg = <0 0x03d6a000 0 0x34000>, 3292 <0 0x3de0000 0 0x10000>, 3293 <0 0x0b290000 0 0x10000>; 3294 reg-names = "gmu", "rscc", "gmu_pdc"; 3295 interrupts = <GIC_SPI 304 IRQ_TYPE_LEVEL_HIGH>, 3296 <GIC_SPI 305 IRQ_TYPE_LEVEL_HIGH>; 3297 interrupt-names = "hfi", "gmu"; 3298 clocks = <&gpucc GPU_CC_CX_GMU_CLK>, 3299 <&gpucc GPU_CC_CXO_CLK>, 3300 <&gcc GCC_DDRSS_GPU_AXI_CLK>, 3301 <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3302 <&gpucc GPU_CC_AHB_CLK>, 3303 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3304 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>; 3305 clock-names = "gmu", 3306 "cxo", 3307 "axi", 3308 "memnoc", 3309 "ahb", 3310 "hub", 3311 "smmu_vote"; 3312 power-domains = <&gpucc GPU_CC_CX_GDSC>, 3313 <&gpucc GPU_CC_GX_GDSC>; 3314 power-domain-names = "cx", 3315 "gx"; 3316 iommus = <&adreno_smmu 5 0x400>; 3317 operating-points-v2 = <&gmu_opp_table>; 3318 3319 gmu_opp_table: opp-table { 3320 compatible = "operating-points-v2"; 3321 3322 opp-200000000 { 3323 opp-hz = /bits/ 64 <200000000>; 3324 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 3325 }; 3326 }; 3327 }; 3328 3329 gpucc: clock-controller@3d90000 { 3330 compatible = "qcom,sc7280-gpucc"; 3331 reg = <0 0x03d90000 0 0x9000>; 3332 clocks = <&rpmhcc RPMH_CXO_CLK>, 3333 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 3334 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 3335 clock-names = "bi_tcxo", 3336 "gcc_gpu_gpll0_clk_src", 3337 "gcc_gpu_gpll0_div_clk_src"; 3338 #clock-cells = <1>; 3339 #reset-cells = <1>; 3340 #power-domain-cells = <1>; 3341 }; 3342 3343 dma@117f000 { 3344 compatible = "qcom,sc7280-dcc", "qcom,dcc"; 3345 reg = <0x0 0x0117f000 0x0 0x1000>, 3346 <0x0 0x01112000 0x0 0x6000>; 3347 }; 3348 3349 adreno_smmu: iommu@3da0000 { 3350 compatible = "qcom,sc7280-smmu-500", "qcom,adreno-smmu", 3351 "qcom,smmu-500", "arm,mmu-500"; 3352 reg = <0 0x03da0000 0 0x20000>; 3353 #iommu-cells = <2>; 3354 #global-interrupts = <2>; 3355 interrupts = <GIC_SPI 673 IRQ_TYPE_LEVEL_HIGH>, 3356 <GIC_SPI 675 IRQ_TYPE_LEVEL_HIGH>, 3357 <GIC_SPI 678 IRQ_TYPE_LEVEL_HIGH>, 3358 <GIC_SPI 679 IRQ_TYPE_LEVEL_HIGH>, 3359 <GIC_SPI 680 IRQ_TYPE_LEVEL_HIGH>, 3360 <GIC_SPI 681 IRQ_TYPE_LEVEL_HIGH>, 3361 <GIC_SPI 682 IRQ_TYPE_LEVEL_HIGH>, 3362 <GIC_SPI 683 IRQ_TYPE_LEVEL_HIGH>, 3363 <GIC_SPI 684 IRQ_TYPE_LEVEL_HIGH>, 3364 <GIC_SPI 685 IRQ_TYPE_LEVEL_HIGH>, 3365 <GIC_SPI 686 IRQ_TYPE_LEVEL_HIGH>, 3366 <GIC_SPI 687 IRQ_TYPE_LEVEL_HIGH>; 3367 3368 clocks = <&gcc GCC_GPU_MEMNOC_GFX_CLK>, 3369 <&gcc GCC_GPU_SNOC_DVM_GFX_CLK>, 3370 <&gpucc GPU_CC_AHB_CLK>, 3371 <&gpucc GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK>, 3372 <&gpucc GPU_CC_CX_GMU_CLK>, 3373 <&gpucc GPU_CC_HUB_CX_INT_CLK>, 3374 <&gpucc GPU_CC_HUB_AON_CLK>; 3375 clock-names = "gcc_gpu_memnoc_gfx_clk", 3376 "gcc_gpu_snoc_dvm_gfx_clk", 3377 "gpu_cc_ahb_clk", 3378 "gpu_cc_hlos1_vote_gpu_smmu_clk", 3379 "gpu_cc_cx_gmu_clk", 3380 "gpu_cc_hub_cx_int_clk", 3381 "gpu_cc_hub_aon_clk"; 3382 3383 power-domains = <&gpucc GPU_CC_CX_GDSC>; 3384 dma-coherent; 3385 }; 3386 3387 gfx_0_tbu: tbu@3dd9000 { 3388 compatible = "qcom,sc7280-tbu"; 3389 reg = <0x0 0x3dd9000 0x0 0x1000>; 3390 qcom,stream-id-range = <&adreno_smmu 0x0 0x400>; 3391 }; 3392 3393 gfx_1_tbu: tbu@3ddd000 { 3394 compatible = "qcom,sc7280-tbu"; 3395 reg = <0x0 0x3ddd000 0x0 0x1000>; 3396 qcom,stream-id-range = <&adreno_smmu 0x400 0x400>; 3397 }; 3398 3399 remoteproc_mpss: remoteproc@4080000 { 3400 compatible = "qcom,sc7280-mpss-pas"; 3401 reg = <0 0x04080000 0 0x10000>; 3402 3403 interrupts-extended = <&intc GIC_SPI 264 IRQ_TYPE_EDGE_RISING>, 3404 <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 3405 <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 3406 <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 3407 <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 3408 <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 3409 interrupt-names = "wdog", "fatal", "ready", "handover", 3410 "stop-ack", "shutdown-ack"; 3411 3412 clocks = <&rpmhcc RPMH_CXO_CLK>; 3413 clock-names = "xo"; 3414 3415 power-domains = <&rpmhpd SC7280_CX>, 3416 <&rpmhpd SC7280_MSS>; 3417 power-domain-names = "cx", "mss"; 3418 3419 memory-region = <&mpss_mem>; 3420 3421 qcom,qmp = <&aoss_qmp>; 3422 3423 qcom,smem-states = <&modem_smp2p_out 0>; 3424 qcom,smem-state-names = "stop"; 3425 3426 status = "disabled"; 3427 3428 glink-edge { 3429 interrupts-extended = <&ipcc IPCC_CLIENT_MPSS 3430 IPCC_MPROC_SIGNAL_GLINK_QMP 3431 IRQ_TYPE_EDGE_RISING>; 3432 mboxes = <&ipcc IPCC_CLIENT_MPSS 3433 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3434 label = "modem"; 3435 qcom,remote-pid = <1>; 3436 }; 3437 }; 3438 3439 stm@6002000 { 3440 compatible = "arm,coresight-stm", "arm,primecell"; 3441 reg = <0 0x06002000 0 0x1000>, 3442 <0 0x16280000 0 0x180000>; 3443 reg-names = "stm-base", "stm-stimulus-base"; 3444 3445 clocks = <&aoss_qmp>; 3446 clock-names = "apb_pclk"; 3447 3448 out-ports { 3449 port { 3450 stm_out: endpoint { 3451 remote-endpoint = <&funnel0_in7>; 3452 }; 3453 }; 3454 }; 3455 }; 3456 3457 tpda@6004000 { 3458 compatible = "qcom,coresight-tpda", "arm,primecell"; 3459 reg = <0x0 0x06004000 0x0 0x1000>; 3460 3461 clocks = <&aoss_qmp>; 3462 clock-names = "apb_pclk"; 3463 3464 in-ports { 3465 #address-cells = <1>; 3466 #size-cells = <0>; 3467 3468 port@1c { 3469 reg = <0x1c>; 3470 3471 qdss_tpda_in28: endpoint { 3472 remote-endpoint = <&spdm_tpdm_out>; 3473 }; 3474 }; 3475 }; 3476 3477 out-ports { 3478 port { 3479 qdss_tpda_out: endpoint { 3480 remote-endpoint = <&qdss_dl_funnel_in0>; 3481 }; 3482 }; 3483 }; 3484 }; 3485 3486 funnel@6005000 { 3487 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3488 reg = <0x0 0x06005000 0x0 0x1000>; 3489 3490 clocks = <&aoss_qmp>; 3491 clock-names = "apb_pclk"; 3492 3493 in-ports { 3494 port { 3495 qdss_dl_funnel_in0: endpoint { 3496 remote-endpoint = <&qdss_tpda_out>; 3497 }; 3498 }; 3499 }; 3500 3501 out-ports { 3502 port { 3503 qdss_dl_funnel_out: endpoint { 3504 remote-endpoint = <&funnel0_in6>; 3505 }; 3506 }; 3507 }; 3508 }; 3509 3510 tpdm@600f000 { 3511 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3512 reg = <0x0 0x0600f000 0x0 0x1000>; 3513 3514 clocks = <&aoss_qmp>; 3515 clock-names = "apb_pclk"; 3516 3517 qcom,cmb-element-bits = <32>; 3518 qcom,cmb-msrs-num = <32>; 3519 3520 out-ports { 3521 port { 3522 spdm_tpdm_out: endpoint { 3523 remote-endpoint = <&qdss_tpda_in28>; 3524 }; 3525 }; 3526 }; 3527 }; 3528 3529 cti@6010000 { 3530 compatible = "arm,coresight-cti", "arm,primecell"; 3531 reg = <0x0 0x06010000 0x0 0x1000>; 3532 3533 clocks = <&aoss_qmp>; 3534 clock-names = "apb_pclk"; 3535 }; 3536 3537 funnel@6041000 { 3538 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3539 reg = <0 0x06041000 0 0x1000>; 3540 3541 clocks = <&aoss_qmp>; 3542 clock-names = "apb_pclk"; 3543 3544 out-ports { 3545 port { 3546 funnel0_out: endpoint { 3547 remote-endpoint = <&merge_funnel_in0>; 3548 }; 3549 }; 3550 }; 3551 3552 in-ports { 3553 #address-cells = <1>; 3554 #size-cells = <0>; 3555 3556 port@6 { 3557 reg = <6>; 3558 3559 funnel0_in6: endpoint { 3560 remote-endpoint = <&qdss_dl_funnel_out>; 3561 }; 3562 }; 3563 3564 port@7 { 3565 reg = <7>; 3566 funnel0_in7: endpoint { 3567 remote-endpoint = <&stm_out>; 3568 }; 3569 }; 3570 }; 3571 }; 3572 3573 funnel@6042000 { 3574 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3575 reg = <0 0x06042000 0 0x1000>; 3576 3577 clocks = <&aoss_qmp>; 3578 clock-names = "apb_pclk"; 3579 3580 out-ports { 3581 port { 3582 funnel1_out: endpoint { 3583 remote-endpoint = <&merge_funnel_in1>; 3584 }; 3585 }; 3586 }; 3587 3588 in-ports { 3589 #address-cells = <1>; 3590 #size-cells = <0>; 3591 3592 port@4 { 3593 reg = <4>; 3594 funnel1_in4: endpoint { 3595 remote-endpoint = <&apss_merge_funnel_out>; 3596 }; 3597 }; 3598 }; 3599 }; 3600 3601 funnel@6045000 { 3602 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3603 reg = <0 0x06045000 0 0x1000>; 3604 3605 clocks = <&aoss_qmp>; 3606 clock-names = "apb_pclk"; 3607 3608 out-ports { 3609 port { 3610 merge_funnel_out: endpoint { 3611 remote-endpoint = <&swao_funnel_in>; 3612 }; 3613 }; 3614 }; 3615 3616 in-ports { 3617 #address-cells = <1>; 3618 #size-cells = <0>; 3619 3620 port@0 { 3621 reg = <0>; 3622 merge_funnel_in0: endpoint { 3623 remote-endpoint = <&funnel0_out>; 3624 }; 3625 }; 3626 3627 port@1 { 3628 reg = <1>; 3629 merge_funnel_in1: endpoint { 3630 remote-endpoint = <&funnel1_out>; 3631 }; 3632 }; 3633 }; 3634 }; 3635 3636 replicator@6046000 { 3637 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3638 reg = <0 0x06046000 0 0x1000>; 3639 3640 clocks = <&aoss_qmp>; 3641 clock-names = "apb_pclk"; 3642 3643 out-ports { 3644 port { 3645 replicator_out: endpoint { 3646 remote-endpoint = <&etr_in>; 3647 }; 3648 }; 3649 }; 3650 3651 in-ports { 3652 port { 3653 replicator_in: endpoint { 3654 remote-endpoint = <&swao_replicator_out>; 3655 }; 3656 }; 3657 }; 3658 }; 3659 3660 etr@6048000 { 3661 compatible = "arm,coresight-tmc", "arm,primecell"; 3662 reg = <0 0x06048000 0 0x1000>; 3663 iommus = <&apps_smmu 0x04c0 0>; 3664 3665 clocks = <&aoss_qmp>; 3666 clock-names = "apb_pclk"; 3667 arm,scatter-gather; 3668 3669 in-ports { 3670 port { 3671 etr_in: endpoint { 3672 remote-endpoint = <&replicator_out>; 3673 }; 3674 }; 3675 }; 3676 }; 3677 3678 cti@6b00000 { 3679 compatible = "arm,coresight-cti", "arm,primecell"; 3680 reg = <0x0 0x06b00000 0x0 0x1000>; 3681 3682 clocks = <&aoss_qmp>; 3683 clock-names = "apb_pclk"; 3684 }; 3685 3686 cti@6b01000 { 3687 compatible = "arm,coresight-cti", "arm,primecell"; 3688 reg = <0x0 0x06b01000 0x0 0x1000>; 3689 3690 clocks = <&aoss_qmp>; 3691 clock-names = "apb_pclk"; 3692 }; 3693 3694 cti@6b02000 { 3695 compatible = "arm,coresight-cti", "arm,primecell"; 3696 reg = <0x0 0x06b02000 0x0 0x1000>; 3697 3698 clocks = <&aoss_qmp>; 3699 clock-names = "apb_pclk"; 3700 }; 3701 3702 cti@6b03000 { 3703 compatible = "arm,coresight-cti", "arm,primecell"; 3704 reg = <0x0 0x06b03000 0x0 0x1000>; 3705 3706 clocks = <&aoss_qmp>; 3707 clock-names = "apb_pclk"; 3708 }; 3709 3710 funnel@6b04000 { 3711 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 3712 reg = <0 0x06b04000 0 0x1000>; 3713 3714 clocks = <&aoss_qmp>; 3715 clock-names = "apb_pclk"; 3716 3717 out-ports { 3718 port { 3719 swao_funnel_out: endpoint { 3720 remote-endpoint = <&etf_in>; 3721 }; 3722 }; 3723 }; 3724 3725 in-ports { 3726 #address-cells = <1>; 3727 #size-cells = <0>; 3728 3729 port@6 { 3730 reg = <6>; 3731 3732 swao_funnel_in6: endpoint { 3733 remote-endpoint = <&aoss_tpda_out>; 3734 }; 3735 }; 3736 3737 port@7 { 3738 reg = <7>; 3739 swao_funnel_in: endpoint { 3740 remote-endpoint = <&merge_funnel_out>; 3741 }; 3742 }; 3743 }; 3744 }; 3745 3746 etf@6b05000 { 3747 compatible = "arm,coresight-tmc", "arm,primecell"; 3748 reg = <0 0x06b05000 0 0x1000>; 3749 3750 clocks = <&aoss_qmp>; 3751 clock-names = "apb_pclk"; 3752 3753 out-ports { 3754 port { 3755 etf_out: endpoint { 3756 remote-endpoint = <&swao_replicator_in>; 3757 }; 3758 }; 3759 }; 3760 3761 in-ports { 3762 port { 3763 etf_in: endpoint { 3764 remote-endpoint = <&swao_funnel_out>; 3765 }; 3766 }; 3767 }; 3768 }; 3769 3770 replicator@6b06000 { 3771 compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; 3772 reg = <0 0x06b06000 0 0x1000>; 3773 3774 clocks = <&aoss_qmp>; 3775 clock-names = "apb_pclk"; 3776 qcom,replicator-loses-context; 3777 3778 out-ports { 3779 port { 3780 swao_replicator_out: endpoint { 3781 remote-endpoint = <&replicator_in>; 3782 }; 3783 }; 3784 }; 3785 3786 in-ports { 3787 port { 3788 swao_replicator_in: endpoint { 3789 remote-endpoint = <&etf_out>; 3790 }; 3791 }; 3792 }; 3793 }; 3794 3795 tpda@6b08000 { 3796 compatible = "qcom,coresight-tpda", "arm,primecell"; 3797 reg = <0x0 0x06b08000 0x0 0x1000>; 3798 3799 clocks = <&aoss_qmp>; 3800 clock-names = "apb_pclk"; 3801 3802 in-ports { 3803 #address-cells = <1>; 3804 #size-cells = <0>; 3805 3806 port@0 { 3807 reg = <0>; 3808 3809 aoss_tpda_in0: endpoint { 3810 remote-endpoint = <&swao_prio0_tpdm_out>; 3811 }; 3812 }; 3813 3814 port@1 { 3815 reg = <1>; 3816 3817 aoss_tpda_in1: endpoint { 3818 remote-endpoint = <&swao_prio1_tpdm_out>; 3819 }; 3820 }; 3821 3822 port@2 { 3823 reg = <2>; 3824 3825 aoss_tpda_in2: endpoint { 3826 remote-endpoint = <&swao_prio2_tpdm_out>; 3827 }; 3828 }; 3829 3830 port@3 { 3831 reg = <3>; 3832 3833 aoss_tpda_in3: endpoint { 3834 remote-endpoint = <&swao_prio3_tpdm_out>; 3835 }; 3836 }; 3837 3838 port@4 { 3839 reg = <4>; 3840 3841 aoss_tpda_in4: endpoint { 3842 remote-endpoint = <&swao_tpdm_out>; 3843 }; 3844 }; 3845 }; 3846 3847 out-ports { 3848 port { 3849 aoss_tpda_out: endpoint { 3850 remote-endpoint = <&swao_funnel_in6>; 3851 }; 3852 }; 3853 }; 3854 }; 3855 3856 tpdm@6b09000 { 3857 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3858 reg = <0x0 0x06b09000 0x0 0x1000>; 3859 3860 clocks = <&aoss_qmp>; 3861 clock-names = "apb_pclk"; 3862 3863 qcom,cmb-element-bits = <64>; 3864 qcom,cmb-msrs-num = <32>; 3865 3866 out-ports { 3867 port { 3868 swao_prio0_tpdm_out: endpoint { 3869 remote-endpoint = <&aoss_tpda_in0>; 3870 }; 3871 }; 3872 }; 3873 }; 3874 3875 tpdm@6b0a000 { 3876 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3877 reg = <0x0 0x06b0a000 0x0 0x1000>; 3878 3879 clocks = <&aoss_qmp>; 3880 clock-names = "apb_pclk"; 3881 3882 qcom,cmb-element-bits = <64>; 3883 qcom,cmb-msrs-num = <32>; 3884 3885 out-ports { 3886 port { 3887 swao_prio1_tpdm_out: endpoint { 3888 remote-endpoint = <&aoss_tpda_in1>; 3889 }; 3890 }; 3891 }; 3892 }; 3893 3894 tpdm@6b0b000 { 3895 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3896 reg = <0x0 0x06b0b000 0x0 0x1000>; 3897 3898 clocks = <&aoss_qmp>; 3899 clock-names = "apb_pclk"; 3900 3901 qcom,cmb-element-bits = <64>; 3902 qcom,cmb-msrs-num = <32>; 3903 3904 out-ports { 3905 port { 3906 swao_prio2_tpdm_out: endpoint { 3907 remote-endpoint = <&aoss_tpda_in2>; 3908 }; 3909 }; 3910 }; 3911 }; 3912 3913 tpdm@6b0c000 { 3914 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3915 reg = <0x0 0x06b0c000 0x0 0x1000>; 3916 3917 clocks = <&aoss_qmp>; 3918 clock-names = "apb_pclk"; 3919 3920 qcom,cmb-element-bits = <64>; 3921 qcom,cmb-msrs-num = <32>; 3922 3923 out-ports { 3924 port { 3925 swao_prio3_tpdm_out: endpoint { 3926 remote-endpoint = <&aoss_tpda_in3>; 3927 }; 3928 }; 3929 }; 3930 }; 3931 3932 tpdm@6b0d000 { 3933 compatible = "qcom,coresight-tpdm", "arm,primecell"; 3934 reg = <0x0 0x06b0d000 0x0 0x1000>; 3935 3936 clocks = <&aoss_qmp>; 3937 clock-names = "apb_pclk"; 3938 3939 qcom,dsb-element-bits = <32>; 3940 qcom,dsb-msrs-num = <32>; 3941 3942 out-ports { 3943 port { 3944 swao_tpdm_out: endpoint { 3945 remote-endpoint = <&aoss_tpda_in4>; 3946 }; 3947 }; 3948 }; 3949 }; 3950 3951 cti@6b11000 { 3952 compatible = "arm,coresight-cti", "arm,primecell"; 3953 reg = <0x0 0x06b11000 0x0 0x1000>; 3954 3955 clocks = <&aoss_qmp>; 3956 clock-names = "apb_pclk"; 3957 }; 3958 3959 etm@7040000 { 3960 compatible = "arm,coresight-etm4x", "arm,primecell"; 3961 reg = <0 0x07040000 0 0x1000>; 3962 3963 cpu = <&cpu0>; 3964 3965 clocks = <&aoss_qmp>; 3966 clock-names = "apb_pclk"; 3967 arm,coresight-loses-context-with-cpu; 3968 qcom,skip-power-up; 3969 3970 out-ports { 3971 port { 3972 etm0_out: endpoint { 3973 remote-endpoint = <&apss_funnel_in0>; 3974 }; 3975 }; 3976 }; 3977 }; 3978 3979 etm@7140000 { 3980 compatible = "arm,coresight-etm4x", "arm,primecell"; 3981 reg = <0 0x07140000 0 0x1000>; 3982 3983 cpu = <&cpu1>; 3984 3985 clocks = <&aoss_qmp>; 3986 clock-names = "apb_pclk"; 3987 arm,coresight-loses-context-with-cpu; 3988 qcom,skip-power-up; 3989 3990 out-ports { 3991 port { 3992 etm1_out: endpoint { 3993 remote-endpoint = <&apss_funnel_in1>; 3994 }; 3995 }; 3996 }; 3997 }; 3998 3999 etm@7240000 { 4000 compatible = "arm,coresight-etm4x", "arm,primecell"; 4001 reg = <0 0x07240000 0 0x1000>; 4002 4003 cpu = <&cpu2>; 4004 4005 clocks = <&aoss_qmp>; 4006 clock-names = "apb_pclk"; 4007 arm,coresight-loses-context-with-cpu; 4008 qcom,skip-power-up; 4009 4010 out-ports { 4011 port { 4012 etm2_out: endpoint { 4013 remote-endpoint = <&apss_funnel_in2>; 4014 }; 4015 }; 4016 }; 4017 }; 4018 4019 etm@7340000 { 4020 compatible = "arm,coresight-etm4x", "arm,primecell"; 4021 reg = <0 0x07340000 0 0x1000>; 4022 4023 cpu = <&cpu3>; 4024 4025 clocks = <&aoss_qmp>; 4026 clock-names = "apb_pclk"; 4027 arm,coresight-loses-context-with-cpu; 4028 qcom,skip-power-up; 4029 4030 out-ports { 4031 port { 4032 etm3_out: endpoint { 4033 remote-endpoint = <&apss_funnel_in3>; 4034 }; 4035 }; 4036 }; 4037 }; 4038 4039 etm@7440000 { 4040 compatible = "arm,coresight-etm4x", "arm,primecell"; 4041 reg = <0 0x07440000 0 0x1000>; 4042 4043 cpu = <&cpu4>; 4044 4045 clocks = <&aoss_qmp>; 4046 clock-names = "apb_pclk"; 4047 arm,coresight-loses-context-with-cpu; 4048 qcom,skip-power-up; 4049 4050 out-ports { 4051 port { 4052 etm4_out: endpoint { 4053 remote-endpoint = <&apss_funnel_in4>; 4054 }; 4055 }; 4056 }; 4057 }; 4058 4059 etm@7540000 { 4060 compatible = "arm,coresight-etm4x", "arm,primecell"; 4061 reg = <0 0x07540000 0 0x1000>; 4062 4063 cpu = <&cpu5>; 4064 4065 clocks = <&aoss_qmp>; 4066 clock-names = "apb_pclk"; 4067 arm,coresight-loses-context-with-cpu; 4068 qcom,skip-power-up; 4069 4070 out-ports { 4071 port { 4072 etm5_out: endpoint { 4073 remote-endpoint = <&apss_funnel_in5>; 4074 }; 4075 }; 4076 }; 4077 }; 4078 4079 etm@7640000 { 4080 compatible = "arm,coresight-etm4x", "arm,primecell"; 4081 reg = <0 0x07640000 0 0x1000>; 4082 4083 cpu = <&cpu6>; 4084 4085 clocks = <&aoss_qmp>; 4086 clock-names = "apb_pclk"; 4087 arm,coresight-loses-context-with-cpu; 4088 qcom,skip-power-up; 4089 4090 out-ports { 4091 port { 4092 etm6_out: endpoint { 4093 remote-endpoint = <&apss_funnel_in6>; 4094 }; 4095 }; 4096 }; 4097 }; 4098 4099 etm@7740000 { 4100 compatible = "arm,coresight-etm4x", "arm,primecell"; 4101 reg = <0 0x07740000 0 0x1000>; 4102 4103 cpu = <&cpu7>; 4104 4105 clocks = <&aoss_qmp>; 4106 clock-names = "apb_pclk"; 4107 arm,coresight-loses-context-with-cpu; 4108 qcom,skip-power-up; 4109 4110 out-ports { 4111 port { 4112 etm7_out: endpoint { 4113 remote-endpoint = <&apss_funnel_in7>; 4114 }; 4115 }; 4116 }; 4117 }; 4118 4119 funnel@7800000 { /* APSS Funnel */ 4120 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4121 reg = <0 0x07800000 0 0x1000>; 4122 4123 clocks = <&aoss_qmp>; 4124 clock-names = "apb_pclk"; 4125 4126 out-ports { 4127 port { 4128 apss_funnel_out: endpoint { 4129 remote-endpoint = <&apss_merge_funnel_in>; 4130 }; 4131 }; 4132 }; 4133 4134 in-ports { 4135 #address-cells = <1>; 4136 #size-cells = <0>; 4137 4138 port@0 { 4139 reg = <0>; 4140 apss_funnel_in0: endpoint { 4141 remote-endpoint = <&etm0_out>; 4142 }; 4143 }; 4144 4145 port@1 { 4146 reg = <1>; 4147 apss_funnel_in1: endpoint { 4148 remote-endpoint = <&etm1_out>; 4149 }; 4150 }; 4151 4152 port@2 { 4153 reg = <2>; 4154 apss_funnel_in2: endpoint { 4155 remote-endpoint = <&etm2_out>; 4156 }; 4157 }; 4158 4159 port@3 { 4160 reg = <3>; 4161 apss_funnel_in3: endpoint { 4162 remote-endpoint = <&etm3_out>; 4163 }; 4164 }; 4165 4166 port@4 { 4167 reg = <4>; 4168 apss_funnel_in4: endpoint { 4169 remote-endpoint = <&etm4_out>; 4170 }; 4171 }; 4172 4173 port@5 { 4174 reg = <5>; 4175 apss_funnel_in5: endpoint { 4176 remote-endpoint = <&etm5_out>; 4177 }; 4178 }; 4179 4180 port@6 { 4181 reg = <6>; 4182 apss_funnel_in6: endpoint { 4183 remote-endpoint = <&etm6_out>; 4184 }; 4185 }; 4186 4187 port@7 { 4188 reg = <7>; 4189 apss_funnel_in7: endpoint { 4190 remote-endpoint = <&etm7_out>; 4191 }; 4192 }; 4193 }; 4194 }; 4195 4196 funnel@7810000 { 4197 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4198 reg = <0 0x07810000 0 0x1000>; 4199 4200 clocks = <&aoss_qmp>; 4201 clock-names = "apb_pclk"; 4202 4203 out-ports { 4204 port { 4205 apss_merge_funnel_out: endpoint { 4206 remote-endpoint = <&funnel1_in4>; 4207 }; 4208 }; 4209 }; 4210 4211 in-ports { 4212 port { 4213 apss_merge_funnel_in: endpoint { 4214 remote-endpoint = <&apss_funnel_out>; 4215 }; 4216 }; 4217 }; 4218 }; 4219 4220 sdhc_2: mmc@8804000 { 4221 compatible = "qcom,sc7280-sdhci", "qcom,sdhci-msm-v5"; 4222 pinctrl-names = "default", "sleep"; 4223 pinctrl-0 = <&sdc2_clk>, <&sdc2_cmd>, <&sdc2_data>; 4224 pinctrl-1 = <&sdc2_clk_sleep>, <&sdc2_cmd_sleep>, <&sdc2_data_sleep>; 4225 status = "disabled"; 4226 4227 reg = <0 0x08804000 0 0x1000>; 4228 4229 iommus = <&apps_smmu 0x100 0x0>; 4230 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 4231 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 4232 interrupt-names = "hc_irq", "pwr_irq"; 4233 4234 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 4235 <&gcc GCC_SDCC2_APPS_CLK>, 4236 <&rpmhcc RPMH_CXO_CLK>; 4237 clock-names = "iface", "core", "xo"; 4238 interconnects = <&aggre1_noc MASTER_SDCC_2 0 &mc_virt SLAVE_EBI1 0>, 4239 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_SDCC_2 0>; 4240 interconnect-names = "sdhc-ddr","cpu-sdhc"; 4241 power-domains = <&rpmhpd SC7280_CX>; 4242 operating-points-v2 = <&sdhc2_opp_table>; 4243 4244 bus-width = <4>; 4245 dma-coherent; 4246 4247 qcom,dll-config = <0x0007642c>; 4248 4249 resets = <&gcc GCC_SDCC2_BCR>; 4250 4251 sdhc2_opp_table: opp-table { 4252 compatible = "operating-points-v2"; 4253 4254 opp-100000000 { 4255 opp-hz = /bits/ 64 <100000000>; 4256 required-opps = <&rpmhpd_opp_low_svs>; 4257 opp-peak-kBps = <1800000 400000>; 4258 opp-avg-kBps = <100000 0>; 4259 }; 4260 4261 opp-202000000 { 4262 opp-hz = /bits/ 64 <202000000>; 4263 required-opps = <&rpmhpd_opp_nom>; 4264 opp-peak-kBps = <5400000 1600000>; 4265 opp-avg-kBps = <200000 0>; 4266 }; 4267 }; 4268 }; 4269 4270 usb_1_hsphy: phy@88e3000 { 4271 compatible = "qcom,sc7280-usb-hs-phy", 4272 "qcom,usb-snps-hs-7nm-phy"; 4273 reg = <0 0x088e3000 0 0x400>; 4274 status = "disabled"; 4275 #phy-cells = <0>; 4276 4277 clocks = <&rpmhcc RPMH_CXO_CLK>; 4278 clock-names = "ref"; 4279 4280 resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>; 4281 }; 4282 4283 usb_2_hsphy: phy@88e4000 { 4284 compatible = "qcom,sc7280-usb-hs-phy", 4285 "qcom,usb-snps-hs-7nm-phy"; 4286 reg = <0 0x088e4000 0 0x400>; 4287 status = "disabled"; 4288 #phy-cells = <0>; 4289 4290 clocks = <&rpmhcc RPMH_CXO_CLK>; 4291 clock-names = "ref"; 4292 4293 resets = <&gcc GCC_QUSB2PHY_SEC_BCR>; 4294 }; 4295 4296 refgen: regulator@88e7000 { 4297 compatible = "qcom,sc7280-refgen-regulator", 4298 "qcom,sm8250-refgen-regulator"; 4299 reg = <0x0 0x088e7000 0x0 0x84>; 4300 }; 4301 4302 usb_1_qmpphy: phy@88e8000 { 4303 compatible = "qcom,sc7280-qmp-usb3-dp-phy"; 4304 reg = <0 0x088e8000 0 0x3000>; 4305 status = "disabled"; 4306 4307 clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>, 4308 <&rpmhcc RPMH_CXO_CLK>, 4309 <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>, 4310 <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>; 4311 clock-names = "aux", 4312 "ref", 4313 "com_aux", 4314 "usb3_pipe"; 4315 4316 resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>, 4317 <&gcc GCC_USB3_PHY_PRIM_BCR>; 4318 reset-names = "phy", "common"; 4319 4320 #clock-cells = <1>; 4321 #phy-cells = <1>; 4322 4323 orientation-switch; 4324 4325 ports { 4326 #address-cells = <1>; 4327 #size-cells = <0>; 4328 4329 port@0 { 4330 reg = <0>; 4331 4332 usb_dp_qmpphy_out: endpoint { 4333 }; 4334 }; 4335 4336 port@1 { 4337 reg = <1>; 4338 4339 usb_dp_qmpphy_usb_ss_in: endpoint { 4340 remote-endpoint = <&usb_1_dwc3_ss>; 4341 }; 4342 }; 4343 4344 port@2 { 4345 reg = <2>; 4346 4347 usb_dp_qmpphy_dp_in: endpoint { 4348 remote-endpoint = <&mdss_dp_out>; 4349 }; 4350 }; 4351 }; 4352 }; 4353 4354 usb_2: usb@8c00000 { 4355 compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3"; 4356 reg = <0 0x08c00000 0 0xfc100>; 4357 status = "disabled"; 4358 4359 clocks = <&gcc GCC_CFG_NOC_USB3_SEC_AXI_CLK>, 4360 <&gcc GCC_USB30_SEC_MASTER_CLK>, 4361 <&gcc GCC_AGGRE_USB3_SEC_AXI_CLK>, 4362 <&gcc GCC_USB30_SEC_SLEEP_CLK>, 4363 <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>; 4364 clock-names = "cfg_noc", 4365 "core", 4366 "iface", 4367 "sleep", 4368 "mock_utmi"; 4369 4370 assigned-clocks = <&gcc GCC_USB30_SEC_MOCK_UTMI_CLK>, 4371 <&gcc GCC_USB30_SEC_MASTER_CLK>; 4372 assigned-clock-rates = <19200000>, <200000000>; 4373 4374 interrupts-extended = <&intc GIC_SPI 242 IRQ_TYPE_LEVEL_HIGH>, 4375 <&intc GIC_SPI 241 IRQ_TYPE_LEVEL_HIGH>, 4376 <&intc GIC_SPI 240 IRQ_TYPE_LEVEL_HIGH>, 4377 <&pdc 12 IRQ_TYPE_EDGE_BOTH>, 4378 <&pdc 13 IRQ_TYPE_EDGE_BOTH>; 4379 interrupt-names = "dwc_usb3", 4380 "pwr_event", 4381 "hs_phy_irq", 4382 "dp_hs_phy_irq", 4383 "dm_hs_phy_irq"; 4384 4385 power-domains = <&gcc GCC_USB30_SEC_GDSC>; 4386 required-opps = <&rpmhpd_opp_nom>; 4387 4388 resets = <&gcc GCC_USB30_SEC_BCR>; 4389 4390 interconnects = <&aggre1_noc MASTER_USB2 0 &mc_virt SLAVE_EBI1 0>, 4391 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB2 0>; 4392 interconnect-names = "usb-ddr", "apps-usb"; 4393 4394 iommus = <&apps_smmu 0xa0 0x0>; 4395 snps,dis_u2_susphy_quirk; 4396 snps,dis_enblslpm_quirk; 4397 snps,dis-u1-entry-quirk; 4398 snps,dis-u2-entry-quirk; 4399 phys = <&usb_2_hsphy>; 4400 phy-names = "usb2-phy"; 4401 maximum-speed = "high-speed"; 4402 usb-role-switch; 4403 4404 port { 4405 usb2_role_switch: endpoint { 4406 remote-endpoint = <&eud_ep>; 4407 }; 4408 }; 4409 }; 4410 4411 qspi: spi@88dc000 { 4412 compatible = "qcom,sc7280-qspi", "qcom,qspi-v1"; 4413 reg = <0 0x088dc000 0 0x1000>; 4414 iommus = <&apps_smmu 0x20 0x0>; 4415 #address-cells = <1>; 4416 #size-cells = <0>; 4417 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; 4418 clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, 4419 <&gcc GCC_QSPI_CORE_CLK>; 4420 clock-names = "iface", "core"; 4421 interconnects = <&gem_noc MASTER_APPSS_PROC 0 4422 &cnoc2 SLAVE_QSPI_0 0>; 4423 interconnect-names = "qspi-config"; 4424 power-domains = <&rpmhpd SC7280_CX>; 4425 operating-points-v2 = <&qspi_opp_table>; 4426 status = "disabled"; 4427 }; 4428 4429 remoteproc_adsp: remoteproc@3700000 { 4430 compatible = "qcom,sc7280-adsp-pas"; 4431 reg = <0 0x03700000 0 0x100>; 4432 4433 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 4434 <&adsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4435 <&adsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4436 <&adsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4437 <&adsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4438 <&adsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4439 interrupt-names = "wdog", "fatal", "ready", "handover", 4440 "stop-ack", "shutdown-ack"; 4441 4442 clocks = <&rpmhcc RPMH_CXO_CLK>; 4443 clock-names = "xo"; 4444 4445 power-domains = <&rpmhpd SC7280_LCX>, 4446 <&rpmhpd SC7280_LMX>; 4447 power-domain-names = "lcx", "lmx"; 4448 4449 memory-region = <&adsp_mem>; 4450 4451 qcom,qmp = <&aoss_qmp>; 4452 4453 qcom,smem-states = <&adsp_smp2p_out 0>; 4454 qcom,smem-state-names = "stop"; 4455 4456 status = "disabled"; 4457 4458 remoteproc_adsp_glink: glink-edge { 4459 interrupts-extended = <&ipcc IPCC_CLIENT_LPASS 4460 IPCC_MPROC_SIGNAL_GLINK_QMP 4461 IRQ_TYPE_EDGE_RISING>; 4462 4463 mboxes = <&ipcc IPCC_CLIENT_LPASS 4464 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4465 4466 label = "lpass"; 4467 qcom,remote-pid = <2>; 4468 4469 apr { 4470 compatible = "qcom,apr-v2"; 4471 qcom,glink-channels = "apr_audio_svc"; 4472 qcom,domain = <APR_DOMAIN_ADSP>; 4473 #address-cells = <1>; 4474 #size-cells = <0>; 4475 4476 service@3 { 4477 reg = <APR_SVC_ADSP_CORE>; 4478 compatible = "qcom,q6core"; 4479 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4480 }; 4481 4482 q6afe: service@4 { 4483 compatible = "qcom,q6afe"; 4484 reg = <APR_SVC_AFE>; 4485 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4486 4487 q6afedai: dais { 4488 compatible = "qcom,q6afe-dais"; 4489 #address-cells = <1>; 4490 #size-cells = <0>; 4491 #sound-dai-cells = <1>; 4492 }; 4493 4494 q6afecc: clock-controller { 4495 compatible = "qcom,q6afe-clocks"; 4496 #clock-cells = <2>; 4497 }; 4498 4499 q6usbdai: usbd { 4500 compatible = "qcom,q6usb"; 4501 iommus = <&apps_smmu 0x180f 0x0>; 4502 #sound-dai-cells = <1>; 4503 qcom,usb-audio-intr-idx = /bits/ 16 <2>; 4504 }; 4505 }; 4506 4507 q6asm: service@7 { 4508 compatible = "qcom,q6asm"; 4509 reg = <APR_SVC_ASM>; 4510 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4511 4512 q6asmdai: dais { 4513 compatible = "qcom,q6asm-dais"; 4514 #address-cells = <1>; 4515 #size-cells = <0>; 4516 #sound-dai-cells = <1>; 4517 iommus = <&apps_smmu 0x1801 0x0>; 4518 4519 dai@0 { 4520 reg = <MSM_FRONTEND_DAI_MULTIMEDIA1>; 4521 }; 4522 4523 dai@1 { 4524 reg = <MSM_FRONTEND_DAI_MULTIMEDIA2>; 4525 }; 4526 4527 dai@2 { 4528 reg = <MSM_FRONTEND_DAI_MULTIMEDIA3>; 4529 }; 4530 }; 4531 }; 4532 4533 q6adm: service@8 { 4534 compatible = "qcom,q6adm"; 4535 reg = <APR_SVC_ADM>; 4536 qcom,protection-domain = "avs/audio", "msm/adsp/audio_pd"; 4537 4538 q6routing: routing { 4539 compatible = "qcom,q6adm-routing"; 4540 #sound-dai-cells = <0>; 4541 }; 4542 }; 4543 }; 4544 4545 fastrpc { 4546 compatible = "qcom,fastrpc"; 4547 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4548 label = "adsp"; 4549 qcom,non-secure-domain; 4550 memory-region = <&adsp_rpc_remote_heap_mem>; 4551 qcom,vmids = <QCOM_SCM_VMID_LPASS 4552 QCOM_SCM_VMID_ADSP_HEAP>; 4553 #address-cells = <1>; 4554 #size-cells = <0>; 4555 4556 compute-cb@3 { 4557 compatible = "qcom,fastrpc-compute-cb"; 4558 reg = <3>; 4559 iommus = <&apps_smmu 0x1803 0x0>; 4560 dma-coherent; 4561 }; 4562 4563 compute-cb@4 { 4564 compatible = "qcom,fastrpc-compute-cb"; 4565 reg = <4>; 4566 iommus = <&apps_smmu 0x1804 0x0>; 4567 dma-coherent; 4568 }; 4569 4570 compute-cb@5 { 4571 compatible = "qcom,fastrpc-compute-cb"; 4572 reg = <5>; 4573 iommus = <&apps_smmu 0x1805 0x0>; 4574 dma-coherent; 4575 }; 4576 }; 4577 }; 4578 }; 4579 4580 remoteproc_wpss: remoteproc@8a00000 { 4581 compatible = "qcom,sc7280-wpss-pas"; 4582 reg = <0 0x08a00000 0 0x10000>; 4583 4584 interrupts-extended = <&intc GIC_SPI 587 IRQ_TYPE_EDGE_RISING>, 4585 <&wpss_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4586 <&wpss_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4587 <&wpss_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4588 <&wpss_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4589 <&wpss_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4590 interrupt-names = "wdog", "fatal", "ready", "handover", 4591 "stop-ack", "shutdown-ack"; 4592 4593 clocks = <&rpmhcc RPMH_CXO_CLK>; 4594 clock-names = "xo"; 4595 4596 power-domains = <&rpmhpd SC7280_CX>, 4597 <&rpmhpd SC7280_MX>; 4598 power-domain-names = "cx", "mx"; 4599 4600 memory-region = <&wpss_mem>; 4601 4602 qcom,qmp = <&aoss_qmp>; 4603 4604 qcom,smem-states = <&wpss_smp2p_out 0>; 4605 qcom,smem-state-names = "stop"; 4606 4607 4608 status = "disabled"; 4609 4610 glink-edge { 4611 interrupts-extended = <&ipcc IPCC_CLIENT_WPSS 4612 IPCC_MPROC_SIGNAL_GLINK_QMP 4613 IRQ_TYPE_EDGE_RISING>; 4614 mboxes = <&ipcc IPCC_CLIENT_WPSS 4615 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4616 4617 label = "wpss"; 4618 qcom,remote-pid = <13>; 4619 }; 4620 }; 4621 4622 pmu@9091000 { 4623 compatible = "qcom,sc7280-llcc-bwmon"; 4624 reg = <0 0x09091000 0 0x1000>; 4625 4626 interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; 4627 4628 interconnects = <&mc_virt MASTER_LLCC 3 &mc_virt SLAVE_EBI1 3>; 4629 4630 operating-points-v2 = <&llcc_bwmon_opp_table>; 4631 4632 llcc_bwmon_opp_table: opp-table { 4633 compatible = "operating-points-v2"; 4634 4635 opp-0 { 4636 opp-peak-kBps = <800000>; 4637 }; 4638 opp-1 { 4639 opp-peak-kBps = <1804000>; 4640 }; 4641 opp-2 { 4642 opp-peak-kBps = <2188000>; 4643 }; 4644 opp-3 { 4645 opp-peak-kBps = <3072000>; 4646 }; 4647 opp-4 { 4648 opp-peak-kBps = <4068000>; 4649 }; 4650 opp-5 { 4651 opp-peak-kBps = <6220000>; 4652 }; 4653 opp-6 { 4654 opp-peak-kBps = <6832000>; 4655 }; 4656 opp-7 { 4657 opp-peak-kBps = <8532000>; 4658 }; 4659 opp-8 { 4660 opp-peak-kBps = <10944000>; 4661 }; 4662 opp-9 { 4663 opp-peak-kBps = <12787200>; 4664 }; 4665 }; 4666 }; 4667 4668 pmu@90b6400 { 4669 compatible = "qcom,sc7280-cpu-bwmon", "qcom,sdm845-bwmon"; 4670 reg = <0 0x090b6400 0 0x600>; 4671 4672 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 4673 4674 interconnects = <&gem_noc MASTER_APPSS_PROC 3 &gem_noc SLAVE_LLCC 3>; 4675 operating-points-v2 = <&cpu_bwmon_opp_table>; 4676 4677 cpu_bwmon_opp_table: opp-table { 4678 compatible = "operating-points-v2"; 4679 4680 opp-0 { 4681 opp-peak-kBps = <2400000>; 4682 }; 4683 opp-1 { 4684 opp-peak-kBps = <4800000>; 4685 }; 4686 opp-2 { 4687 opp-peak-kBps = <7456000>; 4688 }; 4689 opp-3 { 4690 opp-peak-kBps = <9600000>; 4691 }; 4692 opp-4 { 4693 opp-peak-kBps = <12896000>; 4694 }; 4695 opp-5 { 4696 opp-peak-kBps = <14928000>; 4697 }; 4698 opp-6 { 4699 opp-peak-kBps = <17056000>; 4700 }; 4701 }; 4702 }; 4703 4704 dc_noc: interconnect@90e0000 { 4705 reg = <0 0x090e0000 0 0x5080>; 4706 compatible = "qcom,sc7280-dc-noc"; 4707 #interconnect-cells = <2>; 4708 qcom,bcm-voters = <&apps_bcm_voter>; 4709 }; 4710 4711 gem_noc: interconnect@9100000 { 4712 reg = <0 0x09100000 0 0xe2200>; 4713 compatible = "qcom,sc7280-gem-noc"; 4714 #interconnect-cells = <2>; 4715 qcom,bcm-voters = <&apps_bcm_voter>; 4716 }; 4717 4718 system-cache-controller@9200000 { 4719 compatible = "qcom,sc7280-llcc"; 4720 reg = <0 0x09200000 0 0x58000>, <0 0x09280000 0 0x58000>, 4721 <0 0x09600000 0 0x58000>; 4722 reg-names = "llcc0_base", "llcc1_base", "llcc_broadcast_base"; 4723 interrupts = <GIC_SPI 582 IRQ_TYPE_LEVEL_HIGH>; 4724 }; 4725 4726 eud: eud@88e0000 { 4727 compatible = "qcom,sc7280-eud", "qcom,eud"; 4728 reg = <0 0x88e0000 0 0x2000>, 4729 <0 0x88e2000 0 0x1000>; 4730 interrupts-extended = <&pdc 11 IRQ_TYPE_LEVEL_HIGH>; 4731 4732 status = "disabled"; 4733 4734 ports { 4735 #address-cells = <1>; 4736 #size-cells = <0>; 4737 4738 port@0 { 4739 reg = <0>; 4740 eud_ep: endpoint { 4741 remote-endpoint = <&usb2_role_switch>; 4742 }; 4743 }; 4744 }; 4745 }; 4746 4747 nsp_noc: interconnect@a0c0000 { 4748 reg = <0 0x0a0c0000 0 0x10000>; 4749 compatible = "qcom,sc7280-nsp-noc"; 4750 #interconnect-cells = <2>; 4751 qcom,bcm-voters = <&apps_bcm_voter>; 4752 }; 4753 4754 remoteproc_cdsp: remoteproc@a300000 { 4755 compatible = "qcom,sc7280-cdsp-pas"; 4756 reg = <0 0x0a300000 0 0x10000>; 4757 4758 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 4759 <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>, 4760 <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>, 4761 <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>, 4762 <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>, 4763 <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>; 4764 interrupt-names = "wdog", "fatal", "ready", "handover", 4765 "stop-ack", "shutdown-ack"; 4766 4767 clocks = <&rpmhcc RPMH_CXO_CLK>; 4768 clock-names = "xo"; 4769 4770 power-domains = <&rpmhpd SC7280_CX>, 4771 <&rpmhpd SC7280_MX>; 4772 power-domain-names = "cx", "mx"; 4773 4774 interconnects = <&nsp_noc MASTER_CDSP_PROC 0 &mc_virt SLAVE_EBI1 0>; 4775 4776 memory-region = <&cdsp_mem>; 4777 4778 qcom,qmp = <&aoss_qmp>; 4779 4780 qcom,smem-states = <&cdsp_smp2p_out 0>; 4781 qcom,smem-state-names = "stop"; 4782 4783 status = "disabled"; 4784 4785 glink-edge { 4786 interrupts-extended = <&ipcc IPCC_CLIENT_CDSP 4787 IPCC_MPROC_SIGNAL_GLINK_QMP 4788 IRQ_TYPE_EDGE_RISING>; 4789 mboxes = <&ipcc IPCC_CLIENT_CDSP 4790 IPCC_MPROC_SIGNAL_GLINK_QMP>; 4791 4792 label = "cdsp"; 4793 qcom,remote-pid = <5>; 4794 4795 fastrpc { 4796 compatible = "qcom,fastrpc"; 4797 qcom,glink-channels = "fastrpcglink-apps-dsp"; 4798 label = "cdsp"; 4799 qcom,non-secure-domain; 4800 #address-cells = <1>; 4801 #size-cells = <0>; 4802 4803 compute-cb@1 { 4804 compatible = "qcom,fastrpc-compute-cb"; 4805 reg = <1>; 4806 iommus = <&apps_smmu 0x11a1 0x0420>, 4807 <&apps_smmu 0x1181 0x0420>; 4808 dma-coherent; 4809 }; 4810 4811 compute-cb@2 { 4812 compatible = "qcom,fastrpc-compute-cb"; 4813 reg = <2>; 4814 iommus = <&apps_smmu 0x11a2 0x0420>, 4815 <&apps_smmu 0x1182 0x0420>; 4816 dma-coherent; 4817 }; 4818 4819 compute-cb@3 { 4820 compatible = "qcom,fastrpc-compute-cb"; 4821 reg = <3>; 4822 iommus = <&apps_smmu 0x11a3 0x0420>, 4823 <&apps_smmu 0x1183 0x0420>; 4824 dma-coherent; 4825 }; 4826 4827 compute-cb@4 { 4828 compatible = "qcom,fastrpc-compute-cb"; 4829 reg = <4>; 4830 iommus = <&apps_smmu 0x11a4 0x0420>, 4831 <&apps_smmu 0x1184 0x0420>; 4832 dma-coherent; 4833 }; 4834 4835 compute-cb@5 { 4836 compatible = "qcom,fastrpc-compute-cb"; 4837 reg = <5>; 4838 iommus = <&apps_smmu 0x11a5 0x0420>, 4839 <&apps_smmu 0x1185 0x0420>; 4840 dma-coherent; 4841 }; 4842 4843 compute-cb@6 { 4844 compatible = "qcom,fastrpc-compute-cb"; 4845 reg = <6>; 4846 iommus = <&apps_smmu 0x11a6 0x0420>, 4847 <&apps_smmu 0x1186 0x0420>; 4848 dma-coherent; 4849 }; 4850 4851 compute-cb@7 { 4852 compatible = "qcom,fastrpc-compute-cb"; 4853 reg = <7>; 4854 iommus = <&apps_smmu 0x11a7 0x0420>, 4855 <&apps_smmu 0x1187 0x0420>; 4856 dma-coherent; 4857 }; 4858 4859 compute-cb@8 { 4860 compatible = "qcom,fastrpc-compute-cb"; 4861 reg = <8>; 4862 iommus = <&apps_smmu 0x11a8 0x0420>, 4863 <&apps_smmu 0x1188 0x0420>; 4864 dma-coherent; 4865 }; 4866 4867 /* note: secure cb9 in downstream */ 4868 4869 compute-cb@11 { 4870 compatible = "qcom,fastrpc-compute-cb"; 4871 reg = <11>; 4872 iommus = <&apps_smmu 0x11ab 0x0420>, 4873 <&apps_smmu 0x118b 0x0420>; 4874 dma-coherent; 4875 }; 4876 4877 compute-cb@12 { 4878 compatible = "qcom,fastrpc-compute-cb"; 4879 reg = <12>; 4880 iommus = <&apps_smmu 0x11ac 0x0420>, 4881 <&apps_smmu 0x118c 0x0420>; 4882 dma-coherent; 4883 }; 4884 4885 compute-cb@13 { 4886 compatible = "qcom,fastrpc-compute-cb"; 4887 reg = <13>; 4888 iommus = <&apps_smmu 0x11ad 0x0420>, 4889 <&apps_smmu 0x118d 0x0420>; 4890 dma-coherent; 4891 }; 4892 4893 compute-cb@14 { 4894 compatible = "qcom,fastrpc-compute-cb"; 4895 reg = <14>; 4896 iommus = <&apps_smmu 0x11ae 0x0420>, 4897 <&apps_smmu 0x118e 0x0420>; 4898 dma-coherent; 4899 }; 4900 }; 4901 }; 4902 }; 4903 4904 usb_1: usb@a600000 { 4905 compatible = "qcom,sc7280-dwc3", "qcom,snps-dwc3"; 4906 reg = <0 0x0a600000 0 0xfc100>; 4907 status = "disabled"; 4908 4909 clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, 4910 <&gcc GCC_USB30_PRIM_MASTER_CLK>, 4911 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 4912 <&gcc GCC_USB30_PRIM_SLEEP_CLK>, 4913 <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>; 4914 clock-names = "cfg_noc", 4915 "core", 4916 "iface", 4917 "sleep", 4918 "mock_utmi"; 4919 4920 assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, 4921 <&gcc GCC_USB30_PRIM_MASTER_CLK>; 4922 assigned-clock-rates = <19200000>, <200000000>; 4923 4924 interrupts-extended = <&intc GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 4925 <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 4926 <&intc GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 4927 <&pdc 14 IRQ_TYPE_EDGE_BOTH>, 4928 <&pdc 15 IRQ_TYPE_EDGE_BOTH>, 4929 <&pdc 17 IRQ_TYPE_LEVEL_HIGH>; 4930 interrupt-names = "dwc_usb3", 4931 "pwr_event", 4932 "hs_phy_irq", 4933 "dp_hs_phy_irq", 4934 "dm_hs_phy_irq", 4935 "ss_phy_irq"; 4936 4937 power-domains = <&gcc GCC_USB30_PRIM_GDSC>; 4938 required-opps = <&rpmhpd_opp_nom>; 4939 4940 resets = <&gcc GCC_USB30_PRIM_BCR>; 4941 4942 interconnects = <&aggre1_noc MASTER_USB3_0 0 &mc_virt SLAVE_EBI1 0>, 4943 <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_USB3_0 0>; 4944 interconnect-names = "usb-ddr", "apps-usb"; 4945 4946 wakeup-source; 4947 4948 iommus = <&apps_smmu 0xe0 0x0>; 4949 snps,dis_u2_susphy_quirk; 4950 snps,dis_enblslpm_quirk; 4951 snps,parkmode-disable-ss-quirk; 4952 snps,dis-u1-entry-quirk; 4953 snps,dis-u2-entry-quirk; 4954 num-hc-interrupters = /bits/ 16 <3>; 4955 phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>; 4956 phy-names = "usb2-phy", "usb3-phy"; 4957 maximum-speed = "super-speed"; 4958 usb-role-switch; 4959 4960 ports { 4961 #address-cells = <1>; 4962 #size-cells = <0>; 4963 4964 port@0 { 4965 reg = <0>; 4966 4967 usb_1_dwc3_hs: endpoint { 4968 }; 4969 }; 4970 4971 port@1 { 4972 reg = <1>; 4973 4974 usb_1_dwc3_ss: endpoint { 4975 remote-endpoint = <&usb_dp_qmpphy_usb_ss_in>; 4976 }; 4977 }; 4978 }; 4979 }; 4980 4981 venus: video-codec@aa00000 { 4982 compatible = "qcom,sc7280-venus"; 4983 reg = <0 0x0aa00000 0 0xd0600>; 4984 interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 4985 4986 clocks = <&videocc VIDEO_CC_MVSC_CORE_CLK>, 4987 <&videocc VIDEO_CC_MVSC_CTL_AXI_CLK>, 4988 <&videocc VIDEO_CC_VENUS_AHB_CLK>, 4989 <&videocc VIDEO_CC_MVS0_CORE_CLK>, 4990 <&videocc VIDEO_CC_MVS0_AXI_CLK>; 4991 clock-names = "core", "bus", "iface", 4992 "vcodec_core", "vcodec_bus"; 4993 4994 power-domains = <&videocc MVSC_GDSC>, 4995 <&videocc MVS0_GDSC>, 4996 <&rpmhpd SC7280_CX>; 4997 power-domain-names = "venus", "vcodec0", "cx"; 4998 operating-points-v2 = <&venus_opp_table>; 4999 5000 interconnects = <&gem_noc MASTER_APPSS_PROC 0 &cnoc2 SLAVE_VENUS_CFG 0>, 5001 <&mmss_noc MASTER_VIDEO_P0 0 &mc_virt SLAVE_EBI1 0>; 5002 interconnect-names = "cpu-cfg", "video-mem"; 5003 5004 iommus = <&apps_smmu 0x2180 0x20>; 5005 memory-region = <&video_mem>; 5006 5007 status = "disabled"; 5008 5009 venus_opp_table: opp-table { 5010 compatible = "operating-points-v2"; 5011 5012 opp-133330000 { 5013 opp-hz = /bits/ 64 <133330000>; 5014 required-opps = <&rpmhpd_opp_low_svs>; 5015 }; 5016 5017 opp-240000000 { 5018 opp-hz = /bits/ 64 <240000000>; 5019 required-opps = <&rpmhpd_opp_svs>; 5020 }; 5021 5022 opp-335000000 { 5023 opp-hz = /bits/ 64 <335000000>; 5024 required-opps = <&rpmhpd_opp_svs_l1>; 5025 }; 5026 5027 opp-424000000 { 5028 opp-hz = /bits/ 64 <424000000>; 5029 required-opps = <&rpmhpd_opp_nom>; 5030 }; 5031 5032 opp-460000048 { 5033 opp-hz = /bits/ 64 <460000048>; 5034 required-opps = <&rpmhpd_opp_turbo>; 5035 }; 5036 }; 5037 }; 5038 5039 videocc: clock-controller@aaf0000 { 5040 compatible = "qcom,sc7280-videocc"; 5041 reg = <0 0x0aaf0000 0 0x10000>; 5042 clocks = <&rpmhcc RPMH_CXO_CLK>, 5043 <&rpmhcc RPMH_CXO_CLK_A>; 5044 clock-names = "bi_tcxo", "bi_tcxo_ao"; 5045 #clock-cells = <1>; 5046 #reset-cells = <1>; 5047 #power-domain-cells = <1>; 5048 }; 5049 5050 cci0: cci@ac4a000 { 5051 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 5052 reg = <0 0x0ac4a000 0 0x1000>; 5053 interrupts = <GIC_SPI 460 IRQ_TYPE_EDGE_RISING>; 5054 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5055 5056 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5057 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 5058 <&camcc CAM_CC_CPAS_AHB_CLK>, 5059 <&camcc CAM_CC_CCI_0_CLK>, 5060 <&camcc CAM_CC_CCI_0_CLK_SRC>; 5061 clock-names = "camnoc_axi", 5062 "slow_ahb_src", 5063 "cpas_ahb", 5064 "cci", 5065 "cci_src"; 5066 pinctrl-0 = <&cci0_default &cci1_default>; 5067 pinctrl-1 = <&cci0_sleep &cci1_sleep>; 5068 pinctrl-names = "default", "sleep"; 5069 5070 #address-cells = <1>; 5071 #size-cells = <0>; 5072 5073 status = "disabled"; 5074 5075 cci0_i2c0: i2c-bus@0 { 5076 reg = <0>; 5077 clock-frequency = <1000000>; 5078 #address-cells = <1>; 5079 #size-cells = <0>; 5080 }; 5081 5082 cci0_i2c1: i2c-bus@1 { 5083 reg = <1>; 5084 clock-frequency = <1000000>; 5085 #address-cells = <1>; 5086 #size-cells = <0>; 5087 }; 5088 }; 5089 5090 cci1: cci@ac4b000 { 5091 compatible = "qcom,sc7280-cci", "qcom,msm8996-cci"; 5092 reg = <0 0x0ac4b000 0 0x1000>; 5093 interrupts = <GIC_SPI 271 IRQ_TYPE_EDGE_RISING>; 5094 power-domains = <&camcc CAM_CC_TITAN_TOP_GDSC>; 5095 5096 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5097 <&camcc CAM_CC_SLOW_AHB_CLK_SRC>, 5098 <&camcc CAM_CC_CPAS_AHB_CLK>, 5099 <&camcc CAM_CC_CCI_1_CLK>, 5100 <&camcc CAM_CC_CCI_1_CLK_SRC>; 5101 clock-names = "camnoc_axi", 5102 "slow_ahb_src", 5103 "cpas_ahb", 5104 "cci", 5105 "cci_src"; 5106 pinctrl-0 = <&cci2_default &cci3_default>; 5107 pinctrl-1 = <&cci2_sleep &cci3_sleep>; 5108 pinctrl-names = "default", "sleep"; 5109 5110 #address-cells = <1>; 5111 #size-cells = <0>; 5112 5113 status = "disabled"; 5114 5115 cci1_i2c0: i2c-bus@0 { 5116 reg = <0>; 5117 clock-frequency = <1000000>; 5118 #address-cells = <1>; 5119 #size-cells = <0>; 5120 }; 5121 5122 cci1_i2c1: i2c-bus@1 { 5123 reg = <1>; 5124 clock-frequency = <1000000>; 5125 #address-cells = <1>; 5126 #size-cells = <0>; 5127 }; 5128 }; 5129 5130 camss: isp@acb3000 { 5131 compatible = "qcom,sc7280-camss"; 5132 5133 reg = <0x0 0x0acb3000 0x0 0x1000>, 5134 <0x0 0x0acba000 0x0 0x1000>, 5135 <0x0 0x0acc1000 0x0 0x1000>, 5136 <0x0 0x0acc8000 0x0 0x1000>, 5137 <0x0 0x0accf000 0x0 0x1000>, 5138 <0x0 0x0ace0000 0x0 0x2000>, 5139 <0x0 0x0ace2000 0x0 0x2000>, 5140 <0x0 0x0ace4000 0x0 0x2000>, 5141 <0x0 0x0ace6000 0x0 0x2000>, 5142 <0x0 0x0ace8000 0x0 0x2000>, 5143 <0x0 0x0acaf000 0x0 0x4000>, 5144 <0x0 0x0acb6000 0x0 0x4000>, 5145 <0x0 0x0acbd000 0x0 0x4000>, 5146 <0x0 0x0acc4000 0x0 0x4000>, 5147 <0x0 0x0accb000 0x0 0x4000>; 5148 reg-names = "csid0", 5149 "csid1", 5150 "csid2", 5151 "csid_lite0", 5152 "csid_lite1", 5153 "csiphy0", 5154 "csiphy1", 5155 "csiphy2", 5156 "csiphy3", 5157 "csiphy4", 5158 "vfe0", 5159 "vfe1", 5160 "vfe2", 5161 "vfe_lite0", 5162 "vfe_lite1"; 5163 5164 clocks = <&camcc CAM_CC_CAMNOC_AXI_CLK>, 5165 <&camcc CAM_CC_CPAS_AHB_CLK>, 5166 <&camcc CAM_CC_CSIPHY0_CLK>, 5167 <&camcc CAM_CC_CSI0PHYTIMER_CLK>, 5168 <&camcc CAM_CC_CSIPHY1_CLK>, 5169 <&camcc CAM_CC_CSI1PHYTIMER_CLK>, 5170 <&camcc CAM_CC_CSIPHY2_CLK>, 5171 <&camcc CAM_CC_CSI2PHYTIMER_CLK>, 5172 <&camcc CAM_CC_CSIPHY3_CLK>, 5173 <&camcc CAM_CC_CSI3PHYTIMER_CLK>, 5174 <&camcc CAM_CC_CSIPHY4_CLK>, 5175 <&camcc CAM_CC_CSI4PHYTIMER_CLK>, 5176 <&gcc GCC_CAMERA_HF_AXI_CLK>, 5177 <&gcc GCC_CAMERA_SF_AXI_CLK>, 5178 <&camcc CAM_CC_ICP_AHB_CLK>, 5179 <&camcc CAM_CC_IFE_0_CLK>, 5180 <&camcc CAM_CC_IFE_0_AXI_CLK>, 5181 <&camcc CAM_CC_IFE_0_CPHY_RX_CLK>, 5182 <&camcc CAM_CC_IFE_0_CSID_CLK>, 5183 <&camcc CAM_CC_IFE_1_CLK>, 5184 <&camcc CAM_CC_IFE_1_AXI_CLK>, 5185 <&camcc CAM_CC_IFE_1_CPHY_RX_CLK>, 5186 <&camcc CAM_CC_IFE_1_CSID_CLK>, 5187 <&camcc CAM_CC_IFE_2_CLK>, 5188 <&camcc CAM_CC_IFE_2_AXI_CLK>, 5189 <&camcc CAM_CC_IFE_2_CPHY_RX_CLK>, 5190 <&camcc CAM_CC_IFE_2_CSID_CLK>, 5191 <&camcc CAM_CC_IFE_LITE_0_CLK>, 5192 <&camcc CAM_CC_IFE_LITE_0_CPHY_RX_CLK>, 5193 <&camcc CAM_CC_IFE_LITE_0_CSID_CLK>, 5194 <&camcc CAM_CC_IFE_LITE_1_CLK>, 5195 <&camcc CAM_CC_IFE_LITE_1_CPHY_RX_CLK>, 5196 <&camcc CAM_CC_IFE_LITE_1_CSID_CLK>; 5197 clock-names = "camnoc_axi", 5198 "cpas_ahb", 5199 "csiphy0", 5200 "csiphy0_timer", 5201 "csiphy1", 5202 "csiphy1_timer", 5203 "csiphy2", 5204 "csiphy2_timer", 5205 "csiphy3", 5206 "csiphy3_timer", 5207 "csiphy4", 5208 "csiphy4_timer", 5209 "gcc_axi_hf", 5210 "gcc_axi_sf", 5211 "icp_ahb", 5212 "vfe0", 5213 "vfe0_axi", 5214 "vfe0_cphy_rx", 5215 "vfe0_csid", 5216 "vfe1", 5217 "vfe1_axi", 5218 "vfe1_cphy_rx", 5219 "vfe1_csid", 5220 "vfe2", 5221 "vfe2_axi", 5222 "vfe2_cphy_rx", 5223 "vfe2_csid", 5224 "vfe_lite0", 5225 "vfe_lite0_cphy_rx", 5226 "vfe_lite0_csid", 5227 "vfe_lite1", 5228 "vfe_lite1_cphy_rx", 5229 "vfe_lite1_csid"; 5230 5231 interrupts = <GIC_SPI 464 IRQ_TYPE_EDGE_RISING>, 5232 <GIC_SPI 466 IRQ_TYPE_EDGE_RISING>, 5233 <GIC_SPI 640 IRQ_TYPE_EDGE_RISING>, 5234 <GIC_SPI 468 IRQ_TYPE_EDGE_RISING>, 5235 <GIC_SPI 359 IRQ_TYPE_EDGE_RISING>, 5236 <GIC_SPI 477 IRQ_TYPE_EDGE_RISING>, 5237 <GIC_SPI 478 IRQ_TYPE_EDGE_RISING>, 5238 <GIC_SPI 479 IRQ_TYPE_EDGE_RISING>, 5239 <GIC_SPI 448 IRQ_TYPE_EDGE_RISING>, 5240 <GIC_SPI 122 IRQ_TYPE_EDGE_RISING>, 5241 <GIC_SPI 465 IRQ_TYPE_EDGE_RISING>, 5242 <GIC_SPI 467 IRQ_TYPE_EDGE_RISING>, 5243 <GIC_SPI 641 IRQ_TYPE_EDGE_RISING>, 5244 <GIC_SPI 469 IRQ_TYPE_EDGE_RISING>, 5245 <GIC_SPI 360 IRQ_TYPE_EDGE_RISING>; 5246 interrupt-names = "csid0", 5247 "csid1", 5248 "csid2", 5249 "csid_lite0", 5250 "csid_lite1", 5251 "csiphy0", 5252 "csiphy1", 5253 "csiphy2", 5254 "csiphy3", 5255 "csiphy4", 5256 "vfe0", 5257 "vfe1", 5258 "vfe2", 5259 "vfe_lite0", 5260 "vfe_lite1"; 5261 5262 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5263 &cnoc2 SLAVE_CAMERA_CFG QCOM_ICC_TAG_ACTIVE_ONLY>, 5264 <&mmss_noc MASTER_CAMNOC_HF QCOM_ICC_TAG_ALWAYS 5265 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5266 interconnect-names = "ahb", 5267 "hf_0"; 5268 5269 iommus = <&apps_smmu 0x800 0x4e0>; 5270 5271 power-domains = <&camcc CAM_CC_IFE_0_GDSC>, 5272 <&camcc CAM_CC_IFE_1_GDSC>, 5273 <&camcc CAM_CC_IFE_2_GDSC>, 5274 <&camcc CAM_CC_TITAN_TOP_GDSC>; 5275 power-domain-names = "ife0", 5276 "ife1", 5277 "ife2", 5278 "top"; 5279 5280 status = "disabled"; 5281 5282 ports { 5283 #address-cells = <1>; 5284 #size-cells = <0>; 5285 5286 port@0 { 5287 reg = <0>; 5288 }; 5289 5290 port@1 { 5291 reg = <1>; 5292 }; 5293 5294 port@2 { 5295 reg = <2>; 5296 }; 5297 5298 port@3 { 5299 reg = <3>; 5300 }; 5301 5302 port@4 { 5303 reg = <4>; 5304 }; 5305 }; 5306 }; 5307 5308 camcc: clock-controller@ad00000 { 5309 compatible = "qcom,sc7280-camcc"; 5310 reg = <0 0x0ad00000 0 0x10000>; 5311 clocks = <&rpmhcc RPMH_CXO_CLK>, 5312 <&rpmhcc RPMH_CXO_CLK_A>, 5313 <&sleep_clk>; 5314 clock-names = "bi_tcxo", "bi_tcxo_ao", "sleep_clk"; 5315 #clock-cells = <1>; 5316 #reset-cells = <1>; 5317 #power-domain-cells = <1>; 5318 }; 5319 5320 dispcc: clock-controller@af00000 { 5321 compatible = "qcom,sc7280-dispcc"; 5322 reg = <0 0x0af00000 0 0x20000>; 5323 clocks = <&rpmhcc RPMH_CXO_CLK>, 5324 <&gcc GCC_DISP_GPLL0_CLK_SRC>, 5325 <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, 5326 <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>, 5327 <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5328 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>, 5329 <&mdss_edp_phy 0>, 5330 <&mdss_edp_phy 1>; 5331 clock-names = "bi_tcxo", 5332 "gcc_disp_gpll0_clk", 5333 "dsi0_phy_pll_out_byteclk", 5334 "dsi0_phy_pll_out_dsiclk", 5335 "dp_phy_pll_link_clk", 5336 "dp_phy_pll_vco_div_clk", 5337 "edp_phy_pll_link_clk", 5338 "edp_phy_pll_vco_div_clk"; 5339 #clock-cells = <1>; 5340 #reset-cells = <1>; 5341 #power-domain-cells = <1>; 5342 }; 5343 5344 mdss: display-subsystem@ae00000 { 5345 compatible = "qcom,sc7280-mdss"; 5346 reg = <0 0x0ae00000 0 0x1000>; 5347 reg-names = "mdss"; 5348 5349 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 5350 5351 clocks = <&gcc GCC_DISP_AHB_CLK>, 5352 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5353 <&dispcc DISP_CC_MDSS_MDP_CLK>; 5354 clock-names = "iface", 5355 "ahb", 5356 "core"; 5357 5358 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 5359 interrupt-controller; 5360 #interrupt-cells = <1>; 5361 5362 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ALWAYS 5363 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 5364 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 5365 &cnoc2 SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ALWAYS>; 5366 interconnect-names = "mdp0-mem", 5367 "cpu-cfg"; 5368 5369 iommus = <&apps_smmu 0x900 0x402>; 5370 5371 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 5372 5373 #address-cells = <2>; 5374 #size-cells = <2>; 5375 ranges; 5376 5377 status = "disabled"; 5378 5379 mdss_mdp: display-controller@ae01000 { 5380 compatible = "qcom,sc7280-dpu"; 5381 reg = <0 0x0ae01000 0 0x8f030>, 5382 <0 0x0aeb0000 0 0x3000>; 5383 reg-names = "mdp", "vbif"; 5384 5385 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 5386 <&gcc GCC_DISP_SF_AXI_CLK>, 5387 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5388 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 5389 <&dispcc DISP_CC_MDSS_MDP_CLK>, 5390 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 5391 clock-names = "bus", 5392 "nrt_bus", 5393 "iface", 5394 "lut", 5395 "core", 5396 "vsync"; 5397 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>, 5398 <&dispcc DISP_CC_MDSS_AHB_CLK>; 5399 assigned-clock-rates = <19200000>, 5400 <19200000>; 5401 operating-points-v2 = <&mdp_opp_table>; 5402 power-domains = <&rpmhpd SC7280_CX>; 5403 5404 interrupt-parent = <&mdss>; 5405 interrupts = <0>; 5406 5407 ports { 5408 #address-cells = <1>; 5409 #size-cells = <0>; 5410 5411 port@0 { 5412 reg = <0>; 5413 dpu_intf1_out: endpoint { 5414 remote-endpoint = <&mdss_dsi0_in>; 5415 }; 5416 }; 5417 5418 port@1 { 5419 reg = <1>; 5420 dpu_intf5_out: endpoint { 5421 remote-endpoint = <&edp_in>; 5422 }; 5423 }; 5424 5425 port@2 { 5426 reg = <2>; 5427 dpu_intf0_out: endpoint { 5428 remote-endpoint = <&dp_in>; 5429 }; 5430 }; 5431 }; 5432 5433 mdp_opp_table: opp-table { 5434 compatible = "operating-points-v2"; 5435 5436 opp-200000000 { 5437 opp-hz = /bits/ 64 <200000000>; 5438 required-opps = <&rpmhpd_opp_low_svs>; 5439 }; 5440 5441 opp-300000000 { 5442 opp-hz = /bits/ 64 <300000000>; 5443 required-opps = <&rpmhpd_opp_svs>; 5444 }; 5445 5446 opp-380000000 { 5447 opp-hz = /bits/ 64 <380000000>; 5448 required-opps = <&rpmhpd_opp_svs_l1>; 5449 }; 5450 5451 opp-506666667 { 5452 opp-hz = /bits/ 64 <506666667>; 5453 required-opps = <&rpmhpd_opp_nom>; 5454 }; 5455 5456 opp-608000000 { 5457 opp-hz = /bits/ 64 <608000000>; 5458 required-opps = <&rpmhpd_opp_turbo>; 5459 }; 5460 }; 5461 }; 5462 5463 mdss_dsi: dsi@ae94000 { 5464 compatible = "qcom,sc7280-dsi-ctrl", 5465 "qcom,mdss-dsi-ctrl"; 5466 reg = <0 0x0ae94000 0 0x400>; 5467 reg-names = "dsi_ctrl"; 5468 5469 interrupt-parent = <&mdss>; 5470 interrupts = <4>; 5471 5472 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 5473 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 5474 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 5475 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 5476 <&dispcc DISP_CC_MDSS_AHB_CLK>, 5477 <&gcc GCC_DISP_HF_AXI_CLK>; 5478 clock-names = "byte", 5479 "byte_intf", 5480 "pixel", 5481 "core", 5482 "iface", 5483 "bus"; 5484 5485 assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 5486 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 5487 assigned-clock-parents = <&mdss_dsi_phy DSI_BYTE_PLL_CLK>, 5488 <&mdss_dsi_phy DSI_PIXEL_PLL_CLK>; 5489 5490 operating-points-v2 = <&dsi_opp_table>; 5491 power-domains = <&rpmhpd SC7280_CX>; 5492 5493 phys = <&mdss_dsi_phy>; 5494 5495 refgen-supply = <&refgen>; 5496 5497 #address-cells = <1>; 5498 #size-cells = <0>; 5499 5500 status = "disabled"; 5501 5502 ports { 5503 #address-cells = <1>; 5504 #size-cells = <0>; 5505 5506 port@0 { 5507 reg = <0>; 5508 mdss_dsi0_in: endpoint { 5509 remote-endpoint = <&dpu_intf1_out>; 5510 }; 5511 }; 5512 5513 port@1 { 5514 reg = <1>; 5515 mdss_dsi0_out: endpoint { 5516 }; 5517 }; 5518 }; 5519 5520 dsi_opp_table: opp-table { 5521 compatible = "operating-points-v2"; 5522 5523 opp-187500000 { 5524 opp-hz = /bits/ 64 <187500000>; 5525 required-opps = <&rpmhpd_opp_low_svs>; 5526 }; 5527 5528 opp-300000000 { 5529 opp-hz = /bits/ 64 <300000000>; 5530 required-opps = <&rpmhpd_opp_svs>; 5531 }; 5532 5533 opp-358000000 { 5534 opp-hz = /bits/ 64 <358000000>; 5535 required-opps = <&rpmhpd_opp_svs_l1>; 5536 }; 5537 }; 5538 }; 5539 5540 mdss_dsi_phy: phy@ae94400 { 5541 compatible = "qcom,sc7280-dsi-phy-7nm"; 5542 reg = <0 0x0ae94400 0 0x200>, 5543 <0 0x0ae94600 0 0x280>, 5544 <0 0x0ae94900 0 0x280>; 5545 reg-names = "dsi_phy", 5546 "dsi_phy_lane", 5547 "dsi_pll"; 5548 5549 #clock-cells = <1>; 5550 #phy-cells = <0>; 5551 5552 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5553 <&rpmhcc RPMH_CXO_CLK>; 5554 clock-names = "iface", "ref"; 5555 5556 status = "disabled"; 5557 }; 5558 5559 mdss_edp: edp@aea0000 { 5560 compatible = "qcom,sc7280-edp"; 5561 pinctrl-names = "default"; 5562 pinctrl-0 = <&edp_hot_plug_det>; 5563 5564 reg = <0 0x0aea0000 0 0x200>, 5565 <0 0x0aea0200 0 0x200>, 5566 <0 0x0aea0400 0 0xc00>, 5567 <0 0x0aea1000 0 0x400>, 5568 <0 0x0aea1400 0 0x400>; 5569 5570 interrupt-parent = <&mdss>; 5571 interrupts = <14>; 5572 5573 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5574 <&dispcc DISP_CC_MDSS_EDP_AUX_CLK>, 5575 <&dispcc DISP_CC_MDSS_EDP_LINK_CLK>, 5576 <&dispcc DISP_CC_MDSS_EDP_LINK_INTF_CLK>, 5577 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK>; 5578 clock-names = "core_iface", 5579 "core_aux", 5580 "ctrl_link", 5581 "ctrl_link_iface", 5582 "stream_pixel"; 5583 assigned-clocks = <&dispcc DISP_CC_MDSS_EDP_LINK_CLK_SRC>, 5584 <&dispcc DISP_CC_MDSS_EDP_PIXEL_CLK_SRC>; 5585 assigned-clock-parents = <&mdss_edp_phy 0>, <&mdss_edp_phy 1>; 5586 5587 phys = <&mdss_edp_phy>; 5588 phy-names = "dp"; 5589 5590 operating-points-v2 = <&edp_opp_table>; 5591 power-domains = <&rpmhpd SC7280_CX>; 5592 5593 status = "disabled"; 5594 5595 ports { 5596 #address-cells = <1>; 5597 #size-cells = <0>; 5598 5599 port@0 { 5600 reg = <0>; 5601 edp_in: endpoint { 5602 remote-endpoint = <&dpu_intf5_out>; 5603 }; 5604 }; 5605 5606 port@1 { 5607 reg = <1>; 5608 mdss_edp_out: endpoint { }; 5609 }; 5610 }; 5611 5612 edp_opp_table: opp-table { 5613 compatible = "operating-points-v2"; 5614 5615 opp-162000000 { 5616 opp-hz = /bits/ 64 <162000000>; 5617 required-opps = <&rpmhpd_opp_low_svs>; 5618 }; 5619 5620 opp-270000000 { 5621 opp-hz = /bits/ 64 <270000000>; 5622 required-opps = <&rpmhpd_opp_svs>; 5623 }; 5624 5625 opp-540000000 { 5626 opp-hz = /bits/ 64 <540000000>; 5627 required-opps = <&rpmhpd_opp_nom>; 5628 }; 5629 5630 opp-810000000 { 5631 opp-hz = /bits/ 64 <810000000>; 5632 required-opps = <&rpmhpd_opp_nom>; 5633 }; 5634 }; 5635 }; 5636 5637 mdss_edp_phy: phy@aec2a00 { 5638 compatible = "qcom,sc7280-edp-phy"; 5639 5640 reg = <0 0x0aec2a00 0 0x19c>, 5641 <0 0x0aec2200 0 0xa0>, 5642 <0 0x0aec2600 0 0xa0>, 5643 <0 0x0aec2000 0 0x1c0>; 5644 5645 clocks = <&rpmhcc RPMH_CXO_CLK>, 5646 <&gcc GCC_EDP_CLKREF_EN>; 5647 clock-names = "aux", 5648 "cfg_ahb"; 5649 5650 #clock-cells = <1>; 5651 #phy-cells = <0>; 5652 5653 status = "disabled"; 5654 }; 5655 5656 mdss_dp: displayport-controller@ae90000 { 5657 compatible = "qcom,sc7280-dp"; 5658 5659 reg = <0 0x0ae90000 0 0x200>, 5660 <0 0x0ae90200 0 0x200>, 5661 <0 0x0ae90400 0 0xc00>, 5662 <0 0x0ae91000 0 0x400>, 5663 <0 0x0ae91400 0 0x400>; 5664 5665 interrupt-parent = <&mdss>; 5666 interrupts = <12>; 5667 5668 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 5669 <&dispcc DISP_CC_MDSS_DP_AUX_CLK>, 5670 <&dispcc DISP_CC_MDSS_DP_LINK_CLK>, 5671 <&dispcc DISP_CC_MDSS_DP_LINK_INTF_CLK>, 5672 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK>; 5673 clock-names = "core_iface", 5674 "core_aux", 5675 "ctrl_link", 5676 "ctrl_link_iface", 5677 "stream_pixel"; 5678 assigned-clocks = <&dispcc DISP_CC_MDSS_DP_LINK_CLK_SRC>, 5679 <&dispcc DISP_CC_MDSS_DP_PIXEL_CLK_SRC>; 5680 assigned-clock-parents = <&usb_1_qmpphy QMP_USB43DP_DP_LINK_CLK>, 5681 <&usb_1_qmpphy QMP_USB43DP_DP_VCO_DIV_CLK>; 5682 phys = <&usb_1_qmpphy QMP_USB43DP_DP_PHY>; 5683 phy-names = "dp"; 5684 5685 operating-points-v2 = <&dp_opp_table>; 5686 power-domains = <&rpmhpd SC7280_CX>; 5687 5688 #sound-dai-cells = <0>; 5689 5690 status = "disabled"; 5691 5692 ports { 5693 #address-cells = <1>; 5694 #size-cells = <0>; 5695 5696 port@0 { 5697 reg = <0>; 5698 dp_in: endpoint { 5699 remote-endpoint = <&dpu_intf0_out>; 5700 }; 5701 }; 5702 5703 port@1 { 5704 reg = <1>; 5705 mdss_dp_out: endpoint { 5706 remote-endpoint = <&usb_dp_qmpphy_dp_in>; 5707 }; 5708 }; 5709 }; 5710 5711 dp_opp_table: opp-table { 5712 compatible = "operating-points-v2"; 5713 5714 opp-162000000 { 5715 opp-hz = /bits/ 64 <162000000>; 5716 required-opps = <&rpmhpd_opp_low_svs>; 5717 }; 5718 5719 opp-270000000 { 5720 opp-hz = /bits/ 64 <270000000>; 5721 required-opps = <&rpmhpd_opp_svs>; 5722 }; 5723 5724 opp-540000000 { 5725 opp-hz = /bits/ 64 <540000000>; 5726 required-opps = <&rpmhpd_opp_svs_l1>; 5727 }; 5728 5729 opp-810000000 { 5730 opp-hz = /bits/ 64 <810000000>; 5731 required-opps = <&rpmhpd_opp_nom>; 5732 }; 5733 }; 5734 }; 5735 }; 5736 5737 pdc: interrupt-controller@b220000 { 5738 compatible = "qcom,sc7280-pdc", "qcom,pdc"; 5739 reg = <0 0x0b220000 0 0x30000>; 5740 qcom,pdc-ranges = <0 480 40>, <40 140 14>, <54 263 1>, 5741 <55 306 4>, <59 312 3>, <62 374 2>, 5742 <64 434 2>, <66 438 3>, <69 86 1>, 5743 <70 520 54>, <124 609 31>, <155 63 1>, 5744 <156 716 12>; 5745 #interrupt-cells = <2>; 5746 interrupt-parent = <&intc>; 5747 interrupt-controller; 5748 }; 5749 5750 pdc_reset: reset-controller@b5e0000 { 5751 compatible = "qcom,sc7280-pdc-global"; 5752 reg = <0 0x0b5e0000 0 0x20000>; 5753 #reset-cells = <1>; 5754 status = "reserved"; /* Owned by firmware */ 5755 }; 5756 5757 tsens0: thermal-sensor@c263000 { 5758 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 5759 reg = <0 0x0c263000 0 0x1ff>, /* TM */ 5760 <0 0x0c222000 0 0x1ff>; /* SROT */ 5761 #qcom,sensors = <15>; 5762 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 5763 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>; 5764 interrupt-names = "uplow","critical"; 5765 #thermal-sensor-cells = <1>; 5766 }; 5767 5768 tsens1: thermal-sensor@c265000 { 5769 compatible = "qcom,sc7280-tsens","qcom,tsens-v2"; 5770 reg = <0 0x0c265000 0 0x1ff>, /* TM */ 5771 <0 0x0c223000 0 0x1ff>; /* SROT */ 5772 #qcom,sensors = <12>; 5773 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 5774 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>; 5775 interrupt-names = "uplow","critical"; 5776 #thermal-sensor-cells = <1>; 5777 }; 5778 5779 aoss_reset: reset-controller@c2a0000 { 5780 compatible = "qcom,sc7280-aoss-cc", "qcom,sdm845-aoss-cc"; 5781 reg = <0 0x0c2a0000 0 0x31000>; 5782 #reset-cells = <1>; 5783 }; 5784 5785 aoss_qmp: power-management@c300000 { 5786 compatible = "qcom,sc7280-aoss-qmp", "qcom,aoss-qmp"; 5787 reg = <0 0x0c300000 0 0x400>; 5788 interrupts-extended = <&ipcc IPCC_CLIENT_AOP 5789 IPCC_MPROC_SIGNAL_GLINK_QMP 5790 IRQ_TYPE_EDGE_RISING>; 5791 mboxes = <&ipcc IPCC_CLIENT_AOP 5792 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5793 5794 #clock-cells = <0>; 5795 }; 5796 5797 sram@c3f0000 { 5798 compatible = "qcom,rpmh-stats"; 5799 reg = <0 0x0c3f0000 0 0x400>; 5800 }; 5801 5802 spmi_bus: spmi@c440000 { 5803 compatible = "qcom,spmi-pmic-arb"; 5804 reg = <0 0x0c440000 0 0x1100>, 5805 <0 0x0c600000 0 0x2000000>, 5806 <0 0x0e600000 0 0x100000>, 5807 <0 0x0e700000 0 0xa0000>, 5808 <0 0x0c40a000 0 0x26000>; 5809 reg-names = "core", "chnls", "obsrvr", "intr", "cnfg"; 5810 interrupt-names = "periph_irq"; 5811 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 5812 qcom,ee = <0>; 5813 qcom,channel = <0>; 5814 #address-cells = <2>; 5815 #size-cells = <0>; 5816 interrupt-controller; 5817 #interrupt-cells = <4>; 5818 }; 5819 5820 tlmm: pinctrl@f100000 { 5821 compatible = "qcom,sc7280-pinctrl"; 5822 reg = <0 0x0f100000 0 0x300000>; 5823 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 5824 gpio-controller; 5825 #gpio-cells = <2>; 5826 interrupt-controller; 5827 #interrupt-cells = <2>; 5828 gpio-ranges = <&tlmm 0 0 175>; 5829 wakeup-parent = <&pdc>; 5830 5831 cam_mclk3_default: cam-mclk3-default-state { 5832 pins = "gpio67"; 5833 function = "cam_mclk"; 5834 drive-strength = <2>; 5835 bias-disable; 5836 }; 5837 5838 cci0_default: cci0-default-state { 5839 pins = "gpio69", "gpio70"; 5840 function = "cci_i2c"; 5841 drive-strength = <2>; 5842 bias-pull-up; 5843 }; 5844 5845 cci0_sleep: cci0-sleep-state { 5846 pins = "gpio69", "gpio70"; 5847 function = "cci_i2c"; 5848 drive-strength = <2>; 5849 bias-pull-down; 5850 }; 5851 5852 cci1_default: cci1-default-state { 5853 pins = "gpio71", "gpio72"; 5854 function = "cci_i2c"; 5855 drive-strength = <2>; 5856 bias-pull-up; 5857 }; 5858 5859 cci1_sleep: cci1-sleep-state { 5860 pins = "gpio71", "gpio72"; 5861 function = "cci_i2c"; 5862 drive-strength = <2>; 5863 bias-pull-down; 5864 }; 5865 5866 cci2_default: cci2-default-state { 5867 pins = "gpio73", "gpio74"; 5868 function = "cci_i2c"; 5869 drive-strength = <2>; 5870 bias-pull-up; 5871 }; 5872 5873 cci2_sleep: cci2-sleep-state { 5874 pins = "gpio73", "gpio74"; 5875 function = "cci_i2c"; 5876 drive-strength = <2>; 5877 bias-pull-down; 5878 }; 5879 5880 cci3_default: cci3-default-state { 5881 pins = "gpio75", "gpio76"; 5882 function = "cci_i2c"; 5883 drive-strength = <2>; 5884 bias-pull-up; 5885 }; 5886 5887 cci3_sleep: cci3-sleep-state { 5888 pins = "gpio75", "gpio76"; 5889 function = "cci_i2c"; 5890 drive-strength = <2>; 5891 bias-pull-down; 5892 }; 5893 5894 dp_hot_plug_det: dp-hot-plug-det-state { 5895 pins = "gpio47"; 5896 function = "dp_hot"; 5897 }; 5898 5899 edp_hot_plug_det: edp-hot-plug-det-state { 5900 pins = "gpio60"; 5901 function = "edp_hot"; 5902 }; 5903 5904 mi2s0_data0: mi2s0-data0-state { 5905 pins = "gpio98"; 5906 function = "mi2s0_data0"; 5907 }; 5908 5909 mi2s0_data1: mi2s0-data1-state { 5910 pins = "gpio99"; 5911 function = "mi2s0_data1"; 5912 }; 5913 5914 mi2s0_mclk: mi2s0-mclk-state { 5915 pins = "gpio96"; 5916 function = "pri_mi2s"; 5917 }; 5918 5919 mi2s0_sclk: mi2s0-sclk-state { 5920 pins = "gpio97"; 5921 function = "mi2s0_sck"; 5922 }; 5923 5924 mi2s0_ws: mi2s0-ws-state { 5925 pins = "gpio100"; 5926 function = "mi2s0_ws"; 5927 }; 5928 5929 mi2s1_data0: mi2s1-data0-state { 5930 pins = "gpio107"; 5931 function = "mi2s1_data0"; 5932 }; 5933 5934 mi2s1_sclk: mi2s1-sclk-state { 5935 pins = "gpio106"; 5936 function = "mi2s1_sck"; 5937 }; 5938 5939 mi2s1_ws: mi2s1-ws-state { 5940 pins = "gpio108"; 5941 function = "mi2s1_ws"; 5942 }; 5943 5944 pcie0_clkreq_n: pcie0-clkreq-n-state { 5945 pins = "gpio88"; 5946 function = "pcie0_clkreqn"; 5947 }; 5948 5949 pcie1_clkreq_n: pcie1-clkreq-n-state { 5950 pins = "gpio79"; 5951 function = "pcie1_clkreqn"; 5952 }; 5953 5954 qspi_clk: qspi-clk-state { 5955 pins = "gpio14"; 5956 function = "qspi_clk"; 5957 }; 5958 5959 qspi_cs0: qspi-cs0-state { 5960 pins = "gpio15"; 5961 function = "qspi_cs"; 5962 }; 5963 5964 qspi_cs1: qspi-cs1-state { 5965 pins = "gpio19"; 5966 function = "qspi_cs"; 5967 }; 5968 5969 qspi_data0: qspi-data0-state { 5970 pins = "gpio12"; 5971 function = "qspi_data"; 5972 }; 5973 5974 qspi_data1: qspi-data1-state { 5975 pins = "gpio13"; 5976 function = "qspi_data"; 5977 }; 5978 5979 qspi_data23: qspi-data23-state { 5980 pins = "gpio16", "gpio17"; 5981 function = "qspi_data"; 5982 }; 5983 5984 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 5985 pins = "gpio0", "gpio1"; 5986 function = "qup00"; 5987 }; 5988 5989 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 5990 pins = "gpio4", "gpio5"; 5991 function = "qup01"; 5992 }; 5993 5994 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 5995 pins = "gpio8", "gpio9"; 5996 function = "qup02"; 5997 }; 5998 5999 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 6000 pins = "gpio12", "gpio13"; 6001 function = "qup03"; 6002 }; 6003 6004 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 6005 pins = "gpio16", "gpio17"; 6006 function = "qup04"; 6007 }; 6008 6009 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 6010 pins = "gpio20", "gpio21"; 6011 function = "qup05"; 6012 }; 6013 6014 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 6015 pins = "gpio24", "gpio25"; 6016 function = "qup06"; 6017 }; 6018 6019 qup_i2c7_data_clk: qup-i2c7-data-clk-state { 6020 pins = "gpio28", "gpio29"; 6021 function = "qup07"; 6022 }; 6023 6024 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 6025 pins = "gpio32", "gpio33"; 6026 function = "qup10"; 6027 }; 6028 6029 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 6030 pins = "gpio36", "gpio37"; 6031 function = "qup11"; 6032 }; 6033 6034 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 6035 pins = "gpio40", "gpio41"; 6036 function = "qup12"; 6037 }; 6038 6039 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 6040 pins = "gpio44", "gpio45"; 6041 function = "qup13"; 6042 }; 6043 6044 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 6045 pins = "gpio48", "gpio49"; 6046 function = "qup14"; 6047 }; 6048 6049 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 6050 pins = "gpio52", "gpio53"; 6051 function = "qup15"; 6052 }; 6053 6054 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 6055 pins = "gpio56", "gpio57"; 6056 function = "qup16"; 6057 }; 6058 6059 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 6060 pins = "gpio60", "gpio61"; 6061 function = "qup17"; 6062 }; 6063 6064 qup_spi0_data_clk: qup-spi0-data-clk-state { 6065 pins = "gpio0", "gpio1", "gpio2"; 6066 function = "qup00"; 6067 }; 6068 6069 qup_spi0_cs: qup-spi0-cs-state { 6070 pins = "gpio3"; 6071 function = "qup00"; 6072 }; 6073 6074 qup_spi0_cs_gpio: qup-spi0-cs-gpio-state { 6075 pins = "gpio3"; 6076 function = "gpio"; 6077 }; 6078 6079 qup_spi1_data_clk: qup-spi1-data-clk-state { 6080 pins = "gpio4", "gpio5", "gpio6"; 6081 function = "qup01"; 6082 }; 6083 6084 qup_spi1_cs: qup-spi1-cs-state { 6085 pins = "gpio7"; 6086 function = "qup01"; 6087 }; 6088 6089 qup_spi1_cs_gpio: qup-spi1-cs-gpio-state { 6090 pins = "gpio7"; 6091 function = "gpio"; 6092 }; 6093 6094 qup_spi2_data_clk: qup-spi2-data-clk-state { 6095 pins = "gpio8", "gpio9", "gpio10"; 6096 function = "qup02"; 6097 }; 6098 6099 qup_spi2_cs: qup-spi2-cs-state { 6100 pins = "gpio11"; 6101 function = "qup02"; 6102 }; 6103 6104 qup_spi2_cs_gpio: qup-spi2-cs-gpio-state { 6105 pins = "gpio11"; 6106 function = "gpio"; 6107 }; 6108 6109 qup_spi3_data_clk: qup-spi3-data-clk-state { 6110 pins = "gpio12", "gpio13", "gpio14"; 6111 function = "qup03"; 6112 }; 6113 6114 qup_spi3_cs: qup-spi3-cs-state { 6115 pins = "gpio15"; 6116 function = "qup03"; 6117 }; 6118 6119 qup_spi3_cs_gpio: qup-spi3-cs-gpio-state { 6120 pins = "gpio15"; 6121 function = "gpio"; 6122 }; 6123 6124 qup_spi4_data_clk: qup-spi4-data-clk-state { 6125 pins = "gpio16", "gpio17", "gpio18"; 6126 function = "qup04"; 6127 }; 6128 6129 qup_spi4_cs: qup-spi4-cs-state { 6130 pins = "gpio19"; 6131 function = "qup04"; 6132 }; 6133 6134 qup_spi4_cs_gpio: qup-spi4-cs-gpio-state { 6135 pins = "gpio19"; 6136 function = "gpio"; 6137 }; 6138 6139 qup_spi5_data_clk: qup-spi5-data-clk-state { 6140 pins = "gpio20", "gpio21", "gpio22"; 6141 function = "qup05"; 6142 }; 6143 6144 qup_spi5_cs: qup-spi5-cs-state { 6145 pins = "gpio23"; 6146 function = "qup05"; 6147 }; 6148 6149 qup_spi5_cs_gpio: qup-spi5-cs-gpio-state { 6150 pins = "gpio23"; 6151 function = "gpio"; 6152 }; 6153 6154 qup_spi6_data_clk: qup-spi6-data-clk-state { 6155 pins = "gpio24", "gpio25", "gpio26"; 6156 function = "qup06"; 6157 }; 6158 6159 qup_spi6_cs: qup-spi6-cs-state { 6160 pins = "gpio27"; 6161 function = "qup06"; 6162 }; 6163 6164 qup_spi6_cs_gpio: qup-spi6-cs-gpio-state { 6165 pins = "gpio27"; 6166 function = "gpio"; 6167 }; 6168 6169 qup_spi7_data_clk: qup-spi7-data-clk-state { 6170 pins = "gpio28", "gpio29", "gpio30"; 6171 function = "qup07"; 6172 }; 6173 6174 qup_spi7_cs: qup-spi7-cs-state { 6175 pins = "gpio31"; 6176 function = "qup07"; 6177 }; 6178 6179 qup_spi7_cs_gpio: qup-spi7-cs-gpio-state { 6180 pins = "gpio31"; 6181 function = "gpio"; 6182 }; 6183 6184 qup_spi8_data_clk: qup-spi8-data-clk-state { 6185 pins = "gpio32", "gpio33", "gpio34"; 6186 function = "qup10"; 6187 }; 6188 6189 qup_spi8_cs: qup-spi8-cs-state { 6190 pins = "gpio35"; 6191 function = "qup10"; 6192 }; 6193 6194 qup_spi8_cs_gpio: qup-spi8-cs-gpio-state { 6195 pins = "gpio35"; 6196 function = "gpio"; 6197 }; 6198 6199 qup_spi9_data_clk: qup-spi9-data-clk-state { 6200 pins = "gpio36", "gpio37", "gpio38"; 6201 function = "qup11"; 6202 }; 6203 6204 qup_spi9_cs: qup-spi9-cs-state { 6205 pins = "gpio39"; 6206 function = "qup11"; 6207 }; 6208 6209 qup_spi9_cs_gpio: qup-spi9-cs-gpio-state { 6210 pins = "gpio39"; 6211 function = "gpio"; 6212 }; 6213 6214 qup_spi10_data_clk: qup-spi10-data-clk-state { 6215 pins = "gpio40", "gpio41", "gpio42"; 6216 function = "qup12"; 6217 }; 6218 6219 qup_spi10_cs: qup-spi10-cs-state { 6220 pins = "gpio43"; 6221 function = "qup12"; 6222 }; 6223 6224 qup_spi10_cs_gpio: qup-spi10-cs-gpio-state { 6225 pins = "gpio43"; 6226 function = "gpio"; 6227 }; 6228 6229 qup_spi11_data_clk: qup-spi11-data-clk-state { 6230 pins = "gpio44", "gpio45", "gpio46"; 6231 function = "qup13"; 6232 }; 6233 6234 qup_spi11_cs: qup-spi11-cs-state { 6235 pins = "gpio47"; 6236 function = "qup13"; 6237 }; 6238 6239 qup_spi11_cs_gpio: qup-spi11-cs-gpio-state { 6240 pins = "gpio47"; 6241 function = "gpio"; 6242 }; 6243 6244 qup_spi12_data_clk: qup-spi12-data-clk-state { 6245 pins = "gpio48", "gpio49", "gpio50"; 6246 function = "qup14"; 6247 }; 6248 6249 qup_spi12_cs: qup-spi12-cs-state { 6250 pins = "gpio51"; 6251 function = "qup14"; 6252 }; 6253 6254 qup_spi12_cs_gpio: qup-spi12-cs-gpio-state { 6255 pins = "gpio51"; 6256 function = "gpio"; 6257 }; 6258 6259 qup_spi13_data_clk: qup-spi13-data-clk-state { 6260 pins = "gpio52", "gpio53", "gpio54"; 6261 function = "qup15"; 6262 }; 6263 6264 qup_spi13_cs: qup-spi13-cs-state { 6265 pins = "gpio55"; 6266 function = "qup15"; 6267 }; 6268 6269 qup_spi13_cs_gpio: qup-spi13-cs-gpio-state { 6270 pins = "gpio55"; 6271 function = "gpio"; 6272 }; 6273 6274 qup_spi14_data_clk: qup-spi14-data-clk-state { 6275 pins = "gpio56", "gpio57", "gpio58"; 6276 function = "qup16"; 6277 }; 6278 6279 qup_spi14_cs: qup-spi14-cs-state { 6280 pins = "gpio59"; 6281 function = "qup16"; 6282 }; 6283 6284 qup_spi14_cs_gpio: qup-spi14-cs-gpio-state { 6285 pins = "gpio59"; 6286 function = "gpio"; 6287 }; 6288 6289 qup_spi15_data_clk: qup-spi15-data-clk-state { 6290 pins = "gpio60", "gpio61", "gpio62"; 6291 function = "qup17"; 6292 }; 6293 6294 qup_spi15_cs: qup-spi15-cs-state { 6295 pins = "gpio63"; 6296 function = "qup17"; 6297 }; 6298 6299 qup_spi15_cs_gpio: qup-spi15-cs-gpio-state { 6300 pins = "gpio63"; 6301 function = "gpio"; 6302 }; 6303 6304 qup_uart0_cts: qup-uart0-cts-state { 6305 pins = "gpio0"; 6306 function = "qup00"; 6307 }; 6308 6309 qup_uart0_rts: qup-uart0-rts-state { 6310 pins = "gpio1"; 6311 function = "qup00"; 6312 }; 6313 6314 qup_uart0_tx: qup-uart0-tx-state { 6315 pins = "gpio2"; 6316 function = "qup00"; 6317 }; 6318 6319 qup_uart0_rx: qup-uart0-rx-state { 6320 pins = "gpio3"; 6321 function = "qup00"; 6322 }; 6323 6324 qup_uart1_cts: qup-uart1-cts-state { 6325 pins = "gpio4"; 6326 function = "qup01"; 6327 }; 6328 6329 qup_uart1_rts: qup-uart1-rts-state { 6330 pins = "gpio5"; 6331 function = "qup01"; 6332 }; 6333 6334 qup_uart1_tx: qup-uart1-tx-state { 6335 pins = "gpio6"; 6336 function = "qup01"; 6337 }; 6338 6339 qup_uart1_rx: qup-uart1-rx-state { 6340 pins = "gpio7"; 6341 function = "qup01"; 6342 }; 6343 6344 qup_uart2_cts: qup-uart2-cts-state { 6345 pins = "gpio8"; 6346 function = "qup02"; 6347 }; 6348 6349 qup_uart2_rts: qup-uart2-rts-state { 6350 pins = "gpio9"; 6351 function = "qup02"; 6352 }; 6353 6354 qup_uart2_tx: qup-uart2-tx-state { 6355 pins = "gpio10"; 6356 function = "qup02"; 6357 }; 6358 6359 qup_uart2_rx: qup-uart2-rx-state { 6360 pins = "gpio11"; 6361 function = "qup02"; 6362 }; 6363 6364 qup_uart3_cts: qup-uart3-cts-state { 6365 pins = "gpio12"; 6366 function = "qup03"; 6367 }; 6368 6369 qup_uart3_rts: qup-uart3-rts-state { 6370 pins = "gpio13"; 6371 function = "qup03"; 6372 }; 6373 6374 qup_uart3_tx: qup-uart3-tx-state { 6375 pins = "gpio14"; 6376 function = "qup03"; 6377 }; 6378 6379 qup_uart3_rx: qup-uart3-rx-state { 6380 pins = "gpio15"; 6381 function = "qup03"; 6382 }; 6383 6384 qup_uart4_cts: qup-uart4-cts-state { 6385 pins = "gpio16"; 6386 function = "qup04"; 6387 }; 6388 6389 qup_uart4_rts: qup-uart4-rts-state { 6390 pins = "gpio17"; 6391 function = "qup04"; 6392 }; 6393 6394 qup_uart4_tx: qup-uart4-tx-state { 6395 pins = "gpio18"; 6396 function = "qup04"; 6397 }; 6398 6399 qup_uart4_rx: qup-uart4-rx-state { 6400 pins = "gpio19"; 6401 function = "qup04"; 6402 }; 6403 6404 qup_uart5_tx: qup-uart5-tx-state { 6405 pins = "gpio22"; 6406 function = "qup05"; 6407 }; 6408 6409 qup_uart5_rx: qup-uart5-rx-state { 6410 pins = "gpio23"; 6411 function = "qup05"; 6412 }; 6413 6414 qup_uart6_cts: qup-uart6-cts-state { 6415 pins = "gpio24"; 6416 function = "qup06"; 6417 }; 6418 6419 qup_uart6_rts: qup-uart6-rts-state { 6420 pins = "gpio25"; 6421 function = "qup06"; 6422 }; 6423 6424 qup_uart6_tx: qup-uart6-tx-state { 6425 pins = "gpio26"; 6426 function = "qup06"; 6427 }; 6428 6429 qup_uart6_rx: qup-uart6-rx-state { 6430 pins = "gpio27"; 6431 function = "qup06"; 6432 }; 6433 6434 qup_uart7_cts: qup-uart7-cts-state { 6435 pins = "gpio28"; 6436 function = "qup07"; 6437 }; 6438 6439 qup_uart7_rts: qup-uart7-rts-state { 6440 pins = "gpio29"; 6441 function = "qup07"; 6442 }; 6443 6444 qup_uart7_tx: qup-uart7-tx-state { 6445 pins = "gpio30"; 6446 function = "qup07"; 6447 }; 6448 6449 qup_uart7_rx: qup-uart7-rx-state { 6450 pins = "gpio31"; 6451 function = "qup07"; 6452 }; 6453 6454 qup_uart8_cts: qup-uart8-cts-state { 6455 pins = "gpio32"; 6456 function = "qup10"; 6457 }; 6458 6459 qup_uart8_rts: qup-uart8-rts-state { 6460 pins = "gpio33"; 6461 function = "qup10"; 6462 }; 6463 6464 qup_uart8_tx: qup-uart8-tx-state { 6465 pins = "gpio34"; 6466 function = "qup10"; 6467 }; 6468 6469 qup_uart8_rx: qup-uart8-rx-state { 6470 pins = "gpio35"; 6471 function = "qup10"; 6472 }; 6473 6474 qup_uart9_cts: qup-uart9-cts-state { 6475 pins = "gpio36"; 6476 function = "qup11"; 6477 }; 6478 6479 qup_uart9_rts: qup-uart9-rts-state { 6480 pins = "gpio37"; 6481 function = "qup11"; 6482 }; 6483 6484 qup_uart9_tx: qup-uart9-tx-state { 6485 pins = "gpio38"; 6486 function = "qup11"; 6487 }; 6488 6489 qup_uart9_rx: qup-uart9-rx-state { 6490 pins = "gpio39"; 6491 function = "qup11"; 6492 }; 6493 6494 qup_uart10_cts: qup-uart10-cts-state { 6495 pins = "gpio40"; 6496 function = "qup12"; 6497 }; 6498 6499 qup_uart10_rts: qup-uart10-rts-state { 6500 pins = "gpio41"; 6501 function = "qup12"; 6502 }; 6503 6504 qup_uart10_tx: qup-uart10-tx-state { 6505 pins = "gpio42"; 6506 function = "qup12"; 6507 }; 6508 6509 qup_uart10_rx: qup-uart10-rx-state { 6510 pins = "gpio43"; 6511 function = "qup12"; 6512 }; 6513 6514 qup_uart11_cts: qup-uart11-cts-state { 6515 pins = "gpio44"; 6516 function = "qup13"; 6517 }; 6518 6519 qup_uart11_rts: qup-uart11-rts-state { 6520 pins = "gpio45"; 6521 function = "qup13"; 6522 }; 6523 6524 qup_uart11_tx: qup-uart11-tx-state { 6525 pins = "gpio46"; 6526 function = "qup13"; 6527 }; 6528 6529 qup_uart11_rx: qup-uart11-rx-state { 6530 pins = "gpio47"; 6531 function = "qup13"; 6532 }; 6533 6534 qup_uart12_cts: qup-uart12-cts-state { 6535 pins = "gpio48"; 6536 function = "qup14"; 6537 }; 6538 6539 qup_uart12_rts: qup-uart12-rts-state { 6540 pins = "gpio49"; 6541 function = "qup14"; 6542 }; 6543 6544 qup_uart12_tx: qup-uart12-tx-state { 6545 pins = "gpio50"; 6546 function = "qup14"; 6547 }; 6548 6549 qup_uart12_rx: qup-uart12-rx-state { 6550 pins = "gpio51"; 6551 function = "qup14"; 6552 }; 6553 6554 qup_uart13_cts: qup-uart13-cts-state { 6555 pins = "gpio52"; 6556 function = "qup15"; 6557 }; 6558 6559 qup_uart13_rts: qup-uart13-rts-state { 6560 pins = "gpio53"; 6561 function = "qup15"; 6562 }; 6563 6564 qup_uart13_tx: qup-uart13-tx-state { 6565 pins = "gpio54"; 6566 function = "qup15"; 6567 }; 6568 6569 qup_uart13_rx: qup-uart13-rx-state { 6570 pins = "gpio55"; 6571 function = "qup15"; 6572 }; 6573 6574 qup_uart14_cts: qup-uart14-cts-state { 6575 pins = "gpio56"; 6576 function = "qup16"; 6577 }; 6578 6579 qup_uart14_rts: qup-uart14-rts-state { 6580 pins = "gpio57"; 6581 function = "qup16"; 6582 }; 6583 6584 qup_uart14_tx: qup-uart14-tx-state { 6585 pins = "gpio58"; 6586 function = "qup16"; 6587 }; 6588 6589 qup_uart14_rx: qup-uart14-rx-state { 6590 pins = "gpio59"; 6591 function = "qup16"; 6592 }; 6593 6594 qup_uart15_cts: qup-uart15-cts-state { 6595 pins = "gpio60"; 6596 function = "qup17"; 6597 }; 6598 6599 qup_uart15_rts: qup-uart15-rts-state { 6600 pins = "gpio61"; 6601 function = "qup17"; 6602 }; 6603 6604 qup_uart15_tx: qup-uart15-tx-state { 6605 pins = "gpio62"; 6606 function = "qup17"; 6607 }; 6608 6609 qup_uart15_rx: qup-uart15-rx-state { 6610 pins = "gpio63"; 6611 function = "qup17"; 6612 }; 6613 6614 sdc1_clk: sdc1-clk-state { 6615 pins = "sdc1_clk"; 6616 }; 6617 6618 sdc1_cmd: sdc1-cmd-state { 6619 pins = "sdc1_cmd"; 6620 }; 6621 6622 sdc1_data: sdc1-data-state { 6623 pins = "sdc1_data"; 6624 }; 6625 6626 sdc1_rclk: sdc1-rclk-state { 6627 pins = "sdc1_rclk"; 6628 }; 6629 6630 sdc1_clk_sleep: sdc1-clk-sleep-state { 6631 pins = "sdc1_clk"; 6632 drive-strength = <2>; 6633 bias-bus-hold; 6634 }; 6635 6636 sdc1_cmd_sleep: sdc1-cmd-sleep-state { 6637 pins = "sdc1_cmd"; 6638 drive-strength = <2>; 6639 bias-bus-hold; 6640 }; 6641 6642 sdc1_data_sleep: sdc1-data-sleep-state { 6643 pins = "sdc1_data"; 6644 drive-strength = <2>; 6645 bias-bus-hold; 6646 }; 6647 6648 sdc1_rclk_sleep: sdc1-rclk-sleep-state { 6649 pins = "sdc1_rclk"; 6650 drive-strength = <2>; 6651 bias-bus-hold; 6652 }; 6653 6654 sdc2_clk: sdc2-clk-state { 6655 pins = "sdc2_clk"; 6656 }; 6657 6658 sdc2_cmd: sdc2-cmd-state { 6659 pins = "sdc2_cmd"; 6660 }; 6661 6662 sdc2_data: sdc2-data-state { 6663 pins = "sdc2_data"; 6664 }; 6665 6666 sdc2_clk_sleep: sdc2-clk-sleep-state { 6667 pins = "sdc2_clk"; 6668 drive-strength = <2>; 6669 bias-bus-hold; 6670 }; 6671 6672 sdc2_cmd_sleep: sdc2-cmd-sleep-state { 6673 pins = "sdc2_cmd"; 6674 drive-strength = <2>; 6675 bias-bus-hold; 6676 }; 6677 6678 sdc2_data_sleep: sdc2-data-sleep-state { 6679 pins = "sdc2_data"; 6680 drive-strength = <2>; 6681 bias-bus-hold; 6682 }; 6683 }; 6684 6685 sram@146a5000 { 6686 compatible = "qcom,sc7280-imem", "syscon", "simple-mfd"; 6687 reg = <0 0x146a5000 0 0x6000>; 6688 6689 #address-cells = <1>; 6690 #size-cells = <1>; 6691 6692 ranges = <0 0 0x146a5000 0x6000>; 6693 6694 ipa_modem_tables: modem-tables@3000 { 6695 reg = <0x3000 0x2000>; 6696 }; 6697 6698 pil-reloc@594c { 6699 compatible = "qcom,pil-reloc-info"; 6700 reg = <0x594c 0xc8>; 6701 }; 6702 }; 6703 6704 apps_smmu: iommu@15000000 { 6705 compatible = "qcom,sc7280-smmu-500", "arm,mmu-500"; 6706 reg = <0 0x15000000 0 0x100000>; 6707 #iommu-cells = <2>; 6708 #global-interrupts = <1>; 6709 dma-coherent; 6710 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 6711 <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 6712 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 6713 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 6714 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 6715 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 6716 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 6717 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 6718 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 6719 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 6720 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 6721 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 6722 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 6723 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 6724 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 6725 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 6726 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 6727 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 6728 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 6729 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 6730 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 6731 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 6732 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 6733 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 6734 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 6735 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 6736 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 6737 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 6738 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 6739 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 6740 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 6741 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 6742 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 6743 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 6744 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 6745 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 6746 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 6747 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 6748 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 6749 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 6750 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 6751 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 6752 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 6753 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 6754 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 6755 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 6756 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 6757 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 6758 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 6759 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 6760 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 6761 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 6762 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 6763 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 6764 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 6765 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 6766 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 6767 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 6768 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 6769 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 6770 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 6771 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 6772 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 6773 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 6774 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 6775 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 6776 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 6777 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 6778 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 6779 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 6780 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 6781 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 6782 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 6783 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 6784 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 6785 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 6786 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 6787 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 6788 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 6789 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 6790 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>; 6791 }; 6792 6793 anoc_1_tbu: tbu@151dd000 { 6794 compatible = "qcom,sc7280-tbu"; 6795 reg = <0x0 0x151dd000 0x0 0x1000>; 6796 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6797 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6798 qcom,stream-id-range = <&apps_smmu 0x0 0x400>; 6799 }; 6800 6801 anoc_2_tbu: tbu@151e1000 { 6802 compatible = "qcom,sc7280-tbu"; 6803 reg = <0x0 0x151e1000 0x0 0x1000>; 6804 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6805 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6806 qcom,stream-id-range = <&apps_smmu 0x400 0x400>; 6807 }; 6808 6809 mnoc_hf_0_tbu: tbu@151e5000 { 6810 compatible = "qcom,sc7280-tbu"; 6811 reg = <0x0 0x151e5000 0x0 0x1000>; 6812 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 6813 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6814 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC>; 6815 qcom,stream-id-range = <&apps_smmu 0x800 0x400>; 6816 }; 6817 6818 mnoc_hf_1_tbu: tbu@151e9000 { 6819 compatible = "qcom,sc7280-tbu"; 6820 reg = <0x0 0x151e9000 0x0 0x1000>; 6821 interconnects = <&mmss_noc MASTER_MDP0 QCOM_ICC_TAG_ACTIVE_ONLY 6822 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6823 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_HF1_GDSC>; 6824 qcom,stream-id-range = <&apps_smmu 0xc00 0x400>; 6825 }; 6826 6827 compute_dsp_1_tbu: tbu@151ed000 { 6828 compatible = "qcom,sc7280-tbu"; 6829 reg = <0x0 0x151ed000 0x0 0x1000>; 6830 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6831 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6832 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU1_GDSC>; 6833 qcom,stream-id-range = <&apps_smmu 0x1000 0x400>; 6834 }; 6835 6836 compute_dsp_0_tbu: tbu@151f1000 { 6837 compatible = "qcom,sc7280-tbu"; 6838 reg = <0x0 0x151f1000 0x0 0x1000>; 6839 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6840 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6841 power-domains = <&gcc HLOS1_VOTE_TURING_MMU_TBU0_GDSC>; 6842 qcom,stream-id-range = <&apps_smmu 0x1400 0x400>; 6843 }; 6844 6845 adsp_tbu: tbu@151f5000 { 6846 compatible = "qcom,sc7280-tbu"; 6847 reg = <0x0 0x151f5000 0x0 0x1000>; 6848 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6849 &lpass_ag_noc SLAVE_LPASS_CORE_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 6850 qcom,stream-id-range = <&apps_smmu 0x1800 0x400>; 6851 }; 6852 6853 anoc_1_pcie_tbu: tbu@151f9000 { 6854 compatible = "qcom,sc7280-tbu"; 6855 reg = <0x0 0x151f9000 0x0 0x1000>; 6856 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 6857 &cnoc3 SLAVE_TCU QCOM_ICC_TAG_ACTIVE_ONLY>; 6858 qcom,stream-id-range = <&apps_smmu 0x1c00 0x400>; 6859 }; 6860 6861 mnoc_sf_0_tbu: tbu@151fd000 { 6862 compatible = "qcom,sc7280-tbu"; 6863 reg = <0x0 0x151fd000 0x0 0x1000>; 6864 interconnects = <&mmss_noc MASTER_CAMNOC_SF QCOM_ICC_TAG_ACTIVE_ONLY 6865 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 6866 power-domains = <&gcc HLOS1_VOTE_MMNOC_MMU_TBU_SF0_GDSC>; 6867 qcom,stream-id-range = <&apps_smmu 0x2000 0x400>; 6868 }; 6869 6870 intc: interrupt-controller@17a00000 { 6871 compatible = "arm,gic-v3"; 6872 reg = <0 0x17a00000 0 0x10000>, /* GICD */ 6873 <0 0x17a60000 0 0x100000>; /* GICR * 8 */ 6874 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_LOW>; 6875 #interrupt-cells = <3>; 6876 interrupt-controller; 6877 #address-cells = <2>; 6878 #size-cells = <2>; 6879 ranges; 6880 6881 msi-controller@17a40000 { 6882 compatible = "arm,gic-v3-its"; 6883 reg = <0 0x17a40000 0 0x20000>; 6884 msi-controller; 6885 #msi-cells = <1>; 6886 status = "disabled"; 6887 }; 6888 }; 6889 6890 watchdog: watchdog@17c10000 { 6891 compatible = "qcom,apss-wdt-sc7280", "qcom,kpss-wdt"; 6892 reg = <0 0x17c10000 0 0x1000>; 6893 clocks = <&sleep_clk>; 6894 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 6895 status = "reserved"; /* Owned by Gunyah hyp */ 6896 }; 6897 6898 timer@17c20000 { 6899 #address-cells = <1>; 6900 #size-cells = <1>; 6901 ranges = <0 0 0 0x20000000>; 6902 compatible = "arm,armv7-timer-mem"; 6903 reg = <0 0x17c20000 0 0x1000>; 6904 6905 frame@17c21000 { 6906 frame-number = <0>; 6907 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 6908 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 6909 reg = <0x17c21000 0x1000>, 6910 <0x17c22000 0x1000>; 6911 }; 6912 6913 frame@17c23000 { 6914 frame-number = <1>; 6915 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 6916 reg = <0x17c23000 0x1000>; 6917 status = "disabled"; 6918 }; 6919 6920 frame@17c25000 { 6921 frame-number = <2>; 6922 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 6923 reg = <0x17c25000 0x1000>; 6924 status = "disabled"; 6925 }; 6926 6927 frame@17c27000 { 6928 frame-number = <3>; 6929 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 6930 reg = <0x17c27000 0x1000>; 6931 status = "disabled"; 6932 }; 6933 6934 frame@17c29000 { 6935 frame-number = <4>; 6936 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 6937 reg = <0x17c29000 0x1000>; 6938 status = "disabled"; 6939 }; 6940 6941 frame@17c2b000 { 6942 frame-number = <5>; 6943 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 6944 reg = <0x17c2b000 0x1000>; 6945 status = "disabled"; 6946 }; 6947 6948 frame@17c2d000 { 6949 frame-number = <6>; 6950 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 6951 reg = <0x17c2d000 0x1000>; 6952 status = "disabled"; 6953 }; 6954 }; 6955 6956 apps_rsc: rsc@18200000 { 6957 compatible = "qcom,rpmh-rsc"; 6958 reg = <0 0x18200000 0 0x10000>, 6959 <0 0x18210000 0 0x10000>, 6960 <0 0x18220000 0 0x10000>; 6961 reg-names = "drv-0", "drv-1", "drv-2"; 6962 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 6963 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 6964 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 6965 qcom,tcs-offset = <0xd00>; 6966 qcom,drv-id = <2>; 6967 qcom,tcs-config = <ACTIVE_TCS 2>, 6968 <SLEEP_TCS 3>, 6969 <WAKE_TCS 3>, 6970 <CONTROL_TCS 1>; 6971 power-domains = <&cluster_pd>; 6972 6973 apps_bcm_voter: bcm-voter { 6974 compatible = "qcom,bcm-voter"; 6975 }; 6976 6977 rpmhpd: power-controller { 6978 compatible = "qcom,sc7280-rpmhpd"; 6979 #power-domain-cells = <1>; 6980 operating-points-v2 = <&rpmhpd_opp_table>; 6981 6982 rpmhpd_opp_table: opp-table { 6983 compatible = "operating-points-v2"; 6984 6985 rpmhpd_opp_ret: opp1 { 6986 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 6987 }; 6988 6989 rpmhpd_opp_low_svs: opp2 { 6990 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 6991 }; 6992 6993 rpmhpd_opp_svs: opp3 { 6994 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 6995 }; 6996 6997 rpmhpd_opp_svs_l1: opp4 { 6998 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 6999 }; 7000 7001 rpmhpd_opp_svs_l2: opp5 { 7002 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 7003 }; 7004 7005 rpmhpd_opp_nom: opp6 { 7006 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 7007 }; 7008 7009 rpmhpd_opp_nom_l1: opp7 { 7010 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 7011 }; 7012 7013 rpmhpd_opp_turbo: opp8 { 7014 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 7015 }; 7016 7017 rpmhpd_opp_turbo_l1: opp9 { 7018 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 7019 }; 7020 }; 7021 }; 7022 7023 rpmhcc: clock-controller { 7024 compatible = "qcom,sc7280-rpmh-clk"; 7025 clocks = <&xo_board>; 7026 clock-names = "xo"; 7027 #clock-cells = <1>; 7028 }; 7029 }; 7030 7031 epss_l3: interconnect@18590000 { 7032 compatible = "qcom,sc7280-epss-l3", "qcom,epss-l3"; 7033 reg = <0 0x18590000 0 0x1000>; 7034 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7035 clock-names = "xo", "alternate"; 7036 #interconnect-cells = <1>; 7037 }; 7038 7039 cpufreq_hw: cpufreq@18591000 { 7040 compatible = "qcom,sc7280-cpufreq-epss", "qcom,cpufreq-epss"; 7041 reg = <0 0x18591000 0 0x1000>, 7042 <0 0x18592000 0 0x1000>, 7043 <0 0x18593000 0 0x1000>; 7044 7045 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 7046 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 7047 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 7048 interrupt-names = "dcvsh-irq-0", 7049 "dcvsh-irq-1", 7050 "dcvsh-irq-2"; 7051 7052 clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GCC_GPLL0>; 7053 clock-names = "xo", "alternate"; 7054 #freq-domain-cells = <1>; 7055 #clock-cells = <1>; 7056 }; 7057 }; 7058 7059 sound: sound { 7060 }; 7061 7062 thermal_zones: thermal-zones { 7063 cpu0-thermal { 7064 polling-delay-passive = <250>; 7065 7066 thermal-sensors = <&tsens0 1>; 7067 7068 trips { 7069 cpu0_alert0: trip-point0 { 7070 temperature = <90000>; 7071 hysteresis = <2000>; 7072 type = "passive"; 7073 }; 7074 7075 cpu0_alert1: trip-point1 { 7076 temperature = <95000>; 7077 hysteresis = <2000>; 7078 type = "passive"; 7079 }; 7080 7081 cpu0_crit: cpu-crit { 7082 temperature = <110000>; 7083 hysteresis = <0>; 7084 type = "critical"; 7085 }; 7086 }; 7087 7088 cooling-maps { 7089 map0 { 7090 trip = <&cpu0_alert0>; 7091 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7092 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7093 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7094 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7095 }; 7096 map1 { 7097 trip = <&cpu0_alert1>; 7098 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7099 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7100 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7101 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7102 }; 7103 }; 7104 }; 7105 7106 cpu1-thermal { 7107 polling-delay-passive = <250>; 7108 7109 thermal-sensors = <&tsens0 2>; 7110 7111 trips { 7112 cpu1_alert0: trip-point0 { 7113 temperature = <90000>; 7114 hysteresis = <2000>; 7115 type = "passive"; 7116 }; 7117 7118 cpu1_alert1: trip-point1 { 7119 temperature = <95000>; 7120 hysteresis = <2000>; 7121 type = "passive"; 7122 }; 7123 7124 cpu1_crit: cpu-crit { 7125 temperature = <110000>; 7126 hysteresis = <0>; 7127 type = "critical"; 7128 }; 7129 }; 7130 7131 cooling-maps { 7132 map0 { 7133 trip = <&cpu1_alert0>; 7134 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7135 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7136 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7137 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7138 }; 7139 map1 { 7140 trip = <&cpu1_alert1>; 7141 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7142 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7143 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7144 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7145 }; 7146 }; 7147 }; 7148 7149 cpu2-thermal { 7150 polling-delay-passive = <250>; 7151 7152 thermal-sensors = <&tsens0 3>; 7153 7154 trips { 7155 cpu2_alert0: trip-point0 { 7156 temperature = <90000>; 7157 hysteresis = <2000>; 7158 type = "passive"; 7159 }; 7160 7161 cpu2_alert1: trip-point1 { 7162 temperature = <95000>; 7163 hysteresis = <2000>; 7164 type = "passive"; 7165 }; 7166 7167 cpu2_crit: cpu-crit { 7168 temperature = <110000>; 7169 hysteresis = <0>; 7170 type = "critical"; 7171 }; 7172 }; 7173 7174 cooling-maps { 7175 map0 { 7176 trip = <&cpu2_alert0>; 7177 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7178 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7179 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7180 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7181 }; 7182 map1 { 7183 trip = <&cpu2_alert1>; 7184 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7185 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7186 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7187 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7188 }; 7189 }; 7190 }; 7191 7192 cpu3-thermal { 7193 polling-delay-passive = <250>; 7194 7195 thermal-sensors = <&tsens0 4>; 7196 7197 trips { 7198 cpu3_alert0: trip-point0 { 7199 temperature = <90000>; 7200 hysteresis = <2000>; 7201 type = "passive"; 7202 }; 7203 7204 cpu3_alert1: trip-point1 { 7205 temperature = <95000>; 7206 hysteresis = <2000>; 7207 type = "passive"; 7208 }; 7209 7210 cpu3_crit: cpu-crit { 7211 temperature = <110000>; 7212 hysteresis = <0>; 7213 type = "critical"; 7214 }; 7215 }; 7216 7217 cooling-maps { 7218 map0 { 7219 trip = <&cpu3_alert0>; 7220 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7221 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7222 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7223 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7224 }; 7225 map1 { 7226 trip = <&cpu3_alert1>; 7227 cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7228 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7229 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7230 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7231 }; 7232 }; 7233 }; 7234 7235 cpu4-thermal { 7236 polling-delay-passive = <250>; 7237 7238 thermal-sensors = <&tsens0 7>; 7239 7240 trips { 7241 cpu4_alert0: trip-point0 { 7242 temperature = <90000>; 7243 hysteresis = <2000>; 7244 type = "passive"; 7245 }; 7246 7247 cpu4_alert1: trip-point1 { 7248 temperature = <95000>; 7249 hysteresis = <2000>; 7250 type = "passive"; 7251 }; 7252 7253 cpu4_crit: cpu-crit { 7254 temperature = <110000>; 7255 hysteresis = <0>; 7256 type = "critical"; 7257 }; 7258 }; 7259 7260 cooling-maps { 7261 map0 { 7262 trip = <&cpu4_alert0>; 7263 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7264 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7265 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7266 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7267 }; 7268 map1 { 7269 trip = <&cpu4_alert1>; 7270 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7271 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7272 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7273 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7274 }; 7275 }; 7276 }; 7277 7278 cpu5-thermal { 7279 polling-delay-passive = <250>; 7280 7281 thermal-sensors = <&tsens0 8>; 7282 7283 trips { 7284 cpu5_alert0: trip-point0 { 7285 temperature = <90000>; 7286 hysteresis = <2000>; 7287 type = "passive"; 7288 }; 7289 7290 cpu5_alert1: trip-point1 { 7291 temperature = <95000>; 7292 hysteresis = <2000>; 7293 type = "passive"; 7294 }; 7295 7296 cpu5_crit: cpu-crit { 7297 temperature = <110000>; 7298 hysteresis = <0>; 7299 type = "critical"; 7300 }; 7301 }; 7302 7303 cooling-maps { 7304 map0 { 7305 trip = <&cpu5_alert0>; 7306 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7307 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7308 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7309 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7310 }; 7311 map1 { 7312 trip = <&cpu5_alert1>; 7313 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7314 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7315 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7316 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7317 }; 7318 }; 7319 }; 7320 7321 cpu6-thermal { 7322 polling-delay-passive = <250>; 7323 7324 thermal-sensors = <&tsens0 9>; 7325 7326 trips { 7327 cpu6_alert0: trip-point0 { 7328 temperature = <90000>; 7329 hysteresis = <2000>; 7330 type = "passive"; 7331 }; 7332 7333 cpu6_alert1: trip-point1 { 7334 temperature = <95000>; 7335 hysteresis = <2000>; 7336 type = "passive"; 7337 }; 7338 7339 cpu6_crit: cpu-crit { 7340 temperature = <110000>; 7341 hysteresis = <0>; 7342 type = "critical"; 7343 }; 7344 }; 7345 7346 cooling-maps { 7347 map0 { 7348 trip = <&cpu6_alert0>; 7349 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7350 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7351 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7352 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7353 }; 7354 map1 { 7355 trip = <&cpu6_alert1>; 7356 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7357 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7358 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7359 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7360 }; 7361 }; 7362 }; 7363 7364 cpu7-thermal { 7365 polling-delay-passive = <250>; 7366 7367 thermal-sensors = <&tsens0 10>; 7368 7369 trips { 7370 cpu7_alert0: trip-point0 { 7371 temperature = <90000>; 7372 hysteresis = <2000>; 7373 type = "passive"; 7374 }; 7375 7376 cpu7_alert1: trip-point1 { 7377 temperature = <95000>; 7378 hysteresis = <2000>; 7379 type = "passive"; 7380 }; 7381 7382 cpu7_crit: cpu-crit { 7383 temperature = <110000>; 7384 hysteresis = <0>; 7385 type = "critical"; 7386 }; 7387 }; 7388 7389 cooling-maps { 7390 map0 { 7391 trip = <&cpu7_alert0>; 7392 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7393 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7394 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7395 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7396 }; 7397 map1 { 7398 trip = <&cpu7_alert1>; 7399 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7400 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7401 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7402 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7403 }; 7404 }; 7405 }; 7406 7407 cpu8-thermal { 7408 polling-delay-passive = <250>; 7409 7410 thermal-sensors = <&tsens0 11>; 7411 7412 trips { 7413 cpu8_alert0: trip-point0 { 7414 temperature = <90000>; 7415 hysteresis = <2000>; 7416 type = "passive"; 7417 }; 7418 7419 cpu8_alert1: trip-point1 { 7420 temperature = <95000>; 7421 hysteresis = <2000>; 7422 type = "passive"; 7423 }; 7424 7425 cpu8_crit: cpu-crit { 7426 temperature = <110000>; 7427 hysteresis = <0>; 7428 type = "critical"; 7429 }; 7430 }; 7431 7432 cooling-maps { 7433 map0 { 7434 trip = <&cpu8_alert0>; 7435 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7436 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7437 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7438 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7439 }; 7440 map1 { 7441 trip = <&cpu8_alert1>; 7442 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7443 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7444 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7445 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7446 }; 7447 }; 7448 }; 7449 7450 cpu9-thermal { 7451 polling-delay-passive = <250>; 7452 7453 thermal-sensors = <&tsens0 12>; 7454 7455 trips { 7456 cpu9_alert0: trip-point0 { 7457 temperature = <90000>; 7458 hysteresis = <2000>; 7459 type = "passive"; 7460 }; 7461 7462 cpu9_alert1: trip-point1 { 7463 temperature = <95000>; 7464 hysteresis = <2000>; 7465 type = "passive"; 7466 }; 7467 7468 cpu9_crit: cpu-crit { 7469 temperature = <110000>; 7470 hysteresis = <0>; 7471 type = "critical"; 7472 }; 7473 }; 7474 7475 cooling-maps { 7476 map0 { 7477 trip = <&cpu9_alert0>; 7478 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7479 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7480 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7481 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7482 }; 7483 map1 { 7484 trip = <&cpu9_alert1>; 7485 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7486 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7487 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7488 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7489 }; 7490 }; 7491 }; 7492 7493 cpu10-thermal { 7494 polling-delay-passive = <250>; 7495 7496 thermal-sensors = <&tsens0 13>; 7497 7498 trips { 7499 cpu10_alert0: trip-point0 { 7500 temperature = <90000>; 7501 hysteresis = <2000>; 7502 type = "passive"; 7503 }; 7504 7505 cpu10_alert1: trip-point1 { 7506 temperature = <95000>; 7507 hysteresis = <2000>; 7508 type = "passive"; 7509 }; 7510 7511 cpu10_crit: cpu-crit { 7512 temperature = <110000>; 7513 hysteresis = <0>; 7514 type = "critical"; 7515 }; 7516 }; 7517 7518 cooling-maps { 7519 map0 { 7520 trip = <&cpu10_alert0>; 7521 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7522 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7523 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7524 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7525 }; 7526 map1 { 7527 trip = <&cpu10_alert1>; 7528 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7529 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7530 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7531 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7532 }; 7533 }; 7534 }; 7535 7536 cpu11-thermal { 7537 polling-delay-passive = <250>; 7538 7539 thermal-sensors = <&tsens0 14>; 7540 7541 trips { 7542 cpu11_alert0: trip-point0 { 7543 temperature = <90000>; 7544 hysteresis = <2000>; 7545 type = "passive"; 7546 }; 7547 7548 cpu11_alert1: trip-point1 { 7549 temperature = <95000>; 7550 hysteresis = <2000>; 7551 type = "passive"; 7552 }; 7553 7554 cpu11_crit: cpu-crit { 7555 temperature = <110000>; 7556 hysteresis = <0>; 7557 type = "critical"; 7558 }; 7559 }; 7560 7561 cooling-maps { 7562 map0 { 7563 trip = <&cpu11_alert0>; 7564 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7565 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7566 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7567 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7568 }; 7569 map1 { 7570 trip = <&cpu11_alert1>; 7571 cooling-device = <&cpu4 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7572 <&cpu5 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7573 <&cpu6 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, 7574 <&cpu7 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7575 }; 7576 }; 7577 }; 7578 7579 aoss0-thermal { 7580 polling-delay-passive = <0>; 7581 7582 thermal-sensors = <&tsens0 0>; 7583 7584 trips { 7585 aoss0_alert0: trip-point0 { 7586 temperature = <90000>; 7587 hysteresis = <2000>; 7588 type = "hot"; 7589 }; 7590 7591 aoss0_crit: aoss0-crit { 7592 temperature = <110000>; 7593 hysteresis = <0>; 7594 type = "critical"; 7595 }; 7596 }; 7597 }; 7598 7599 aoss1-thermal { 7600 polling-delay-passive = <0>; 7601 7602 thermal-sensors = <&tsens1 0>; 7603 7604 trips { 7605 aoss1_alert0: trip-point0 { 7606 temperature = <90000>; 7607 hysteresis = <2000>; 7608 type = "hot"; 7609 }; 7610 7611 aoss1_crit: aoss1-crit { 7612 temperature = <110000>; 7613 hysteresis = <0>; 7614 type = "critical"; 7615 }; 7616 }; 7617 }; 7618 7619 cpuss0-thermal { 7620 polling-delay-passive = <0>; 7621 7622 thermal-sensors = <&tsens0 5>; 7623 7624 trips { 7625 cpuss0_alert0: trip-point0 { 7626 temperature = <90000>; 7627 hysteresis = <2000>; 7628 type = "hot"; 7629 }; 7630 cpuss0_crit: cluster0-crit { 7631 temperature = <110000>; 7632 hysteresis = <0>; 7633 type = "critical"; 7634 }; 7635 }; 7636 }; 7637 7638 cpuss1-thermal { 7639 polling-delay-passive = <0>; 7640 7641 thermal-sensors = <&tsens0 6>; 7642 7643 trips { 7644 cpuss1_alert0: trip-point0 { 7645 temperature = <90000>; 7646 hysteresis = <2000>; 7647 type = "hot"; 7648 }; 7649 cpuss1_crit: cluster0-crit { 7650 temperature = <110000>; 7651 hysteresis = <0>; 7652 type = "critical"; 7653 }; 7654 }; 7655 }; 7656 7657 gpuss0-thermal { 7658 polling-delay-passive = <100>; 7659 7660 thermal-sensors = <&tsens1 1>; 7661 7662 trips { 7663 gpuss0_alert0: trip-point0 { 7664 temperature = <95000>; 7665 hysteresis = <2000>; 7666 type = "passive"; 7667 }; 7668 7669 gpuss0_crit: gpuss0-crit { 7670 temperature = <110000>; 7671 hysteresis = <0>; 7672 type = "critical"; 7673 }; 7674 }; 7675 7676 cooling-maps { 7677 map0 { 7678 trip = <&gpuss0_alert0>; 7679 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7680 }; 7681 }; 7682 }; 7683 7684 gpuss1-thermal { 7685 polling-delay-passive = <100>; 7686 7687 thermal-sensors = <&tsens1 2>; 7688 7689 trips { 7690 gpuss1_alert0: trip-point0 { 7691 temperature = <95000>; 7692 hysteresis = <2000>; 7693 type = "passive"; 7694 }; 7695 7696 gpuss1_crit: gpuss1-crit { 7697 temperature = <110000>; 7698 hysteresis = <0>; 7699 type = "critical"; 7700 }; 7701 }; 7702 7703 cooling-maps { 7704 map0 { 7705 trip = <&gpuss1_alert0>; 7706 cooling-device = <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 7707 }; 7708 }; 7709 }; 7710 7711 nspss0-thermal { 7712 thermal-sensors = <&tsens1 3>; 7713 7714 trips { 7715 nspss0_alert0: trip-point0 { 7716 temperature = <90000>; 7717 hysteresis = <2000>; 7718 type = "hot"; 7719 }; 7720 7721 nspss0_crit: nspss0-crit { 7722 temperature = <110000>; 7723 hysteresis = <0>; 7724 type = "critical"; 7725 }; 7726 }; 7727 }; 7728 7729 nspss1-thermal { 7730 thermal-sensors = <&tsens1 4>; 7731 7732 trips { 7733 nspss1_alert0: trip-point0 { 7734 temperature = <90000>; 7735 hysteresis = <2000>; 7736 type = "hot"; 7737 }; 7738 7739 nspss1_crit: nspss1-crit { 7740 temperature = <110000>; 7741 hysteresis = <0>; 7742 type = "critical"; 7743 }; 7744 }; 7745 }; 7746 7747 video-thermal { 7748 thermal-sensors = <&tsens1 5>; 7749 7750 trips { 7751 video_alert0: trip-point0 { 7752 temperature = <90000>; 7753 hysteresis = <2000>; 7754 type = "hot"; 7755 }; 7756 7757 video_crit: video-crit { 7758 temperature = <110000>; 7759 hysteresis = <0>; 7760 type = "critical"; 7761 }; 7762 }; 7763 }; 7764 7765 ddr-thermal { 7766 thermal-sensors = <&tsens1 6>; 7767 7768 trips { 7769 ddr_alert0: trip-point0 { 7770 temperature = <90000>; 7771 hysteresis = <2000>; 7772 type = "hot"; 7773 }; 7774 7775 ddr_crit: ddr-crit { 7776 temperature = <110000>; 7777 hysteresis = <0>; 7778 type = "critical"; 7779 }; 7780 }; 7781 }; 7782 7783 mdmss0-thermal { 7784 thermal-sensors = <&tsens1 7>; 7785 7786 trips { 7787 mdmss0_alert0: trip-point0 { 7788 temperature = <90000>; 7789 hysteresis = <2000>; 7790 type = "hot"; 7791 }; 7792 7793 mdmss0_crit: mdmss0-crit { 7794 temperature = <110000>; 7795 hysteresis = <0>; 7796 type = "critical"; 7797 }; 7798 }; 7799 }; 7800 7801 mdmss1-thermal { 7802 thermal-sensors = <&tsens1 8>; 7803 7804 trips { 7805 mdmss1_alert0: trip-point0 { 7806 temperature = <90000>; 7807 hysteresis = <2000>; 7808 type = "hot"; 7809 }; 7810 7811 mdmss1_crit: mdmss1-crit { 7812 temperature = <110000>; 7813 hysteresis = <0>; 7814 type = "critical"; 7815 }; 7816 }; 7817 }; 7818 7819 mdmss2-thermal { 7820 thermal-sensors = <&tsens1 9>; 7821 7822 trips { 7823 mdmss2_alert0: trip-point0 { 7824 temperature = <90000>; 7825 hysteresis = <2000>; 7826 type = "hot"; 7827 }; 7828 7829 mdmss2_crit: mdmss2-crit { 7830 temperature = <110000>; 7831 hysteresis = <0>; 7832 type = "critical"; 7833 }; 7834 }; 7835 }; 7836 7837 mdmss3-thermal { 7838 thermal-sensors = <&tsens1 10>; 7839 7840 trips { 7841 mdmss3_alert0: trip-point0 { 7842 temperature = <90000>; 7843 hysteresis = <2000>; 7844 type = "hot"; 7845 }; 7846 7847 mdmss3_crit: mdmss3-crit { 7848 temperature = <110000>; 7849 hysteresis = <0>; 7850 type = "critical"; 7851 }; 7852 }; 7853 }; 7854 7855 camera0-thermal { 7856 thermal-sensors = <&tsens1 11>; 7857 7858 trips { 7859 camera0_alert0: trip-point0 { 7860 temperature = <90000>; 7861 hysteresis = <2000>; 7862 type = "hot"; 7863 }; 7864 7865 camera0_crit: camera0-crit { 7866 temperature = <110000>; 7867 hysteresis = <0>; 7868 type = "critical"; 7869 }; 7870 }; 7871 }; 7872 }; 7873 7874 timer { 7875 compatible = "arm,armv8-timer"; 7876 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 7877 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 7878 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 7879 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 7880 }; 7881}; 7882