1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,dsi-phy-28nm.h> 7#include <dt-bindings/clock/qcom,kaanapali-cambistmclkcc.h> 8#include <dt-bindings/clock/qcom,kaanapali-camcc.h> 9#include <dt-bindings/clock/qcom,kaanapali-dispcc.h> 10#include <dt-bindings/clock/qcom,kaanapali-gcc.h> 11#include <dt-bindings/clock/qcom,kaanapali-gpucc.h> 12#include <dt-bindings/clock/qcom,kaanapali-gxclkctl.h> 13#include <dt-bindings/clock/qcom,kaanapali-videocc.h> 14#include <dt-bindings/clock/qcom,rpmh.h> 15#include <dt-bindings/clock/qcom,sm8750-tcsr.h> 16#include <dt-bindings/dma/qcom-gpi.h> 17#include <dt-bindings/firmware/qcom,scm.h> 18#include <dt-bindings/gpio/gpio.h> 19#include <dt-bindings/interconnect/qcom,icc.h> 20#include <dt-bindings/interconnect/qcom,kaanapali-rpmh.h> 21#include <dt-bindings/interrupt-controller/arm-gic.h> 22#include <dt-bindings/mailbox/qcom-ipcc.h> 23#include <dt-bindings/phy/phy-qcom-qmp.h> 24#include <dt-bindings/power/qcom-rpmpd.h> 25#include <dt-bindings/regulator/qcom,rpmh-regulator.h> 26#include <dt-bindings/soc/qcom,gpr.h> 27#include <dt-bindings/soc/qcom,rpmh-rsc.h> 28#include <dt-bindings/sound/qcom,q6dsp-lpass-ports.h> 29 30#include "kaanapali-ipcc.h" 31 32/ { 33 interrupt-parent = <&intc>; 34 35 #address-cells = <2>; 36 #size-cells = <2>; 37 38 cpus { 39 #address-cells = <2>; 40 #size-cells = <0>; 41 42 cpu0: cpu@0 { 43 device_type = "cpu"; 44 compatible = "qcom,oryon"; 45 reg = <0x0 0x0>; 46 enable-method = "psci"; 47 next-level-cache = <&l2_0>; 48 power-domains = <&cpu_pd0>; 49 power-domain-names = "psci"; 50 clocks = <&pdp_scmi_perf 0>; 51 52 l2_0: l2-cache { 53 compatible = "cache"; 54 cache-level = <2>; 55 cache-unified; 56 }; 57 }; 58 59 cpu1: cpu@100 { 60 device_type = "cpu"; 61 compatible = "qcom,oryon"; 62 reg = <0x0 0x100>; 63 enable-method = "psci"; 64 next-level-cache = <&l2_0>; 65 power-domains = <&cpu_pd1>; 66 power-domain-names = "psci"; 67 clocks = <&pdp_scmi_perf 0>; 68 }; 69 70 cpu2: cpu@200 { 71 device_type = "cpu"; 72 compatible = "qcom,oryon"; 73 reg = <0x0 0x200>; 74 enable-method = "psci"; 75 next-level-cache = <&l2_0>; 76 power-domains = <&cpu_pd2>; 77 power-domain-names = "psci"; 78 clocks = <&pdp_scmi_perf 0>; 79 }; 80 81 cpu3: cpu@300 { 82 device_type = "cpu"; 83 compatible = "qcom,oryon"; 84 reg = <0x0 0x300>; 85 enable-method = "psci"; 86 next-level-cache = <&l2_0>; 87 power-domains = <&cpu_pd3>; 88 power-domain-names = "psci"; 89 clocks = <&pdp_scmi_perf 0>; 90 }; 91 92 cpu4: cpu@400 { 93 device_type = "cpu"; 94 compatible = "qcom,oryon"; 95 reg = <0x0 0x400>; 96 enable-method = "psci"; 97 next-level-cache = <&l2_0>; 98 power-domains = <&cpu_pd4>; 99 power-domain-names = "psci"; 100 clocks = <&pdp_scmi_perf 0>; 101 }; 102 103 cpu5: cpu@500 { 104 device_type = "cpu"; 105 compatible = "qcom,oryon"; 106 reg = <0x0 0x500>; 107 enable-method = "psci"; 108 next-level-cache = <&l2_0>; 109 power-domains = <&cpu_pd5>; 110 power-domain-names = "psci"; 111 clocks = <&pdp_scmi_perf 0>; 112 }; 113 114 cpu6: cpu@10000 { 115 device_type = "cpu"; 116 compatible = "qcom,oryon"; 117 reg = <0x0 0x10000>; 118 enable-method = "psci"; 119 next-level-cache = <&l2_1>; 120 power-domains = <&cpu_pd6>; 121 power-domain-names = "psci"; 122 clocks = <&pdp_scmi_perf 1>; 123 124 l2_1: l2-cache { 125 compatible = "cache"; 126 cache-level = <2>; 127 cache-unified; 128 }; 129 }; 130 131 cpu7: cpu@10100 { 132 device_type = "cpu"; 133 compatible = "qcom,oryon"; 134 reg = <0x0 0x10100>; 135 enable-method = "psci"; 136 next-level-cache = <&l2_1>; 137 power-domains = <&cpu_pd7>; 138 power-domain-names = "psci"; 139 clocks = <&pdp_scmi_perf 1>; 140 }; 141 142 cpu-map { 143 cluster0 { 144 core0 { 145 cpu = <&cpu0>; 146 }; 147 148 core1 { 149 cpu = <&cpu1>; 150 }; 151 152 core2 { 153 cpu = <&cpu2>; 154 }; 155 156 core3 { 157 cpu = <&cpu3>; 158 }; 159 160 core4 { 161 cpu = <&cpu4>; 162 }; 163 164 core5 { 165 cpu = <&cpu5>; 166 }; 167 }; 168 169 cluster1 { 170 core0 { 171 cpu = <&cpu6>; 172 }; 173 174 core1 { 175 cpu = <&cpu7>; 176 }; 177 }; 178 }; 179 180 idle-states { 181 entry-method = "psci"; 182 183 cluster0_c4: cpu-sleep-0 { 184 compatible = "arm,idle-state"; 185 idle-state-name = "retention"; 186 arm,psci-suspend-param = <0x00000004>; 187 entry-latency-us = <93>; 188 exit-latency-us = <129>; 189 min-residency-us = <560>; 190 }; 191 192 cluster1_c4: cpu-sleep-1 { 193 compatible = "arm,idle-state"; 194 idle-state-name = "retention"; 195 arm,psci-suspend-param = <0x00000004>; 196 entry-latency-us = <172>; 197 exit-latency-us = <130>; 198 min-residency-us = <686>; 199 }; 200 }; 201 202 domain-idle-states { 203 cluster_cl5: cluster-sleep-0 { 204 compatible = "domain-idle-state"; 205 arm,psci-suspend-param = <0x01000054>; 206 entry-latency-us = <2150>; 207 exit-latency-us = <1983>; 208 min-residency-us = <9144>; 209 }; 210 211 domain_ss3: domain-sleep-0 { 212 compatible = "domain-idle-state"; 213 arm,psci-suspend-param = <0x0200c354>; 214 entry-latency-us = <2800>; 215 exit-latency-us = <4400>; 216 min-residency-us = <10150>; 217 }; 218 }; 219 }; 220 221 firmware { 222 scm: scm { 223 compatible = "qcom,scm-kaanapali", "qcom,scm"; 224 qcom,dload-mode = <&tcsr 0x19000>; 225 interconnects = <&aggre_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 226 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 227 }; 228 229 scmi: scmi { 230 compatible = "arm,scmi"; 231 mboxes = <&pdp0_mbox 0>, <&pdp0_mbox 1>; 232 mbox-names = "tx", "rx"; 233 shmem = <&pdp_tx>, <&pdp_rx>; 234 235 #address-cells = <1>; 236 #size-cells = <0>; 237 238 pdp_scmi_perf: protocol@13 { 239 reg = <0x13>; 240 #clock-cells = <1>; 241 }; 242 }; 243 }; 244 245 clk_virt: interconnect-0 { 246 compatible = "qcom,kaanapali-clk-virt"; 247 #interconnect-cells = <2>; 248 qcom,bcm-voters = <&apps_bcm_voter>; 249 }; 250 251 mc_virt: interconnect-1 { 252 compatible = "qcom,kaanapali-mc-virt"; 253 #interconnect-cells = <2>; 254 qcom,bcm-voters = <&apps_bcm_voter>; 255 }; 256 257 memory@a0000000 { 258 device_type = "memory"; 259 /* We expect the bootloader to fill in the size */ 260 reg = <0x0 0xa0000000 0x0 0x0>; 261 }; 262 263 pmu { 264 compatible = "arm,armv8-pmuv3"; 265 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_LOW>; 266 }; 267 268 psci { 269 compatible = "arm,psci-1.0"; 270 method = "smc"; 271 272 cpu_pd0: power-domain-cpu0 { 273 #power-domain-cells = <0>; 274 power-domains = <&cluster_pd>; 275 domain-idle-states = <&cluster0_c4>; 276 }; 277 278 cpu_pd1: power-domain-cpu1 { 279 #power-domain-cells = <0>; 280 power-domains = <&cluster_pd>; 281 domain-idle-states = <&cluster0_c4>; 282 }; 283 284 cpu_pd2: power-domain-cpu2 { 285 #power-domain-cells = <0>; 286 power-domains = <&cluster_pd>; 287 domain-idle-states = <&cluster0_c4>; 288 }; 289 290 cpu_pd3: power-domain-cpu3 { 291 #power-domain-cells = <0>; 292 power-domains = <&cluster_pd>; 293 domain-idle-states = <&cluster0_c4>; 294 }; 295 296 cpu_pd4: power-domain-cpu4 { 297 #power-domain-cells = <0>; 298 power-domains = <&cluster_pd>; 299 domain-idle-states = <&cluster0_c4>; 300 }; 301 302 cpu_pd5: power-domain-cpu5 { 303 #power-domain-cells = <0>; 304 power-domains = <&cluster_pd>; 305 domain-idle-states = <&cluster0_c4>; 306 }; 307 308 cpu_pd6: power-domain-cpu6 { 309 #power-domain-cells = <0>; 310 power-domains = <&cluster_pd>; 311 domain-idle-states = <&cluster1_c4>; 312 }; 313 314 cpu_pd7: power-domain-cpu7 { 315 #power-domain-cells = <0>; 316 power-domains = <&cluster_pd>; 317 domain-idle-states = <&cluster1_c4>; 318 }; 319 320 cluster_pd: power-domain-cluster { 321 #power-domain-cells = <0>; 322 domain-idle-states = <&cluster_cl5>; 323 power-domains = <&system_pd>; 324 }; 325 326 system_pd: power-domain-system { 327 #power-domain-cells = <0>; 328 domain-idle-states = <&domain_ss3>; 329 }; 330 }; 331 332 reserved-memory { 333 #address-cells = <2>; 334 #size-cells = <2>; 335 ranges; 336 337 pdp_mem: pdp@81300000 { 338 reg = <0x0 0x81300000 0x0 0x100000>; 339 no-map; 340 }; 341 342 aop_cmd_db_mem: aop-cmd-db@81c60000 { 343 compatible = "qcom,cmd-db"; 344 reg = <0x0 0x81c60000 0x0 0x20000>; 345 no-map; 346 }; 347 348 smem_mem: smem@81d00000 { 349 compatible = "qcom,smem"; 350 reg = <0x0 0x81d00000 0x0 0x200000>; 351 hwlocks = <&tcsr_mutex 3>; 352 no-map; 353 }; 354 355 pdp_ns_shared_mem: pdp-ns-shared@81f00000 { 356 reg = <0x0 0x81f00000 0x0 0x100000>; 357 no-map; 358 }; 359 360 dsm_partition_1_mem: dsm-partition-1@84a00000 { 361 reg = <0x0 0x84a00000 0x0 0x5500000>; 362 no-map; 363 }; 364 365 dsm_partition_2_mem: dsm-partition-2@89f00000 { 366 reg = <0x0 0x89f00000 0x0 0xa80000>; 367 no-map; 368 }; 369 370 mpss_mem: mpss@8aa00000 { 371 reg = <0x0 0x8aa00000 0x0 0xeb00000>; 372 no-map; 373 }; 374 375 q6_mpss_dtb_mem: q6-mpss-dtb@99500000 { 376 reg = <0x0 0x99500000 0x0 0x80000>; 377 no-map; 378 }; 379 380 ipa_fw_mem: ipa-fw@99580000 { 381 reg = <0x0 0x99580000 0x0 0x10000>; 382 no-map; 383 }; 384 385 ipa_gsi_mem: ipa-gsi@99590000 { 386 reg = <0x0 0x99590000 0x0 0xa000>; 387 no-map; 388 }; 389 390 gpu_microcode_mem: gpu-microcode@9959a000 { 391 reg = <0x0 0x9959a000 0x0 0x2000>; 392 no-map; 393 }; 394 395 camera_mem: camera@99600000 { 396 reg = <0x0 0x99600000 0x0 0x800000>; 397 no-map; 398 }; 399 400 camera_2_mem: camera-2@99e00000 { 401 reg = <0x0 0x99e00000 0x0 0x800000>; 402 no-map; 403 }; 404 405 video_mem: video@9a600000 { 406 reg = <0x0 0x9a600000 0x0 0x800000>; 407 no-map; 408 }; 409 410 cvp_mem: cvp@9ae00000 { 411 reg = <0x0 0x9ae00000 0x0 0x700000>; 412 no-map; 413 }; 414 415 cdsp_mem: cdsp@9b500000 { 416 reg = <0x0 0x9b500000 0x0 0x1900000>; 417 no-map; 418 }; 419 420 q6_cdsp_dtb_mem: q6-cdsp-dtb@9ce00000 { 421 reg = <0x0 0x9ce00000 0x0 0x80000>; 422 no-map; 423 }; 424 425 soccp_mem: soccp@a03d0000 { 426 reg = <0x0 0xa03d0000 0x0 0x500000>; 427 no-map; 428 }; 429 430 soccp_dtb_mem: soccp-dtb@a08d0000 { 431 reg = <0x0 0xa08d0000 0x0 0x40000>; 432 no-map; 433 }; 434 435 q6_adsp_dtb_mem: q6-adsp-dtb@a1380000 { 436 reg = <0x0 0xa1380000 0x0 0x80000>; 437 no-map; 438 }; 439 440 adspslpi_mem: adspslpi@a1400000 { 441 reg = <0x0 0xa1400000 0x0 0x4c00000>; 442 no-map; 443 }; 444 445 rmtfs_mem: rmtfs@d7c00000 { 446 compatible = "qcom,rmtfs-mem"; 447 reg = <0x0 0xd7c00000 0x0 0x400000>; 448 no-map; 449 450 qcom,client-id = <1>; 451 qcom,vmid = <QCOM_SCM_VMID_MSS_MSA>; 452 }; 453 }; 454 455 smp2p-adsp { 456 compatible = "qcom,smp2p"; 457 458 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 459 IPCC_MPROC_SIGNAL_SMP2P 460 IRQ_TYPE_EDGE_RISING>; 461 462 mboxes = <&ipcc IPCC_MPROC_LPASS 463 IPCC_MPROC_SIGNAL_SMP2P>; 464 465 qcom,smem = <443>, <429>; 466 qcom,local-pid = <0>; 467 qcom,remote-pid = <2>; 468 469 smp2p_adsp_out: master-kernel { 470 qcom,entry-name = "master-kernel"; 471 #qcom,smem-state-cells = <1>; 472 }; 473 474 smp2p_adsp_in: slave-kernel { 475 qcom,entry-name = "slave-kernel"; 476 interrupt-controller; 477 #interrupt-cells = <2>; 478 }; 479 }; 480 481 smp2p-cdsp { 482 compatible = "qcom,smp2p"; 483 484 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 485 IPCC_MPROC_SIGNAL_SMP2P 486 IRQ_TYPE_EDGE_RISING>; 487 488 mboxes = <&ipcc IPCC_MPROC_CDSP 489 IPCC_MPROC_SIGNAL_SMP2P>; 490 491 qcom,smem = <94>, <432>; 492 qcom,local-pid = <0>; 493 qcom,remote-pid = <5>; 494 495 smp2p_cdsp_out: master-kernel { 496 qcom,entry-name = "master-kernel"; 497 #qcom,smem-state-cells = <1>; 498 }; 499 500 smp2p_cdsp_in: slave-kernel { 501 qcom,entry-name = "slave-kernel"; 502 interrupt-controller; 503 #interrupt-cells = <2>; 504 }; 505 }; 506 507 soc: soc@0 { 508 compatible = "simple-bus"; 509 510 #address-cells = <2>; 511 #size-cells = <2>; 512 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 513 ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 514 515 gcc: clock-controller@100000 { 516 compatible = "qcom,kaanapali-gcc"; 517 reg = <0x0 0x00100000 0x0 0x1f4200>; 518 519 clocks = <&bi_tcxo_div2>, 520 <&bi_tcxo_ao_div2>, 521 <&sleep_clk>, 522 <&pcie0_phy>, 523 <&ufs_mem_phy 0>, 524 <&ufs_mem_phy 1>, 525 <&ufs_mem_phy 2>, 526 <0>; 527 528 #clock-cells = <1>; 529 #reset-cells = <1>; 530 #power-domain-cells = <1>; 531 }; 532 533 gpi_dma2: dma-controller@800000 { 534 compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; 535 reg = <0x0 0x00800000 0x0 0x60000>; 536 537 interrupts = <GIC_SPI 279 IRQ_TYPE_LEVEL_HIGH>, 538 <GIC_SPI 280 IRQ_TYPE_LEVEL_HIGH>, 539 <GIC_SPI 281 IRQ_TYPE_LEVEL_HIGH>, 540 <GIC_SPI 282 IRQ_TYPE_LEVEL_HIGH>, 541 <GIC_SPI 283 IRQ_TYPE_LEVEL_HIGH>, 542 <GIC_SPI 848 IRQ_TYPE_LEVEL_HIGH>, 543 <GIC_SPI 849 IRQ_TYPE_LEVEL_HIGH>, 544 <GIC_SPI 850 IRQ_TYPE_LEVEL_HIGH>, 545 <GIC_SPI 851 IRQ_TYPE_LEVEL_HIGH>, 546 <GIC_SPI 852 IRQ_TYPE_LEVEL_HIGH>, 547 <GIC_SPI 853 IRQ_TYPE_LEVEL_HIGH>, 548 <GIC_SPI 854 IRQ_TYPE_LEVEL_HIGH>; 549 550 dma-channels = <12>; 551 dma-channel-mask = <0x1f>; 552 #dma-cells = <3>; 553 554 iommus = <&apps_smmu 0x436 0x0>; 555 dma-coherent; 556 }; 557 558 qupv3_2: geniqup@8c0000 { 559 compatible = "qcom,geni-se-qup"; 560 reg = <0x0 0x008c0000 0x0 0x2000>; 561 562 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 563 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 564 clock-names = "m-ahb", 565 "s-ahb"; 566 567 iommus = <&apps_smmu 0x423 0x0>; 568 569 dma-coherent; 570 571 #address-cells = <2>; 572 #size-cells = <2>; 573 ranges; 574 575 i2c8: i2c@880000 { 576 compatible = "qcom,geni-i2c"; 577 reg = <0x0 0x00880000 0x0 0x4000>; 578 579 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 580 581 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 582 clock-names = "se"; 583 584 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 585 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 586 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 587 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 588 <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 589 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 590 interconnect-names = "qup-core", 591 "qup-config", 592 "qup-memory"; 593 594 dmas = <&gpi_dma2 0 0 QCOM_GPI_I2C>, 595 <&gpi_dma2 1 0 QCOM_GPI_I2C>; 596 dma-names = "tx", 597 "rx"; 598 599 pinctrl-0 = <&qup_i2c8_data_clk>; 600 pinctrl-names = "default"; 601 602 #address-cells = <1>; 603 #size-cells = <0>; 604 605 status = "disabled"; 606 }; 607 608 spi8: spi@880000 { 609 compatible = "qcom,geni-spi"; 610 reg = <0x0 0x00880000 0x0 0x4000>; 611 612 interrupts = <GIC_SPI 353 IRQ_TYPE_LEVEL_HIGH>; 613 614 clocks = <&gcc GCC_QUPV3_WRAP2_S0_CLK>; 615 clock-names = "se"; 616 617 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 618 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 619 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 620 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 621 interconnect-names = "qup-core", 622 "qup-config"; 623 624 dmas = <&gpi_dma2 0 0 QCOM_GPI_SPI>, 625 <&gpi_dma2 1 0 QCOM_GPI_SPI>; 626 dma-names = "tx", 627 "rx"; 628 629 pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>; 630 pinctrl-names = "default"; 631 632 #address-cells = <1>; 633 #size-cells = <0>; 634 635 status = "disabled"; 636 }; 637 638 i2c9: i2c@884000 { 639 compatible = "qcom,geni-i2c"; 640 reg = <0x0 0x00884000 0x0 0x4000>; 641 642 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 643 644 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 645 clock-names = "se"; 646 647 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 648 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 649 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 650 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 651 <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 652 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 653 interconnect-names = "qup-core", 654 "qup-config", 655 "qup-memory"; 656 657 dmas = <&gpi_dma2 0 1 QCOM_GPI_I2C>, 658 <&gpi_dma2 1 1 QCOM_GPI_I2C>; 659 dma-names = "tx", 660 "rx"; 661 662 pinctrl-0 = <&qup_i2c9_data_clk>; 663 pinctrl-names = "default"; 664 665 #address-cells = <1>; 666 #size-cells = <0>; 667 668 status = "disabled"; 669 }; 670 671 spi9: spi@884000 { 672 compatible = "qcom,geni-spi"; 673 reg = <0x0 0x00884000 0x0 0x4000>; 674 675 interrupts = <GIC_SPI 354 IRQ_TYPE_LEVEL_HIGH>; 676 677 clocks = <&gcc GCC_QUPV3_WRAP2_S1_CLK>; 678 clock-names = "se"; 679 680 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 681 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 682 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 683 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 684 interconnect-names = "qup-core", 685 "qup-config"; 686 687 dmas = <&gpi_dma2 0 1 QCOM_GPI_SPI>, 688 <&gpi_dma2 1 1 QCOM_GPI_SPI>; 689 dma-names = "tx", 690 "rx"; 691 692 pinctrl-0 = <&qup_spi9_data_clk>, <&qup_spi9_cs>; 693 pinctrl-names = "default"; 694 695 #address-cells = <1>; 696 #size-cells = <0>; 697 698 status = "disabled"; 699 }; 700 701 i2c10: i2c@888000 { 702 compatible = "qcom,geni-i2c"; 703 reg = <0x0 0x00888000 0x0 0x4000>; 704 705 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 706 707 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 708 clock-names = "se"; 709 710 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 711 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 712 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 713 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 714 <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 715 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 716 interconnect-names = "qup-core", 717 "qup-config", 718 "qup-memory"; 719 720 dmas = <&gpi_dma2 0 2 QCOM_GPI_I2C>, 721 <&gpi_dma2 1 2 QCOM_GPI_I2C>; 722 dma-names = "tx", 723 "rx"; 724 725 pinctrl-0 = <&qup_i2c10_data_clk>; 726 pinctrl-names = "default"; 727 728 #address-cells = <1>; 729 #size-cells = <0>; 730 731 status = "disabled"; 732 }; 733 734 spi10: spi@888000 { 735 compatible = "qcom,geni-spi"; 736 reg = <0x0 0x00888000 0x0 0x4000>; 737 738 interrupts = <GIC_SPI 355 IRQ_TYPE_LEVEL_HIGH>; 739 740 clocks = <&gcc GCC_QUPV3_WRAP2_S2_CLK>; 741 clock-names = "se"; 742 743 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 744 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 745 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 746 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 747 interconnect-names = "qup-core", 748 "qup-config"; 749 750 dmas = <&gpi_dma2 0 2 QCOM_GPI_SPI>, 751 <&gpi_dma2 1 2 QCOM_GPI_SPI>; 752 dma-names = "tx", 753 "rx"; 754 755 pinctrl-0 = <&qup_spi10_data_clk>, <&qup_spi10_cs>; 756 pinctrl-names = "default"; 757 758 #address-cells = <1>; 759 #size-cells = <0>; 760 761 status = "disabled"; 762 }; 763 764 i2c11: i2c@88c000 { 765 compatible = "qcom,geni-i2c"; 766 reg = <0x0 0x0088c000 0x0 0x4000>; 767 768 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 769 770 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 771 clock-names = "se"; 772 773 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 774 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 775 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 776 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 777 <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 778 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 779 interconnect-names = "qup-core", 780 "qup-config", 781 "qup-memory"; 782 783 dmas = <&gpi_dma2 0 3 QCOM_GPI_I2C>, 784 <&gpi_dma2 1 3 QCOM_GPI_I2C>; 785 dma-names = "tx", 786 "rx"; 787 788 pinctrl-0 = <&qup_i2c11_data_clk>; 789 pinctrl-names = "default"; 790 791 #address-cells = <1>; 792 #size-cells = <0>; 793 794 status = "disabled"; 795 }; 796 797 spi11: spi@88c000 { 798 compatible = "qcom,geni-spi"; 799 reg = <0x0 0x0088c000 0x0 0x4000>; 800 801 interrupts = <GIC_SPI 356 IRQ_TYPE_LEVEL_HIGH>; 802 803 clocks = <&gcc GCC_QUPV3_WRAP2_S3_CLK>; 804 clock-names = "se"; 805 806 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 807 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 808 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 809 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 810 interconnect-names = "qup-core", 811 "qup-config"; 812 813 dmas = <&gpi_dma2 0 3 QCOM_GPI_SPI>, 814 <&gpi_dma2 1 3 QCOM_GPI_SPI>; 815 dma-names = "tx", 816 "rx"; 817 818 pinctrl-0 = <&qup_spi11_data_clk>, <&qup_spi11_cs>; 819 pinctrl-names = "default"; 820 821 #address-cells = <1>; 822 #size-cells = <0>; 823 824 status = "disabled"; 825 }; 826 827 i2c12: i2c@890000 { 828 compatible = "qcom,geni-i2c"; 829 reg = <0x0 0x00890000 0x0 0x4000>; 830 831 interrupts = <GIC_SPI 357 IRQ_TYPE_LEVEL_HIGH>; 832 833 clocks = <&gcc GCC_QUPV3_WRAP2_S4_CLK>; 834 clock-names = "se"; 835 836 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 837 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 838 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 839 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>, 840 <&aggre_noc MASTER_QUP_2 QCOM_ICC_TAG_ALWAYS 841 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 842 interconnect-names = "qup-core", 843 "qup-config", 844 "qup-memory"; 845 846 dmas = <&gpi_dma2 0 4 QCOM_GPI_I2C>, 847 <&gpi_dma2 1 4 QCOM_GPI_I2C>; 848 dma-names = "tx", 849 "rx"; 850 851 pinctrl-0 = <&qup_i2c12_data_clk>; 852 pinctrl-names = "default"; 853 854 #address-cells = <1>; 855 #size-cells = <0>; 856 857 status = "disabled"; 858 }; 859 }; 860 861 i2c_master_hub: geniqup@9c0000 { 862 compatible = "qcom,geni-se-i2c-master-hub"; 863 reg = <0x0 0x009c0000 0x0 0x2000>; 864 865 clocks = <&gcc GCC_QUPV3_I2C_S_AHB_CLK>; 866 clock-names = "s-ahb"; 867 868 #address-cells = <2>; 869 #size-cells = <2>; 870 ranges; 871 872 status = "disabled"; 873 874 i2c_hub_0: i2c@980000 { 875 compatible = "qcom,geni-i2c-master-hub"; 876 reg = <0x0 0x00980000 0x0 0x4000>; 877 878 interrupts = <GIC_SPI 464 IRQ_TYPE_LEVEL_HIGH>; 879 880 clocks = <&gcc GCC_QUPV3_I2C_S0_CLK>, 881 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 882 clock-names = "se", 883 "core"; 884 885 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 886 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 887 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 888 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 889 interconnect-names = "qup-core", 890 "qup-config"; 891 892 pinctrl-0 = <&hub_i2c0_data_clk>; 893 pinctrl-names = "default"; 894 895 #address-cells = <1>; 896 #size-cells = <0>; 897 898 status = "disabled"; 899 }; 900 901 i2c_hub_1: i2c@984000 { 902 compatible = "qcom,geni-i2c-master-hub"; 903 reg = <0x0 0x00984000 0x0 0x4000>; 904 905 interrupts = <GIC_SPI 465 IRQ_TYPE_LEVEL_HIGH>; 906 907 clocks = <&gcc GCC_QUPV3_I2C_S1_CLK>, 908 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 909 clock-names = "se", 910 "core"; 911 912 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 913 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 914 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 915 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 916 interconnect-names = "qup-core", 917 "qup-config"; 918 919 pinctrl-0 = <&hub_i2c1_data_clk>; 920 pinctrl-names = "default"; 921 922 #address-cells = <1>; 923 #size-cells = <0>; 924 925 status = "disabled"; 926 }; 927 928 i2c_hub_2: i2c@988000 { 929 compatible = "qcom,geni-i2c-master-hub"; 930 reg = <0x0 0x00988000 0x0 0x4000>; 931 932 interrupts = <GIC_SPI 466 IRQ_TYPE_LEVEL_HIGH>; 933 934 clocks = <&gcc GCC_QUPV3_I2C_S2_CLK>, 935 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 936 clock-names = "se", 937 "core"; 938 939 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 940 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 941 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 942 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 943 interconnect-names = "qup-core", 944 "qup-config"; 945 946 pinctrl-0 = <&hub_i2c2_data_clk>; 947 pinctrl-names = "default"; 948 949 #address-cells = <1>; 950 #size-cells = <0>; 951 952 status = "disabled"; 953 }; 954 955 i2c_hub_3: i2c@98c000 { 956 compatible = "qcom,geni-i2c-master-hub"; 957 reg = <0x0 0x0098c000 0x0 0x4000>; 958 959 interrupts = <GIC_SPI 467 IRQ_TYPE_LEVEL_HIGH>; 960 961 clocks = <&gcc GCC_QUPV3_I2C_S3_CLK>, 962 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 963 clock-names = "se", 964 "core"; 965 966 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 967 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 968 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 969 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 970 interconnect-names = "qup-core", 971 "qup-config"; 972 973 pinctrl-0 = <&hub_i2c3_data_clk>; 974 pinctrl-names = "default"; 975 976 #address-cells = <1>; 977 #size-cells = <0>; 978 979 status = "disabled"; 980 }; 981 982 i2c_hub_4: i2c@990000 { 983 compatible = "qcom,geni-i2c-master-hub"; 984 reg = <0x0 0x00990000 0x0 0x4000>; 985 986 interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH>; 987 988 clocks = <&gcc GCC_QUPV3_I2C_S4_CLK>, 989 <&gcc GCC_QUPV3_I2C_CORE_CLK>; 990 clock-names = "se", 991 "core"; 992 993 interconnects = <&clk_virt MASTER_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS 994 &clk_virt SLAVE_QUP_CORE_0 QCOM_ICC_TAG_ALWAYS>, 995 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 996 &config_noc SLAVE_I2C QCOM_ICC_TAG_ALWAYS>; 997 interconnect-names = "qup-core", 998 "qup-config"; 999 1000 pinctrl-0 = <&hub_i2c4_data_clk>; 1001 pinctrl-names = "default"; 1002 1003 #address-cells = <1>; 1004 #size-cells = <0>; 1005 1006 status = "disabled"; 1007 }; 1008 }; 1009 1010 gpi_dma1: dma-controller@a00000 { 1011 compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; 1012 reg = <0x0 0x00a00000 0x0 0x60000>; 1013 1014 interrupts = <GIC_SPI 836 IRQ_TYPE_LEVEL_HIGH>, 1015 <GIC_SPI 837 IRQ_TYPE_LEVEL_HIGH>, 1016 <GIC_SPI 838 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 839 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 840 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 841 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 842 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 843 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 844 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 845 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 846 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 847 IRQ_TYPE_LEVEL_HIGH>; 1026 1027 dma-channels = <12>; 1028 dma-channel-mask = <0x1f>; 1029 #dma-cells = <3>; 1030 1031 iommus = <&apps_smmu 0xb6 0x0>; 1032 dma-coherent; 1033 }; 1034 1035 qupv3_1: geniqup@ac0000 { 1036 compatible = "qcom,geni-se-qup"; 1037 reg = <0x0 0x00ac0000 0x0 0x2000>; 1038 1039 clocks = <&gcc GCC_QUPV3_WRAP_1_M_AXI_CLK>, 1040 <&gcc GCC_QUPV3_WRAP_1_S_AHB_CLK>; 1041 clock-names = "m-ahb", 1042 "s-ahb"; 1043 1044 iommus = <&apps_smmu 0xa3 0x0>; 1045 1046 dma-coherent; 1047 1048 #address-cells = <2>; 1049 #size-cells = <2>; 1050 ranges; 1051 1052 i2c0: i2c@a80000 { 1053 compatible = "qcom,geni-i2c"; 1054 reg = <0x0 0x00a80000 0x0 0x4000>; 1055 1056 interrupts = <GIC_SPI 828 IRQ_TYPE_LEVEL_HIGH>; 1057 1058 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1059 clock-names = "se"; 1060 1061 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1062 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1063 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1064 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1065 <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1066 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1067 interconnect-names = "qup-core", 1068 "qup-config", 1069 "qup-memory"; 1070 1071 dmas = <&gpi_dma1 0 0 QCOM_GPI_I2C>, 1072 <&gpi_dma1 1 0 QCOM_GPI_I2C>; 1073 dma-names = "tx", 1074 "rx"; 1075 1076 pinctrl-0 = <&qup_i2c0_data_clk>; 1077 pinctrl-names = "default"; 1078 1079 #address-cells = <1>; 1080 #size-cells = <0>; 1081 1082 status = "disabled"; 1083 }; 1084 1085 spi0: spi@a80000 { 1086 compatible = "qcom,geni-spi"; 1087 reg = <0x0 0x00a80000 0x0 0x4000>; 1088 1089 interrupts = <GIC_SPI 828 IRQ_TYPE_LEVEL_HIGH>; 1090 1091 clocks = <&gcc GCC_QUPV3_WRAP1_S0_CLK>; 1092 clock-names = "se"; 1093 1094 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1095 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1096 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1097 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1098 interconnect-names = "qup-core", 1099 "qup-config"; 1100 1101 dmas = <&gpi_dma1 0 0 QCOM_GPI_SPI>, 1102 <&gpi_dma1 1 0 QCOM_GPI_SPI>; 1103 dma-names = "tx", 1104 "rx"; 1105 1106 pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>; 1107 pinctrl-names = "default"; 1108 1109 #address-cells = <1>; 1110 #size-cells = <0>; 1111 1112 status = "disabled"; 1113 }; 1114 1115 i2c1: i2c@a84000 { 1116 compatible = "qcom,geni-i2c"; 1117 reg = <0x0 0x00a84000 0x0 0x4000>; 1118 1119 interrupts = <GIC_SPI 829 IRQ_TYPE_LEVEL_HIGH>; 1120 1121 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1122 clock-names = "se"; 1123 1124 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1125 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1126 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1127 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1128 <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1129 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1130 interconnect-names = "qup-core", 1131 "qup-config", 1132 "qup-memory"; 1133 1134 dmas = <&gpi_dma1 0 1 QCOM_GPI_I2C>, 1135 <&gpi_dma1 1 1 QCOM_GPI_I2C>; 1136 dma-names = "tx", 1137 "rx"; 1138 1139 pinctrl-0 = <&qup_i2c1_data_clk>; 1140 pinctrl-names = "default"; 1141 1142 #address-cells = <1>; 1143 #size-cells = <0>; 1144 1145 status = "disabled"; 1146 }; 1147 1148 spi1: spi@a84000 { 1149 compatible = "qcom,geni-spi"; 1150 reg = <0x0 0x00a84000 0x0 0x4000>; 1151 1152 interrupts = <GIC_SPI 829 IRQ_TYPE_LEVEL_HIGH>; 1153 1154 clocks = <&gcc GCC_QUPV3_WRAP1_S1_CLK>; 1155 clock-names = "se"; 1156 1157 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1158 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1159 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1160 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1161 interconnect-names = "qup-core", 1162 "qup-config"; 1163 1164 dmas = <&gpi_dma1 0 1 QCOM_GPI_SPI>, 1165 <&gpi_dma1 1 1 QCOM_GPI_SPI>; 1166 dma-names = "tx", 1167 "rx"; 1168 1169 pinctrl-0 = <&qup_spi1_data_clk>, <&qup_spi1_cs>; 1170 pinctrl-names = "default"; 1171 1172 #address-cells = <1>; 1173 #size-cells = <0>; 1174 1175 status = "disabled"; 1176 }; 1177 1178 i2c2: i2c@a88000 { 1179 compatible = "qcom,geni-i2c"; 1180 reg = <0x0 0x00a88000 0x0 0x4000>; 1181 1182 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 1183 1184 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1185 clock-names = "se"; 1186 1187 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1188 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1189 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1190 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1191 <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1192 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1193 interconnect-names = "qup-core", 1194 "qup-config", 1195 "qup-memory"; 1196 1197 dmas = <&gpi_dma1 0 2 QCOM_GPI_I2C>, 1198 <&gpi_dma1 1 2 QCOM_GPI_I2C>; 1199 dma-names = "tx", 1200 "rx"; 1201 1202 pinctrl-0 = <&qup_i2c2_data_clk>; 1203 pinctrl-names = "default"; 1204 1205 #address-cells = <1>; 1206 #size-cells = <0>; 1207 1208 status = "disabled"; 1209 }; 1210 1211 spi2: spi@a88000 { 1212 compatible = "qcom,geni-spi"; 1213 reg = <0x0 0x00a88000 0x0 0x4000>; 1214 1215 interrupts = <GIC_SPI 830 IRQ_TYPE_LEVEL_HIGH>; 1216 1217 clocks = <&gcc GCC_QUPV3_WRAP1_S2_CLK>; 1218 clock-names = "se"; 1219 1220 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1221 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1222 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1223 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1224 interconnect-names = "qup-core", 1225 "qup-config"; 1226 1227 dmas = <&gpi_dma1 0 2 QCOM_GPI_SPI>, 1228 <&gpi_dma1 1 2 QCOM_GPI_SPI>; 1229 dma-names = "tx", 1230 "rx"; 1231 1232 pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>; 1233 pinctrl-names = "default"; 1234 1235 #address-cells = <1>; 1236 #size-cells = <0>; 1237 1238 status = "disabled"; 1239 }; 1240 1241 i2c3: i2c@a8c000 { 1242 compatible = "qcom,geni-i2c"; 1243 reg = <0x0 0x00a8c000 0x0 0x4000>; 1244 1245 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 1246 1247 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1248 clock-names = "se"; 1249 1250 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1251 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1252 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1253 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1254 <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1255 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1256 interconnect-names = "qup-core", 1257 "qup-config", 1258 "qup-memory"; 1259 1260 dmas = <&gpi_dma1 0 3 QCOM_GPI_I2C>, 1261 <&gpi_dma1 1 3 QCOM_GPI_I2C>; 1262 dma-names = "tx", 1263 "rx"; 1264 1265 pinctrl-0 = <&qup_i2c3_data_clk>; 1266 pinctrl-names = "default"; 1267 1268 #address-cells = <1>; 1269 #size-cells = <0>; 1270 1271 status = "disabled"; 1272 }; 1273 1274 spi3: spi@a8c000 { 1275 compatible = "qcom,geni-spi"; 1276 reg = <0x0 0x00a8c000 0x0 0x4000>; 1277 1278 interrupts = <GIC_SPI 831 IRQ_TYPE_LEVEL_HIGH>; 1279 1280 clocks = <&gcc GCC_QUPV3_WRAP1_S3_CLK>; 1281 clock-names = "se"; 1282 1283 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1284 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1285 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1286 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1287 interconnect-names = "qup-core", 1288 "qup-config"; 1289 1290 dmas = <&gpi_dma1 0 3 QCOM_GPI_SPI>, 1291 <&gpi_dma1 1 3 QCOM_GPI_SPI>; 1292 dma-names = "tx", 1293 "rx"; 1294 1295 pinctrl-0 = <&qup_spi3_data_clk>, <&qup_spi3_cs>; 1296 pinctrl-names = "default"; 1297 1298 #address-cells = <1>; 1299 #size-cells = <0>; 1300 1301 status = "disabled"; 1302 }; 1303 1304 i2c4: i2c@a90000 { 1305 compatible = "qcom,geni-i2c"; 1306 reg = <0x0 0x00a90000 0x0 0x4000>; 1307 1308 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>; 1309 1310 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1311 clock-names = "se"; 1312 1313 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1314 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1315 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1316 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1317 <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1318 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1319 interconnect-names = "qup-core", 1320 "qup-config", 1321 "qup-memory"; 1322 1323 dmas = <&gpi_dma1 0 4 QCOM_GPI_I2C>, 1324 <&gpi_dma1 1 4 QCOM_GPI_I2C>; 1325 dma-names = "tx", 1326 "rx"; 1327 1328 pinctrl-0 = <&qup_i2c4_data_clk>; 1329 pinctrl-names = "default"; 1330 1331 #address-cells = <1>; 1332 #size-cells = <0>; 1333 1334 status = "disabled"; 1335 }; 1336 1337 spi4: spi@a90000 { 1338 compatible = "qcom,geni-spi"; 1339 reg = <0x0 0x00a90000 0x0 0x4000>; 1340 1341 interrupts = <GIC_SPI 832 IRQ_TYPE_LEVEL_HIGH>; 1342 1343 clocks = <&gcc GCC_QUPV3_WRAP1_S4_CLK>; 1344 clock-names = "se"; 1345 1346 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1347 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1348 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1349 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1350 interconnect-names = "qup-core", 1351 "qup-config"; 1352 1353 dmas = <&gpi_dma1 0 4 QCOM_GPI_SPI>, 1354 <&gpi_dma1 1 4 QCOM_GPI_SPI>; 1355 dma-names = "tx", 1356 "rx"; 1357 1358 pinctrl-0 = <&qup_spi4_data_clk>, <&qup_spi4_cs>; 1359 pinctrl-names = "default"; 1360 1361 #address-cells = <1>; 1362 #size-cells = <0>; 1363 1364 status = "disabled"; 1365 }; 1366 1367 i2c5: i2c@a94000 { 1368 compatible = "qcom,geni-i2c"; 1369 reg = <0x0 0x00a94000 0x0 0x4000>; 1370 1371 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1372 1373 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1374 clock-names = "se"; 1375 1376 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1377 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1378 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1379 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1380 <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1381 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1382 interconnect-names = "qup-core", 1383 "qup-config", 1384 "qup-memory"; 1385 1386 dmas = <&gpi_dma1 0 5 QCOM_GPI_I2C>, 1387 <&gpi_dma1 1 5 QCOM_GPI_I2C>; 1388 dma-names = "tx", 1389 "rx"; 1390 1391 pinctrl-0 = <&qup_i2c5_data_clk>; 1392 pinctrl-names = "default"; 1393 1394 #address-cells = <1>; 1395 #size-cells = <0>; 1396 1397 status = "disabled"; 1398 }; 1399 1400 spi5: spi@a94000 { 1401 compatible = "qcom,geni-spi"; 1402 reg = <0x0 0x00a94000 0x0 0x4000>; 1403 1404 interrupts = <GIC_SPI 833 IRQ_TYPE_LEVEL_HIGH>; 1405 1406 clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>; 1407 clock-names = "se"; 1408 1409 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1410 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1411 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1412 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1413 interconnect-names = "qup-core", 1414 "qup-config"; 1415 1416 dmas = <&gpi_dma1 0 5 QCOM_GPI_SPI>, 1417 <&gpi_dma1 1 5 QCOM_GPI_SPI>; 1418 dma-names = "tx", 1419 "rx"; 1420 1421 pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>; 1422 pinctrl-names = "default"; 1423 1424 #address-cells = <1>; 1425 #size-cells = <0>; 1426 1427 status = "disabled"; 1428 }; 1429 1430 i2c6: i2c@a98000 { 1431 compatible = "qcom,geni-i2c"; 1432 reg = <0x0 0x00a98000 0x0 0x4000>; 1433 1434 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1435 1436 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1437 clock-names = "se"; 1438 1439 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1440 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1441 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1442 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>, 1443 <&aggre_noc MASTER_QUP_1 QCOM_ICC_TAG_ALWAYS 1444 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1445 interconnect-names = "qup-core", 1446 "qup-config", 1447 "qup-memory"; 1448 1449 dmas = <&gpi_dma1 0 6 QCOM_GPI_I2C>, 1450 <&gpi_dma1 1 6 QCOM_GPI_I2C>; 1451 dma-names = "tx", 1452 "rx"; 1453 1454 pinctrl-0 = <&qup_i2c6_data_clk>; 1455 pinctrl-names = "default"; 1456 1457 #address-cells = <1>; 1458 #size-cells = <0>; 1459 1460 status = "disabled"; 1461 }; 1462 1463 spi6: spi@a98000 { 1464 compatible = "qcom,geni-spi"; 1465 reg = <0x0 0x00a98000 0x0 0x4000>; 1466 1467 interrupts = <GIC_SPI 834 IRQ_TYPE_LEVEL_HIGH>; 1468 1469 clocks = <&gcc GCC_QUPV3_WRAP1_S6_CLK>; 1470 clock-names = "se"; 1471 1472 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1473 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1474 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1475 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1476 interconnect-names = "qup-core", 1477 "qup-config"; 1478 1479 dmas = <&gpi_dma1 0 6 QCOM_GPI_SPI>, 1480 <&gpi_dma1 1 6 QCOM_GPI_SPI>; 1481 dma-names = "tx", 1482 "rx"; 1483 1484 pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>; 1485 pinctrl-names = "default"; 1486 1487 #address-cells = <1>; 1488 #size-cells = <0>; 1489 1490 status = "disabled"; 1491 }; 1492 1493 uart7: serial@a9c000 { 1494 compatible = "qcom,geni-debug-uart"; 1495 reg = <0x0 0x00a9c000 0x0 0x4000>; 1496 1497 interrupts = <GIC_SPI 835 IRQ_TYPE_LEVEL_HIGH>; 1498 1499 clocks = <&gcc GCC_QUPV3_WRAP1_S7_CLK>; 1500 clock-names = "se"; 1501 1502 interconnects = <&clk_virt MASTER_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS 1503 &clk_virt SLAVE_QUP_CORE_1 QCOM_ICC_TAG_ALWAYS>, 1504 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1505 &config_noc SLAVE_QUP_1 QCOM_ICC_TAG_ACTIVE_ONLY>; 1506 interconnect-names = "qup-core", 1507 "qup-config"; 1508 1509 pinctrl-0 = <&qup_uart7_default>; 1510 pinctrl-names = "default"; 1511 1512 status = "disabled"; 1513 }; 1514 }; 1515 1516 ipcc: mailbox@1106000 { 1517 compatible = "qcom,kaanapali-ipcc", "qcom,ipcc"; 1518 reg = <0x0 0x01106000 0x0 0x1000>; 1519 1520 interrupts = <GIC_SPI 246 IRQ_TYPE_LEVEL_HIGH>; 1521 interrupt-controller; 1522 #interrupt-cells = <3>; 1523 1524 #mbox-cells = <2>; 1525 }; 1526 1527 cnoc_main: interconnect@1500000 { 1528 compatible = "qcom,kaanapali-cnoc-main"; 1529 reg = <0x0 0x01500000 0x0 0x1a080>; 1530 qcom,bcm-voters = <&apps_bcm_voter>; 1531 #interconnect-cells = <2>; 1532 }; 1533 1534 config_noc: interconnect@1600000 { 1535 compatible = "qcom,kaanapali-cnoc-cfg"; 1536 reg = <0x0 0x01600000 0x0 0x6200>; 1537 qcom,bcm-voters = <&apps_bcm_voter>; 1538 #interconnect-cells = <2>; 1539 }; 1540 1541 system_noc: interconnect@1680000 { 1542 compatible = "qcom,kaanapali-system-noc"; 1543 reg = <0x0 0x01680000 0x0 0x1f080>; 1544 qcom,bcm-voters = <&apps_bcm_voter>; 1545 #interconnect-cells = <2>; 1546 }; 1547 1548 pcie_noc: interconnect@16c0000 { 1549 compatible = "qcom,kaanapali-pcie-anoc"; 1550 reg = <0x0 0x016c0000 0x0 0x11400>; 1551 qcom,bcm-voters = <&apps_bcm_voter>; 1552 #interconnect-cells = <2>; 1553 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 1554 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 1555 }; 1556 1557 aggre_noc: interconnect@16e0000 { 1558 compatible = "qcom,kaanapali-aggre-noc"; 1559 reg = <0x0 0x016e0000 0x0 0x42400>; 1560 qcom,bcm-voters = <&apps_bcm_voter>; 1561 #interconnect-cells = <2>; 1562 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 1563 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, 1564 <&rpmhcc RPMH_IPA_CLK>; 1565 }; 1566 1567 cambistmclkcc: clock-controller@1760000 { 1568 compatible = "qcom,kaanapali-cambistmclkcc"; 1569 reg = <0x0 0x01760000 0x0 0x8000>; 1570 1571 clocks = <&gcc GCC_CAM_BIST_MCLK_AHB_CLK>, 1572 <&bi_tcxo_div2>, 1573 <&bi_tcxo_ao_div2>, 1574 <&sleep_clk>; 1575 1576 power-domains = <&rpmhpd RPMHPD_MMCX>, 1577 <&rpmhpd RPMHPD_MX>; 1578 required-opps = <&rpmhpd_opp_low_svs>, 1579 <&rpmhpd_opp_low_svs>; 1580 1581 #clock-cells = <1>; 1582 #reset-cells = <1>; 1583 }; 1584 1585 mmss_noc: interconnect@1780000 { 1586 compatible = "qcom,kaanapali-mmss-noc"; 1587 reg = <0x0 0x01780000 0x0 0x5b800>; 1588 qcom,bcm-voters = <&apps_bcm_voter>; 1589 #interconnect-cells = <2>; 1590 }; 1591 1592 gpi_dma3: dma-controller@1900000 { 1593 compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; 1594 reg = <0x0 0x01900000 0x0 0x60000>; 1595 1596 interrupts = <GIC_SPI 588 IRQ_TYPE_LEVEL_HIGH>, 1597 <GIC_SPI 589 IRQ_TYPE_LEVEL_HIGH>, 1598 <GIC_SPI 590 IRQ_TYPE_LEVEL_HIGH>, 1599 <GIC_SPI 591 IRQ_TYPE_LEVEL_HIGH>, 1600 <GIC_SPI 592 IRQ_TYPE_LEVEL_HIGH>, 1601 <GIC_SPI 593 IRQ_TYPE_LEVEL_HIGH>, 1602 <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH>, 1603 <GIC_SPI 595 IRQ_TYPE_LEVEL_HIGH>, 1604 <GIC_SPI 596 IRQ_TYPE_LEVEL_HIGH>, 1605 <GIC_SPI 597 IRQ_TYPE_LEVEL_HIGH>, 1606 <GIC_SPI 598 IRQ_TYPE_LEVEL_HIGH>, 1607 <GIC_SPI 599 IRQ_TYPE_LEVEL_HIGH>; 1608 1609 dma-channels = <12>; 1610 dma-channel-mask = <0x1e>; 1611 #dma-cells = <3>; 1612 1613 iommus = <&apps_smmu 0x4d6 0x0>; 1614 dma-coherent; 1615 }; 1616 1617 qupv3_3: geniqup@19c0000 { 1618 compatible = "qcom,geni-se-qup"; 1619 reg = <0x0 0x019c0000 0x0 0x2000>; 1620 1621 clocks = <&gcc GCC_QUPV3_WRAP_3_M_AHB_CLK>, 1622 <&gcc GCC_QUPV3_WRAP_3_S_AHB_CLK>; 1623 clock-names = "m-ahb", 1624 "s-ahb"; 1625 1626 iommus = <&apps_smmu 0x4c3 0x0>; 1627 1628 dma-coherent; 1629 1630 #address-cells = <2>; 1631 #size-cells = <2>; 1632 ranges; 1633 1634 i2c13: i2c@1980000 { 1635 compatible = "qcom,geni-i2c"; 1636 reg = <0x0 0x01980000 0x0 0x4000>; 1637 1638 interrupts = <GIC_SPI 373 IRQ_TYPE_LEVEL_HIGH>; 1639 1640 clocks = <&gcc GCC_QUPV3_WRAP3_S0_CLK>; 1641 clock-names = "se"; 1642 1643 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1644 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1645 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1646 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, 1647 <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1648 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1649 interconnect-names = "qup-core", 1650 "qup-config", 1651 "qup-memory"; 1652 1653 dmas = <&gpi_dma3 0 0 QCOM_GPI_I2C>, 1654 <&gpi_dma3 1 0 QCOM_GPI_I2C>; 1655 dma-names = "tx", 1656 "rx"; 1657 1658 pinctrl-0 = <&qup_i2c13_data_clk>; 1659 pinctrl-names = "default"; 1660 1661 #address-cells = <1>; 1662 #size-cells = <0>; 1663 1664 status = "disabled"; 1665 }; 1666 1667 i2c14: i2c@1984000 { 1668 compatible = "qcom,geni-i2c"; 1669 reg = <0x0 0x01984000 0x0 0x4000>; 1670 1671 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1672 1673 clocks = <&gcc GCC_QUPV3_WRAP3_S1_CLK>; 1674 clock-names = "se"; 1675 1676 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1677 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1678 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1679 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, 1680 <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1681 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1682 interconnect-names = "qup-core", 1683 "qup-config", 1684 "qup-memory"; 1685 1686 dmas = <&gpi_dma3 0 1 QCOM_GPI_I2C>, 1687 <&gpi_dma3 1 1 QCOM_GPI_I2C>; 1688 dma-names = "tx", 1689 "rx"; 1690 1691 pinctrl-0 = <&qup_i2c14_data_clk>; 1692 pinctrl-names = "default"; 1693 1694 #address-cells = <1>; 1695 #size-cells = <0>; 1696 1697 status = "disabled"; 1698 }; 1699 1700 spi14: spi@1984000 { 1701 compatible = "qcom,geni-spi"; 1702 reg = <0x0 0x01984000 0x0 0x4000>; 1703 1704 interrupts = <GIC_SPI 583 IRQ_TYPE_LEVEL_HIGH>; 1705 1706 clocks = <&gcc GCC_QUPV3_WRAP3_S1_CLK>; 1707 clock-names = "se"; 1708 1709 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1710 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1711 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1712 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; 1713 interconnect-names = "qup-core", 1714 "qup-config"; 1715 1716 dmas = <&gpi_dma3 0 1 QCOM_GPI_SPI>, 1717 <&gpi_dma3 1 1 QCOM_GPI_SPI>; 1718 dma-names = "tx", 1719 "rx"; 1720 1721 pinctrl-0 = <&qup_spi14_data_clk>, <&qup_spi14_cs>; 1722 pinctrl-names = "default"; 1723 1724 #address-cells = <1>; 1725 #size-cells = <0>; 1726 1727 status = "disabled"; 1728 }; 1729 1730 i2c15: i2c@1988000 { 1731 compatible = "qcom,geni-i2c"; 1732 reg = <0x0 0x01988000 0x0 0x4000>; 1733 1734 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1735 1736 clocks = <&gcc GCC_QUPV3_WRAP3_S2_CLK>; 1737 clock-names = "se"; 1738 1739 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1740 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1741 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1742 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, 1743 <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1744 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1745 interconnect-names = "qup-core", 1746 "qup-config", 1747 "qup-memory"; 1748 1749 dmas = <&gpi_dma3 0 2 QCOM_GPI_I2C>, 1750 <&gpi_dma3 1 2 QCOM_GPI_I2C>; 1751 dma-names = "tx", 1752 "rx"; 1753 1754 pinctrl-0 = <&qup_i2c15_data_clk>; 1755 pinctrl-names = "default"; 1756 1757 #address-cells = <1>; 1758 #size-cells = <0>; 1759 1760 status = "disabled"; 1761 }; 1762 1763 spi15: spi@1988000 { 1764 compatible = "qcom,geni-spi"; 1765 reg = <0x0 0x01988000 0x0 0x4000>; 1766 1767 interrupts = <GIC_SPI 584 IRQ_TYPE_LEVEL_HIGH>; 1768 1769 clocks = <&gcc GCC_QUPV3_WRAP3_S2_CLK>; 1770 clock-names = "se"; 1771 1772 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1773 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1774 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1775 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; 1776 interconnect-names = "qup-core", 1777 "qup-config"; 1778 1779 dmas = <&gpi_dma3 0 2 QCOM_GPI_SPI>, 1780 <&gpi_dma3 1 2 QCOM_GPI_SPI>; 1781 dma-names = "tx", 1782 "rx"; 1783 1784 pinctrl-0 = <&qup_spi15_data_clk>, <&qup_spi15_cs>; 1785 pinctrl-names = "default"; 1786 1787 #address-cells = <1>; 1788 #size-cells = <0>; 1789 1790 status = "disabled"; 1791 }; 1792 1793 i2c16: i2c@198c000 { 1794 compatible = "qcom,geni-i2c"; 1795 reg = <0x0 0x0198c000 0x0 0x4000>; 1796 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1797 1798 clocks = <&gcc GCC_QUPV3_WRAP3_S3_CLK>; 1799 clock-names = "se"; 1800 1801 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1802 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1803 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1804 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, 1805 <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1806 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1807 interconnect-names = "qup-core", 1808 "qup-config", 1809 "qup-memory"; 1810 1811 dmas = <&gpi_dma3 0 3 QCOM_GPI_I2C>, 1812 <&gpi_dma3 1 3 QCOM_GPI_I2C>; 1813 dma-names = "tx", 1814 "rx"; 1815 1816 pinctrl-0 = <&qup_i2c16_data_clk>; 1817 pinctrl-names = "default"; 1818 1819 #address-cells = <1>; 1820 #size-cells = <0>; 1821 1822 status = "disabled"; 1823 }; 1824 1825 spi16: spi@198c000 { 1826 compatible = "qcom,geni-spi"; 1827 reg = <0x0 0x198c000 0x0 0x4000>; 1828 1829 interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>; 1830 1831 clocks = <&gcc GCC_QUPV3_WRAP3_S3_CLK>; 1832 clock-names = "se"; 1833 1834 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 1835 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 1836 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1837 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 1838 interconnect-names = "qup-core", 1839 "qup-config"; 1840 1841 dmas = <&gpi_dma3 0 3 QCOM_GPI_SPI>, 1842 <&gpi_dma3 1 3 QCOM_GPI_SPI>; 1843 dma-names = "tx", 1844 "rx"; 1845 1846 pinctrl-0 = <&qup_spi16_data_clk>, <&qup_spi16_cs>; 1847 pinctrl-names = "default"; 1848 1849 #address-cells = <1>; 1850 #size-cells = <0>; 1851 1852 status = "disabled"; 1853 }; 1854 1855 i2c17: i2c@1990000 { 1856 compatible = "qcom,geni-i2c"; 1857 reg = <0x0 0x01990000 0x0 0x4000>; 1858 1859 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1860 1861 clocks = <&gcc GCC_QUPV3_WRAP3_S4_CLK>; 1862 clock-names = "se"; 1863 1864 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1865 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1866 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1867 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>, 1868 <&aggre_noc MASTER_QUP_3 QCOM_ICC_TAG_ALWAYS 1869 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1870 interconnect-names = "qup-core", 1871 "qup-config", 1872 "qup-memory"; 1873 1874 dmas = <&gpi_dma3 0 4 QCOM_GPI_I2C>, 1875 <&gpi_dma3 1 4 QCOM_GPI_I2C>; 1876 dma-names = "tx", 1877 "rx"; 1878 1879 pinctrl-0 = <&qup_i2c17_data_clk>; 1880 pinctrl-names = "default"; 1881 1882 #address-cells = <1>; 1883 #size-cells = <0>; 1884 1885 status = "disabled"; 1886 }; 1887 1888 spi17: spi@1990000 { 1889 compatible = "qcom,geni-spi"; 1890 reg = <0x0 0x01990000 0x0 0x4000>; 1891 1892 interrupts = <GIC_SPI 586 IRQ_TYPE_LEVEL_HIGH>; 1893 1894 clocks = <&gcc GCC_QUPV3_WRAP3_S4_CLK>; 1895 clock-names = "se"; 1896 1897 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1898 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1899 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1900 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; 1901 interconnect-names = "qup-core", 1902 "qup-config"; 1903 1904 dmas = <&gpi_dma3 0 4 QCOM_GPI_SPI>, 1905 <&gpi_dma3 1 4 QCOM_GPI_SPI>; 1906 dma-names = "tx", 1907 "rx"; 1908 1909 pinctrl-0 = <&qup_spi17_data_clk>, <&qup_spi17_cs>; 1910 pinctrl-names = "default"; 1911 1912 #address-cells = <1>; 1913 #size-cells = <0>; 1914 1915 status = "disabled"; 1916 }; 1917 1918 uart18: serial@1994000 { 1919 compatible = "qcom,geni-uart"; 1920 reg = <0x0 0x01994000 0x0 0x4000>; 1921 1922 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 1923 1924 clocks = <&gcc GCC_QUPV3_WRAP3_S5_CLK>; 1925 clock-names = "se"; 1926 1927 interconnects = <&clk_virt MASTER_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS 1928 &clk_virt SLAVE_QUP_CORE_3 QCOM_ICC_TAG_ALWAYS>, 1929 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1930 &config_noc SLAVE_QUP_3 QCOM_ICC_TAG_ACTIVE_ONLY>; 1931 interconnect-names = "qup-core", 1932 "qup-config"; 1933 1934 pinctrl-0 = <&qup_uart18_default>, <&qup_uart18_cts_rts>; 1935 pinctrl-names = "default"; 1936 1937 status = "disabled"; 1938 }; 1939 }; 1940 1941 gpi_dma4: dma-controller@1a00000 { 1942 compatible = "qcom,kaanapali-gpi-dma", "qcom,sm6350-gpi-dma"; 1943 reg = <0x0 0x01a00000 0x0 0x60000>; 1944 1945 interrupts = <GIC_SPI 504 IRQ_TYPE_LEVEL_HIGH>, 1946 <GIC_SPI 505 IRQ_TYPE_LEVEL_HIGH>, 1947 <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 1948 <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 1949 <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 1950 <GIC_SPI 509 IRQ_TYPE_LEVEL_HIGH>, 1951 <GIC_SPI 510 IRQ_TYPE_LEVEL_HIGH>, 1952 <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH>, 1953 <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH>, 1954 <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH>, 1955 <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH>, 1956 <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH>; 1957 1958 dma-channels = <12>; 1959 dma-channel-mask = <0x1e>; 1960 #dma-cells = <3>; 1961 1962 iommus = <&apps_smmu 0x536 0x0>; 1963 dma-coherent; 1964 }; 1965 1966 qupv3_4: geniqup@1ac0000 { 1967 compatible = "qcom,geni-se-qup"; 1968 reg = <0x0 0x01ac0000 0x0 0x2000>; 1969 1970 clocks = <&gcc GCC_QUPV3_WRAP_4_M_AHB_CLK>, 1971 <&gcc GCC_QUPV3_WRAP_4_S_AHB_CLK>; 1972 clock-names = "m-ahb", 1973 "s-ahb"; 1974 1975 iommus = <&apps_smmu 0x523 0x0>; 1976 1977 dma-coherent; 1978 1979 #address-cells = <2>; 1980 #size-cells = <2>; 1981 ranges; 1982 1983 i2c19: i2c@1a80000 { 1984 compatible = "qcom,geni-i2c"; 1985 reg = <0x0 0x01a80000 0x0 0x4000>; 1986 1987 interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; 1988 1989 clocks = <&gcc GCC_QUPV3_WRAP4_S0_CLK>; 1990 clock-names = "se"; 1991 1992 interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS 1993 &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, 1994 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 1995 &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, 1996 <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS 1997 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 1998 interconnect-names = "qup-core", 1999 "qup-config", 2000 "qup-memory"; 2001 2002 dmas = <&gpi_dma4 0 0 QCOM_GPI_I2C>, 2003 <&gpi_dma4 1 0 QCOM_GPI_I2C>; 2004 dma-names = "tx", 2005 "rx"; 2006 2007 pinctrl-0 = <&qup_i2c19_data_clk>; 2008 pinctrl-names = "default"; 2009 2010 #address-cells = <1>; 2011 #size-cells = <0>; 2012 2013 status = "disabled"; 2014 }; 2015 2016 spi19: spi@1a80000 { 2017 compatible = "qcom,geni-spi"; 2018 reg = <0x0 0x01a80000 0x0 0x4000>; 2019 2020 interrupts = <GIC_SPI 856 IRQ_TYPE_LEVEL_HIGH>; 2021 2022 clocks = <&gcc GCC_QUPV3_WRAP4_S0_CLK>; 2023 clock-names = "se"; 2024 2025 interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS 2026 &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, 2027 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2028 &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 2029 interconnect-names = "qup-core", 2030 "qup-config"; 2031 2032 dmas = <&gpi_dma4 0 0 QCOM_GPI_SPI>, 2033 <&gpi_dma4 1 0 QCOM_GPI_SPI>; 2034 dma-names = "tx", 2035 "rx"; 2036 2037 pinctrl-0 = <&qup_spi19_data_clk>, <&qup_spi19_cs>; 2038 pinctrl-names = "default"; 2039 2040 #address-cells = <1>; 2041 #size-cells = <0>; 2042 2043 status = "disabled"; 2044 }; 2045 2046 i2c20: i2c@1a84000 { 2047 compatible = "qcom,geni-i2c"; 2048 reg = <0x0 0x01a84000 0x0 0x4000>; 2049 2050 interrupts = <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>; 2051 2052 clocks = <&gcc GCC_QUPV3_WRAP4_S1_CLK>; 2053 clock-names = "se"; 2054 2055 interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS 2056 &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, 2057 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2058 &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, 2059 <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS 2060 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2061 interconnect-names = "qup-core", 2062 "qup-config", 2063 "qup-memory"; 2064 2065 dmas = <&gpi_dma4 0 1 QCOM_GPI_I2C>, 2066 <&gpi_dma4 1 1 QCOM_GPI_I2C>; 2067 dma-names = "tx", 2068 "rx"; 2069 2070 pinctrl-0 = <&qup_i2c20_data_clk>; 2071 pinctrl-names = "default"; 2072 2073 #address-cells = <1>; 2074 #size-cells = <0>; 2075 2076 status = "disabled"; 2077 }; 2078 2079 spi20: spi@1a84000 { 2080 compatible = "qcom,geni-spi"; 2081 reg = <0x0 0x01a84000 0x0 0x4000>; 2082 2083 interrupts = <GIC_SPI 857 IRQ_TYPE_LEVEL_HIGH>; 2084 2085 clocks = <&gcc GCC_QUPV3_WRAP4_S1_CLK>; 2086 clock-names = "se"; 2087 2088 interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS 2089 &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, 2090 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2091 &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 2092 interconnect-names = "qup-core", 2093 "qup-config"; 2094 2095 dmas = <&gpi_dma4 0 1 QCOM_GPI_SPI>, 2096 <&gpi_dma4 1 1 QCOM_GPI_SPI>; 2097 dma-names = "tx", 2098 "rx"; 2099 2100 pinctrl-0 = <&qup_spi20_data_clk>, <&qup_spi20_cs>; 2101 pinctrl-names = "default"; 2102 2103 #address-cells = <1>; 2104 #size-cells = <0>; 2105 2106 status = "disabled"; 2107 }; 2108 2109 i2c21: i2c@1a88000 { 2110 compatible = "qcom,geni-i2c"; 2111 reg = <0x0 0x01a88000 0x0 0x4000>; 2112 2113 interrupts = <GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 2114 2115 clocks = <&gcc GCC_QUPV3_WRAP4_S2_CLK>; 2116 clock-names = "se"; 2117 2118 interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS 2119 &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, 2120 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2121 &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, 2122 <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS 2123 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2124 interconnect-names = "qup-core", 2125 "qup-config", 2126 "qup-memory"; 2127 2128 dmas = <&gpi_dma4 0 2 QCOM_GPI_I2C>, 2129 <&gpi_dma4 1 2 QCOM_GPI_I2C>; 2130 dma-names = "tx", 2131 "rx"; 2132 2133 pinctrl-0 = <&qup_i2c21_data_clk>; 2134 pinctrl-names = "default"; 2135 2136 #address-cells = <1>; 2137 #size-cells = <0>; 2138 2139 status = "disabled"; 2140 }; 2141 2142 spi21: spi@1a88000 { 2143 compatible = "qcom,geni-spi"; 2144 reg = <0x0 0x01a88000 0x0 0x4000>; 2145 2146 interrupts = <GIC_SPI 858 IRQ_TYPE_LEVEL_HIGH>; 2147 2148 clocks = <&gcc GCC_QUPV3_WRAP4_S2_CLK>; 2149 clock-names = "se"; 2150 2151 interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS 2152 &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, 2153 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2154 &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>; 2155 interconnect-names = "qup-core", 2156 "qup-config"; 2157 2158 dmas = <&gpi_dma4 0 2 QCOM_GPI_SPI>, 2159 <&gpi_dma4 1 2 QCOM_GPI_SPI>; 2160 dma-names = "tx", 2161 "rx"; 2162 2163 pinctrl-0 = <&qup_spi21_data_clk>, <&qup_spi21_cs>; 2164 pinctrl-names = "default"; 2165 2166 #address-cells = <1>; 2167 #size-cells = <0>; 2168 2169 status = "disabled"; 2170 }; 2171 2172 i2c22: i2c@1a8c000 { 2173 compatible = "qcom,geni-i2c"; 2174 reg = <0x0 0x01a8c000 0x0 0x4000>; 2175 2176 interrupts = <GIC_SPI 859 IRQ_TYPE_LEVEL_HIGH>; 2177 2178 clocks = <&gcc GCC_QUPV3_WRAP4_S3_CLK>; 2179 clock-names = "se"; 2180 2181 interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS 2182 &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, 2183 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2184 &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, 2185 <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS 2186 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2187 interconnect-names = "qup-core", 2188 "qup-config", 2189 "qup-memory"; 2190 2191 dmas = <&gpi_dma4 0 3 QCOM_GPI_I2C>, 2192 <&gpi_dma4 1 3 QCOM_GPI_I2C>; 2193 dma-names = "tx", 2194 "rx"; 2195 2196 pinctrl-0 = <&qup_i2c22_data_clk>; 2197 pinctrl-names = "default"; 2198 2199 #address-cells = <1>; 2200 #size-cells = <0>; 2201 2202 status = "disabled"; 2203 }; 2204 2205 i2c23: i2c@1a90000 { 2206 compatible = "qcom,geni-i2c"; 2207 reg = <0x0 0x01a90000 0x0 0x4000>; 2208 2209 interrupts = <GIC_SPI 860 IRQ_TYPE_LEVEL_HIGH>; 2210 2211 clocks = <&gcc GCC_QUPV3_WRAP4_S4_CLK>; 2212 clock-names = "se"; 2213 2214 interconnects = <&clk_virt MASTER_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS 2215 &clk_virt SLAVE_QUP_CORE_4 QCOM_ICC_TAG_ALWAYS>, 2216 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2217 &config_noc SLAVE_QUP_4 QCOM_ICC_TAG_ACTIVE_ONLY>, 2218 <&aggre_noc MASTER_QUP_4 QCOM_ICC_TAG_ALWAYS 2219 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2220 interconnect-names = "qup-core", 2221 "qup-config", 2222 "qup-memory"; 2223 2224 dmas = <&gpi_dma4 0 4 QCOM_GPI_I2C>, 2225 <&gpi_dma4 1 4 QCOM_GPI_I2C>; 2226 dma-names = "tx", 2227 "rx"; 2228 2229 pinctrl-0 = <&qup_i2c23_data_clk>; 2230 pinctrl-names = "default"; 2231 2232 #address-cells = <1>; 2233 #size-cells = <0>; 2234 2235 status = "disabled"; 2236 }; 2237 }; 2238 2239 pcie0: pcie@1c00000 { 2240 device_type = "pci"; 2241 compatible = "qcom,kaanapali-pcie", "qcom,pcie-sm8550"; 2242 reg = <0x0 0x01c00000 0x0 0x3000>, 2243 <0x0 0x40000000 0x0 0xf1d>, 2244 <0x0 0x40000f20 0x0 0xa8>, 2245 <0x0 0x40001000 0x0 0x1000>, 2246 <0x0 0x40100000 0x0 0x100000>, 2247 <0x0 0x01c03000 0x0 0x1000>; 2248 reg-names = "parf", 2249 "dbi", 2250 "elbi", 2251 "atu", 2252 "config", 2253 "mhi"; 2254 #address-cells = <3>; 2255 #size-cells = <2>; 2256 ranges = <0x01000000 0x0 0x00000000 0x0 0x40200000 0x0 0x100000>, 2257 <0x02000000 0x0 0x40300000 0x0 0x40300000 0x0 0x23d00000>; 2258 2259 interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 2260 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 2261 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 2262 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 2263 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 2264 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 2265 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 2266 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 2267 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; 2268 interrupt-names = "msi0", 2269 "msi1", 2270 "msi2", 2271 "msi3", 2272 "msi4", 2273 "msi5", 2274 "msi6", 2275 "msi7", 2276 "global"; 2277 2278 clocks = <&gcc GCC_PCIE_0_AUX_CLK>, 2279 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2280 <&gcc GCC_PCIE_0_MSTR_AXI_CLK>, 2281 <&gcc GCC_PCIE_0_SLV_AXI_CLK>, 2282 <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>, 2283 <&gcc GCC_DDRSS_PCIE_SF_QTB_CLK>, 2284 <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 2285 <&gcc GCC_CNOC_PCIE_SF_AXI_CLK>; 2286 clock-names = "aux", 2287 "cfg", 2288 "bus_master", 2289 "bus_slave", 2290 "slave_q2a", 2291 "ddrss_sf_tbu", 2292 "noc_aggr", 2293 "cnoc_sf_axi"; 2294 2295 resets = <&gcc GCC_PCIE_0_BCR>, 2296 <&gcc GCC_PCIE_0_LINK_DOWN_BCR>; 2297 reset-names = "pci", 2298 "link_down"; 2299 2300 interconnects = <&pcie_noc MASTER_PCIE_0 QCOM_ICC_TAG_ALWAYS 2301 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2302 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2303 &cnoc_main SLAVE_PCIE_0 QCOM_ICC_TAG_ACTIVE_ONLY>; 2304 interconnect-names = "pcie-mem", 2305 "cpu-pcie"; 2306 2307 power-domains = <&gcc GCC_PCIE_0_GDSC>; 2308 2309 eq-presets-8gts = /bits/ 16 <0x5555 0x5555>; 2310 2311 operating-points-v2 = <&pcie0_opp_table>; 2312 2313 iommu-map = <0 &apps_smmu 0x1400 0x1>, 2314 <0x100 &apps_smmu 0x1401 0x1>; 2315 2316 interrupt-map = <0 0 0 1 &intc 0 0 0 149 IRQ_TYPE_LEVEL_HIGH>, 2317 <0 0 0 2 &intc 0 0 0 150 IRQ_TYPE_LEVEL_HIGH>, 2318 <0 0 0 3 &intc 0 0 0 151 IRQ_TYPE_LEVEL_HIGH>, 2319 <0 0 0 4 &intc 0 0 0 152 IRQ_TYPE_LEVEL_HIGH>; 2320 interrupt-map-mask = <0 0 0 0x7>; 2321 #interrupt-cells = <1>; 2322 2323 msi-map = <0x0 &gic_its 0x1400 0x1>, 2324 <0x100 &gic_its 0x1401 0x1>; 2325 msi-map-mask = <0xff00>; 2326 max-link-speed = <3>; 2327 linux,pci-domain = <0>; 2328 num-lanes = <2>; 2329 bus-range = <0x00 0xff>; 2330 2331 dma-coherent; 2332 2333 status = "disabled"; 2334 2335 pcie0_opp_table: opp-table { 2336 compatible = "operating-points-v2"; 2337 2338 /* GEN 1 x1 */ 2339 opp-2500000 { 2340 opp-hz = /bits/ 64 <2500000>; 2341 required-opps = <&rpmhpd_opp_low_svs>; 2342 opp-peak-kBps = <250000 1>; 2343 }; 2344 2345 /* GEN 1 x2 and GEN 2 x1 */ 2346 opp-5000000 { 2347 opp-hz = /bits/ 64 <5000000>; 2348 required-opps = <&rpmhpd_opp_low_svs>; 2349 opp-peak-kBps = <500000 1>; 2350 }; 2351 2352 /* GEN 2 x2 */ 2353 opp-10000000 { 2354 opp-hz = /bits/ 64 <10000000>; 2355 required-opps = <&rpmhpd_opp_low_svs>; 2356 opp-peak-kBps = <1000000 1>; 2357 }; 2358 2359 /* GEN 3 x1 */ 2360 opp-8000000 { 2361 opp-hz = /bits/ 64 <8000000>; 2362 required-opps = <&rpmhpd_opp_nom>; 2363 opp-peak-kBps = <984500 1>; 2364 }; 2365 2366 /* GEN 3 x2 */ 2367 opp-16000000 { 2368 opp-hz = /bits/ 64 <16000000>; 2369 required-opps = <&rpmhpd_opp_nom>; 2370 opp-peak-kBps = <1969000 1>; 2371 }; 2372 }; 2373 2374 pcie_port0: pcie@0 { 2375 device_type = "pci"; 2376 reg = <0x0 0x0 0x0 0x0 0x0>; 2377 bus-range = <0x01 0xff>; 2378 2379 #address-cells = <3>; 2380 #size-cells = <2>; 2381 ranges; 2382 phys = <&pcie0_phy>; 2383 }; 2384 }; 2385 2386 pcie0_phy: phy@1c06000 { 2387 compatible = "qcom,kaanapali-qmp-gen3x2-pcie-phy"; 2388 reg = <0x0 0x01c06000 0x0 0x2000>; 2389 2390 clocks = <&gcc GCC_PCIE_0_PHY_AUX_CLK>, 2391 <&gcc GCC_PCIE_0_CFG_AHB_CLK>, 2392 <&tcsr TCSR_PCIE_0_CLKREF_EN>, 2393 <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>, 2394 <&gcc GCC_PCIE_0_PIPE_CLK>; 2395 clock-names = "aux", 2396 "cfg_ahb", 2397 "ref", 2398 "rchng", 2399 "pipe"; 2400 2401 assigned-clocks = <&gcc GCC_PCIE_0_PHY_RCHNG_CLK>; 2402 assigned-clock-rates = <100000000>; 2403 2404 resets = <&gcc GCC_PCIE_0_PHY_BCR>, 2405 <&gcc GCC_PCIE_0_NOCSR_COM_PHY_BCR>; 2406 reset-names = "phy", 2407 "phy_nocsr"; 2408 2409 power-domains = <&gcc GCC_PCIE_0_PHY_GDSC>; 2410 2411 #clock-cells = <0>; 2412 clock-output-names = "pcie0_pipe_clk"; 2413 2414 #phy-cells = <0>; 2415 2416 status = "disabled"; 2417 }; 2418 2419 ufs_mem_phy: phy@1d80000 { 2420 compatible = "qcom,kaanapali-qmp-ufs-phy", "qcom,sm8750-qmp-ufs-phy"; 2421 reg = <0x0 0x01d80000 0x0 0x2000>; 2422 2423 clocks = <&rpmhcc RPMH_CXO_CLK>, 2424 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 2425 <&tcsr TCSR_UFS_CLKREF_EN>; 2426 2427 clock-names = "ref", 2428 "ref_aux", 2429 "qref"; 2430 2431 resets = <&ufs_mem_hc 0>; 2432 reset-names = "ufsphy"; 2433 2434 power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; 2435 2436 #clock-cells = <1>; 2437 #phy-cells = <0>; 2438 2439 status = "disabled"; 2440 }; 2441 2442 ufs_mem_hc: ufs@1d84000 { 2443 compatible = "qcom,kaanapali-ufshc", 2444 "qcom,ufshc", 2445 "jedec,ufs-2.0"; 2446 reg = <0x0 0x01d84000 0x0 0x3000>; 2447 2448 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 2449 2450 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 2451 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 2452 <&gcc GCC_UFS_PHY_AHB_CLK>, 2453 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 2454 <&rpmhcc RPMH_LN_BB_CLK3>, 2455 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 2456 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 2457 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 2458 clock-names = "core_clk", 2459 "bus_aggr_clk", 2460 "iface_clk", 2461 "core_clk_unipro", 2462 "ref_clk", 2463 "tx_lane0_sync_clk", 2464 "rx_lane0_sync_clk", 2465 "rx_lane1_sync_clk"; 2466 2467 operating-points-v2 = <&ufs_opp_table>; 2468 2469 resets = <&gcc GCC_UFS_PHY_BCR>; 2470 reset-names = "rst"; 2471 2472 interconnects = <&aggre_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 2473 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 2474 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 2475 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 2476 interconnect-names = "ufs-ddr", 2477 "cpu-ufs"; 2478 2479 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 2480 required-opps = <&rpmhpd_opp_nom>; 2481 2482 iommus = <&apps_smmu 0x60 0x0>; 2483 dma-coherent; 2484 2485 lanes-per-direction = <2>; 2486 qcom,ice = <&ice>; 2487 2488 phys = <&ufs_mem_phy>; 2489 phy-names = "ufsphy"; 2490 2491 #reset-cells = <1>; 2492 2493 status = "disabled"; 2494 2495 ufs_opp_table: opp-table { 2496 compatible = "operating-points-v2"; 2497 2498 opp-75000000 { 2499 opp-hz = /bits/ 64 <75000000>, 2500 /bits/ 64 <0>, 2501 /bits/ 64 <0>, 2502 /bits/ 64 <75000000>, 2503 /bits/ 64 <0>, 2504 /bits/ 64 <0>, 2505 /bits/ 64 <0>, 2506 /bits/ 64 <0>; 2507 required-opps = <&rpmhpd_opp_low_svs_d1>; 2508 }; 2509 2510 opp-100000000 { 2511 opp-hz = /bits/ 64 <100000000>, 2512 /bits/ 64 <0>, 2513 /bits/ 64 <0>, 2514 /bits/ 64 <100000000>, 2515 /bits/ 64 <0>, 2516 /bits/ 64 <0>, 2517 /bits/ 64 <0>, 2518 /bits/ 64 <0>; 2519 required-opps = <&rpmhpd_opp_low_svs>; 2520 }; 2521 2522 opp-403000000 { 2523 opp-hz = /bits/ 64 <403000000>, 2524 /bits/ 64 <0>, 2525 /bits/ 64 <0>, 2526 /bits/ 64 <403000000>, 2527 /bits/ 64 <0>, 2528 /bits/ 64 <0>, 2529 /bits/ 64 <0>, 2530 /bits/ 64 <0>; 2531 required-opps = <&rpmhpd_opp_nom>; 2532 }; 2533 }; 2534 }; 2535 2536 ice: crypto@1d88000 { 2537 compatible = "qcom,kaanapali-inline-crypto-engine", 2538 "qcom,inline-crypto-engine"; 2539 reg = <0x0 0x01d88000 0x0 0x18000>; 2540 2541 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>; 2542 }; 2543 2544 tcsr_mutex: hwlock@1f40000 { 2545 compatible = "qcom,tcsr-mutex"; 2546 reg = <0x0 0x01f40000 0x0 0x20000>; 2547 #hwlock-cells = <1>; 2548 }; 2549 2550 tcsr: clock-controller@1fc0000 { 2551 compatible = "qcom,kaanapali-tcsr", "syscon"; 2552 reg = <0x0 0x01fc0000 0x0 0x30000>; 2553 2554 clocks = <&rpmhcc RPMH_CXO_CLK>; 2555 2556 #clock-cells = <1>; 2557 #reset-cells = <1>; 2558 }; 2559 2560 videocc: clock-controller@20f0000 { 2561 compatible = "qcom,kaanapali-videocc"; 2562 reg = <0x0 0x020f0000 0x0 0x10000>; 2563 clocks = <&bi_tcxo_div2>, 2564 <&gcc GCC_VIDEO_AHB_CLK>; 2565 2566 power-domains = <&rpmhpd RPMHPD_MMCX>, 2567 <&rpmhpd RPMHPD_MXC>; 2568 required-opps = <&rpmhpd_opp_low_svs>, 2569 <&rpmhpd_opp_low_svs>; 2570 2571 #clock-cells = <1>; 2572 #reset-cells = <1>; 2573 #power-domain-cells = <1>; 2574 }; 2575 2576 gxclkctl: clock-controller@3d64000 { 2577 compatible = "qcom,kaanapali-gxclkctl"; 2578 reg = <0x0 0x03d64000 0x0 0x6000>; 2579 2580 power-domains = <&rpmhpd RPMHPD_GFX>, 2581 <&rpmhpd RPMHPD_GMXC>, 2582 <&gpucc GPU_CC_CX_GDSC>; 2583 2584 #power-domain-cells = <1>; 2585 }; 2586 2587 gpucc: clock-controller@3d90000 { 2588 compatible = "qcom,kaanapali-gpucc"; 2589 reg = <0x0 0x03d90000 0x0 0x9800>; 2590 2591 clocks = <&bi_tcxo_div2>, 2592 <&gcc GCC_GPU_GPLL0_CLK_SRC>, 2593 <&gcc GCC_GPU_GPLL0_DIV_CLK_SRC>; 2594 2595 #clock-cells = <1>; 2596 #reset-cells = <1>; 2597 #power-domain-cells = <1>; 2598 }; 2599 2600 remoteproc_adsp: remoteproc@6800000 { 2601 compatible = "qcom,kaanapali-adsp-pas", "qcom,sm8550-adsp-pas"; 2602 reg = <0x0 0x06800000 0x0 0x10000>; 2603 2604 interrupts-extended = <&pdc 6 IRQ_TYPE_EDGE_RISING>, 2605 <&smp2p_adsp_in 0 IRQ_TYPE_EDGE_RISING>, 2606 <&smp2p_adsp_in 1 IRQ_TYPE_EDGE_RISING>, 2607 <&smp2p_adsp_in 2 IRQ_TYPE_EDGE_RISING>, 2608 <&smp2p_adsp_in 3 IRQ_TYPE_EDGE_RISING>, 2609 <&smp2p_adsp_in 7 IRQ_TYPE_EDGE_RISING>; 2610 interrupt-names = "wdog", 2611 "fatal", 2612 "ready", 2613 "handover", 2614 "stop-ack", 2615 "shutdown-ack"; 2616 2617 clocks = <&rpmhcc RPMH_CXO_CLK>; 2618 clock-names = "xo"; 2619 2620 interconnects = <&lpass_lpicx_noc MASTER_LPASS_PROC QCOM_ICC_TAG_ALWAYS 2621 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 2622 2623 power-domains = <&rpmhpd RPMHPD_LCX>, 2624 <&rpmhpd RPMHPD_LMX>; 2625 power-domain-names = "lcx", 2626 "lmx"; 2627 2628 memory-region = <&adspslpi_mem>, <&q6_adsp_dtb_mem>; 2629 2630 qcom,qmp = <&aoss_qmp>; 2631 2632 qcom,smem-states = <&smp2p_adsp_out 0>; 2633 qcom,smem-state-names = "stop"; 2634 2635 status = "disabled"; 2636 2637 remoteproc_adsp_glink: glink-edge { 2638 interrupts-extended = <&ipcc IPCC_MPROC_LPASS 2639 IPCC_MPROC_SIGNAL_GLINK_QMP 2640 IRQ_TYPE_EDGE_RISING>; 2641 2642 mboxes = <&ipcc IPCC_MPROC_LPASS 2643 IPCC_MPROC_SIGNAL_GLINK_QMP>; 2644 2645 qcom,remote-pid = <2>; 2646 2647 label = "lpass"; 2648 2649 fastrpc { 2650 compatible = "qcom,kaanapali-fastrpc"; 2651 qcom,glink-channels = "fastrpcglink-apps-dsp"; 2652 label = "adsp"; 2653 #address-cells = <1>; 2654 #size-cells = <0>; 2655 2656 compute-cb@3 { 2657 compatible = "qcom,fastrpc-compute-cb"; 2658 reg = <3>; 2659 2660 iommus = <&apps_smmu 0x1003 0x80>, 2661 <&apps_smmu 0x1043 0x20>; 2662 dma-coherent; 2663 }; 2664 2665 compute-cb@4 { 2666 compatible = "qcom,fastrpc-compute-cb"; 2667 reg = <4>; 2668 2669 iommus = <&apps_smmu 0x1004 0x80>, 2670 <&apps_smmu 0x1044 0x20>; 2671 dma-coherent; 2672 }; 2673 2674 compute-cb@5 { 2675 compatible = "qcom,fastrpc-compute-cb"; 2676 reg = <5>; 2677 2678 iommus = <&apps_smmu 0x1005 0x80>, 2679 <&apps_smmu 0x1045 0x20>; 2680 dma-coherent; 2681 }; 2682 2683 compute-cb@6 { 2684 compatible = "qcom,fastrpc-compute-cb"; 2685 reg = <6>; 2686 2687 iommus = <&apps_smmu 0x1006 0x80>, 2688 <&apps_smmu 0x1046 0x20>; 2689 dma-coherent; 2690 }; 2691 2692 compute-cb@7 { 2693 compatible = "qcom,fastrpc-compute-cb"; 2694 reg = <7>; 2695 2696 iommus = <&apps_smmu 0x1007 0x40>, 2697 <&apps_smmu 0x1067 0x0>, 2698 <&apps_smmu 0x1087 0x0>; 2699 dma-coherent; 2700 }; 2701 }; 2702 2703 gpr { 2704 compatible = "qcom,gpr"; 2705 qcom,glink-channels = "adsp_apps"; 2706 qcom,domain = <GPR_DOMAIN_ID_ADSP>; 2707 qcom,intents = <512 20>; 2708 #address-cells = <1>; 2709 #size-cells = <0>; 2710 2711 q6apm: service@1 { 2712 compatible = "qcom,q6apm"; 2713 reg = <GPR_APM_MODULE_IID>; 2714 #sound-dai-cells = <0>; 2715 qcom,protection-domain = "avs/audio", 2716 "msm/adsp/audio_pd"; 2717 2718 q6apmbedai: bedais { 2719 compatible = "qcom,q6apm-lpass-dais"; 2720 #sound-dai-cells = <1>; 2721 }; 2722 2723 q6apmdai: dais { 2724 compatible = "qcom,q6apm-dais"; 2725 iommus = <&apps_smmu 0x1001 0x80>, 2726 <&apps_smmu 0x1041 0x20>; 2727 }; 2728 }; 2729 2730 q6prm: service@2 { 2731 compatible = "qcom,q6prm"; 2732 reg = <GPR_PRM_MODULE_IID>; 2733 qcom,protection-domain = "avs/audio", 2734 "msm/adsp/audio_pd"; 2735 2736 q6prmcc: clock-controller { 2737 compatible = "qcom,q6prm-lpass-clocks"; 2738 #clock-cells = <2>; 2739 }; 2740 }; 2741 }; 2742 }; 2743 }; 2744 2745 lpass_wsa2macro: codec@6aa0000 { 2746 compatible = "qcom,kaanapali-lpass-wsa-macro", 2747 "qcom,sm8550-lpass-wsa-macro"; 2748 reg = <0x0 0x06aa0000 0x0 0x1000>; 2749 clocks = <&q6prmcc LPASS_CLK_ID_WSA2_CORE_TX_MCLK 2750 LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2751 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2752 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2753 <&lpass_vamacro>; 2754 clock-names = "mclk", 2755 "macro", 2756 "dcodec", 2757 "fsgen"; 2758 2759 #clock-cells = <0>; 2760 clock-output-names = "wsa2-mclk"; 2761 #sound-dai-cells = <1>; 2762 }; 2763 2764 swr3: soundwire@6ab0000 { 2765 compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; 2766 reg = <0 0x06ab0000 0 0x10000>; 2767 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 2768 clocks = <&lpass_wsa2macro>; 2769 clock-names = "iface"; 2770 label = "WSA2"; 2771 2772 pinctrl-0 = <&wsa2_swr_active>; 2773 pinctrl-names = "default"; 2774 2775 qcom,din-ports = <4>; 2776 qcom,dout-ports = <9>; 2777 2778 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2779 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2780 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2781 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2782 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2783 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2784 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2785 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2786 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2787 2788 #address-cells = <2>; 2789 #size-cells = <0>; 2790 #sound-dai-cells = <1>; 2791 status = "disabled"; 2792 }; 2793 2794 lpass_rxmacro: codec@6ac0000 { 2795 compatible = "qcom,kaanapali-lpass-rx-macro", "qcom,sm8550-lpass-rx-macro"; 2796 reg = <0x0 0x06ac0000 0x0 0x1000>; 2797 clocks = <&q6prmcc LPASS_CLK_ID_RX_CORE_TX_MCLK 2798 LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2799 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2800 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2801 <&lpass_vamacro>; 2802 clock-names = "mclk", 2803 "macro", 2804 "dcodec", 2805 "fsgen"; 2806 2807 #clock-cells = <0>; 2808 clock-output-names = "mclk"; 2809 #sound-dai-cells = <1>; 2810 }; 2811 2812 swr1: soundwire@6ad0000 { 2813 compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; 2814 reg = <0 0x06ad0000 0 0x10000>; 2815 interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>; 2816 clocks = <&lpass_rxmacro>; 2817 clock-names = "iface"; 2818 label = "RX"; 2819 2820 pinctrl-0 = <&rx_swr_active>; 2821 pinctrl-names = "default"; 2822 2823 qcom,din-ports = <1>; 2824 qcom,dout-ports = <11>; 2825 2826 qcom,ports-sinterval = /bits/ 16 <0x03 0x3f 0x1f 0x07 0x00 0x18f 0xff 0xff 0xff 0xff 0xff 0xff>; 2827 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x0b 0x01 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2828 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x0b 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2829 qcom,ports-hstart = /bits/ 8 <0xff 0x03 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2830 qcom,ports-hstop = /bits/ 8 <0xff 0x06 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0xff>; 2831 qcom,ports-word-length = /bits/ 8 <0x01 0x07 0x04 0xff 0xff 0x0f 0xff 0xff 0xff 0xff 0xff 0xff>; 2832 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0x00 0x01 0xff 0xff 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2833 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2834 qcom,ports-lane-control = /bits/ 8 <0x01 0x00 0x00 0x00 0x00 0x00 0xff 0xff 0xff 0xff 0xff 0xff>; 2835 2836 #address-cells = <2>; 2837 #size-cells = <0>; 2838 #sound-dai-cells = <1>; 2839 status = "disabled"; 2840 }; 2841 2842 lpass_txmacro: codec@6ae0000 { 2843 compatible = "qcom,kaanapali-lpass-tx-macro", "qcom,sm8550-lpass-tx-macro"; 2844 reg = <0x0 0x06ae0000 0x0 0x1000>; 2845 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2846 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2847 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2848 <&lpass_vamacro>; 2849 clock-names = "mclk", 2850 "macro", 2851 "dcodec", 2852 "fsgen"; 2853 2854 #clock-cells = <0>; 2855 clock-output-names = "mclk"; 2856 #sound-dai-cells = <1>; 2857 }; 2858 2859 lpass_wsamacro: codec@6b00000 { 2860 compatible = "qcom,kaanapali-lpass-wsa-macro", 2861 "qcom,sm8550-lpass-wsa-macro"; 2862 reg = <0x0 0x06b00000 0x0 0x1000>; 2863 clocks = <&q6prmcc LPASS_CLK_ID_WSA_CORE_TX_MCLK 2864 LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2865 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2866 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2867 <&lpass_vamacro>; 2868 clock-names = "mclk", 2869 "macro", 2870 "dcodec", 2871 "fsgen"; 2872 2873 #clock-cells = <0>; 2874 clock-output-names = "mclk"; 2875 #sound-dai-cells = <1>; 2876 }; 2877 2878 swr0: soundwire@6b10000 { 2879 compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; 2880 reg = <0 0x06b10000 0 0x10000>; 2881 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 2882 clocks = <&lpass_wsamacro>; 2883 clock-names = "iface"; 2884 label = "WSA"; 2885 2886 pinctrl-0 = <&wsa_swr_active>; 2887 pinctrl-names = "default"; 2888 2889 qcom,din-ports = <4>; 2890 qcom,dout-ports = <9>; 2891 2892 qcom,ports-sinterval = /bits/ 16 <0x07 0x1f 0x3f 0x07 0x1f 0x3f 0x18f 0xff 0xff 0x0f 0x0f 0xff 0x31f>; 2893 qcom,ports-offset1 = /bits/ 8 <0x01 0x03 0x05 0x02 0x04 0x15 0x00 0xff 0xff 0x06 0x0d 0xff 0x00>; 2894 qcom,ports-offset2 = /bits/ 8 <0xff 0x07 0x1f 0xff 0x07 0x1f 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2895 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2896 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x0f>; 2897 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0x08 0xff 0xff 0xff 0xff 0xff 0x18>; 2898 qcom,ports-block-pack-mode = /bits/ 8 <0x00 0x01 0x01 0x00 0x01 0x01 0x00 0x00 0x00 0x01 0x01 0x00 0x00>; 2899 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2900 qcom,ports-lane-control = /bits/ 8 <0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff 0xff>; 2901 2902 #address-cells = <2>; 2903 #size-cells = <0>; 2904 #sound-dai-cells = <1>; 2905 status = "disabled"; 2906 }; 2907 2908 lpass_lpiaon_noc: interconnect@7400000 { 2909 compatible = "qcom,kaanapali-lpass-lpiaon-noc"; 2910 reg = <0x0 0x07400000 0x0 0x19080>; 2911 qcom,bcm-voters = <&apps_bcm_voter>; 2912 #interconnect-cells = <2>; 2913 }; 2914 2915 lpass_lpicx_noc: interconnect@7420000 { 2916 compatible = "qcom,kaanapali-lpass-lpicx-noc"; 2917 reg = <0x0 0x07420000 0x0 0x44080>; 2918 qcom,bcm-voters = <&apps_bcm_voter>; 2919 #interconnect-cells = <2>; 2920 }; 2921 2922 swr2: soundwire@7630000 { 2923 compatible = "qcom,soundwire-v2.2.0", "qcom,soundwire-v2.0.0"; 2924 reg = <0 0x07630000 0 0x10000>; 2925 interrupts-extended = <&intc GIC_SPI 761 IRQ_TYPE_LEVEL_HIGH>, 2926 <&pdc 40 IRQ_TYPE_LEVEL_HIGH>; 2927 interrupt-names = "core", "wakeup"; 2928 clocks = <&lpass_txmacro>; 2929 clock-names = "iface"; 2930 label = "TX"; 2931 2932 pinctrl-0 = <&tx_swr_active>; 2933 pinctrl-names = "default"; 2934 2935 qcom,din-ports = <4>; 2936 qcom,dout-ports = <0>; 2937 qcom,ports-sinterval-low = /bits/ 8 <0x01 0x01 0x03 0x03>; 2938 qcom,ports-offset1 = /bits/ 8 <0x00 0x00 0x01 0x01>; 2939 qcom,ports-offset2 = /bits/ 8 <0x00 0x00 0x00 0x00>; 2940 qcom,ports-hstart = /bits/ 8 <0xff 0xff 0xff 0xff>; 2941 qcom,ports-hstop = /bits/ 8 <0xff 0xff 0xff 0xff>; 2942 qcom,ports-word-length = /bits/ 8 <0xff 0xff 0xff 0xff>; 2943 qcom,ports-block-pack-mode = /bits/ 8 <0xff 0xff 0xff 0xff>; 2944 qcom,ports-block-group-count = /bits/ 8 <0xff 0xff 0xff 0xff>; 2945 qcom,ports-lane-control = /bits/ 8 <0x01 0x02 0x00 0x00>; 2946 2947 #address-cells = <2>; 2948 #size-cells = <0>; 2949 #sound-dai-cells = <1>; 2950 status = "disabled"; 2951 }; 2952 2953 lpass_vamacro: codec@7660000 { 2954 compatible = "qcom,kaanapali-lpass-va-macro", "qcom,sm8550-lpass-va-macro"; 2955 reg = <0 0x07660000 0 0x2000>; 2956 clocks = <&q6prmcc LPASS_CLK_ID_TX_CORE_MCLK LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2957 <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2958 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2959 clock-names = "mclk", "macro", "dcodec"; 2960 2961 #clock-cells = <0>; 2962 clock-output-names = "fsgen"; 2963 #sound-dai-cells = <1>; 2964 }; 2965 2966 lpass_tlmm: pinctrl@7760000 { 2967 compatible = "qcom,sm8750-lpass-lpi-pinctrl", 2968 "qcom,sm8650-lpass-lpi-pinctrl"; 2969 reg = <0 0x07760000 0 0x20000>; 2970 2971 clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, 2972 <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; 2973 clock-names = "core", "audio"; 2974 2975 gpio-controller; 2976 #gpio-cells = <2>; 2977 gpio-ranges = <&lpass_tlmm 0 0 23>; 2978 2979 tx_swr_active: tx-swr-active-state { 2980 clk-pins { 2981 pins = "gpio0"; 2982 function = "swr_tx_clk"; 2983 drive-strength = <2>; 2984 slew-rate = <1>; 2985 bias-disable; 2986 }; 2987 2988 data-pins { 2989 pins = "gpio1", "gpio2", "gpio14"; 2990 function = "swr_tx_data"; 2991 drive-strength = <2>; 2992 slew-rate = <1>; 2993 bias-bus-hold; 2994 }; 2995 }; 2996 2997 rx_swr_active: rx-swr-active-state { 2998 clk-pins { 2999 pins = "gpio3"; 3000 function = "swr_rx_clk"; 3001 drive-strength = <2>; 3002 slew-rate = <1>; 3003 bias-disable; 3004 }; 3005 3006 data-pins { 3007 pins = "gpio4", "gpio5"; 3008 function = "swr_rx_data"; 3009 drive-strength = <2>; 3010 slew-rate = <1>; 3011 bias-bus-hold; 3012 }; 3013 }; 3014 3015 dmic01_default: dmic01-default-state { 3016 clk-pins { 3017 pins = "gpio6"; 3018 function = "dmic1_clk"; 3019 drive-strength = <8>; 3020 output-high; 3021 }; 3022 3023 data-pins { 3024 pins = "gpio7"; 3025 function = "dmic1_data"; 3026 drive-strength = <8>; 3027 input-enable; 3028 }; 3029 }; 3030 3031 dmic23_default: dmic23-default-state { 3032 clk-pins { 3033 pins = "gpio8"; 3034 function = "dmic2_clk"; 3035 drive-strength = <8>; 3036 output-high; 3037 }; 3038 3039 data-pins { 3040 pins = "gpio9"; 3041 function = "dmic2_data"; 3042 drive-strength = <8>; 3043 input-enable; 3044 }; 3045 }; 3046 3047 wsa_swr_active: wsa-swr-active-state { 3048 clk-pins { 3049 pins = "gpio10"; 3050 function = "wsa_swr_clk"; 3051 drive-strength = <2>; 3052 slew-rate = <1>; 3053 bias-disable; 3054 }; 3055 3056 data-pins { 3057 pins = "gpio11"; 3058 function = "wsa_swr_data"; 3059 drive-strength = <2>; 3060 slew-rate = <1>; 3061 bias-bus-hold; 3062 }; 3063 }; 3064 3065 wsa2_swr_active: wsa2-swr-active-state { 3066 clk-pins { 3067 pins = "gpio15"; 3068 function = "wsa2_swr_clk"; 3069 drive-strength = <2>; 3070 slew-rate = <1>; 3071 bias-disable; 3072 }; 3073 3074 data-pins { 3075 pins = "gpio16"; 3076 function = "wsa2_swr_data"; 3077 drive-strength = <2>; 3078 slew-rate = <1>; 3079 bias-bus-hold; 3080 }; 3081 }; 3082 }; 3083 3084 lpass_ag_noc: interconnect@7f40000 { 3085 compatible = "qcom,kaanapali-lpass-ag-noc"; 3086 reg = <0x0 0x07f40000 0x0 0xe080>; 3087 qcom,bcm-voters = <&apps_bcm_voter>; 3088 #interconnect-cells = <2>; 3089 }; 3090 3091 sdhc_2: mmc@8804000 { 3092 compatible = "qcom,kaanapali-sdhci", "qcom,sdhci-msm-v5"; 3093 reg = <0x0 0x08804000 0x0 0x1000>; 3094 3095 interrupts = <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, 3096 <GIC_SPI 223 IRQ_TYPE_LEVEL_HIGH>; 3097 interrupt-names = "hc_irq", "pwr_irq"; 3098 3099 clocks = <&gcc GCC_SDCC2_AHB_CLK>, 3100 <&gcc GCC_SDCC2_APPS_CLK>, 3101 <&rpmhcc RPMH_CXO_CLK>; 3102 clock-names = "iface", "core", "xo"; 3103 3104 interconnects = <&aggre_noc MASTER_SDCC_2 QCOM_ICC_TAG_ALWAYS 3105 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3106 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3107 &config_noc SLAVE_SDCC_2 QCOM_ICC_TAG_ACTIVE_ONLY>; 3108 interconnect-names = "sdhc-ddr", "cpu-sdhc"; 3109 3110 power-domains = <&rpmhpd RPMHPD_CX>; 3111 operating-points-v2 = <&sdhc2_opp_table>; 3112 3113 qcom,dll-config = <0x0007442c>; 3114 qcom,ddr-config = <0x80040868>; 3115 3116 iommus = <&apps_smmu 0x540 0x0>; 3117 dma-coherent; 3118 3119 resets = <&gcc GCC_SDCC2_BCR>; 3120 status = "disabled"; 3121 3122 sdhc2_opp_table: opp-table { 3123 compatible = "operating-points-v2"; 3124 3125 opp-100000000 { 3126 opp-hz = /bits/ 64 <100000000>; 3127 opp-peak-kBps = <160000 100000>; 3128 opp-avg-kBps = <50000 0>; 3129 required-opps = <&rpmhpd_opp_nom>; 3130 }; 3131 3132 opp-202000000 { 3133 opp-hz = /bits/ 64 <202000000>; 3134 opp-peak-kBps = <200000 120000>; 3135 opp-avg-kBps = <104000 0>; 3136 required-opps = <&rpmhpd_opp_nom>; 3137 }; 3138 }; 3139 }; 3140 3141 camcc: clock-controller@956d000 { 3142 compatible = "qcom,kaanapali-camcc"; 3143 reg = <0x0 0x0956d000 0x0 0x80000>; 3144 3145 clocks = <&gcc GCC_CAMERA_AHB_CLK>, 3146 <&bi_tcxo_div2>, 3147 <&bi_tcxo_ao_div2>, 3148 <&sleep_clk>; 3149 3150 power-domains = <&rpmhpd RPMHPD_MMCX>, 3151 <&rpmhpd RPMHPD_MXC>; 3152 required-opps = <&rpmhpd_opp_low_svs>, 3153 <&rpmhpd_opp_low_svs>; 3154 3155 #clock-cells = <1>; 3156 #reset-cells = <1>; 3157 #power-domain-cells = <1>; 3158 }; 3159 3160 mdss: display-subsystem@9800000 { 3161 compatible = "qcom,kaanapali-mdss"; 3162 reg = <0x0 0x09800000 0x0 0x1000>; 3163 reg-names = "mdss"; 3164 3165 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; 3166 3167 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3168 <&gcc GCC_DISP_HF_AXI_CLK>, 3169 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3170 <&dispcc DISP_CC_MDSS_AHB_SWI_CLK>; 3171 resets = <&dispcc DISP_CC_MDSS_CORE_BCR>; 3172 3173 interconnects = <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS 3174 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 3175 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 3176 &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 3177 interconnect-names = "mdp0-mem", 3178 "cpu-cfg"; 3179 3180 power-domains = <&dispcc DISP_CC_MDSS_CORE_GDSC>; 3181 3182 iommus = <&apps_smmu 0x800 0x2>; 3183 3184 interrupt-controller; 3185 #interrupt-cells = <1>; 3186 3187 #address-cells = <2>; 3188 #size-cells = <2>; 3189 ranges; 3190 3191 status = "disabled"; 3192 3193 mdss_mdp: display-controller@9801000 { 3194 compatible = "qcom,kaanapali-dpu"; 3195 reg = <0x0 0x09801000 0x0 0x1c8000>, 3196 <0x0 0x09b16000 0x0 0x3000>; 3197 reg-names = "mdp", 3198 "vbif"; 3199 3200 interrupts-extended = <&mdss 0>; 3201 3202 clocks = <&gcc GCC_DISP_HF_AXI_CLK>, 3203 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3204 <&dispcc DISP_CC_MDSS_MDP_LUT_CLK>, 3205 <&dispcc DISP_CC_MDSS_MDP_CLK>, 3206 <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3207 clock-names = "nrt_bus", 3208 "iface", 3209 "lut", 3210 "core", 3211 "vsync"; 3212 3213 assigned-clocks = <&dispcc DISP_CC_MDSS_VSYNC_CLK>; 3214 assigned-clock-rates = <19200000>; 3215 3216 operating-points-v2 = <&mdp_opp_table>; 3217 3218 power-domains = <&rpmhpd RPMHPD_MMCX>; 3219 3220 ports { 3221 #address-cells = <1>; 3222 #size-cells = <0>; 3223 3224 port@0 { 3225 reg = <0>; 3226 3227 dpu_intf1_out: endpoint { 3228 remote-endpoint = <&mdss_dsi0_in>; 3229 }; 3230 }; 3231 3232 port@1 { 3233 reg = <1>; 3234 3235 dpu_intf2_out: endpoint { 3236 }; 3237 }; 3238 3239 port@2 { 3240 reg = <2>; 3241 3242 dpu_intf0_out: endpoint { 3243 }; 3244 }; 3245 }; 3246 3247 mdp_opp_table: opp-table { 3248 compatible = "operating-points-v2"; 3249 3250 opp-156000000 { 3251 opp-hz = /bits/ 64 <156000000>; 3252 required-opps = <&rpmhpd_opp_low_svs_d1>; 3253 }; 3254 3255 opp-207000000 { 3256 opp-hz = /bits/ 64 <207000000>; 3257 required-opps = <&rpmhpd_opp_low_svs>; 3258 }; 3259 3260 opp-337000000 { 3261 opp-hz = /bits/ 64 <337000000>; 3262 required-opps = <&rpmhpd_opp_svs>; 3263 }; 3264 3265 opp-417000000 { 3266 opp-hz = /bits/ 64 <417000000>; 3267 required-opps = <&rpmhpd_opp_svs_l1>; 3268 }; 3269 3270 opp-532000000 { 3271 opp-hz = /bits/ 64 <532000000>; 3272 required-opps = <&rpmhpd_opp_nom>; 3273 }; 3274 3275 opp-600000000 { 3276 opp-hz = /bits/ 64 <600000000>; 3277 required-opps = <&rpmhpd_opp_nom_l1>; 3278 }; 3279 3280 opp-650000000 { 3281 opp-hz = /bits/ 64 <650000000>; 3282 required-opps = <&rpmhpd_opp_turbo>; 3283 }; 3284 }; 3285 }; 3286 3287 mdss_dsi0: dsi@9ac0000 { 3288 compatible = "qcom,kaanapali-dsi-ctrl", "qcom,mdss-dsi-ctrl"; 3289 reg = <0x0 0x09ac0000 0x0 0x1000>; 3290 reg-names = "dsi_ctrl"; 3291 3292 interrupts-extended = <&mdss 4>; 3293 3294 clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK>, 3295 <&dispcc DISP_CC_MDSS_BYTE0_INTF_CLK>, 3296 <&dispcc DISP_CC_MDSS_PCLK0_CLK>, 3297 <&dispcc DISP_CC_MDSS_ESC0_CLK>, 3298 <&dispcc DISP_CC_MDSS_AHB_CLK>, 3299 <&gcc GCC_DISP_HF_AXI_CLK>, 3300 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3301 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3302 <&dispcc DISP_CC_ESYNC0_CLK>, 3303 <&dispcc DISP_CC_OSC_CLK>, 3304 <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, 3305 <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; 3306 clock-names = "byte", 3307 "byte_intf", 3308 "pixel", 3309 "core", 3310 "iface", 3311 "bus", 3312 "dsi_pll_pixel", 3313 "dsi_pll_byte", 3314 "esync", 3315 "osc", 3316 "byte_src", 3317 "pixel_src"; 3318 3319 operating-points-v2 = <&mdss_dsi_opp_table>; 3320 3321 power-domains = <&rpmhpd RPMHPD_MMCX>; 3322 3323 phys = <&mdss_dsi0_phy>; 3324 phy-names = "dsi"; 3325 3326 #address-cells = <1>; 3327 #size-cells = <0>; 3328 3329 status = "disabled"; 3330 3331 ports { 3332 #address-cells = <1>; 3333 #size-cells = <0>; 3334 3335 port@0 { 3336 reg = <0>; 3337 3338 mdss_dsi0_in: endpoint { 3339 remote-endpoint = <&dpu_intf1_out>; 3340 }; 3341 }; 3342 3343 port@1 { 3344 reg = <1>; 3345 3346 mdss_dsi0_out: endpoint { 3347 }; 3348 }; 3349 }; 3350 3351 mdss_dsi_opp_table: opp-table { 3352 compatible = "operating-points-v2"; 3353 3354 opp-187500000 { 3355 opp-hz = /bits/ 64 <187500000>; 3356 required-opps = <&rpmhpd_opp_low_svs_d1>; 3357 }; 3358 3359 opp-250000000 { 3360 opp-hz = /bits/ 64 <250000000>; 3361 required-opps = <&rpmhpd_opp_low_svs>; 3362 }; 3363 3364 opp-312500000 { 3365 opp-hz = /bits/ 64 <312500000>; 3366 required-opps = <&rpmhpd_opp_svs>; 3367 }; 3368 3369 opp-358000000 { 3370 opp-hz = /bits/ 64 <358000000>; 3371 required-opps = <&rpmhpd_opp_svs_l1>; 3372 }; 3373 }; 3374 }; 3375 3376 mdss_dsi0_phy: phy@9ac1000 { 3377 compatible = "qcom,kaanapali-dsi-phy-3nm"; 3378 reg = <0x0 0x09ac1000 0x0 0x1cc>, 3379 <0x0 0x09ac1200 0x0 0x280>, 3380 <0x0 0x09ac1500 0x0 0x400>; 3381 reg-names = "dsi_phy", 3382 "dsi_phy_lane", 3383 "dsi_pll"; 3384 3385 clocks = <&dispcc DISP_CC_MDSS_AHB_CLK>, 3386 <&rpmhcc RPMH_CXO_CLK>; 3387 clock-names = "iface", 3388 "ref"; 3389 3390 #clock-cells = <1>; 3391 #phy-cells = <0>; 3392 3393 status = "disabled"; 3394 }; 3395 }; 3396 3397 dispcc: clock-controller@9ba2000 { 3398 compatible = "qcom,kaanapali-dispcc"; 3399 reg = <0x0 0x09ba2000 0x0 0x20000>; 3400 clocks = <&bi_tcxo_div2>, 3401 <&bi_tcxo_ao_div2>, 3402 <&gcc GCC_DISP_AHB_CLK>, 3403 <&sleep_clk>, 3404 <0>, 3405 <0>, 3406 <0>, 3407 <0>, 3408 <0>, 3409 <0>, 3410 <0>, 3411 <0>, 3412 <&mdss_dsi0_phy DSI_BYTE_PLL_CLK>, 3413 <&mdss_dsi0_phy DSI_PIXEL_PLL_CLK>, 3414 <0>, 3415 <0>; 3416 3417 power-domains = <&rpmhpd RPMHPD_MMCX>; 3418 required-opps = <&rpmhpd_opp_low_svs>; 3419 3420 #clock-cells = <1>; 3421 #power-domain-cells = <1>; 3422 #reset-cells = <1>; 3423 }; 3424 3425 pdc: interrupt-controller@b220000 { 3426 compatible = "qcom,kaanapali-pdc", "qcom,pdc"; 3427 reg = <0x0 0x0b220000 0x0 0x10000>, 3428 <0x0 0x179600f0 0x0 0xf4>; 3429 3430 qcom,pdc-ranges = <0 745 38>, 3431 <40 785 11>, 3432 <51 527 4>, 3433 <58 534 2>, 3434 <61 537 20>, 3435 <84 559 14>, 3436 <98 609 32>, 3437 <130 717 12>, 3438 <142 251 5>, 3439 <147 796 16>, 3440 <163 783 2>, 3441 <165 531 2>, 3442 <167 536 1>, 3443 <168 557 2>, 3444 <170 415 1>, 3445 <171 438 1>, 3446 <172 579 1>, 3447 <173 703 1>, 3448 <174 708 1>, 3449 <175 714 1>, 3450 <176 68 1>, 3451 <177 86 1>, 3452 <178 96 1>, 3453 <179 249 1>; 3454 #interrupt-cells = <2>; 3455 interrupt-parent = <&intc>; 3456 interrupt-controller; 3457 }; 3458 3459 tsens0: thermal-sensor@c229000 { 3460 compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; 3461 reg = <0x0 0x0c229000 0x0 0x1000>, 3462 <0x0 0x0c222000 0x0 0x1000>; 3463 interrupts = <GIC_SPI 771 IRQ_TYPE_LEVEL_HIGH>, 3464 <GIC_SPI 484 IRQ_TYPE_LEVEL_HIGH>; 3465 interrupt-names = "uplow", 3466 "critical"; 3467 #qcom,sensors = <5>; 3468 #thermal-sensor-cells = <1>; 3469 }; 3470 3471 tsens1: thermal-sensor@c22a000 { 3472 compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; 3473 reg = <0x0 0x0c22a000 0x0 0x1000>, 3474 <0x0 0x0c223000 0x0 0x1000>; 3475 interrupts = <GIC_SPI 772 IRQ_TYPE_LEVEL_HIGH>, 3476 <GIC_SPI 485 IRQ_TYPE_LEVEL_HIGH>; 3477 interrupt-names = "uplow", 3478 "critical"; 3479 #qcom,sensors = <12>; 3480 #thermal-sensor-cells = <1>; 3481 }; 3482 3483 tsens2: thermal-sensor@c22b000 { 3484 compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; 3485 reg = <0x0 0x0c22b000 0x0 0x1000>, 3486 <0x0 0x0c224000 0x0 0x1000>; 3487 interrupts = <GIC_SPI 773 IRQ_TYPE_LEVEL_HIGH>, 3488 <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>; 3489 interrupt-names = "uplow", 3490 "critical"; 3491 #qcom,sensors = <7>; 3492 #thermal-sensor-cells = <1>; 3493 }; 3494 3495 tsens3: thermal-sensor@c22c000 { 3496 compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; 3497 reg = <0x0 0x0c22c000 0x0 0x1000>, 3498 <0x0 0x0c225000 0x0 0x1000>; 3499 interrupts = <GIC_SPI 774 IRQ_TYPE_LEVEL_HIGH>, 3500 <GIC_SPI 487 IRQ_TYPE_LEVEL_HIGH>; 3501 interrupt-names = "uplow", 3502 "critical"; 3503 #qcom,sensors = <4>; 3504 #thermal-sensor-cells = <1>; 3505 }; 3506 3507 tsens4: thermal-sensor@c22d000 { 3508 compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; 3509 reg = <0x0 0x0c22d000 0x0 0x1000>, 3510 <0x0 0x0c226000 0x0 0x1000>; 3511 interrupts = <GIC_SPI 543 IRQ_TYPE_LEVEL_HIGH>, 3512 <GIC_SPI 461 IRQ_TYPE_LEVEL_HIGH>; 3513 interrupt-names = "uplow", 3514 "critical"; 3515 #qcom,sensors = <8>; 3516 #thermal-sensor-cells = <1>; 3517 }; 3518 3519 tsens5: thermal-sensor@c22e000 { 3520 compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; 3521 reg = <0x0 0x0c22e000 0x0 0x1000>, 3522 <0x0 0x0c227000 0x0 0x1000>; 3523 interrupts = <GIC_SPI 544 IRQ_TYPE_LEVEL_HIGH>, 3524 <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH>; 3525 interrupt-names = "uplow", 3526 "critical"; 3527 #qcom,sensors = <12>; 3528 #thermal-sensor-cells = <1>; 3529 }; 3530 3531 tsens6: thermal-sensor@c22f000 { 3532 compatible = "qcom,kaanapali-tsens", "qcom,tsens-v2"; 3533 reg = <0x0 0x0c22f000 0x0 0x1000>, 3534 <0x0 0x0c228000 0x0 0x1000>; 3535 interrupts = <GIC_SPI 545 IRQ_TYPE_LEVEL_HIGH>, 3536 <GIC_SPI 474 IRQ_TYPE_LEVEL_HIGH>; 3537 interrupt-names = "uplow", 3538 "critical"; 3539 #qcom,sensors = <7>; 3540 #thermal-sensor-cells = <1>; 3541 }; 3542 3543 aoss_qmp: power-management@c300000 { 3544 compatible = "qcom,kaanapali-aoss-qmp", "qcom,aoss-qmp"; 3545 reg = <0x0 0x0c300000 0x0 0x400>; 3546 3547 interrupts-extended = <&ipcc IPCC_MPROC_AOP 3548 IPCC_MPROC_SIGNAL_GLINK_QMP 3549 IRQ_TYPE_EDGE_RISING>; 3550 3551 mboxes = <&ipcc IPCC_MPROC_AOP 3552 IPCC_MPROC_SIGNAL_GLINK_QMP>; 3553 3554 #clock-cells = <0>; 3555 }; 3556 3557 arbiter@c400000 { 3558 compatible = "qcom,kaanapali-spmi-pmic-arb", "qcom,glymur-spmi-pmic-arb"; 3559 reg = <0x0 0x0c400000 0x0 0x3000>, 3560 <0x0 0x0c900000 0x0 0x400000>, 3561 <0x0 0x0c4c0000 0x0 0x400000>, 3562 <0x0 0x0c403000 0x0 0x8000>; 3563 reg-names = "core", 3564 "chnls", 3565 "obsrvr", 3566 "chnl_map"; 3567 #address-cells = <2>; 3568 #size-cells = <2>; 3569 ranges; 3570 qcom,channel = <0>; 3571 qcom,ee = <0>; 3572 3573 spmi_bus0: spmi@c426000 { 3574 reg = <0x0 0x0c426000 0x0 0x4000>, 3575 <0x0 0x0c8c0000 0x0 0x10000>, 3576 <0x0 0x0c42a000 0x0 0x8000>; 3577 reg-names = "cnfg", 3578 "intr", 3579 "chnl_owner"; 3580 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 3581 interrupt-names = "periph_irq"; 3582 interrupt-controller; 3583 #interrupt-cells = <4>; 3584 #address-cells = <2>; 3585 #size-cells = <0>; 3586 }; 3587 3588 spmi_bus1: spmi@c437000 { 3589 reg = <0x0 0x0c437000 0x0 0x4000>, 3590 <0x0 0x0c8d0000 0x0 0x10000>, 3591 <0x0 0x0c43b000 0x0 0x8000>; 3592 reg-names = "cnfg", 3593 "intr", 3594 "chnl_owner"; 3595 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 3596 interrupt-names = "periph_irq"; 3597 interrupt-controller; 3598 #interrupt-cells = <4>; 3599 #address-cells = <2>; 3600 #size-cells = <0>; 3601 }; 3602 }; 3603 3604 tlmm: pinctrl@f100000 { 3605 compatible = "qcom,kaanapali-tlmm"; 3606 reg = <0x0 0x0f100000 0x0 0x300000>; 3607 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 3608 gpio-controller; 3609 #gpio-cells = <2>; 3610 gpio-ranges = <&tlmm 0 0 218>; 3611 interrupt-controller; 3612 #interrupt-cells = <2>; 3613 wakeup-parent = <&pdc>; 3614 3615 hub_i2c0_data_clk: hub-i2c0-data-clk-state { 3616 /* SDA, SCL */ 3617 pins = "gpio66", "gpio67"; 3618 function = "i2chub0_se0"; 3619 drive-strength = <2>; 3620 bias-pull-up; 3621 }; 3622 3623 hub_i2c1_data_clk: hub-i2c1-data-clk-state { 3624 /* SDA, SCL */ 3625 pins = "gpio78", "gpio79"; 3626 function = "i2chub0_se1"; 3627 drive-strength = <2>; 3628 bias-pull-up; 3629 }; 3630 3631 hub_i2c2_data_clk: hub-i2c2-data-clk-state { 3632 /* SDA, SCL */ 3633 pins = "gpio68", "gpio69"; 3634 function = "i2chub0_se2"; 3635 drive-strength = <2>; 3636 bias-pull-up; 3637 }; 3638 3639 hub_i2c3_data_clk: hub-i2c3-data-clk-state { 3640 /* SDA, SCL */ 3641 pins = "gpio70", "gpio71"; 3642 function = "i2chub0_se3"; 3643 drive-strength = <2>; 3644 bias-pull-up; 3645 }; 3646 3647 hub_i2c4_data_clk: hub-i2c4-data-clk-state { 3648 /* SDA, SCL */ 3649 pins = "gpio72", "gpio73"; 3650 function = "i2chub0_se4"; 3651 drive-strength = <2>; 3652 bias-pull-up; 3653 }; 3654 3655 qup_i2c0_data_clk: qup-i2c0-data-clk-state { 3656 /* SDA, SCL */ 3657 pins = "gpio80", "gpio83"; 3658 function = "qup1_se0"; 3659 drive-strength = <2>; 3660 bias-pull-up; 3661 }; 3662 3663 qup_i2c1_data_clk: qup-i2c1-data-clk-state { 3664 /* SDA, SCL */ 3665 pins = "gpio74", "gpio75"; 3666 function = "qup1_se1"; 3667 drive-strength = <2>; 3668 bias-pull-up; 3669 }; 3670 3671 qup_i2c2_data_clk: qup-i2c2-data-clk-state { 3672 /* SDA, SCL */ 3673 pins = "gpio40", "gpio41"; 3674 function = "qup1_se2"; 3675 drive-strength = <2>; 3676 bias-pull-up; 3677 }; 3678 3679 qup_i2c3_data_clk: qup-i2c3-data-clk-state { 3680 /* SDA, SCL */ 3681 pins = "gpio44", "gpio45"; 3682 function = "qup1_se3"; 3683 drive-strength = <2>; 3684 bias-pull-up; 3685 }; 3686 3687 qup_i2c4_data_clk: qup-i2c4-data-clk-state { 3688 /* SDA, SCL */ 3689 pins = "gpio36", "gpio37"; 3690 function = "qup1_se4"; 3691 drive-strength = <2>; 3692 bias-pull-up; 3693 }; 3694 3695 qup_i2c5_data_clk: qup-i2c5-data-clk-state { 3696 /* SDA, SCL */ 3697 pins = "gpio52", "gpio53"; 3698 function = "qup1_se5"; 3699 drive-strength = <2>; 3700 bias-pull-up; 3701 }; 3702 3703 qup_i2c6_data_clk: qup-i2c6-data-clk-state { 3704 /* SDA, SCL */ 3705 pins = "gpio56", "gpio57"; 3706 function = "qup1_se6"; 3707 drive-strength = <2>; 3708 bias-pull-up; 3709 }; 3710 3711 qup_i2c8_data_clk: qup-i2c8-data-clk-state { 3712 /* SDA, SCL */ 3713 pins = "gpio0", "gpio1"; 3714 function = "qup2_se0"; 3715 drive-strength = <2>; 3716 bias-pull-up; 3717 }; 3718 3719 qup_i2c9_data_clk: qup-i2c9-data-clk-state { 3720 /* SDA, SCL */ 3721 pins = "gpio4", "gpio5"; 3722 function = "qup2_se1"; 3723 drive-strength = <2>; 3724 bias-pull-up; 3725 }; 3726 3727 qup_i2c10_data_clk: qup-i2c10-data-clk-state { 3728 /* SDA, SCL */ 3729 pins = "gpio117", "gpio118"; 3730 function = "qup2_se2"; 3731 drive-strength = <2>; 3732 bias-pull-up; 3733 }; 3734 3735 qup_i2c11_data_clk: qup-i2c11-data-clk-state { 3736 /* SDA, SCL */ 3737 pins = "gpio122", "gpio123"; 3738 function = "qup2_se3"; 3739 drive-strength = <2>; 3740 bias-pull-up; 3741 }; 3742 3743 qup_i2c12_data_clk: qup-i2c12-data-clk-state { 3744 /* SDA, SCL */ 3745 pins = "gpio208", "gpio209"; 3746 function = "qup2_se4"; 3747 drive-strength = <2>; 3748 bias-pull-up; 3749 }; 3750 3751 qup_i2c13_data_clk: qup-i2c13-data-clk-state { 3752 /* SDA, SCL */ 3753 pins = "gpio64", "gpio65"; 3754 function = "qup3_se0"; 3755 drive-strength = <2>; 3756 bias-pull-up; 3757 }; 3758 3759 qup_i2c14_data_clk: qup-i2c14-data-clk-state { 3760 /* SDA, SCL */ 3761 pins = "gpio8", "gpio9"; 3762 function = "qup3_se1"; 3763 drive-strength = <2>; 3764 bias-pull-up; 3765 }; 3766 3767 qup_i2c15_data_clk: qup-i2c15-data-clk-state { 3768 /* SDA, SCL */ 3769 pins = "gpio12", "gpio13"; 3770 function = "qup3_se2"; 3771 drive-strength = <2>; 3772 bias-pull-up; 3773 }; 3774 3775 qup_i2c16_data_clk: qup-i2c16-data-clk-state { 3776 /* SDA, SCL */ 3777 pins = "gpio16", "gpio17"; 3778 function = "qup3_se3"; 3779 drive-strength = <2>; 3780 bias-pull-up; 3781 }; 3782 3783 qup_i2c17_data_clk: qup-i2c17-data-clk-state { 3784 /* SDA, SCL */ 3785 pins = "gpio20", "gpio21"; 3786 function = "qup3_se4"; 3787 drive-strength = <2>; 3788 bias-pull-up; 3789 }; 3790 3791 qup_i2c19_data_clk: qup-i2c19-data-clk-state { 3792 /* SDA, SCL */ 3793 pins = "gpio48", "gpio49"; 3794 function = "qup4_se0"; 3795 drive-strength = <2>; 3796 bias-pull-up; 3797 }; 3798 3799 qup_i2c20_data_clk: qup-i2c20-data-clk-state { 3800 /* SDA, SCL */ 3801 pins = "gpio28", "gpio29"; 3802 function = "qup4_se1"; 3803 drive-strength = <2>; 3804 bias-pull-up; 3805 }; 3806 3807 qup_i2c21_data_clk: qup-i2c21-data-clk-state { 3808 /* SDA, SCL */ 3809 pins = "gpio32", "gpio33"; 3810 function = "qup4_se2"; 3811 drive-strength = <2>; 3812 bias-pull-up; 3813 }; 3814 3815 qup_i2c22_data_clk: qup-i2c22-data-clk-state { 3816 /* SDA, SCL */ 3817 pins = "gpio121", "gpio84"; 3818 function = "qup4_se3"; 3819 drive-strength = <2>; 3820 bias-pull-up; 3821 }; 3822 3823 qup_i2c23_data_clk: qup-i2c23-data-clk-state { 3824 /* SDA, SCL */ 3825 pins = "gpio161", "gpio162"; 3826 function = "qup4_se4"; 3827 drive-strength = <2>; 3828 bias-pull-up; 3829 }; 3830 3831 qup_spi0_cs: qup-spi0-cs-state { 3832 pins = "gpio81"; 3833 function = "qup1_se0"; 3834 drive-strength = <6>; 3835 bias-disable; 3836 }; 3837 3838 qup_spi0_data_clk: qup-spi0-data-clk-state { 3839 /* MISO, MOSI, CLK */ 3840 pins = "gpio80", "gpio83", "gpio82"; 3841 function = "qup1_se0"; 3842 drive-strength = <6>; 3843 bias-disable; 3844 }; 3845 3846 qup_spi1_cs: qup-spi1-cs-state { 3847 pins = "gpio77"; 3848 function = "qup1_se1"; 3849 drive-strength = <6>; 3850 bias-disable; 3851 }; 3852 3853 qup_spi1_data_clk: qup-spi1-data-clk-state { 3854 /* MISO, MOSI, CLK */ 3855 pins = "gpio74", "gpio75", "gpio76"; 3856 function = "qup1_se1"; 3857 drive-strength = <6>; 3858 bias-disable; 3859 }; 3860 3861 qup_spi2_cs: qup-spi2-cs-state { 3862 pins = "gpio43"; 3863 function = "qup1_se2"; 3864 drive-strength = <6>; 3865 bias-disable; 3866 }; 3867 3868 qup_spi2_data_clk: qup-spi2-data-clk-state { 3869 /* MISO, MOSI, CLK */ 3870 pins = "gpio40", "gpio41", "gpio42"; 3871 function = "qup1_se2"; 3872 drive-strength = <6>; 3873 bias-disable; 3874 }; 3875 3876 qup_spi3_cs: qup-spi3-cs-state { 3877 pins = "gpio47"; 3878 function = "qup1_se3"; 3879 drive-strength = <6>; 3880 bias-disable; 3881 }; 3882 3883 qup_spi3_data_clk: qup-spi3-data-clk-state { 3884 /* MISO, MOSI, CLK */ 3885 pins = "gpio44", "gpio45", "gpio46"; 3886 function = "qup1_se3"; 3887 drive-strength = <6>; 3888 bias-disable; 3889 }; 3890 3891 qup_spi4_cs: qup-spi4-cs-state { 3892 pins = "gpio39"; 3893 function = "qup1_se4"; 3894 drive-strength = <6>; 3895 bias-disable; 3896 }; 3897 3898 qup_spi4_data_clk: qup-spi4-data-clk-state { 3899 /* MISO, MOSI, CLK */ 3900 pins = "gpio36", "gpio37", "gpio38"; 3901 function = "qup1_se4"; 3902 drive-strength = <6>; 3903 bias-disable; 3904 }; 3905 3906 qup_spi5_cs: qup-spi5-cs-state { 3907 pins = "gpio55"; 3908 function = "qup1_se5"; 3909 drive-strength = <6>; 3910 bias-disable; 3911 }; 3912 3913 qup_spi5_data_clk: qup-spi5-data-clk-state { 3914 /* MISO, MOSI, CLK */ 3915 pins = "gpio52", "gpio53", "gpio54"; 3916 function = "qup1_se5"; 3917 drive-strength = <6>; 3918 bias-disable; 3919 }; 3920 3921 qup_spi6_cs: qup-spi6-cs-state { 3922 pins = "gpio59"; 3923 function = "qup1_se6"; 3924 drive-strength = <6>; 3925 bias-disable; 3926 }; 3927 3928 qup_spi6_data_clk: qup-spi6-data-clk-state { 3929 /* MISO, MOSI, CLK */ 3930 pins = "gpio56", "gpio57", "gpio58"; 3931 function = "qup1_se6"; 3932 drive-strength = <6>; 3933 bias-disable; 3934 }; 3935 3936 qup_spi8_cs: qup-spi8-cs-state { 3937 pins = "gpio3"; 3938 function = "qup2_se0"; 3939 drive-strength = <6>; 3940 bias-disable; 3941 }; 3942 3943 qup_spi8_data_clk: qup-spi8-data-clk-state { 3944 /* MISO, MOSI, CLK */pins = "gpio0", "gpio1", "gpio2"; 3945 function = "qup2_se0"; 3946 drive-strength = <6>; 3947 bias-disable; 3948 }; 3949 3950 qup_spi9_cs: qup-spi9-cs-state { 3951 pins = "gpio7"; 3952 function = "qup2_se1"; 3953 drive-strength = <6>; 3954 bias-disable; 3955 }; 3956 3957 qup_spi9_data_clk: qup-spi9-data-clk-state { 3958 /* MISO, MOSI, CLK */ 3959 pins = "gpio4", "gpio5", "gpio6"; 3960 function = "qup2_se1"; 3961 drive-strength = <6>; 3962 bias-disable; 3963 }; 3964 3965 qup_spi10_cs: qup-spi10-cs-state { 3966 pins = "gpio120"; 3967 function = "qup2_se2"; 3968 drive-strength = <6>; 3969 bias-disable; 3970 }; 3971 3972 qup_spi10_data_clk: qup-spi10-data-clk-state { 3973 /* MISO, MOSI, CLK */ 3974 pins = "gpio117", "gpio118", "gpio119"; 3975 function = "qup2_se2"; 3976 drive-strength = <6>; 3977 bias-disable; 3978 }; 3979 3980 qup_spi11_cs: qup-spi11-cs-state { 3981 pins = "gpio125"; 3982 function = "qup2_se3"; 3983 drive-strength = <6>; 3984 bias-disable; 3985 }; 3986 3987 qup_spi11_data_clk: qup-spi11-data-clk-state { 3988 /* MISO, MOSI, CLK */ 3989 pins = "gpio122", "gpio123", "gpio124"; 3990 function = "qup2_se3"; 3991 drive-strength = <6>; 3992 bias-disable; 3993 }; 3994 3995 qup_spi14_cs: qup-spi14-cs-state { 3996 pins = "gpio11"; 3997 function = "qup3_se1"; 3998 drive-strength = <6>; 3999 bias-pull-up; 4000 }; 4001 4002 qup_spi14_data_clk: qup-spi14-data-clk-state { 4003 /* MISO, MOSI, CLK */ 4004 pins = "gpio8", "gpio9", "gpio10"; 4005 function = "qup3_se1"; 4006 drive-strength = <6>; 4007 bias-disable; 4008 }; 4009 4010 qup_spi15_cs: qup-spi15-cs-state { 4011 pins = "gpio15"; 4012 function = "qup3_se2"; 4013 drive-strength = <6>; 4014 bias-disable; 4015 }; 4016 4017 qup_spi15_data_clk: qup-spi15-data-clk-state { 4018 /* MISO, MOSI, CLK */ 4019 pins = "gpio12", "gpio13", "gpio14"; 4020 function = "qup3_se2"; 4021 drive-strength = <6>; 4022 bias-disable; 4023 }; 4024 4025 qup_spi16_cs: qup-spi16-cs-state { 4026 pins = "gpio19"; 4027 function = "qup3_se3"; 4028 drive-strength = <6>; 4029 bias-disable; 4030 }; 4031 4032 qup_spi16_data_clk: qup-spi16-data-clk-state { 4033 /* MISO, MOSI, CLK */ 4034 pins = "gpio16", "gpio17", "gpio18"; 4035 function = "qup3_se3"; 4036 drive-strength = <6>; 4037 bias-disable; 4038 }; 4039 4040 qup_spi17_cs: qup-spi17-cs-state { 4041 pins = "gpio23"; 4042 function = "qup3_se4"; 4043 drive-strength = <6>; 4044 bias-disable; 4045 }; 4046 4047 qup_spi17_data_clk: qup-spi17-data-clk-state { 4048 /* MISO, MOSI, CLK */ 4049 pins = "gpio20", "gpio21", "gpio22"; 4050 function = "qup3_se4"; 4051 drive-strength = <6>; 4052 bias-disable; 4053 }; 4054 4055 qup_spi19_cs: qup-spi19-cs-state { 4056 pins = "gpio51"; 4057 function = "qup4_se0"; 4058 drive-strength = <6>; 4059 bias-disable; 4060 }; 4061 4062 qup_spi19_data_clk: qup-spi19-data-clk-state { 4063 /* MISO, MOSI, CLK */ 4064 pins = "gpio48", "gpio49", "gpio50"; 4065 function = "qup4_se0"; 4066 drive-strength = <6>; 4067 bias-disable; 4068 }; 4069 4070 qup_spi20_cs: qup-spi20-cs-state { 4071 pins = "gpio31"; 4072 function = "qup4_se1"; 4073 drive-strength = <6>; 4074 bias-disable; 4075 }; 4076 4077 qup_spi20_data_clk: qup-spi20-data-clk-state { 4078 /* MISO, MOSI, CLK */ 4079 pins = "gpio28", "gpio29", "gpio30"; 4080 function = "qup4_se1"; 4081 drive-strength = <6>; 4082 bias-disable; 4083 }; 4084 4085 qup_spi21_cs: qup-spi21-cs-state { 4086 pins = "gpio35"; 4087 function = "qup4_se2"; 4088 drive-strength = <6>; 4089 bias-disable; 4090 }; 4091 4092 qup_spi21_data_clk: qup-spi21-data-clk-state { 4093 /* MISO, MOSI, CLK */ 4094 pins = "gpio32", "gpio33", "gpio34"; 4095 function = "qup4_se2"; 4096 drive-strength = <6>; 4097 bias-disable; 4098 }; 4099 4100 qup_uart7_default: qup-uart7-state { 4101 /* TX, RX */ 4102 pins = "gpio62", "gpio63"; 4103 function = "qup1_se7"; 4104 drive-strength = <2>; 4105 bias-disable; 4106 }; 4107 4108 qup_uart18_default: qup-uart18-default-state { 4109 /* TX, RX */ 4110 pins = "gpio26", "gpio27"; 4111 function = "qup3_se5"; 4112 drive-strength = <2>; 4113 bias-pull-up; 4114 }; 4115 4116 qup_uart18_cts_rts: qup-uart18-cts-rts-state { 4117 /* CTS, RTS */ 4118 pins = "gpio24", "gpio25"; 4119 function = "qup3_se5"; 4120 drive-strength = <2>; 4121 bias-pull-down; 4122 }; 4123 4124 sdc2_default: sdc2-default-state { 4125 clk-pins { 4126 pins = "sdc2_clk"; 4127 drive-strength = <16>; 4128 bias-disable; 4129 }; 4130 4131 cmd-pins { 4132 pins = "sdc2_cmd"; 4133 drive-strength = <10>; 4134 bias-pull-up; 4135 }; 4136 4137 data-pins { 4138 pins = "sdc2_data"; 4139 drive-strength = <10>; 4140 bias-pull-up; 4141 }; 4142 4143 card-detect-pins { 4144 pins = "gpio55"; 4145 function = "gpio"; 4146 drive-strength = <2>; 4147 bias-pull-up; 4148 }; 4149 }; 4150 4151 sdc2_sleep: sdc2-sleep-state { 4152 clk-pins { 4153 pins = "sdc2_clk"; 4154 drive-strength = <2>; 4155 bias-disable; 4156 }; 4157 4158 cmd-pins { 4159 pins = "sdc2_cmd"; 4160 drive-strength = <2>; 4161 bias-pull-up; 4162 }; 4163 4164 data-pins { 4165 pins = "sdc2_data"; 4166 drive-strength = <2>; 4167 bias-pull-up; 4168 }; 4169 4170 card-detect-pins { 4171 pins = "gpio55"; 4172 function = "gpio"; 4173 drive-strength = <2>; 4174 bias-pull-up; 4175 }; 4176 }; 4177 }; 4178 4179 stm@10002000 { 4180 compatible = "arm,coresight-stm", "arm,primecell"; 4181 reg = <0x0 0x10002000 0x0 0x1000>, 4182 <0x0 0x16280000 0x0 0x180000>; 4183 reg-names = "stm-base", 4184 "stm-stimulus-base"; 4185 4186 clocks = <&aoss_qmp>; 4187 clock-names = "apb_pclk"; 4188 4189 out-ports { 4190 port { 4191 stm_out: endpoint { 4192 remote-endpoint = <&funnel_in0_in7>; 4193 }; 4194 }; 4195 }; 4196 }; 4197 4198 tpdm@10003000 { 4199 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4200 reg = <0x0 0x10003000 0x0 0x1000>; 4201 4202 clocks = <&aoss_qmp>; 4203 clock-names = "apb_pclk"; 4204 4205 qcom,cmb-element-bits = <32>; 4206 4207 out-ports { 4208 port { 4209 tpdm_dcc_out: endpoint { 4210 remote-endpoint = <&tpda_qdss_in0>; 4211 }; 4212 }; 4213 }; 4214 }; 4215 4216 tpda@10004000 { 4217 compatible = "qcom,coresight-tpda", "arm,primecell"; 4218 reg = <0x0 0x10004000 0x0 0x1000>; 4219 4220 clocks = <&aoss_qmp>; 4221 clock-names = "apb_pclk"; 4222 4223 in-ports { 4224 #address-cells = <1>; 4225 #size-cells = <0>; 4226 4227 port@0 { 4228 reg = <0>; 4229 4230 tpda_qdss_in0: endpoint { 4231 remote-endpoint = <&tpdm_dcc_out>; 4232 }; 4233 }; 4234 4235 port@1 { 4236 reg = <1>; 4237 4238 tpda_qdss_in1: endpoint { 4239 remote-endpoint = <&tpdm_spdm_out>; 4240 }; 4241 }; 4242 }; 4243 4244 out-ports { 4245 port { 4246 tpda_qdss_out: endpoint { 4247 remote-endpoint = <&funnel_in0_in6>; 4248 }; 4249 }; 4250 }; 4251 }; 4252 4253 tpdm@1000f000 { 4254 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4255 reg = <0x0 0x1000f000 0x0 0x1000>; 4256 4257 clocks = <&aoss_qmp>; 4258 clock-names = "apb_pclk"; 4259 4260 qcom,cmb-element-bits = <32>; 4261 4262 out-ports { 4263 port { 4264 tpdm_spdm_out: endpoint { 4265 remote-endpoint = <&tpda_qdss_in1>; 4266 }; 4267 }; 4268 }; 4269 }; 4270 4271 funnel@10041000 { 4272 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4273 reg = <0x0 0x10041000 0x0 0x1000>; 4274 4275 clocks = <&aoss_qmp>; 4276 clock-names = "apb_pclk"; 4277 4278 in-ports { 4279 #address-cells = <1>; 4280 #size-cells = <0>; 4281 4282 port@0 { 4283 reg = <0>; 4284 4285 funnel_in0_in0: endpoint { 4286 remote-endpoint = <&tn_ag_out>; 4287 }; 4288 }; 4289 4290 port@6 { 4291 reg = <6>; 4292 4293 funnel_in0_in6: endpoint { 4294 remote-endpoint = <&tpda_qdss_out>; 4295 }; 4296 }; 4297 4298 port@7 { 4299 reg = <7>; 4300 4301 funnel_in0_in7: endpoint { 4302 remote-endpoint = <&stm_out>; 4303 }; 4304 }; 4305 }; 4306 4307 out-ports { 4308 port { 4309 funnel_in0_out: endpoint { 4310 remote-endpoint = <&funnel_aoss_in6>; 4311 }; 4312 }; 4313 }; 4314 }; 4315 4316 tpdm@11000000 { 4317 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4318 reg = <0x0 0x11000000 0x0 0x1000>; 4319 4320 clocks = <&aoss_qmp>; 4321 clock-names = "apb_pclk"; 4322 4323 qcom,dsb-element-bits = <32>; 4324 qcom,dsb-msrs-num = <32>; 4325 4326 out-ports { 4327 port { 4328 tpdm_modem0_out: endpoint { 4329 remote-endpoint = <&tpda_modem_in0>; 4330 }; 4331 }; 4332 }; 4333 }; 4334 4335 tpda@11004000 { 4336 compatible = "qcom,coresight-tpda", "arm,primecell"; 4337 reg = <0x0 0x11004000 0x0 0x1000>; 4338 4339 clocks = <&aoss_qmp>; 4340 clock-names = "apb_pclk"; 4341 4342 in-ports { 4343 #address-cells = <1>; 4344 #size-cells = <0>; 4345 4346 port@0 { 4347 reg = <0>; 4348 4349 tpda_modem_in0: endpoint { 4350 remote-endpoint = <&tpdm_modem0_out>; 4351 }; 4352 }; 4353 4354 port@1 { 4355 reg = <1>; 4356 4357 tpda_modem_in1: endpoint { 4358 remote-endpoint = <&tpdm_modem1_out>; 4359 }; 4360 }; 4361 4362 port@2 { 4363 reg = <2>; 4364 4365 tpda_modem_in2: endpoint { 4366 remote-endpoint = <&tpdm_modem2_out>; 4367 }; 4368 }; 4369 }; 4370 4371 out-ports { 4372 port { 4373 tpda_modem_out: endpoint { 4374 remote-endpoint = <&funnel_modem_dl_in0>; 4375 }; 4376 }; 4377 }; 4378 }; 4379 4380 funnel@11005000 { 4381 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4382 reg = <0x0 0x11005000 0x0 0x1000>; 4383 4384 clocks = <&aoss_qmp>; 4385 clock-names = "apb_pclk"; 4386 4387 in-ports { 4388 port { 4389 funnel_modem_dl_in0: endpoint { 4390 remote-endpoint = <&tpda_modem_out>; 4391 }; 4392 }; 4393 }; 4394 4395 out-ports { 4396 port { 4397 funnel_modem_dl_out: endpoint { 4398 remote-endpoint = <&tn_ag_in13>; 4399 }; 4400 }; 4401 }; 4402 }; 4403 4404 tpdm@1102c000 { 4405 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4406 reg = <0x0 0x1102c000 0x0 0x1000>; 4407 4408 clocks = <&aoss_qmp>; 4409 clock-names = "apb_pclk"; 4410 4411 qcom,dsb-msrs-num = <32>; 4412 4413 out-ports { 4414 port { 4415 tpdm_gcc_out: endpoint { 4416 remote-endpoint = <&tn_ag_in17>; 4417 }; 4418 }; 4419 }; 4420 }; 4421 4422 tpdm@11180000 { 4423 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4424 reg = <0x0 0x11180000 0x0 0x1000>; 4425 4426 clocks = <&aoss_qmp>; 4427 clock-names = "apb_pclk"; 4428 4429 qcom,dsb-element-bits = <32>; 4430 qcom,dsb-msrs-num = <32>; 4431 4432 out-ports { 4433 port { 4434 tpdm_cdsp_out: endpoint { 4435 remote-endpoint = <&tpda_cdsp_in0>; 4436 }; 4437 }; 4438 }; 4439 }; 4440 4441 tpdm@11183000 { 4442 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4443 reg = <0x0 0x11183000 0x0 0x1000>; 4444 4445 clocks = <&aoss_qmp>; 4446 clock-names = "apb_pclk"; 4447 4448 qcom,dsb-element-bits = <32>; 4449 qcom,cmb-element-bits = <32>; 4450 4451 out-ports { 4452 port { 4453 tpdm_cdsp_cmsr1_out: endpoint { 4454 remote-endpoint = <&tpda_cdsp_in3>; 4455 }; 4456 }; 4457 }; 4458 }; 4459 4460 tpdm@11184000 { 4461 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4462 reg = <0x0 0x11184000 0x0 0x1000>; 4463 4464 clocks = <&aoss_qmp>; 4465 clock-names = "apb_pclk"; 4466 4467 qcom,dsb-element-bits = <32>; 4468 qcom,cmb-element-bits = <32>; 4469 4470 out-ports { 4471 port { 4472 tpdm_cdsp_cmsr2_out: endpoint { 4473 remote-endpoint = <&tpda_cdsp_in4>; 4474 }; 4475 }; 4476 }; 4477 }; 4478 4479 tpdm@11185000 { 4480 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4481 reg = <0x0 0x11185000 0x0 0x1000>; 4482 4483 clocks = <&aoss_qmp>; 4484 clock-names = "apb_pclk"; 4485 4486 qcom,cmb-element-bits = <64>; 4487 4488 out-ports { 4489 port { 4490 tpdm_cdsp_dpm1_out: endpoint { 4491 remote-endpoint = <&tpda_cdsp_in5>; 4492 }; 4493 }; 4494 }; 4495 }; 4496 4497 tpdm@11186000 { 4498 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4499 reg = <0x0 0x11186000 0x0 0x1000>; 4500 4501 clocks = <&aoss_qmp>; 4502 clock-names = "apb_pclk"; 4503 4504 qcom,cmb-element-bits = <64>; 4505 4506 out-ports { 4507 port { 4508 tpdm_cdsp_dpm2_out: endpoint { 4509 remote-endpoint = <&tpda_cdsp_in6>; 4510 }; 4511 }; 4512 }; 4513 }; 4514 4515 tpda@11188000 { 4516 compatible = "qcom,coresight-tpda", "arm,primecell"; 4517 reg = <0x0 0x11188000 0x0 0x1000>; 4518 4519 clocks = <&aoss_qmp>; 4520 clock-names = "apb_pclk"; 4521 4522 in-ports { 4523 #address-cells = <1>; 4524 #size-cells = <0>; 4525 4526 port@0 { 4527 reg = <0>; 4528 4529 tpda_cdsp_in0: endpoint { 4530 remote-endpoint = <&tpdm_cdsp_out>; 4531 }; 4532 }; 4533 4534 port@1 { 4535 reg = <1>; 4536 4537 tpda_cdsp_in1: endpoint { 4538 remote-endpoint = <&tpdm_cdsp_llm_out>; 4539 }; 4540 }; 4541 4542 port@2 { 4543 reg = <2>; 4544 4545 tpda_cdsp_in2: endpoint { 4546 remote-endpoint = <&tpdm_cdsp_llm2_out>; 4547 }; 4548 }; 4549 4550 port@3 { 4551 reg = <3>; 4552 4553 tpda_cdsp_in3: endpoint { 4554 remote-endpoint = <&tpdm_cdsp_cmsr1_out>; 4555 }; 4556 }; 4557 4558 port@4 { 4559 reg = <4>; 4560 4561 tpda_cdsp_in4: endpoint { 4562 remote-endpoint = <&tpdm_cdsp_cmsr2_out>; 4563 }; 4564 }; 4565 4566 port@5 { 4567 reg = <5>; 4568 4569 tpda_cdsp_in5: endpoint { 4570 remote-endpoint = <&tpdm_cdsp_dpm1_out>; 4571 }; 4572 }; 4573 4574 port@6 { 4575 reg = <6>; 4576 4577 tpda_cdsp_in6: endpoint { 4578 remote-endpoint = <&tpdm_cdsp_dpm2_out>; 4579 }; 4580 }; 4581 }; 4582 4583 out-ports { 4584 port { 4585 tpda_cdsp_out: endpoint { 4586 remote-endpoint = <&funnel_cdsp_in0>; 4587 }; 4588 }; 4589 }; 4590 }; 4591 4592 funnel@11189000 { 4593 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 4594 reg = <0x0 0x11189000 0x0 0x1000>; 4595 4596 clocks = <&aoss_qmp>; 4597 clock-names = "apb_pclk"; 4598 4599 in-ports { 4600 port { 4601 funnel_cdsp_in0: endpoint { 4602 remote-endpoint = <&tpda_cdsp_out>; 4603 }; 4604 }; 4605 }; 4606 4607 out-ports { 4608 port { 4609 funnel_cdsp_out: endpoint { 4610 remote-endpoint = <&tn_ag_in16>; 4611 }; 4612 }; 4613 }; 4614 }; 4615 4616 tpdm@111a3000 { 4617 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4618 reg = <0x0 0x111a3000 0x0 0x1000>; 4619 4620 clocks = <&aoss_qmp>; 4621 clock-names = "apb_pclk"; 4622 4623 qcom,dsb-msrs-num = <32>; 4624 4625 out-ports { 4626 port { 4627 tpdm_pmu_out: endpoint { 4628 remote-endpoint = <&tn_ag_in29>; 4629 }; 4630 }; 4631 }; 4632 }; 4633 4634 tpdm@111a4000 { 4635 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4636 reg = <0x0 0x111a4000 0x0 0x1000>; 4637 4638 clocks = <&aoss_qmp>; 4639 clock-names = "apb_pclk"; 4640 4641 out-ports { 4642 port { 4643 tpdm_qrng_out: endpoint { 4644 remote-endpoint = <&tn_ag_in18>; 4645 }; 4646 }; 4647 }; 4648 }; 4649 4650 tpdm@111a5000 { 4651 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4652 reg = <0x0 0x111a5000 0x0 0x1000>; 4653 4654 clocks = <&aoss_qmp>; 4655 clock-names = "apb_pclk"; 4656 4657 qcom,dsb-msrs-num = <32>; 4658 4659 out-ports { 4660 port { 4661 tpdm_dlmm_out: endpoint { 4662 remote-endpoint = <&tn_ag_in25>; 4663 }; 4664 }; 4665 }; 4666 }; 4667 4668 tpdm@111a6000 { 4669 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4670 reg = <0x0 0x111a6000 0x0 0x1000>; 4671 4672 clocks = <&aoss_qmp>; 4673 clock-names = "apb_pclk"; 4674 4675 qcom,dsb-msrs-num = <32>; 4676 4677 out-ports { 4678 port { 4679 tpdm_north_dsb_out: endpoint { 4680 remote-endpoint = <&tn_ag_in26>; 4681 }; 4682 }; 4683 }; 4684 }; 4685 4686 tpdm@111a7000 { 4687 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4688 reg = <0x0 0x111a7000 0x0 0x1000>; 4689 4690 clocks = <&aoss_qmp>; 4691 clock-names = "apb_pclk"; 4692 4693 qcom,dsb-msrs-num = <32>; 4694 4695 out-ports { 4696 port { 4697 tpdm_south_dsb_out: endpoint { 4698 remote-endpoint = <&tn_ag_in27>; 4699 }; 4700 }; 4701 }; 4702 }; 4703 4704 tpdm@111a8000 { 4705 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4706 reg = <0x0 0x111a8000 0x0 0x1000>; 4707 4708 clocks = <&aoss_qmp>; 4709 clock-names = "apb_pclk"; 4710 4711 out-ports { 4712 port { 4713 tpdm_rdpm_cmb0_out: endpoint { 4714 remote-endpoint = <&tn_ag_in30>; 4715 }; 4716 }; 4717 }; 4718 }; 4719 4720 tpdm@111a9000 { 4721 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4722 reg = <0x0 0x111a9000 0x0 0x1000>; 4723 4724 clocks = <&aoss_qmp>; 4725 clock-names = "apb_pclk"; 4726 4727 out-ports { 4728 port { 4729 tpdm_rdpm_cmb1_out: endpoint { 4730 remote-endpoint = <&tn_ag_in31>; 4731 }; 4732 }; 4733 }; 4734 }; 4735 4736 tpdm@111aa000 { 4737 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4738 reg = <0x0 0x111aa000 0x0 0x1000>; 4739 4740 clocks = <&aoss_qmp>; 4741 clock-names = "apb_pclk"; 4742 4743 out-ports { 4744 port { 4745 tpdm_rdpm_cmb2_out: endpoint { 4746 remote-endpoint = <&tn_ag_in32>; 4747 }; 4748 }; 4749 }; 4750 }; 4751 4752 tpdm@111ab000 { 4753 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4754 reg = <0x0 0x111ab000 0x0 0x1000>; 4755 4756 clocks = <&aoss_qmp>; 4757 clock-names = "apb_pclk"; 4758 4759 out-ports { 4760 port { 4761 tpdm_ipcc_cmb0_out: endpoint { 4762 remote-endpoint = <&tn_ag_in36>; 4763 }; 4764 }; 4765 }; 4766 }; 4767 4768 tpdm@111ac000 { 4769 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4770 reg = <0x0 0x111ac000 0x0 0x1000>; 4771 4772 clocks = <&aoss_qmp>; 4773 clock-names = "apb_pclk"; 4774 4775 out-ports { 4776 port { 4777 tpdm_ipcc_cmb1_out: endpoint { 4778 remote-endpoint = <&tn_ag_in28>; 4779 }; 4780 }; 4781 }; 4782 }; 4783 4784 tpdm@111ad000 { 4785 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4786 reg = <0x0 0x111ad000 0x0 0x1000>; 4787 4788 clocks = <&aoss_qmp>; 4789 clock-names = "apb_pclk"; 4790 4791 out-ports { 4792 port { 4793 tpdm_ipcc_cmb2_out: endpoint { 4794 remote-endpoint = <&tn_ag_in34>; 4795 }; 4796 }; 4797 }; 4798 }; 4799 4800 tpdm@111ae000 { 4801 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4802 reg = <0x0 0x111ae000 0x0 0x1000>; 4803 4804 clocks = <&aoss_qmp>; 4805 clock-names = "apb_pclk"; 4806 4807 out-ports { 4808 port { 4809 tpdm_ipcc_cmb3_out: endpoint { 4810 remote-endpoint = <&tn_ag_in37>; 4811 }; 4812 }; 4813 }; 4814 }; 4815 4816 tpdm@111af000 { 4817 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4818 reg = <0x0 0x111af000 0x0 0x1000>; 4819 4820 clocks = <&aoss_qmp>; 4821 clock-names = "apb_pclk"; 4822 4823 out-ports { 4824 port { 4825 tpdm_ipcc_cmb4_out: endpoint { 4826 remote-endpoint = <&tn_ag_in35>; 4827 }; 4828 }; 4829 }; 4830 }; 4831 4832 tpdm@111b3000 { 4833 compatible = "qcom,coresight-tpdm", "arm,primecell"; 4834 reg = <0x0 0x111b3000 0x0 0x1000>; 4835 4836 clocks = <&aoss_qmp>; 4837 clock-names = "apb_pclk"; 4838 4839 out-ports { 4840 port { 4841 tpdm_pcie_rscc_out: endpoint { 4842 remote-endpoint = <&tn_ag_in8>; 4843 }; 4844 }; 4845 }; 4846 }; 4847 4848 tn@111b8000 { 4849 compatible = "qcom,coresight-tnoc", "arm,primecell"; 4850 reg = <0x0 0x111b8000 0x0 0x4200>; 4851 4852 clocks = <&aoss_qmp>; 4853 clock-names = "apb_pclk"; 4854 4855 in-ports { 4856 #address-cells = <1>; 4857 #size-cells = <0>; 4858 4859 port@8 { 4860 reg = <8>; 4861 4862 tn_ag_in8: endpoint { 4863 remote-endpoint = <&tpdm_pcie_rscc_out>; 4864 }; 4865 }; 4866 4867 port@d { 4868 reg = <0xd>; 4869 4870 tn_ag_in13: endpoint { 4871 remote-endpoint = <&funnel_modem_dl_out>; 4872 }; 4873 }; 4874 4875 port@10 { 4876 reg = <0x10>; 4877 4878 tn_ag_in16: endpoint { 4879 remote-endpoint = <&funnel_cdsp_out>; 4880 }; 4881 }; 4882 4883 port@11 { 4884 reg = <0x11>; 4885 4886 tn_ag_in17: endpoint { 4887 remote-endpoint = <&tpdm_gcc_out>; 4888 }; 4889 }; 4890 4891 port@12 { 4892 reg = <0x12>; 4893 4894 tn_ag_in18: endpoint { 4895 remote-endpoint = <&tpdm_qrng_out>; 4896 }; 4897 }; 4898 4899 port@13 { 4900 reg = <0x13>; 4901 4902 tn_ag_in19: endpoint { 4903 remote-endpoint = <&tpdm_qm_out>; 4904 }; 4905 }; 4906 4907 port@15 { 4908 reg = <0x15>; 4909 4910 tn_ag_in21: endpoint { 4911 remote-endpoint = <&tpdm_ipa_out>; 4912 }; 4913 }; 4914 4915 port@19 { 4916 reg = <0x19>; 4917 4918 tn_ag_in25: endpoint { 4919 remote-endpoint = <&tpdm_dlmm_out>; 4920 }; 4921 }; 4922 4923 port@1a { 4924 reg = <0x1a>; 4925 4926 tn_ag_in26: endpoint { 4927 remote-endpoint = <&tpdm_north_dsb_out>; 4928 }; 4929 }; 4930 4931 port@1b { 4932 reg = <0x1b>; 4933 4934 tn_ag_in27: endpoint { 4935 remote-endpoint = <&tpdm_south_dsb_out>; 4936 }; 4937 }; 4938 4939 port@1c { 4940 reg = <0x1c>; 4941 4942 tn_ag_in28: endpoint { 4943 remote-endpoint = <&tpdm_ipcc_cmb1_out>; 4944 }; 4945 }; 4946 4947 port@1d { 4948 reg = <0x1d>; 4949 4950 tn_ag_in29: endpoint { 4951 remote-endpoint = <&tpdm_pmu_out>; 4952 }; 4953 }; 4954 4955 port@1e { 4956 reg = <0x1e>; 4957 4958 tn_ag_in30: endpoint { 4959 remote-endpoint = <&tpdm_rdpm_cmb0_out>; 4960 }; 4961 }; 4962 4963 port@1f { 4964 reg = <0x1f>; 4965 4966 tn_ag_in31: endpoint { 4967 remote-endpoint = <&tpdm_rdpm_cmb1_out>; 4968 }; 4969 }; 4970 4971 port@20 { 4972 reg = <0x20>; 4973 4974 tn_ag_in32: endpoint { 4975 remote-endpoint = <&tpdm_rdpm_cmb2_out>; 4976 }; 4977 }; 4978 4979 port@22 { 4980 reg = <0x22>; 4981 4982 tn_ag_in34: endpoint { 4983 remote-endpoint = <&tpdm_ipcc_cmb2_out>; 4984 }; 4985 }; 4986 4987 port@23 { 4988 reg = <0x23>; 4989 4990 tn_ag_in35: endpoint { 4991 remote-endpoint = <&tpdm_ipcc_cmb4_out>; 4992 }; 4993 }; 4994 4995 port@24 { 4996 reg = <0x24>; 4997 4998 tn_ag_in36: endpoint { 4999 remote-endpoint = <&tpdm_ipcc_cmb0_out>; 5000 }; 5001 }; 5002 5003 port@25 { 5004 reg = <37>; 5005 5006 tn_ag_in37: endpoint { 5007 remote-endpoint = <&tpdm_ipcc_cmb3_out>; 5008 }; 5009 }; 5010 }; 5011 5012 out-ports { 5013 port { 5014 tn_ag_out: endpoint { 5015 remote-endpoint = <&funnel_in0_in0>; 5016 }; 5017 }; 5018 }; 5019 }; 5020 5021 tpdm@111d0000 { 5022 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5023 reg = <0x0 0x111d0000 0x0 0x1000>; 5024 5025 clocks = <&aoss_qmp>; 5026 clock-names = "apb_pclk"; 5027 5028 out-ports { 5029 port { 5030 tpdm_qm_out: endpoint { 5031 remote-endpoint = <&tn_ag_in19>; 5032 }; 5033 }; 5034 }; 5035 }; 5036 5037 tpdm@11303000 { 5038 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5039 reg = <0x0 0x11303000 0x0 0x1000>; 5040 5041 clocks = <&aoss_qmp>; 5042 clock-names = "apb_pclk"; 5043 5044 qcom,cmb-element-bits = <64>; 5045 5046 out-ports { 5047 port { 5048 tpdm_swao_prio4_out: endpoint { 5049 remote-endpoint = <&tpda_aoss_in4>; 5050 }; 5051 }; 5052 }; 5053 }; 5054 5055 funnel@11304000 { 5056 compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; 5057 reg = <0x0 0x11304000 0x0 0x1000>; 5058 5059 clocks = <&aoss_qmp>; 5060 clock-names = "apb_pclk"; 5061 5062 in-ports { 5063 #address-cells = <1>; 5064 #size-cells = <0>; 5065 5066 port@5 { 5067 reg = <5>; 5068 5069 funnel_aoss_in5: endpoint { 5070 remote-endpoint = <&tpda_aoss_out>; 5071 }; 5072 }; 5073 5074 port@6 { 5075 reg = <6>; 5076 5077 funnel_aoss_in6: endpoint { 5078 remote-endpoint = <&funnel_in0_out>; 5079 }; 5080 }; 5081 5082 }; 5083 5084 out-ports { 5085 port { 5086 funnel_aoss_out: endpoint { 5087 remote-endpoint = <&tmc_etf_in>; 5088 }; 5089 }; 5090 }; 5091 }; 5092 5093 tmc@11305000 { 5094 compatible = "arm,coresight-tmc", "arm,primecell"; 5095 reg = <0x0 0x11305000 0x0 0x1000>; 5096 5097 clocks = <&aoss_qmp>; 5098 clock-names = "apb_pclk"; 5099 5100 in-ports { 5101 port { 5102 tmc_etf_in: endpoint { 5103 remote-endpoint = <&funnel_aoss_out>; 5104 }; 5105 }; 5106 }; 5107 }; 5108 5109 tpda@11308000 { 5110 compatible = "qcom,coresight-tpda", "arm,primecell"; 5111 reg = <0x0 0x11308000 0x0 0x1000>; 5112 5113 clocks = <&aoss_qmp>; 5114 clock-names = "apb_pclk"; 5115 5116 in-ports { 5117 #address-cells = <1>; 5118 #size-cells = <0>; 5119 5120 port@0 { 5121 reg = <0>; 5122 5123 tpda_aoss_in0: endpoint { 5124 remote-endpoint = <&tpdm_swao_prio0_out>; 5125 }; 5126 }; 5127 5128 port@1 { 5129 reg = <1>; 5130 5131 tpda_aoss_in1: endpoint { 5132 remote-endpoint = <&tpdm_swao_prio1_out>; 5133 }; 5134 }; 5135 5136 port@2 { 5137 reg = <2>; 5138 5139 tpda_aoss_in2: endpoint { 5140 remote-endpoint = <&tpdm_swao_prio2_out>; 5141 }; 5142 }; 5143 5144 port@3 { 5145 reg = <3>; 5146 5147 tpda_aoss_in3: endpoint { 5148 remote-endpoint = <&tpdm_swao_prio3_out>; 5149 }; 5150 }; 5151 5152 port@4 { 5153 reg = <4>; 5154 5155 tpda_aoss_in4: endpoint { 5156 remote-endpoint = <&tpdm_swao_prio4_out>; 5157 }; 5158 }; 5159 5160 port@5 { 5161 reg = <5>; 5162 5163 tpda_aoss_in5: endpoint { 5164 remote-endpoint = <&tpdm_swao_out>; 5165 }; 5166 }; 5167 }; 5168 5169 out-ports { 5170 port { 5171 tpda_aoss_out: endpoint { 5172 remote-endpoint = <&funnel_aoss_in5>; 5173 }; 5174 }; 5175 }; 5176 }; 5177 5178 tpdm@11309000 { 5179 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5180 reg = <0x0 0x11309000 0x0 0x1000>; 5181 5182 clocks = <&aoss_qmp>; 5183 clock-names = "apb_pclk"; 5184 5185 qcom,cmb-element-bits = <64>; 5186 5187 out-ports { 5188 port { 5189 tpdm_swao_prio0_out: endpoint { 5190 remote-endpoint = <&tpda_aoss_in0>; 5191 }; 5192 }; 5193 }; 5194 }; 5195 5196 tpdm@1130a000 { 5197 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5198 reg = <0x0 0x1130a000 0x0 0x1000>; 5199 5200 clocks = <&aoss_qmp>; 5201 clock-names = "apb_pclk"; 5202 5203 qcom,cmb-element-bits = <64>; 5204 5205 out-ports { 5206 port { 5207 tpdm_swao_prio1_out: endpoint { 5208 remote-endpoint = <&tpda_aoss_in1>; 5209 }; 5210 }; 5211 }; 5212 }; 5213 5214 tpdm@1130b000 { 5215 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5216 reg = <0x0 0x1130b000 0x0 0x1000>; 5217 5218 clocks = <&aoss_qmp>; 5219 clock-names = "apb_pclk"; 5220 5221 qcom,cmb-element-bits = <64>; 5222 5223 out-ports { 5224 port { 5225 tpdm_swao_prio2_out: endpoint { 5226 remote-endpoint = <&tpda_aoss_in2>; 5227 }; 5228 }; 5229 }; 5230 }; 5231 5232 tpdm@1130c000 { 5233 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5234 reg = <0x0 0x1130c000 0x0 0x1000>; 5235 5236 clocks = <&aoss_qmp>; 5237 clock-names = "apb_pclk"; 5238 5239 qcom,cmb-element-bits = <64>; 5240 5241 out-ports { 5242 port { 5243 tpdm_swao_prio3_out: endpoint { 5244 remote-endpoint = <&tpda_aoss_in3>; 5245 }; 5246 }; 5247 }; 5248 }; 5249 5250 tpdm@1130d000 { 5251 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5252 reg = <0x0 0x1130d000 0x0 0x1000>; 5253 5254 clocks = <&aoss_qmp>; 5255 clock-names = "apb_pclk"; 5256 5257 qcom,dsb-element-bits = <32>; 5258 qcom,dsb-msrs-num = <32>; 5259 5260 out-ports { 5261 port { 5262 tpdm_swao_out: endpoint { 5263 remote-endpoint = <&tpda_aoss_in5>; 5264 }; 5265 }; 5266 }; 5267 }; 5268 5269 tpdm@11422000 { 5270 compatible = "qcom,coresight-tpdm", "arm,primecell"; 5271 reg = <0x0 0x11422000 0x0 0x1000>; 5272 5273 clocks = <&aoss_qmp>; 5274 clock-names = "apb_pclk"; 5275 5276 qcom,dsb-msrs-num = <32>; 5277 5278 out-ports { 5279 port { 5280 tpdm_ipa_out: endpoint { 5281 remote-endpoint = <&tn_ag_in21>; 5282 }; 5283 }; 5284 }; 5285 }; 5286 5287 sram@14680000 { 5288 compatible = "qcom,kaanapali-imem", "mmio-sram"; 5289 reg = <0x0 0x14680000 0x0 0x1000>; 5290 ranges = <0x0 0x0 0x14680000 0x1000>; 5291 5292 no-memory-wc; 5293 5294 #address-cells = <1>; 5295 #size-cells = <1>; 5296 5297 pil-sram@94c { 5298 compatible = "qcom,pil-reloc-info"; 5299 reg = <0x94c 0xc8>; 5300 }; 5301 }; 5302 5303 apps_smmu: iommu@15000000 { 5304 compatible = "qcom,kaanapali-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 5305 reg = <0x0 0x15000000 0x0 0x100000>; 5306 5307 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 5308 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 5309 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 5310 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 5311 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 5312 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 5313 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 5314 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 5315 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 5316 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 5317 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 5318 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 5319 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 5320 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 5321 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 5322 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 5323 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 5324 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 5325 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 5326 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 5327 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 5328 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 5329 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 5330 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 5331 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 5332 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 5333 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 5334 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 5335 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 5336 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 5337 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 5338 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 5339 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 5340 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 5341 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 5342 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 5343 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 5344 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 5345 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 5346 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 5347 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 5348 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 5349 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 5350 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 5351 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 5352 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 5353 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 5354 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 5355 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 5356 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 5357 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 5358 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 5359 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 5360 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 5361 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 5362 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 5363 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 5364 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 5365 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 5366 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 5367 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 5368 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 5369 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 5370 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 5371 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 5372 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 5373 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 5374 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 5375 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 5376 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 5377 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 5378 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 5379 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 5380 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 5381 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 5382 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 5383 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 5384 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 5385 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 5386 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 5387 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 5388 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 5389 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 5390 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 5391 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 5392 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 5393 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 5394 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 5395 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 5396 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 5397 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 5398 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 5399 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 5400 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 5401 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 5402 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 5403 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 5404 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 5405 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 5406 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 5407 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 5408 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 5409 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 5410 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 5411 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 5412 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 5413 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 5414 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 5415 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 5416 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 5417 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 5418 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 5419 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 5420 5421 #iommu-cells = <2>; 5422 #global-interrupts = <1>; 5423 5424 dma-coherent; 5425 }; 5426 5427 intc: interrupt-controller@17000000 { 5428 compatible = "arm,gic-v3"; 5429 reg = <0x0 0x17000000 0x0 0x10000>, 5430 <0x0 0x17080000 0x0 0x200000>; 5431 5432 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 5433 5434 #interrupt-cells = <3>; 5435 interrupt-controller; 5436 5437 #redistributor-regions = <1>; 5438 redistributor-stride = <0x0 0x40000>; 5439 5440 #address-cells = <2>; 5441 #size-cells = <2>; 5442 ranges; 5443 5444 gic_its: msi-controller@17040000 { 5445 compatible = "arm,gic-v3-its"; 5446 reg = <0x0 0x17040000 0x0 0x40000>; 5447 5448 msi-controller; 5449 #msi-cells = <1>; 5450 }; 5451 }; 5452 5453 watchdog@17600000 { 5454 compatible = "qcom,apss-wdt-kaanapali", "qcom,kpss-wdt"; 5455 reg = <0x0 0x17600000 0x0 0x1000>; 5456 clocks = <&sleep_clk>; 5457 interrupts = <GIC_SPI 0 IRQ_TYPE_EDGE_RISING>; 5458 }; 5459 5460 pdp0_mbox: mailbox@17610000 { 5461 compatible = "qcom,kaanapali-cpucp-mbox", "qcom,x1e80100-cpucp-mbox"; 5462 reg = <0x0 0x17610000 0x0 0x8000>, <0x0 0x19980000 0x0 0x8000>; 5463 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 5464 #mbox-cells = <1>; 5465 }; 5466 5467 timer@17810000 { 5468 compatible = "arm,armv7-timer-mem"; 5469 reg = <0x0 0x17810000 0x0 0x1000>; 5470 5471 #address-cells = <2>; 5472 #size-cells = <1>; 5473 ranges = <0x0 0x0 0x0 0x0 0x20000000>; 5474 5475 frame@17811000 { 5476 reg = <0x0 0x17811000 0x1000>, 5477 <0x0 0x17812000 0x1000>; 5478 frame-number = <0>; 5479 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, 5480 <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>; 5481 }; 5482 5483 frame@17813000 { 5484 reg = <0x0 0x17813000 0x1000>; 5485 frame-number = <1>; 5486 interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>; 5487 status = "disabled"; 5488 }; 5489 5490 frame@17815000 { 5491 reg = <0x0 0x17815000 0x1000>; 5492 frame-number = <2>; 5493 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>; 5494 status = "disabled"; 5495 }; 5496 5497 frame@17817000 { 5498 reg = <0x0 0x17817000 0x1000>; 5499 frame-number = <3>; 5500 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 5501 status = "disabled"; 5502 }; 5503 5504 frame@17819000 { 5505 reg = <0x0 0x17819000 0x1000>; 5506 frame-number = <4>; 5507 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 5508 status = "disabled"; 5509 }; 5510 5511 frame@1781b000 { 5512 reg = <0x0 0x1781b000 0x1000>; 5513 frame-number = <5>; 5514 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 5515 status = "disabled"; 5516 }; 5517 5518 frame@1781d000 { 5519 reg = <0x0 0x1781d000 0x1000>; 5520 frame-number = <6>; 5521 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 5522 status = "disabled"; 5523 }; 5524 }; 5525 5526 apps_rsc: rsc@18900000 { 5527 compatible = "qcom,rpmh-rsc"; 5528 reg = <0x0 0x18900000 0x0 0x10000>, 5529 <0x0 0x18910000 0x0 0x10000>, 5530 <0x0 0x18920000 0x0 0x10000>; 5531 reg-names = "drv-0", 5532 "drv-1", 5533 "drv-2"; 5534 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 5535 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 5536 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 5537 5538 power-domains = <&system_pd>; 5539 label = "apps_rsc"; 5540 5541 qcom,tcs-offset = <0xd00>; 5542 qcom,drv-id = <2>; 5543 qcom,tcs-config = <ACTIVE_TCS 3>, 5544 <SLEEP_TCS 2>, 5545 <WAKE_TCS 2>, 5546 <CONTROL_TCS 0>; 5547 5548 apps_bcm_voter: bcm-voter { 5549 compatible = "qcom,bcm-voter"; 5550 }; 5551 5552 rpmhcc: clock-controller { 5553 compatible = "qcom,kaanapali-rpmh-clk"; 5554 #clock-cells = <1>; 5555 clocks = <&xo_board>; 5556 clock-names = "xo"; 5557 }; 5558 5559 rpmhpd: power-controller { 5560 compatible = "qcom,kaanapali-rpmhpd"; 5561 5562 operating-points-v2 = <&rpmhpd_opp_table>; 5563 5564 #power-domain-cells = <1>; 5565 5566 rpmhpd_opp_table: opp-table { 5567 compatible = "operating-points-v2"; 5568 5569 rpmhpd_opp_ret: opp-16 { 5570 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 5571 }; 5572 5573 rpmhpd_opp_low_svs_d3: opp-50 { 5574 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; 5575 }; 5576 5577 rpmhpd_opp_low_svs_d2_1: opp-51 { 5578 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2_1>; 5579 }; 5580 5581 rpmhpd_opp_low_svs_d2: opp-52 { 5582 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 5583 }; 5584 5585 rpmhpd_opp_low_svs_d1_1: opp-54 { 5586 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1_1>; 5587 }; 5588 5589 rpmhpd_opp_low_svs_d1: opp-56 { 5590 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 5591 }; 5592 5593 rpmhpd_opp_low_svs_d0: opp-60 { 5594 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 5595 }; 5596 5597 rpmhpd_opp_low_svs: opp-64 { 5598 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 5599 }; 5600 5601 rpmhpd_opp_low_svs_l0: opp-76 { 5602 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L0>; 5603 }; 5604 5605 rpmhpd_opp_low_svs_l1: opp-80 { 5606 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 5607 }; 5608 5609 rpmhpd_opp_low_svs_l2: opp-96 { 5610 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L2>; 5611 }; 5612 5613 rpmhpd_opp_svs: opp-128 { 5614 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 5615 }; 5616 5617 rpmhpd_opp_svs_l0: opp-144 { 5618 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 5619 }; 5620 5621 rpmhpd_opp_svs_l1: opp-192 { 5622 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 5623 }; 5624 5625 rpmhpd_opp_svs_l2: opp-224 { 5626 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 5627 }; 5628 5629 rpmhpd_opp_nom: opp-256 { 5630 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 5631 }; 5632 5633 rpmhpd_opp_nom_l1: opp-320 { 5634 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 5635 }; 5636 5637 rpmhpd_opp_nom_l2: opp-336 { 5638 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 5639 }; 5640 5641 rpmhpd_opp_turbo: opp-384 { 5642 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 5643 }; 5644 5645 rpmhpd_opp_turbo_l0: opp-400 { 5646 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L0>; 5647 }; 5648 5649 rpmhpd_opp_turbo_l1: opp-416 { 5650 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 5651 }; 5652 5653 rpmhpd_opp_turbo_l2: opp-432 { 5654 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 5655 }; 5656 5657 rpmhpd_opp_turbo_l3: opp-448 { 5658 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 5659 }; 5660 5661 rpmhpd_opp_turbo_l4: opp-452 { 5662 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 5663 }; 5664 5665 rpmhpd_opp_turbo_l5: opp-456 { 5666 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L5>; 5667 }; 5668 5669 rpmhpd_opp_super_turbo_no_cpr: opp-480 { 5670 opp-level = <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>; 5671 }; 5672 }; 5673 }; 5674 }; 5675 5676 nsp_noc: interconnect@260c0000 { 5677 compatible = "qcom,kaanapali-nsp-noc"; 5678 reg = <0x0 0x260c0000 0x0 0x21280>; 5679 qcom,bcm-voters = <&apps_bcm_voter>; 5680 #interconnect-cells = <2>; 5681 }; 5682 5683 remoteproc_cdsp: remoteproc@26300000 { 5684 compatible = "qcom,kaanapali-cdsp-pas", "qcom,sm8550-cdsp-pas"; 5685 reg = <0x0 0x26300000 0x0 0x10000>; 5686 5687 interrupts-extended = <&intc GIC_SPI 578 IRQ_TYPE_EDGE_RISING>, 5688 <&smp2p_cdsp_in 0 IRQ_TYPE_EDGE_RISING>, 5689 <&smp2p_cdsp_in 1 IRQ_TYPE_EDGE_RISING>, 5690 <&smp2p_cdsp_in 2 IRQ_TYPE_EDGE_RISING>, 5691 <&smp2p_cdsp_in 3 IRQ_TYPE_EDGE_RISING>, 5692 <&smp2p_cdsp_in 7 IRQ_TYPE_EDGE_RISING>; 5693 interrupt-names = "wdog", 5694 "fatal", 5695 "ready", 5696 "handover", 5697 "stop-ack", 5698 "shutdown-ack"; 5699 5700 clocks = <&rpmhcc RPMH_CXO_CLK>; 5701 clock-names = "xo"; 5702 5703 interconnects = <&nsp_noc MASTER_CDSP_PROC QCOM_ICC_TAG_ALWAYS 5704 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 5705 5706 power-domains = <&rpmhpd RPMHPD_CX>, 5707 <&rpmhpd RPMHPD_MXC>, 5708 <&rpmhpd RPMHPD_NSP>; 5709 power-domain-names = "cx", 5710 "mxc", 5711 "nsp"; 5712 5713 memory-region = <&cdsp_mem>, <&q6_cdsp_dtb_mem>; 5714 qcom,qmp = <&aoss_qmp>; 5715 qcom,smem-states = <&smp2p_cdsp_out 0>; 5716 qcom,smem-state-names = "stop"; 5717 5718 status = "disabled"; 5719 5720 glink-edge { 5721 interrupts-extended = <&ipcc IPCC_MPROC_CDSP 5722 IPCC_MPROC_SIGNAL_GLINK_QMP 5723 IRQ_TYPE_EDGE_RISING>; 5724 mboxes = <&ipcc IPCC_MPROC_CDSP 5725 IPCC_MPROC_SIGNAL_GLINK_QMP>; 5726 qcom,remote-pid = <5>; 5727 label = "cdsp"; 5728 5729 fastrpc { 5730 compatible = "qcom,kaanapali-fastrpc"; 5731 qcom,glink-channels = "fastrpcglink-apps-dsp"; 5732 label = "cdsp"; 5733 #address-cells = <1>; 5734 #size-cells = <0>; 5735 5736 compute-cb@1 { 5737 compatible = "qcom,fastrpc-compute-cb"; 5738 reg = <1>; 5739 iommus = <&apps_smmu 0x19c1 0x0>, 5740 <&apps_smmu 0x1961 0x0>, 5741 <&apps_smmu 0x0c21 0x0>, 5742 <&apps_smmu 0x0c01 0x40>; 5743 dma-coherent; 5744 }; 5745 5746 compute-cb@2 { 5747 compatible = "qcom,fastrpc-compute-cb"; 5748 reg = <2>; 5749 iommus = <&apps_smmu 0x1962 0x0>, 5750 <&apps_smmu 0x0c02 0x20>, 5751 <&apps_smmu 0x0c42 0x0>, 5752 <&apps_smmu 0x19c2 0x0>; 5753 dma-coherent; 5754 }; 5755 5756 compute-cb@3 { 5757 compatible = "qcom,fastrpc-compute-cb"; 5758 reg = <3>; 5759 iommus = <&apps_smmu 0x1963 0x0>, 5760 <&apps_smmu 0x0c23 0x0>, 5761 <&apps_smmu 0x0c03 0x40>, 5762 <&apps_smmu 0x19c3 0x0>; 5763 dma-coherent; 5764 }; 5765 5766 compute-cb@4 { 5767 compatible = "qcom,fastrpc-compute-cb"; 5768 reg = <4>; 5769 iommus = <&apps_smmu 0x1964 0x0>, 5770 <&apps_smmu 0x0c44 0x0>, 5771 <&apps_smmu 0x0c04 0x20>, 5772 <&apps_smmu 0x19c4 0x0>; 5773 dma-coherent; 5774 }; 5775 5776 compute-cb@5 { 5777 compatible = "qcom,fastrpc-compute-cb"; 5778 reg = <5>; 5779 iommus = <&apps_smmu 0x1965 0x0>, 5780 <&apps_smmu 0x0c45 0x0>, 5781 <&apps_smmu 0x0c05 0x20>, 5782 <&apps_smmu 0x19c5 0x0>; 5783 dma-coherent; 5784 }; 5785 5786 compute-cb@6 { 5787 compatible = "qcom,fastrpc-compute-cb"; 5788 reg = <6>; 5789 iommus = <&apps_smmu 0x1966 0x0>, 5790 <&apps_smmu 0x0c06 0x20>, 5791 <&apps_smmu 0x0c46 0x0>, 5792 <&apps_smmu 0x19c6 0x0>; 5793 dma-coherent; 5794 }; 5795 5796 compute-cb@7 { 5797 compatible = "qcom,fastrpc-compute-cb"; 5798 reg = <7>; 5799 iommus = <&apps_smmu 0x1967 0x0>, 5800 <&apps_smmu 0x0c27 0x0>, 5801 <&apps_smmu 0x0c07 0x40>, 5802 <&apps_smmu 0x19c7 0x0>; 5803 dma-coherent; 5804 }; 5805 5806 compute-cb@8 { 5807 compatible = "qcom,fastrpc-compute-cb"; 5808 reg = <8>; 5809 iommus = <&apps_smmu 0x1968 0x0>, 5810 <&apps_smmu 0x0c08 0x20>, 5811 <&apps_smmu 0x0c48 0x0>, 5812 <&apps_smmu 0x19c8 0x0>; 5813 dma-coherent; 5814 }; 5815 5816 compute-cb@12 { 5817 compatible = "qcom,fastrpc-compute-cb"; 5818 reg = <12>; 5819 iommus = <&apps_smmu 0x196c 0x0>, 5820 <&apps_smmu 0x0c2c 0x00>, 5821 <&apps_smmu 0x0c0c 0x40>, 5822 <&apps_smmu 0x19cc 0x0>; 5823 dma-coherent; 5824 }; 5825 5826 compute-cb@13 { 5827 compatible = "qcom,fastrpc-compute-cb"; 5828 reg = <13>; 5829 iommus = <&apps_smmu 0x196d 0x0>, 5830 <&apps_smmu 0x0c0d 0x40>, 5831 <&apps_smmu 0x0c2e 0x0>, 5832 <&apps_smmu 0x0c2d 0x0>, 5833 <&apps_smmu 0x19cd 0x0>; 5834 dma-coherent; 5835 }; 5836 }; 5837 }; 5838 }; 5839 5840 /* Cluster 0 */ 5841 pmu@310b3400 { 5842 compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; 5843 reg = <0x0 0x310b3400 0x0 0x600>; 5844 5845 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5846 5847 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5848 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5849 5850 operating-points-v2 = <&cpu_bwmon_opp_table>; 5851 5852 cpu_bwmon_opp_table: opp-table { 5853 compatible = "operating-points-v2"; 5854 5855 opp-0 { 5856 opp-peak-kBps = <2188000>; 5857 }; 5858 5859 opp-1 { 5860 opp-peak-kBps = <5412000>; 5861 }; 5862 5863 opp-2 { 5864 opp-peak-kBps = <6220000>; 5865 }; 5866 5867 opp-3 { 5868 opp-peak-kBps = <6832000>; 5869 }; 5870 5871 opp-4 { 5872 opp-peak-kBps = <8368000>; 5873 }; 5874 5875 opp-5 { 5876 opp-peak-kBps = <10944000>; 5877 }; 5878 5879 opp-6 { 5880 opp-peak-kBps = <12748000>; 5881 }; 5882 5883 opp-7 { 5884 opp-peak-kBps = <14744000>; 5885 }; 5886 5887 opp-8 { 5888 opp-peak-kBps = <16896000>; 5889 }; 5890 5891 opp-9 { 5892 opp-peak-kBps = <19120000>; 5893 }; 5894 5895 opp-10 { 5896 opp-peak-kBps = <21332000>; 5897 }; 5898 }; 5899 }; 5900 5901 /* Cluster 1 */ 5902 pmu@310b7400 { 5903 compatible = "qcom,kaanapali-cpu-bwmon", "qcom,sdm845-bwmon"; 5904 reg = <0x0 0x310b7400 0x0 0x600>; 5905 5906 interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL_HIGH>; 5907 5908 interconnects = <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 5909 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ACTIVE_ONLY>; 5910 5911 operating-points-v2 = <&cpu_bwmon_opp_table>; 5912 }; 5913 5914 gem_noc: interconnect@31100000 { 5915 compatible = "qcom,kaanapali-gem-noc"; 5916 reg = <0x0 0x31100000 0x0 0x153080>; 5917 qcom,bcm-voters = <&apps_bcm_voter>; 5918 #interconnect-cells = <2>; 5919 }; 5920 5921 system-cache-controller@31800000 { 5922 compatible = "qcom,kaanapali-llcc"; 5923 reg = <0x0 0x31800000 0x0 0x200000>, 5924 <0x0 0x32800000 0x0 0x200000>, 5925 <0x0 0x31c00000 0x0 0x200000>, 5926 <0x0 0x32c00000 0x0 0x200000>, 5927 <0x0 0x34800000 0x0 0x200000>, 5928 <0x0 0x34c00000 0x0 0x200000>; 5929 reg-names = "llcc0_base", 5930 "llcc1_base", 5931 "llcc2_base", 5932 "llcc3_base", 5933 "llcc_broadcast_base", 5934 "llcc_broadcast_and_base"; 5935 5936 interrupts = <GIC_SPI 266 IRQ_TYPE_LEVEL_HIGH>; 5937 }; 5938 5939 sram: sram@81f08000 { 5940 compatible = "mmio-sram"; 5941 reg = <0x0 0x81f08000 0x0 0x200>; 5942 5943 #address-cells = <1>; 5944 #size-cells = <1>; 5945 ranges = <0x0 0x0 0x81f08000 0x200>; 5946 5947 pdp_rx: scp-sram-section@0 { 5948 compatible = "arm,scmi-shmem"; 5949 reg = <0x0 0x80>; 5950 }; 5951 5952 pdp_tx: scp-sram-section@100 { 5953 compatible = "arm,scmi-shmem"; 5954 reg = <0x100 0x80>; 5955 }; 5956 }; 5957 }; 5958 5959 thermal-zones { 5960 cpullc-0-0-thermal { 5961 thermal-sensors = <&tsens0 0>; 5962 5963 trips { 5964 cpullc-0-0-hot { 5965 temperature = <120000>; 5966 hysteresis = <5000>; 5967 type = "hot"; 5968 }; 5969 5970 cpullc-0-0-critical { 5971 temperature = <125000>; 5972 hysteresis = <0>; 5973 type = "critical"; 5974 }; 5975 }; 5976 }; 5977 5978 cpullc-0-1-thermal { 5979 thermal-sensors = <&tsens0 1>; 5980 5981 trips { 5982 cpullc-0-1-hot { 5983 temperature = <120000>; 5984 hysteresis = <5000>; 5985 type = "hot"; 5986 }; 5987 5988 cpullc-0-1-critical { 5989 temperature = <125000>; 5990 hysteresis = <0>; 5991 type = "critical"; 5992 }; 5993 }; 5994 }; 5995 5996 qmx-0-0-thermal { 5997 thermal-sensors = <&tsens0 2>; 5998 5999 trips { 6000 qmx-0-0-hot { 6001 temperature = <120000>; 6002 hysteresis = <5000>; 6003 type = "hot"; 6004 }; 6005 6006 qmx-0-0-critical { 6007 temperature = <125000>; 6008 hysteresis = <0>; 6009 type = "critical"; 6010 }; 6011 }; 6012 }; 6013 6014 qmx-0-1-thermal { 6015 thermal-sensors = <&tsens0 3>; 6016 6017 trips { 6018 qmx-0-1-hot { 6019 temperature = <120000>; 6020 hysteresis = <5000>; 6021 type = "hot"; 6022 }; 6023 6024 qmx-0-1-critical { 6025 temperature = <125000>; 6026 hysteresis = <0>; 6027 type = "critical"; 6028 }; 6029 }; 6030 }; 6031 6032 qmx-0-2-thermal { 6033 thermal-sensors = <&tsens0 4>; 6034 6035 trips { 6036 qmx-0-2-hot { 6037 temperature = <120000>; 6038 hysteresis = <5000>; 6039 type = "hot"; 6040 }; 6041 6042 qmx-0-2-critical { 6043 temperature = <125000>; 6044 hysteresis = <0>; 6045 type = "critical"; 6046 }; 6047 }; 6048 }; 6049 6050 cpu-0-0-0-thermal { 6051 thermal-sensors = <&tsens1 0>; 6052 6053 trips { 6054 cpu-0-0-0-hot { 6055 temperature = <120000>; 6056 hysteresis = <5000>; 6057 type = "hot"; 6058 }; 6059 6060 cpu-0-0-0-critical { 6061 temperature = <125000>; 6062 hysteresis = <0>; 6063 type = "critical"; 6064 }; 6065 }; 6066 }; 6067 6068 cpu-0-0-1-thermal { 6069 thermal-sensors = <&tsens1 1>; 6070 6071 trips { 6072 cpu-0-0-1-hot { 6073 temperature = <120000>; 6074 hysteresis = <5000>; 6075 type = "hot"; 6076 }; 6077 6078 cpu-0-0-1-critical { 6079 temperature = <125000>; 6080 hysteresis = <0>; 6081 type = "critical"; 6082 }; 6083 }; 6084 }; 6085 6086 cpu-0-1-0-thermal { 6087 thermal-sensors = <&tsens1 2>; 6088 6089 trips { 6090 cpu-0-1-0-hot { 6091 temperature = <120000>; 6092 hysteresis = <5000>; 6093 type = "hot"; 6094 }; 6095 6096 cpu-0-1-0-critical { 6097 temperature = <125000>; 6098 hysteresis = <0>; 6099 type = "critical"; 6100 }; 6101 }; 6102 }; 6103 6104 cpu-0-1-1-thermal { 6105 thermal-sensors = <&tsens1 3>; 6106 6107 trips { 6108 cpu-0-1-1-hot { 6109 temperature = <120000>; 6110 hysteresis = <5000>; 6111 type = "hot"; 6112 }; 6113 6114 cpu-0-1-1-critical { 6115 temperature = <125000>; 6116 hysteresis = <0>; 6117 type = "critical"; 6118 }; 6119 }; 6120 }; 6121 6122 cpu-0-2-0-thermal { 6123 thermal-sensors = <&tsens1 4>; 6124 6125 trips { 6126 cpu-0-2-0-hot { 6127 temperature = <120000>; 6128 hysteresis = <5000>; 6129 type = "hot"; 6130 }; 6131 6132 cpu-0-2-0-critical { 6133 temperature = <125000>; 6134 hysteresis = <0>; 6135 type = "critical"; 6136 }; 6137 }; 6138 }; 6139 6140 cpu-0-2-1-thermal { 6141 thermal-sensors = <&tsens1 5>; 6142 6143 trips { 6144 cpu-0-2-1-hot { 6145 temperature = <120000>; 6146 hysteresis = <5000>; 6147 type = "hot"; 6148 }; 6149 6150 cpu-0-2-1-critical { 6151 temperature = <125000>; 6152 hysteresis = <0>; 6153 type = "critical"; 6154 }; 6155 }; 6156 }; 6157 6158 cpu-0-3-0-thermal { 6159 thermal-sensors = <&tsens1 6>; 6160 6161 trips { 6162 cpu-0-3-0-hot { 6163 temperature = <120000>; 6164 hysteresis = <5000>; 6165 type = "hot"; 6166 }; 6167 6168 cpu-0-3-0-critical { 6169 temperature = <125000>; 6170 hysteresis = <0>; 6171 type = "critical"; 6172 }; 6173 }; 6174 }; 6175 6176 cpu-0-3-1-thermal { 6177 thermal-sensors = <&tsens1 7>; 6178 6179 trips { 6180 cpu-0-3-1-hot { 6181 temperature = <120000>; 6182 hysteresis = <5000>; 6183 type = "hot"; 6184 }; 6185 6186 cpu-0-3-1-critical { 6187 temperature = <125000>; 6188 hysteresis = <0>; 6189 type = "critical"; 6190 }; 6191 }; 6192 }; 6193 6194 cpu-0-4-0-thermal { 6195 thermal-sensors = <&tsens1 8>; 6196 6197 trips { 6198 cpu-0-4-0-hot { 6199 temperature = <120000>; 6200 hysteresis = <5000>; 6201 type = "hot"; 6202 }; 6203 6204 cpu-0-4-0-critical { 6205 temperature = <125000>; 6206 hysteresis = <0>; 6207 type = "critical"; 6208 }; 6209 }; 6210 }; 6211 6212 cpu-0-4-1-thermal { 6213 thermal-sensors = <&tsens1 9>; 6214 6215 trips { 6216 cpu-0-4-1-hot { 6217 temperature = <120000>; 6218 hysteresis = <5000>; 6219 type = "hot"; 6220 }; 6221 6222 cpu-0-4-1-critical { 6223 temperature = <125000>; 6224 hysteresis = <0>; 6225 type = "critical"; 6226 }; 6227 }; 6228 }; 6229 6230 cpu-0-5-0-thermal { 6231 thermal-sensors = <&tsens1 10>; 6232 6233 trips { 6234 cpu-0-5-0-hot { 6235 temperature = <120000>; 6236 hysteresis = <5000>; 6237 type = "hot"; 6238 }; 6239 6240 cpu-0-5-0-critical { 6241 temperature = <125000>; 6242 hysteresis = <0>; 6243 type = "critical"; 6244 }; 6245 }; 6246 }; 6247 6248 cpu-0-5-1-thermal { 6249 thermal-sensors = <&tsens1 11>; 6250 6251 trips { 6252 cpu-0-5-1-hot { 6253 temperature = <120000>; 6254 hysteresis = <5000>; 6255 type = "hot"; 6256 }; 6257 6258 cpu-0-5-1-critical { 6259 temperature = <125000>; 6260 hysteresis = <0>; 6261 type = "critical"; 6262 }; 6263 }; 6264 }; 6265 6266 cpullc-1-0-thermal { 6267 thermal-sensors = <&tsens2 0>; 6268 6269 trips { 6270 cpullc-1-0-hot { 6271 temperature = <120000>; 6272 hysteresis = <5000>; 6273 type = "hot"; 6274 }; 6275 6276 cpullc-1-0-critical { 6277 temperature = <125000>; 6278 hysteresis = <0>; 6279 type = "critical"; 6280 }; 6281 }; 6282 }; 6283 6284 cpullc-1-1-thermal { 6285 thermal-sensors = <&tsens2 1>; 6286 6287 trips { 6288 cpullc-1-1-hot { 6289 temperature = <120000>; 6290 hysteresis = <5000>; 6291 type = "hot"; 6292 }; 6293 6294 cpullc-1-1-critical { 6295 temperature = <125000>; 6296 hysteresis = <0>; 6297 type = "critical"; 6298 }; 6299 }; 6300 }; 6301 6302 qmx-1-0-thermal { 6303 thermal-sensors = <&tsens2 2>; 6304 6305 trips { 6306 qmx-1-0-hot { 6307 temperature = <120000>; 6308 hysteresis = <5000>; 6309 type = "hot"; 6310 }; 6311 6312 qmx-1-0-critical { 6313 temperature = <125000>; 6314 hysteresis = <0>; 6315 type = "critical"; 6316 }; 6317 }; 6318 }; 6319 6320 qmx-1-1-thermal { 6321 thermal-sensors = <&tsens2 3>; 6322 6323 trips { 6324 qmx-1-1-hot { 6325 temperature = <120000>; 6326 hysteresis = <5000>; 6327 type = "hot"; 6328 }; 6329 6330 qmx-1-1-critical { 6331 temperature = <125000>; 6332 hysteresis = <0>; 6333 type = "critical"; 6334 }; 6335 }; 6336 }; 6337 6338 qmx-1-2-thermal { 6339 thermal-sensors = <&tsens2 4>; 6340 6341 trips { 6342 qmx-1-2-hot { 6343 temperature = <120000>; 6344 hysteresis = <5000>; 6345 type = "hot"; 6346 }; 6347 6348 qmx-1-2-critical { 6349 temperature = <125000>; 6350 hysteresis = <0>; 6351 type = "critical"; 6352 }; 6353 }; 6354 }; 6355 6356 qmx-1-3-thermal { 6357 thermal-sensors = <&tsens2 5>; 6358 6359 trips { 6360 qmx-1-3-hot { 6361 temperature = <120000>; 6362 hysteresis = <5000>; 6363 type = "hot"; 6364 }; 6365 6366 qmx-1-3-critical { 6367 temperature = <125000>; 6368 hysteresis = <0>; 6369 type = "critical"; 6370 }; 6371 }; 6372 }; 6373 6374 qmx-1-4-thermal { 6375 thermal-sensors = <&tsens2 6>; 6376 6377 trips { 6378 qmx-1-4-hot { 6379 temperature = <120000>; 6380 hysteresis = <5000>; 6381 type = "hot"; 6382 }; 6383 6384 qmx-1-4-critical { 6385 temperature = <125000>; 6386 hysteresis = <0>; 6387 type = "critical"; 6388 }; 6389 }; 6390 }; 6391 6392 cpu-1-0-0-thermal { 6393 thermal-sensors = <&tsens3 0>; 6394 6395 trips { 6396 cpu-1-0-0-hot { 6397 temperature = <120000>; 6398 hysteresis = <5000>; 6399 type = "hot"; 6400 }; 6401 6402 cpu-1-0-0-critical { 6403 temperature = <125000>; 6404 hysteresis = <0>; 6405 type = "critical"; 6406 }; 6407 }; 6408 }; 6409 6410 cpu-1-0-1-thermal { 6411 thermal-sensors = <&tsens3 1>; 6412 6413 trips { 6414 cpu-1-0-1-hot { 6415 temperature = <120000>; 6416 hysteresis = <5000>; 6417 type = "hot"; 6418 }; 6419 6420 cpu-1-0-1-critical { 6421 temperature = <125000>; 6422 hysteresis = <0>; 6423 type = "critical"; 6424 }; 6425 }; 6426 }; 6427 6428 cpu-1-1-0-thermal { 6429 thermal-sensors = <&tsens3 2>; 6430 6431 trips { 6432 cpu-1-1-0-hot { 6433 temperature = <120000>; 6434 hysteresis = <5000>; 6435 type = "hot"; 6436 }; 6437 6438 cpu-1-1-0-critical { 6439 temperature = <125000>; 6440 hysteresis = <0>; 6441 type = "critical"; 6442 }; 6443 }; 6444 }; 6445 6446 cpu-1-1-1-thermal { 6447 thermal-sensors = <&tsens3 3>; 6448 6449 trips { 6450 cpu-1-1-1-hot { 6451 temperature = <120000>; 6452 hysteresis = <5000>; 6453 type = "hot"; 6454 }; 6455 6456 cpu-1-1-1-critical { 6457 temperature = <125000>; 6458 hysteresis = <0>; 6459 type = "critical"; 6460 }; 6461 }; 6462 }; 6463 6464 nsphvx-0-thermal { 6465 thermal-sensors = <&tsens4 0>; 6466 6467 trips { 6468 nsphvx-0-hot { 6469 temperature = <120000>; 6470 hysteresis = <5000>; 6471 type = "hot"; 6472 }; 6473 6474 nsphvx-0-critical { 6475 temperature = <125000>; 6476 hysteresis = <0>; 6477 type = "critical"; 6478 }; 6479 }; 6480 }; 6481 6482 nsphvx-1-thermal { 6483 thermal-sensors = <&tsens4 1>; 6484 6485 trips { 6486 nsphvx-1-hot { 6487 temperature = <120000>; 6488 hysteresis = <5000>; 6489 type = "hot"; 6490 }; 6491 6492 nsphvx-1-critical { 6493 temperature = <125000>; 6494 hysteresis = <0>; 6495 type = "critical"; 6496 }; 6497 }; 6498 }; 6499 6500 nsphvx-2-thermal { 6501 thermal-sensors = <&tsens4 2>; 6502 6503 trips { 6504 nsphvx-2-hot { 6505 temperature = <120000>; 6506 hysteresis = <5000>; 6507 type = "hot"; 6508 }; 6509 6510 nsphvx-2-critical { 6511 temperature = <125000>; 6512 hysteresis = <0>; 6513 type = "critical"; 6514 }; 6515 }; 6516 }; 6517 6518 nsphvx-3-thermal { 6519 thermal-sensors = <&tsens4 3>; 6520 6521 trips { 6522 nsphvx-3-hot { 6523 temperature = <120000>; 6524 hysteresis = <5000>; 6525 type = "hot"; 6526 }; 6527 6528 nsphvx-3-critical { 6529 temperature = <125000>; 6530 hysteresis = <0>; 6531 type = "critical"; 6532 }; 6533 }; 6534 }; 6535 6536 nsphmx-0-thermal { 6537 thermal-sensors = <&tsens4 4>; 6538 6539 trips { 6540 nsphmx-0-hot { 6541 temperature = <120000>; 6542 hysteresis = <5000>; 6543 type = "hot"; 6544 }; 6545 6546 nsphmx-0-critical { 6547 temperature = <125000>; 6548 hysteresis = <0>; 6549 type = "critical"; 6550 }; 6551 }; 6552 }; 6553 6554 nsphmx-1-thermal { 6555 thermal-sensors = <&tsens4 5>; 6556 6557 trips { 6558 nsphmx-1-hot { 6559 temperature = <120000>; 6560 hysteresis = <5000>; 6561 type = "hot"; 6562 }; 6563 6564 nsphmx-1-critical { 6565 temperature = <125000>; 6566 hysteresis = <0>; 6567 type = "critical"; 6568 }; 6569 }; 6570 }; 6571 6572 nsphmx-2-thermal { 6573 thermal-sensors = <&tsens4 6>; 6574 6575 trips { 6576 nsphmx-2-hot { 6577 temperature = <120000>; 6578 hysteresis = <5000>; 6579 type = "hot"; 6580 }; 6581 6582 nsphmx-2-critical { 6583 temperature = <125000>; 6584 hysteresis = <0>; 6585 type = "critical"; 6586 }; 6587 }; 6588 }; 6589 6590 nsphmx-3-thermal { 6591 thermal-sensors = <&tsens4 7>; 6592 6593 trips { 6594 nsphmx-3-hot { 6595 temperature = <120000>; 6596 hysteresis = <5000>; 6597 type = "hot"; 6598 }; 6599 6600 nsphmx-3-critical { 6601 temperature = <125000>; 6602 hysteresis = <0>; 6603 type = "critical"; 6604 }; 6605 }; 6606 }; 6607 6608 gpuss-0-thermal { 6609 thermal-sensors = <&tsens5 0>; 6610 6611 trips { 6612 gpuss-0-hot { 6613 temperature = <120000>; 6614 hysteresis = <5000>; 6615 type = "hot"; 6616 }; 6617 6618 gpuss-0-critical { 6619 temperature = <125000>; 6620 hysteresis = <0>; 6621 type = "critical"; 6622 }; 6623 }; 6624 }; 6625 6626 gpuss-1-thermal { 6627 thermal-sensors = <&tsens5 1>; 6628 6629 trips { 6630 gpuss-1-hot { 6631 temperature = <120000>; 6632 hysteresis = <5000>; 6633 type = "hot"; 6634 }; 6635 6636 gpuss-1-critical { 6637 temperature = <125000>; 6638 hysteresis = <0>; 6639 type = "critical"; 6640 }; 6641 }; 6642 }; 6643 6644 gpuss-2-thermal { 6645 thermal-sensors = <&tsens5 2>; 6646 6647 trips { 6648 gpuss-2-hot { 6649 temperature = <120000>; 6650 hysteresis = <5000>; 6651 type = "hot"; 6652 }; 6653 6654 gpuss-2-critical { 6655 temperature = <125000>; 6656 hysteresis = <0>; 6657 type = "critical"; 6658 }; 6659 }; 6660 }; 6661 6662 gpuss-3-thermal { 6663 thermal-sensors = <&tsens5 3>; 6664 6665 trips { 6666 gpuss-3-hot { 6667 temperature = <120000>; 6668 hysteresis = <5000>; 6669 type = "hot"; 6670 }; 6671 6672 gpuss-3-critical { 6673 temperature = <125000>; 6674 hysteresis = <0>; 6675 type = "critical"; 6676 }; 6677 }; 6678 }; 6679 6680 gpuss-4-thermal { 6681 thermal-sensors = <&tsens5 4>; 6682 6683 trips { 6684 gpuss-4-hot { 6685 temperature = <120000>; 6686 hysteresis = <5000>; 6687 type = "hot"; 6688 }; 6689 6690 gpuss-4-critical { 6691 temperature = <125000>; 6692 hysteresis = <0>; 6693 type = "critical"; 6694 }; 6695 }; 6696 }; 6697 6698 gpuss-5-thermal { 6699 thermal-sensors = <&tsens5 5>; 6700 6701 trips { 6702 gpuss-5-hot { 6703 temperature = <120000>; 6704 hysteresis = <5000>; 6705 type = "hot"; 6706 }; 6707 6708 gpuss-5-critical { 6709 temperature = <125000>; 6710 hysteresis = <0>; 6711 type = "critical"; 6712 }; 6713 }; 6714 }; 6715 6716 gpuss-6-thermal { 6717 thermal-sensors = <&tsens5 6>; 6718 6719 trips { 6720 gpuss-6-hot { 6721 temperature = <120000>; 6722 hysteresis = <5000>; 6723 type = "hot"; 6724 }; 6725 6726 gpuss-6-critical { 6727 temperature = <125000>; 6728 hysteresis = <0>; 6729 type = "critical"; 6730 }; 6731 }; 6732 }; 6733 6734 gpuss-7-thermal { 6735 thermal-sensors = <&tsens5 7>; 6736 6737 trips { 6738 gpuss-7-hot { 6739 temperature = <120000>; 6740 hysteresis = <5000>; 6741 type = "hot"; 6742 }; 6743 6744 gpuss-7-critical { 6745 temperature = <125000>; 6746 hysteresis = <0>; 6747 type = "critical"; 6748 }; 6749 }; 6750 }; 6751 6752 gpuss-8-thermal { 6753 thermal-sensors = <&tsens5 8>; 6754 6755 trips { 6756 gpuss-8-hot { 6757 temperature = <120000>; 6758 hysteresis = <5000>; 6759 type = "hot"; 6760 }; 6761 6762 gpuss-8-critical { 6763 temperature = <125000>; 6764 hysteresis = <0>; 6765 type = "critical"; 6766 }; 6767 }; 6768 }; 6769 6770 gpuss-9-thermal { 6771 thermal-sensors = <&tsens5 9>; 6772 6773 trips { 6774 gpuss-9-hot { 6775 temperature = <120000>; 6776 hysteresis = <5000>; 6777 type = "hot"; 6778 }; 6779 6780 gpuss-9-critical { 6781 temperature = <125000>; 6782 hysteresis = <0>; 6783 type = "critical"; 6784 }; 6785 }; 6786 }; 6787 6788 gpuss-10-thermal { 6789 thermal-sensors = <&tsens5 10>; 6790 6791 trips { 6792 gpuss-10-hot { 6793 temperature = <120000>; 6794 hysteresis = <5000>; 6795 type = "hot"; 6796 }; 6797 6798 gpuss-10-critical { 6799 temperature = <125000>; 6800 hysteresis = <0>; 6801 type = "critical"; 6802 }; 6803 }; 6804 }; 6805 6806 ddr-thermal { 6807 thermal-sensors = <&tsens5 11>; 6808 6809 trips { 6810 ddr-hot { 6811 temperature = <120000>; 6812 hysteresis = <5000>; 6813 type = "hot"; 6814 }; 6815 6816 ddr-critical { 6817 temperature = <125000>; 6818 hysteresis = <0>; 6819 type = "critical"; 6820 }; 6821 }; 6822 }; 6823 6824 mdmss-0-thermal { 6825 thermal-sensors = <&tsens6 0>; 6826 6827 trips { 6828 mdmss-0-hot { 6829 temperature = <120000>; 6830 hysteresis = <5000>; 6831 type = "hot"; 6832 }; 6833 6834 mdmss-0-critical { 6835 temperature = <125000>; 6836 hysteresis = <0>; 6837 type = "critical"; 6838 }; 6839 }; 6840 }; 6841 6842 mdmss-1-thermal { 6843 thermal-sensors = <&tsens6 1>; 6844 trips { 6845 mdmss-1-hot { 6846 temperature = <120000>; 6847 hysteresis = <5000>; 6848 type = "hot"; 6849 }; 6850 6851 mdmss-1-critical { 6852 temperature = <125000>; 6853 hysteresis = <0>; 6854 type = "critical"; 6855 }; 6856 }; 6857 }; 6858 6859 mdmss-2-thermal { 6860 thermal-sensors = <&tsens6 2>; 6861 6862 trips { 6863 mdmss-2-hot { 6864 temperature = <120000>; 6865 hysteresis = <5000>; 6866 type = "hot"; 6867 }; 6868 6869 mdmss-2-critical { 6870 temperature = <125000>; 6871 hysteresis = <0>; 6872 type = "critical"; 6873 }; 6874 }; 6875 }; 6876 6877 mdmss-3-thermal { 6878 thermal-sensors = <&tsens6 3>; 6879 6880 trips { 6881 mdmss-3-hot { 6882 temperature = <120000>; 6883 hysteresis = <5000>; 6884 type = "hot"; 6885 }; 6886 6887 mdmss-3-critical { 6888 temperature = <125000>; 6889 hysteresis = <0>; 6890 type = "critical"; 6891 }; 6892 }; 6893 }; 6894 6895 camera-0-thermal { 6896 thermal-sensors = <&tsens6 4>; 6897 6898 trips { 6899 camera-0-hot { 6900 temperature = <120000>; 6901 hysteresis = <5000>; 6902 type = "hot"; 6903 }; 6904 6905 camera-0-critical { 6906 temperature = <125000>; 6907 hysteresis = <0>; 6908 type = "critical"; 6909 }; 6910 }; 6911 }; 6912 6913 camera-1-thermal { 6914 thermal-sensors = <&tsens6 5>; 6915 6916 trips { 6917 camera-1-hot { 6918 temperature = <120000>; 6919 hysteresis = <5000>; 6920 type = "hot"; 6921 }; 6922 6923 camera-1-critical { 6924 temperature = <125000>; 6925 hysteresis = <0>; 6926 type = "critical"; 6927 }; 6928 }; 6929 }; 6930 6931 video-thermal { 6932 thermal-sensors = <&tsens6 6>; 6933 6934 trips { 6935 video-hot { 6936 temperature = <120000>; 6937 hysteresis = <5000>; 6938 type = "hot"; 6939 }; 6940 6941 video-critical { 6942 temperature = <125000>; 6943 hysteresis = <0>; 6944 type = "critical"; 6945 }; 6946 }; 6947 }; 6948 }; 6949 6950 timer { 6951 compatible = "arm,armv8-timer"; 6952 6953 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 6954 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 6955 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 6956 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 6957 }; 6958 6959 tpdm-cdsp-llm { 6960 compatible = "qcom,coresight-static-tpdm"; 6961 qcom,cmb-element-bits = <32>; 6962 6963 out-ports { 6964 port { 6965 tpdm_cdsp_llm_out: endpoint { 6966 remote-endpoint = <&tpda_cdsp_in1>; 6967 }; 6968 }; 6969 }; 6970 }; 6971 6972 tpdm-cdsp-llm2 { 6973 compatible = "qcom,coresight-static-tpdm"; 6974 qcom,cmb-element-bits = <32>; 6975 6976 out-ports { 6977 port { 6978 tpdm_cdsp_llm2_out: endpoint { 6979 remote-endpoint = <&tpda_cdsp_in2>; 6980 }; 6981 }; 6982 }; 6983 }; 6984 6985 tpdm-modem1 { 6986 compatible = "qcom,coresight-static-tpdm"; 6987 qcom,cmb-element-bits = <32>; 6988 6989 out-ports { 6990 port { 6991 tpdm_modem1_out: endpoint { 6992 remote-endpoint = <&tpda_modem_in1>; 6993 }; 6994 }; 6995 }; 6996 }; 6997 6998 tpdm-modem2 { 6999 compatible = "qcom,coresight-static-tpdm"; 7000 qcom,cmb-element-bits = <64>; 7001 7002 out-ports { 7003 port { 7004 tpdm_modem2_out: endpoint { 7005 remote-endpoint = <&tpda_modem_in2>; 7006 }; 7007 }; 7008 }; 7009 }; 7010}; 7011