1// SPDX-License-Identifier: BSD-3-Clause 2/* 3 * Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries. 4 */ 5 6#include <dt-bindings/clock/qcom,eliza-gcc.h> 7#include <dt-bindings/clock/qcom,eliza-tcsr.h> 8#include <dt-bindings/clock/qcom,rpmh.h> 9#include <dt-bindings/interconnect/qcom,eliza-rpmh.h> 10#include <dt-bindings/interconnect/qcom,icc.h> 11#include <dt-bindings/interconnect/qcom,osm-l3.h> 12#include <dt-bindings/interrupt-controller/arm-gic.h> 13#include <dt-bindings/power/qcom,rpmhpd.h> 14#include <dt-bindings/soc/qcom,rpmh-rsc.h> 15 16/ { 17 interrupt-parent = <&intc>; 18 19 #address-cells = <2>; 20 #size-cells = <2>; 21 22 cpus { 23 #address-cells = <2>; 24 #size-cells = <0>; 25 26 cpu0: cpu@0 { 27 device_type = "cpu"; 28 compatible = "arm,cortex-a520"; 29 reg = <0x0 0x0>; 30 31 clocks = <&cpufreq_hw 0>; 32 33 power-domains = <&cpu_pd0>; 34 power-domain-names = "psci"; 35 36 enable-method = "psci"; 37 next-level-cache = <&l2_0>; 38 capacity-dmips-mhz = <1024>; 39 dynamic-power-coefficient = <100>; 40 41 qcom,freq-domain = <&cpufreq_hw 0>; 42 43 l2_0: l2-cache { 44 compatible = "cache"; 45 cache-level = <2>; 46 cache-unified; 47 next-level-cache = <&l3>; 48 49 l3: l3-cache { 50 compatible = "cache"; 51 cache-level = <3>; 52 cache-unified; 53 }; 54 }; 55 }; 56 57 cpu1: cpu@100 { 58 device_type = "cpu"; 59 compatible = "arm,cortex-a520"; 60 reg = <0x0 0x100>; 61 62 clocks = <&cpufreq_hw 0>; 63 64 power-domains = <&cpu_pd1>; 65 power-domain-names = "psci"; 66 67 enable-method = "psci"; 68 next-level-cache = <&l2_0>; 69 capacity-dmips-mhz = <1024>; 70 dynamic-power-coefficient = <100>; 71 72 qcom,freq-domain = <&cpufreq_hw 0>; 73 }; 74 75 cpu2: cpu@200 { 76 device_type = "cpu"; 77 compatible = "arm,cortex-a520"; 78 reg = <0x0 0x200>; 79 80 clocks = <&cpufreq_hw 0>; 81 82 power-domains = <&cpu_pd2>; 83 power-domain-names = "psci"; 84 85 enable-method = "psci"; 86 next-level-cache = <&l2_2>; 87 capacity-dmips-mhz = <1024>; 88 dynamic-power-coefficient = <100>; 89 90 qcom,freq-domain = <&cpufreq_hw 0>; 91 92 l2_2: l2-cache { 93 compatible = "cache"; 94 cache-level = <2>; 95 cache-unified; 96 next-level-cache = <&l3>; 97 }; 98 }; 99 100 cpu3: cpu@300 { 101 device_type = "cpu"; 102 compatible = "arm,cortex-a720"; 103 reg = <0x0 0x300>; 104 105 clocks = <&cpufreq_hw 1>; 106 107 power-domains = <&cpu_pd3>; 108 power-domain-names = "psci"; 109 110 enable-method = "psci"; 111 next-level-cache = <&l2_3>; 112 capacity-dmips-mhz = <1792>; 113 dynamic-power-coefficient = <238>; 114 115 qcom,freq-domain = <&cpufreq_hw 1>; 116 117 l2_3: l2-cache { 118 compatible = "cache"; 119 cache-level = <2>; 120 cache-unified; 121 next-level-cache = <&l3>; 122 }; 123 }; 124 125 cpu4: cpu@400 { 126 device_type = "cpu"; 127 compatible = "arm,cortex-a720"; 128 reg = <0x0 0x400>; 129 130 clocks = <&cpufreq_hw 1>; 131 132 power-domains = <&cpu_pd4>; 133 power-domain-names = "psci"; 134 135 enable-method = "psci"; 136 next-level-cache = <&l2_4>; 137 capacity-dmips-mhz = <1792>; 138 dynamic-power-coefficient = <238>; 139 140 qcom,freq-domain = <&cpufreq_hw 1>; 141 142 l2_4: l2-cache { 143 compatible = "cache"; 144 cache-level = <2>; 145 cache-unified; 146 next-level-cache = <&l3>; 147 }; 148 }; 149 150 cpu5: cpu@500 { 151 device_type = "cpu"; 152 compatible = "arm,cortex-a720"; 153 reg = <0x0 0x500>; 154 155 clocks = <&cpufreq_hw 1>; 156 157 power-domains = <&cpu_pd5>; 158 power-domain-names = "psci"; 159 160 enable-method = "psci"; 161 next-level-cache = <&l2_5>; 162 capacity-dmips-mhz = <1792>; 163 dynamic-power-coefficient = <238>; 164 165 qcom,freq-domain = <&cpufreq_hw 1>; 166 167 l2_5: l2-cache { 168 compatible = "cache"; 169 cache-level = <2>; 170 cache-unified; 171 next-level-cache = <&l3>; 172 }; 173 }; 174 175 cpu6: cpu@600 { 176 device_type = "cpu"; 177 compatible = "arm,cortex-a720"; 178 reg = <0x0 0x600>; 179 180 clocks = <&cpufreq_hw 1>; 181 182 power-domains = <&cpu_pd6>; 183 power-domain-names = "psci"; 184 185 enable-method = "psci"; 186 next-level-cache = <&l2_6>; 187 capacity-dmips-mhz = <1792>; 188 dynamic-power-coefficient = <238>; 189 190 qcom,freq-domain = <&cpufreq_hw 1>; 191 192 l2_6: l2-cache { 193 compatible = "cache"; 194 cache-level = <2>; 195 cache-unified; 196 next-level-cache = <&l3>; 197 }; 198 }; 199 200 cpu7: cpu@700 { 201 device_type = "cpu"; 202 compatible = "arm,cortex-x3"; 203 reg = <0x0 0x700>; 204 205 clocks = <&cpufreq_hw 2>; 206 207 power-domains = <&cpu_pd7>; 208 power-domain-names = "psci"; 209 210 enable-method = "psci"; 211 next-level-cache = <&l2_7>; 212 capacity-dmips-mhz = <1894>; 213 dynamic-power-coefficient = <588>; 214 215 qcom,freq-domain = <&cpufreq_hw 2>; 216 217 l2_7: l2-cache { 218 compatible = "cache"; 219 cache-level = <2>; 220 cache-unified; 221 next-level-cache = <&l3>; 222 }; 223 }; 224 225 cpu-map { 226 cluster0 { 227 core0 { 228 cpu = <&cpu0>; 229 }; 230 231 core1 { 232 cpu = <&cpu1>; 233 }; 234 235 core2 { 236 cpu = <&cpu2>; 237 }; 238 239 core3 { 240 cpu = <&cpu3>; 241 }; 242 243 core4 { 244 cpu = <&cpu4>; 245 }; 246 247 core5 { 248 cpu = <&cpu5>; 249 }; 250 251 core6 { 252 cpu = <&cpu6>; 253 }; 254 255 core7 { 256 cpu = <&cpu7>; 257 }; 258 }; 259 }; 260 261 idle-states { 262 entry-method = "psci"; 263 264 cluster0_c4: cpu-sleep-0 { 265 compatible = "arm,idle-state"; 266 idle-state-name = "silver-rail-power-collapse"; 267 arm,psci-suspend-param = <0x40000004>; 268 entry-latency-us = <550>; 269 exit-latency-us = <750>; 270 min-residency-us = <6700>; 271 }; 272 273 cluster1_c4: cpu-sleep-1 { 274 compatible = "arm,idle-state"; 275 idle-state-name = "gold-rail-power-collapse"; 276 arm,psci-suspend-param = <0x40000004>; 277 entry-latency-us = <550>; 278 exit-latency-us = <1050>; 279 min-residency-us = <7951>; 280 }; 281 282 cluster2_c4: cpu-sleep-2 { 283 compatible = "arm,idle-state"; 284 idle-state-name = "gold-plus-rail-power-collapse"; 285 arm,psci-suspend-param = <0x40000004>; 286 entry-latency-us = <500>; 287 exit-latency-us = <1350>; 288 min-residency-us = <7480>; 289 }; 290 }; 291 292 domain-idle-states { 293 cluster_sleep_0: cluster-sleep-0 { 294 compatible = "domain-idle-state"; 295 arm,psci-suspend-param = <0x41000044>; 296 entry-latency-us = <750>; 297 exit-latency-us = <2350>; 298 min-residency-us = <9144>; 299 }; 300 301 cluster_sleep_1: cluster-sleep-1 { 302 compatible = "domain-idle-state"; 303 arm,psci-suspend-param = <0x4100b344>; 304 entry-latency-us = <2800>; 305 exit-latency-us = <4400>; 306 min-residency-us = <10150>; 307 }; 308 }; 309 }; 310 311 firmware { 312 scm: scm { 313 compatible = "qcom,scm-eliza", "qcom,scm"; 314 interconnects = <&aggre2_noc MASTER_CRYPTO QCOM_ICC_TAG_ALWAYS 315 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>; 316 qcom,dload-mode = <&tcsr 0x1a000>; 317 }; 318 }; 319 320 clk_virt: interconnect-0 { 321 compatible = "qcom,eliza-clk-virt"; 322 #interconnect-cells = <2>; 323 qcom,bcm-voters = <&apps_bcm_voter>; 324 }; 325 326 mc_virt: interconnect-1 { 327 compatible = "qcom,eliza-mc-virt"; 328 #interconnect-cells = <2>; 329 qcom,bcm-voters = <&apps_bcm_voter>; 330 }; 331 332 memory@a0000000 { 333 device_type = "memory"; 334 /* We expect the bootloader to fill in the size */ 335 reg = <0x0 0xa0000000 0x0 0x0>; 336 }; 337 338 psci { 339 compatible = "arm,psci-1.0"; 340 method = "smc"; 341 342 cpu_pd0: power-domain-cpu0 { 343 #power-domain-cells = <0>; 344 power-domains = <&cluster_pd>; 345 domain-idle-states = <&cluster0_c4>; 346 }; 347 348 cpu_pd1: power-domain-cpu1 { 349 #power-domain-cells = <0>; 350 power-domains = <&cluster_pd>; 351 domain-idle-states = <&cluster0_c4>; 352 }; 353 354 cpu_pd2: power-domain-cpu2 { 355 #power-domain-cells = <0>; 356 power-domains = <&cluster_pd>; 357 domain-idle-states = <&cluster0_c4>; 358 }; 359 360 cpu_pd3: power-domain-cpu3 { 361 #power-domain-cells = <0>; 362 power-domains = <&cluster_pd>; 363 domain-idle-states = <&cluster1_c4>; 364 }; 365 366 cpu_pd4: power-domain-cpu4 { 367 #power-domain-cells = <0>; 368 power-domains = <&cluster_pd>; 369 domain-idle-states = <&cluster1_c4>; 370 }; 371 372 cpu_pd5: power-domain-cpu5 { 373 #power-domain-cells = <0>; 374 power-domains = <&cluster_pd>; 375 domain-idle-states = <&cluster1_c4>; 376 }; 377 378 cpu_pd6: power-domain-cpu6 { 379 #power-domain-cells = <0>; 380 power-domains = <&cluster_pd>; 381 domain-idle-states = <&cluster1_c4>; 382 }; 383 384 cpu_pd7: power-domain-cpu7 { 385 #power-domain-cells = <0>; 386 power-domains = <&cluster_pd>; 387 domain-idle-states = <&cluster2_c4>; 388 }; 389 390 cluster_pd: power-domain-cluster { 391 #power-domain-cells = <0>; 392 domain-idle-states = <&cluster_sleep_0>, 393 <&cluster_sleep_1>; 394 }; 395 }; 396 397 reserved-memory { 398 #address-cells = <2>; 399 #size-cells = <2>; 400 ranges; 401 402 gunyah_hyp_mem: gunyah-hyp@80000000 { 403 reg = <0x0 0x80000000 0x0 0xe00000>; 404 no-map; 405 }; 406 407 cpusys_vm_mem: cpusys-vm-mem@80e00000 { 408 reg = <0x0 0x80e00000 0x0 0x40000>; 409 no-map; 410 }; 411 412 cpucp_mem: cpucp@81200000 { 413 reg = <0x0 0x81200000 0x0 0x200000>; 414 no-map; 415 }; 416 417 xbl_dtlog_mem: xbl-dtlog@81a00000 { 418 reg = <0x0 0x81a00000 0x0 0x40000>; 419 no-map; 420 }; 421 422 aop_image_mem: aop-image@81c00000 { 423 reg = <0x0 0x81c00000 0x0 0x60000>; 424 no-map; 425 }; 426 427 aop_cmd_db_mem: aop-cmd-db@81c60000 { 428 compatible = "qcom,cmd-db"; 429 reg = <0x0 0x81c60000 0x0 0x20000>; 430 no-map; 431 }; 432 433 /* Merged aop_config, tme_crash_dump, tme_log and uefi_log regions */ 434 aop_tme_uefi_merged_mem: aop-tme-uefi-merged@81c80000 { 435 reg = <0x0 0x81c80000 0x0 0x74000>; 436 no-map; 437 }; 438 439 /* Secdata region can be reused by apps */ 440 smem_mem: smem@81d00000 { 441 compatible = "qcom,smem"; 442 reg = <0x0 0x81d00000 0x0 0x200000>; 443 hwlocks = <&tcsr_mutex 3>; 444 no-map; 445 }; 446 447 cpucp_scandump_mem: cpucp-scandump@82000000 { 448 reg = <0x0 0x82200000 0x0 0x180000>; 449 no-map; 450 }; 451 452 adsp_mhi_mem: adsp-mhi@82380000 { 453 reg = <0x0 0x82380000 0x0 0x20000>; 454 no-map; 455 }; 456 457 soccp_sdi_mem: soccp-sdi@823a0000 { 458 reg = <0x0 0x823a0000 0x0 0x40000>; 459 no-map; 460 }; 461 462 pmic_minii_dump_mem: pmic-minii-dump@823e0000 { 463 reg = <0x0 0x823e0000 0x0 0x80000>; 464 no-map; 465 }; 466 467 pvmfw_mem: pvmfw@824a0000 { 468 reg = <0x0 0x824a0000 0x0 0x100000>; 469 no-map; 470 }; 471 472 hyp_db_mem: hyp-db@825a0000 { 473 reg = <0x0 0x825a0000 0x0 0x60000>; 474 no-map; 475 }; 476 477 global_sync_mem: global-sync@82600000 { 478 reg = <0x0 0x82600000 0x0 0x100000>; 479 no-map; 480 }; 481 482 tz_stat_mem: tz-stat@82700000 { 483 reg = <0x0 0x82700000 0x0 0x100000>; 484 no-map; 485 }; 486 487 qdss_mem: qdss@82800000 { 488 reg = <0x0 0x82800000 0x0 0x2000000>; 489 no-map; 490 }; 491 492 dsm_partition_1_mem: dsm-partition-1@84a00000 { 493 reg = <0x0 0x84a00000 0x0 0x3700000>; 494 no-map; 495 }; 496 497 mpss_mem: mpss@88100000 { 498 reg = <0x0 0x88100000 0x0 0xcd00000>; 499 no-map; 500 }; 501 502 q6_mpss_dtb_mem: q6-mpss-dtb@94e00000 { 503 reg = <0x0 0x94e00000 0x0 0x80000>; 504 no-map; 505 }; 506 507 ipa_fw_mem: ipa-fw@94e80000 { 508 reg = <0x0 0x94e80000 0x0 0x10000>; 509 no-map; 510 }; 511 512 ipa_gsi_mem: ipa-gsi@94e90000 { 513 reg = <0x0 0x94e90000 0x0 0xa000>; 514 no-map; 515 }; 516 517 gpu_micro_code_mem: gpu-micro-code@94e9a000 { 518 reg = <0x0 0x94e9a000 0x0 0x2000>; 519 no-map; 520 }; 521 522 camera_mem: camera@94f00000 { 523 reg = <0x0 0x94f00000 0x0 0x800000>; 524 no-map; 525 }; 526 527 camera_2_mem: camera-2@95700000 { 528 reg = <0x0 0x95700000 0x0 0x800000>; 529 no-map; 530 }; 531 532 video_mem: video@95f00000 { 533 reg = <0x0 0x95f00000 0x0 0x800000>; 534 no-map; 535 }; 536 537 soccp_mem: soccp@96700000 { 538 reg = <0x0 0x96700000 0x0 0x180000>; 539 no-map; 540 }; 541 542 wpss_mem: wpss@97000000 { 543 reg = <0x0 0x97000000 0x0 0x1900000>; 544 no-map; 545 }; 546 547 cdsp_mem: cdsp@98900000 { 548 reg = <0x0 0x98900000 0x0 0x1400000>; 549 no-map; 550 }; 551 552 q6_cdsp_dtb_mem: q6-cdsp-dtb@99d00000 { 553 reg = <0x0 0x99d00000 0x0 0x80000>; 554 no-map; 555 }; 556 557 q6_adsp_dtb_mem: q6-adsp-dtb@99d80000 { 558 reg = <0x0 0x99d80000 0x0 0x80000>; 559 no-map; 560 }; 561 562 adspslpi_mem: adspslpi@99e00000 { 563 reg = <0x0 0x99e00000 0x0 0x2a00000>; 564 no-map; 565 }; 566 567 wlan_msa_mem: wlan-msa@a6400000 { 568 reg = <0x0 0xa6400000 0x0 0xc00000>; 569 no-map; 570 }; 571 572 xbl_ramdump_mem: xbl-ramdump@b8000000 { 573 reg = <0x0 0xb8000000 0x0 0x1c0000>; 574 no-map; 575 }; 576 577 /* Merged tz_reserved, xbl_sc, and qtee regions */ 578 tz_merged_mem: tz-merged@d8000000 { 579 reg = <0x0 0xd8000000 0x0 0x600000>; 580 no-map; 581 }; 582 583 trust_ui_vm_mem: trust-ui-vm@f3800000 { 584 reg = <0x0 0xf3800000 0x0 0x4400000>; 585 no-map; 586 }; 587 588 oem_vm_mem: oem-vm@f7c00000 { 589 reg = <0x0 0xf7c00000 0x0 0x4c00000>; 590 no-map; 591 }; 592 593 llcc_lpi_mem: llcc-lpi@ff800000 { 594 reg = <0x0 0xff800000 0x0 0x180000>; 595 no-map; 596 }; 597 }; 598 599 soc: soc@0 { 600 compatible = "simple-bus"; 601 602 #address-cells = <2>; 603 #size-cells = <2>; 604 dma-ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 605 ranges = <0x0 0x0 0x0 0x0 0x10 0x0>; 606 607 gcc: clock-controller@100000 { 608 compatible = "qcom,eliza-gcc"; 609 reg = <0x0 0x00100000 0x0 0x1f4200>; 610 611 clocks = <&bi_tcxo_div2>, 612 <&sleep_clk>, 613 <0>, 614 <0>, 615 <&ufs_mem_phy 0>, 616 <&ufs_mem_phy 1>, 617 <&ufs_mem_phy 2>, 618 <0>; 619 620 power-domains = <&rpmhpd RPMHPD_CX>; 621 622 #clock-cells = <1>; 623 #reset-cells = <1>; 624 #power-domain-cells = <1>; 625 }; 626 627 qupv3_2: geniqup@8c0000 { 628 compatible = "qcom,geni-se-qup"; 629 reg = <0x0 0x008c0000 0x0 0x2000>; 630 631 clocks = <&gcc GCC_QUPV3_WRAP_2_M_AHB_CLK>, 632 <&gcc GCC_QUPV3_WRAP_2_S_AHB_CLK>; 633 clock-names = "m-ahb", 634 "s-ahb"; 635 636 iommus = <&apps_smmu 0x423 0x0>; 637 638 #address-cells = <2>; 639 #size-cells = <2>; 640 ranges; 641 642 uart14: serial@894000 { 643 compatible = "qcom,geni-uart"; 644 reg = <0x0 0x00894000 0x0 0x4000>; 645 646 interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL_HIGH>; 647 648 clocks = <&gcc GCC_QUPV3_WRAP2_S5_CLK>; 649 clock-names = "se"; 650 651 interconnects = <&clk_virt MASTER_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS 652 &clk_virt SLAVE_QUP_CORE_2 QCOM_ICC_TAG_ALWAYS>, 653 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ALWAYS 654 &config_noc SLAVE_QUP_2 QCOM_ICC_TAG_ALWAYS>; 655 interconnect-names = "qup-core", 656 "qup-config"; 657 658 pinctrl-0 = <&qup_uart14_default>; 659 pinctrl-names = "default"; 660 661 status = "disabled"; 662 }; 663 }; 664 665 config_noc: interconnect@1600000 { 666 compatible = "qcom,eliza-cnoc-cfg"; 667 reg = <0x0 0x01600000 0x0 0x5200>; 668 qcom,bcm-voters = <&apps_bcm_voter>; 669 #interconnect-cells = <2>; 670 }; 671 672 cnoc_main: interconnect@1500000 { 673 compatible = "qcom,eliza-cnoc-main"; 674 reg = <0x0 0x01500000 0x0 0x16080>; 675 qcom,bcm-voters = <&apps_bcm_voter>; 676 #interconnect-cells = <2>; 677 }; 678 679 system_noc: interconnect@1680000 { 680 compatible = "qcom,eliza-system-noc"; 681 reg = <0x0 0x01680000 0x0 0x40000>; 682 qcom,bcm-voters = <&apps_bcm_voter>; 683 #interconnect-cells = <2>; 684 }; 685 686 pcie_noc: interconnect@16c0000 { 687 compatible = "qcom,eliza-pcie-anoc"; 688 reg = <0x0 0x016c0000 0x0 0x11400>; 689 qcom,bcm-voters = <&apps_bcm_voter>; 690 clocks = <&gcc GCC_AGGRE_NOC_PCIE_AXI_CLK>, 691 <&gcc GCC_CFG_NOC_PCIE_ANOC_AHB_CLK>; 692 #interconnect-cells = <2>; 693 }; 694 695 aggre1_noc: interconnect@16e0000 { 696 compatible = "qcom,eliza-aggre1-noc"; 697 reg = <0x0 0x016e0000 0x0 0x16400>; 698 qcom,bcm-voters = <&apps_bcm_voter>; 699 clocks = <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 700 <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>; 701 #interconnect-cells = <2>; 702 }; 703 704 aggre2_noc: interconnect@1700000 { 705 compatible = "qcom,eliza-aggre2-noc"; 706 reg = <0x0 0x01700000 0x0 0x1f400>; 707 qcom,bcm-voters = <&apps_bcm_voter>; 708 clocks = <&rpmhcc RPMH_IPA_CLK>; 709 #interconnect-cells = <2>; 710 }; 711 712 mmss_noc: interconnect@1780000 { 713 compatible = "qcom,eliza-mmss-noc"; 714 reg = <0x0 0x01780000 0x0 0x7d800>; 715 qcom,bcm-voters = <&apps_bcm_voter>; 716 #interconnect-cells = <2>; 717 }; 718 719 ufs_mem_phy: phy@1d80000 { 720 compatible = "qcom,eliza-qmp-ufs-phy", 721 "qcom,sm8650-qmp-ufs-phy"; 722 reg = <0x0 0x01d80000 0x0 0x2000>; 723 724 clocks = <&rpmhcc RPMH_CXO_CLK>, 725 <&gcc GCC_UFS_PHY_PHY_AUX_CLK>, 726 <&tcsr TCSR_UFS_CLKREF_EN>; 727 clock-names = "ref", 728 "ref_aux", 729 "qref"; 730 731 resets = <&ufs_mem_hc 0>; 732 reset-names = "ufsphy"; 733 734 power-domains = <&gcc GCC_UFS_MEM_PHY_GDSC>; 735 736 #clock-cells = <1>; 737 #phy-cells = <0>; 738 739 status = "disabled"; 740 }; 741 742 ufs_mem_hc: ufshc@1d84000 { 743 compatible = "qcom,eliza-ufshc", 744 "qcom,ufshc", 745 "jedec,ufs-2.0"; 746 reg = <0x0 0x01d84000 0x0 0x3000>, 747 <0x0 0x01da0000 0x0 0x15000>; 748 reg-names = "std", 749 "mcq"; 750 751 interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>; 752 753 clocks = <&gcc GCC_UFS_PHY_AXI_CLK>, 754 <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>, 755 <&gcc GCC_UFS_PHY_AHB_CLK>, 756 <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>, 757 <&rpmhcc RPMH_LN_BB_CLK3>, 758 <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>, 759 <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>, 760 <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>; 761 clock-names = "core_clk", 762 "bus_aggr_clk", 763 "iface_clk", 764 "core_clk_unipro", 765 "ref_clk", 766 "tx_lane0_sync_clk", 767 "rx_lane0_sync_clk", 768 "rx_lane1_sync_clk"; 769 770 operating-points-v2 = <&ufs_opp_table>; 771 772 resets = <&gcc GCC_UFS_PHY_BCR>; 773 reset-names = "rst"; 774 775 interconnects = <&aggre1_noc MASTER_UFS_MEM QCOM_ICC_TAG_ALWAYS 776 &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, 777 <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIVE_ONLY 778 &config_noc SLAVE_UFS_MEM_CFG QCOM_ICC_TAG_ACTIVE_ONLY>; 779 interconnect-names = "ufs-ddr", 780 "cpu-ufs"; 781 782 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 783 required-opps = <&rpmhpd_opp_nom>; 784 785 iommus = <&apps_smmu 0x60 0x0>; 786 dma-coherent; 787 788 msi-parent = <&gic_its 0x60>; 789 790 lanes-per-direction = <2>; 791 qcom,ice = <&ice>; 792 793 phys = <&ufs_mem_phy>; 794 phy-names = "ufsphy"; 795 796 #reset-cells = <1>; 797 798 status = "disabled"; 799 800 ufs_opp_table: opp-table { 801 compatible = "operating-points-v2"; 802 803 opp-100000000 { 804 opp-hz = /bits/ 64 <100000000>, 805 /bits/ 64 <0>, 806 /bits/ 64 <0>, 807 /bits/ 64 <100000000>, 808 /bits/ 64 <0>, 809 /bits/ 64 <0>, 810 /bits/ 64 <0>, 811 /bits/ 64 <0>; 812 required-opps = <&rpmhpd_opp_low_svs>; 813 }; 814 815 opp-201500000 { 816 opp-hz = /bits/ 64 <201500000>, 817 /bits/ 64 <0>, 818 /bits/ 64 <0>, 819 /bits/ 64 <201500000>, 820 /bits/ 64 <0>, 821 /bits/ 64 <0>, 822 /bits/ 64 <0>, 823 /bits/ 64 <0>; 824 required-opps = <&rpmhpd_opp_svs_l1>; 825 }; 826 827 opp-403000000 { 828 opp-hz = /bits/ 64 <403000000>, 829 /bits/ 64 <0>, 830 /bits/ 64 <0>, 831 /bits/ 64 <403000000>, 832 /bits/ 64 <0>, 833 /bits/ 64 <0>, 834 /bits/ 64 <0>, 835 /bits/ 64 <0>; 836 required-opps = <&rpmhpd_opp_nom>; 837 }; 838 }; 839 }; 840 841 ice: crypto@1d88000 { 842 compatible = "qcom,eliza-inline-crypto-engine", 843 "qcom,inline-crypto-engine"; 844 reg = <0x0 0x01d88000 0x0 0x18000>; 845 846 clocks = <&gcc GCC_UFS_PHY_ICE_CORE_CLK>, 847 <&gcc GCC_UFS_PHY_AHB_CLK>; 848 clock-names = "core", 849 "iface"; 850 power-domains = <&gcc GCC_UFS_PHY_GDSC>; 851 }; 852 853 tcsr_mutex: hwlock@1f40000 { 854 compatible = "qcom,tcsr-mutex"; 855 reg = <0x0 0x01f40000 0x0 0x20000>; 856 #hwlock-cells = <1>; 857 }; 858 859 tcsr: clock-controller@1fbf000 { 860 compatible = "qcom,eliza-tcsr", "syscon"; 861 reg = <0x0 0x01fbf000 0x0 0x21000>; 862 863 clocks = <&rpmhcc RPMH_CXO_CLK>; 864 865 #clock-cells = <1>; 866 #reset-cells = <1>; 867 }; 868 869 lpass_ag_noc: interconnect@7e40000 { 870 compatible = "qcom,eliza-lpass-ag-noc"; 871 reg = <0x0 0x07e40000 0x0 0xe080>; 872 qcom,bcm-voters = <&apps_bcm_voter>; 873 #interconnect-cells = <2>; 874 }; 875 876 lpass_lpiaon_noc: interconnect@7400000 { 877 compatible = "qcom,eliza-lpass-lpiaon-noc"; 878 reg = <0x0 0x07400000 0x0 0x19080>; 879 qcom,bcm-voters = <&apps_bcm_voter>; 880 #interconnect-cells = <2>; 881 }; 882 883 lpass_lpicx_noc: interconnect@7420000 { 884 compatible = "qcom,eliza-lpass-lpicx-noc"; 885 reg = <0x0 0x07420000 0x0 0x44080>; 886 qcom,bcm-voters = <&apps_bcm_voter>; 887 #interconnect-cells = <2>; 888 }; 889 890 pdc: interrupt-controller@b220000 { 891 compatible = "qcom,eliza-pdc", "qcom,pdc"; 892 reg = <0x0 0x0b220000 0x0 0x40000>, 893 <0x0 0x174000f0 0x0 0x64>; 894 895 qcom,pdc-ranges = <0 480 8>, <8 719 1>, <9 718 1>, 896 <10 230 1>, <11 724 1>, <12 716 1>, 897 <13 727 1>, <14 720 1>, <15 726 1>, 898 <16 721 1>, <17 262 1>, <18 70 1>, 899 <19 723 1>, <20 234 1>, <22 725 1>, 900 <23 231 1>, <24 504 5>, <30 510 8>, 901 <40 520 6>, <51 531 4>, <58 538 2>, 902 <61 541 5>, <66 92 1>, <67 547 13>, 903 <80 240 1>, <81 235 1>, <82 310 2>, 904 <84 248 1>, <85 241 1>, <86 238 2>, 905 <88 254 1>, <89 509 1>, <90 563 1>, 906 <91 259 2>, <93 201 1>, <94 246 1>, 907 <95 93 1>, <96 611 29>, <125 63 1>, 908 <126 366 2>, <128 374 1>, <129 377 1>, 909 <130 428 1>, <131 434 2>, <133 437 1>, 910 <134 452 2>, <136 458 2>, <138 464 11>, 911 <149 671 1>, <150 688 1>, <151 714 2>, 912 <153 722 1>, <154 255 1>, <155 269 2>, 913 <157 276 1>, <158 287 1>, <159 306 4>; 914 #interrupt-cells = <2>; 915 interrupt-parent = <&intc>; 916 interrupt-controller; 917 }; 918 919 tsens0: thermal-sensor@c228000 { 920 compatible = "qcom,eliza-tsens", "qcom,tsens-v2"; 921 reg = <0x0 0x0c228000 0x0 0x1000>, 922 <0x0 0x0c222000 0x0 0x1000>; 923 924 interrupts = <GIC_SPI 506 IRQ_TYPE_LEVEL_HIGH>, 925 <GIC_SPI 560 IRQ_TYPE_LEVEL_HIGH>; 926 interrupt-names = "uplow", 927 "critical"; 928 929 #qcom,sensors = <13>; 930 931 #thermal-sensor-cells = <1>; 932 }; 933 934 tsens1: thermal-sensor@c229000 { 935 compatible = "qcom,eliza-tsens", "qcom,tsens-v2"; 936 reg = <0x0 0x0c229000 0x0 0x1000>, 937 <0x0 0x0c223000 0x0 0x1000>; 938 939 interrupts = <GIC_SPI 507 IRQ_TYPE_LEVEL_HIGH>, 940 <GIC_SPI 561 IRQ_TYPE_LEVEL_HIGH>; 941 interrupt-names = "uplow", 942 "critical"; 943 944 #qcom,sensors = <14>; 945 946 #thermal-sensor-cells = <1>; 947 }; 948 949 tsens2: thermal-sensor@c22a000 { 950 compatible = "qcom,eliza-tsens", "qcom,tsens-v2"; 951 reg = <0x0 0x0c22a000 0x0 0x1000>, 952 <0x0 0x0c224000 0x0 0x1000>; 953 954 interrupts = <GIC_SPI 508 IRQ_TYPE_LEVEL_HIGH>, 955 <GIC_SPI 562 IRQ_TYPE_LEVEL_HIGH>; 956 interrupt-names = "uplow", 957 "critical"; 958 959 #qcom,sensors = <5>; 960 961 #thermal-sensor-cells = <1>; 962 }; 963 964 spmi: arbiter@c400000 { 965 compatible = "qcom,eliza-spmi-pmic-arb", 966 "qcom,x1e80100-spmi-pmic-arb"; 967 reg = <0x0 0x0c400000 0x0 0x3000>, 968 <0x0 0x0c500000 0x0 0x400000>, 969 <0x0 0x0c440000 0x0 0x80000>; 970 reg-names = "core", 971 "chnls", 972 "obsrvr"; 973 974 qcom,ee = <0>; 975 qcom,channel = <0>; 976 977 #address-cells = <2>; 978 #size-cells = <2>; 979 ranges; 980 981 spmi_bus0: spmi@c42d000 { 982 reg = <0x0 0x0c42d000 0x0 0x4000>, 983 <0x0 0x0c4c0000 0x0 0x10000>; 984 reg-names = "cnfg", 985 "intr"; 986 987 interrupt-names = "periph_irq"; 988 interrupts-extended = <&pdc 1 IRQ_TYPE_LEVEL_HIGH>; 989 interrupt-controller; 990 #interrupt-cells = <4>; 991 992 #address-cells = <2>; 993 #size-cells = <0>; 994 }; 995 996 spmi_bus1: spmi@c432000 { 997 reg = <0x0 0x0c432000 0x0 0x4000>, 998 <0x0 0x0c4d0000 0x0 0x10000>; 999 reg-names = "cnfg", 1000 "intr"; 1001 1002 interrupt-names = "periph_irq"; 1003 interrupts-extended = <&pdc 3 IRQ_TYPE_LEVEL_HIGH>; 1004 interrupt-controller; 1005 #interrupt-cells = <4>; 1006 1007 #address-cells = <2>; 1008 #size-cells = <0>; 1009 }; 1010 }; 1011 1012 apps_smmu: iommu@15000000 { 1013 compatible = "qcom,eliza-smmu-500", "qcom,smmu-500", "arm,mmu-500"; 1014 reg = <0x0 0x15000000 0x0 0x100000>; 1015 1016 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>, 1017 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1018 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1020 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1021 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1022 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1023 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1024 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1025 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1026 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1027 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1028 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1029 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1030 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1031 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1032 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1033 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1034 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1036 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1037 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1038 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1039 <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, 1040 <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, 1041 <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, 1042 <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, 1043 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, 1044 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1045 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1046 <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1047 <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, 1048 <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, 1049 <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, 1050 <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, 1051 <GIC_SPI 315 IRQ_TYPE_LEVEL_HIGH>, 1052 <GIC_SPI 316 IRQ_TYPE_LEVEL_HIGH>, 1053 <GIC_SPI 317 IRQ_TYPE_LEVEL_HIGH>, 1054 <GIC_SPI 318 IRQ_TYPE_LEVEL_HIGH>, 1055 <GIC_SPI 319 IRQ_TYPE_LEVEL_HIGH>, 1056 <GIC_SPI 320 IRQ_TYPE_LEVEL_HIGH>, 1057 <GIC_SPI 321 IRQ_TYPE_LEVEL_HIGH>, 1058 <GIC_SPI 322 IRQ_TYPE_LEVEL_HIGH>, 1059 <GIC_SPI 323 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 324 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 325 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 326 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 327 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 328 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 329 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 330 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 331 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 332 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 333 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 334 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 335 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 336 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 337 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 338 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 339 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 340 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 341 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 342 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 343 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 344 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 345 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 395 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 396 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 397 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 398 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>, 1092 <GIC_SPI 405 IRQ_TYPE_LEVEL_HIGH>, 1093 <GIC_SPI 406 IRQ_TYPE_LEVEL_HIGH>, 1094 <GIC_SPI 407 IRQ_TYPE_LEVEL_HIGH>, 1095 <GIC_SPI 408 IRQ_TYPE_LEVEL_HIGH>, 1096 <GIC_SPI 409 IRQ_TYPE_LEVEL_HIGH>, 1097 <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>, 1098 <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>, 1099 <GIC_SPI 412 IRQ_TYPE_LEVEL_HIGH>, 1100 <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>, 1101 <GIC_SPI 707 IRQ_TYPE_LEVEL_HIGH>, 1102 <GIC_SPI 423 IRQ_TYPE_LEVEL_HIGH>, 1103 <GIC_SPI 424 IRQ_TYPE_LEVEL_HIGH>, 1104 <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH>, 1105 <GIC_SPI 690 IRQ_TYPE_LEVEL_HIGH>, 1106 <GIC_SPI 691 IRQ_TYPE_LEVEL_HIGH>, 1107 <GIC_SPI 692 IRQ_TYPE_LEVEL_HIGH>, 1108 <GIC_SPI 693 IRQ_TYPE_LEVEL_HIGH>, 1109 <GIC_SPI 694 IRQ_TYPE_LEVEL_HIGH>, 1110 <GIC_SPI 695 IRQ_TYPE_LEVEL_HIGH>, 1111 <GIC_SPI 696 IRQ_TYPE_LEVEL_HIGH>, 1112 <GIC_SPI 697 IRQ_TYPE_LEVEL_HIGH>, 1113 <GIC_SPI 410 IRQ_TYPE_LEVEL_HIGH>, 1114 <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, 1115 <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>, 1116 <GIC_SPI 490 IRQ_TYPE_LEVEL_HIGH>, 1117 <GIC_SPI 491 IRQ_TYPE_LEVEL_HIGH>, 1118 <GIC_SPI 492 IRQ_TYPE_LEVEL_HIGH>, 1119 <GIC_SPI 493 IRQ_TYPE_LEVEL_HIGH>, 1120 <GIC_SPI 494 IRQ_TYPE_LEVEL_HIGH>, 1121 <GIC_SPI 495 IRQ_TYPE_LEVEL_HIGH>, 1122 <GIC_SPI 496 IRQ_TYPE_LEVEL_HIGH>, 1123 <GIC_SPI 497 IRQ_TYPE_LEVEL_HIGH>, 1124 <GIC_SPI 498 IRQ_TYPE_LEVEL_HIGH>, 1125 <GIC_SPI 499 IRQ_TYPE_LEVEL_HIGH>, 1126 <GIC_SPI 500 IRQ_TYPE_LEVEL_HIGH>, 1127 <GIC_SPI 501 IRQ_TYPE_LEVEL_HIGH>, 1128 <GIC_SPI 502 IRQ_TYPE_LEVEL_HIGH>; 1129 1130 #iommu-cells = <2>; 1131 #global-interrupts = <1>; 1132 1133 dma-coherent; 1134 }; 1135 1136 intc: interrupt-controller@17100000 { 1137 compatible = "arm,gic-v3"; 1138 reg = <0x0 0x17100000 0x0 0x10000>, 1139 <0x0 0x17180000 0x0 0x200000>; 1140 1141 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 1142 1143 #interrupt-cells = <3>; 1144 interrupt-controller; 1145 1146 #redistributor-regions = <1>; 1147 redistributor-stride = <0x0 0x40000>; 1148 1149 #address-cells = <2>; 1150 #size-cells = <2>; 1151 ranges; 1152 1153 gic_its: msi-controller@17140000 { 1154 compatible = "arm,gic-v3-its"; 1155 reg = <0x0 0x17140000 0x0 0x40000>; 1156 1157 msi-controller; 1158 #msi-cells = <1>; 1159 }; 1160 }; 1161 1162 apps_rsc: rsc@17a00000 { 1163 compatible = "qcom,rpmh-rsc"; 1164 reg = <0x0 0x17a00000 0x0 0x10000>, 1165 <0x0 0x17a10000 0x0 0x10000>, 1166 <0x0 0x17a20000 0x0 0x10000>; 1167 reg-names = "drv-0", 1168 "drv-1", 1169 "drv-2"; 1170 1171 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>, 1172 <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>, 1173 <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>; 1174 1175 power-domains = <&cluster_pd>; 1176 label = "apps_rsc"; 1177 1178 qcom,tcs-offset = <0xd00>; 1179 qcom,drv-id = <2>; 1180 qcom,tcs-config = <ACTIVE_TCS 3>, 1181 <SLEEP_TCS 2>, 1182 <WAKE_TCS 2>, 1183 <CONTROL_TCS 0>; 1184 1185 apps_bcm_voter: bcm-voter { 1186 compatible = "qcom,bcm-voter"; 1187 }; 1188 1189 rpmhcc: clock-controller { 1190 compatible = "qcom,eliza-rpmh-clk"; 1191 #clock-cells = <1>; 1192 clocks = <&xo_board>; 1193 clock-names = "xo"; 1194 }; 1195 1196 rpmhpd: power-controller { 1197 compatible = "qcom,eliza-rpmhpd"; 1198 1199 operating-points-v2 = <&rpmhpd_opp_table>; 1200 1201 #power-domain-cells = <1>; 1202 1203 rpmhpd_opp_table: opp-table { 1204 compatible = "operating-points-v2"; 1205 1206 rpmhpd_opp_ret: opp-16 { 1207 opp-level = <RPMH_REGULATOR_LEVEL_RETENTION>; 1208 }; 1209 1210 rpmhpd_opp_min_svs: opp-48 { 1211 opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>; 1212 }; 1213 1214 rpmhpd_opp_low_svs_d3: opp-50 { 1215 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D3>; 1216 }; 1217 1218 rpmhpd_opp_low_svs_d2: opp-52 { 1219 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D2>; 1220 }; 1221 1222 rpmhpd_opp_low_svs_d1: opp-56 { 1223 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D1>; 1224 }; 1225 1226 rpmhpd_opp_low_svs_d0: opp-60 { 1227 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_D0>; 1228 }; 1229 1230 rpmhpd_opp_low_svs: opp-64 { 1231 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>; 1232 }; 1233 1234 rpmhpd_opp_low_svs_l1: opp-80 { 1235 opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS_L1>; 1236 }; 1237 1238 rpmhpd_opp_svs: opp-128 { 1239 opp-level = <RPMH_REGULATOR_LEVEL_SVS>; 1240 }; 1241 1242 rpmhpd_opp_svs_l0: opp-144 { 1243 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L0>; 1244 }; 1245 1246 rpmhpd_opp_svs_l1: opp-192 { 1247 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>; 1248 }; 1249 1250 rpmhpd_opp_svs_l2: opp-224 { 1251 opp-level = <RPMH_REGULATOR_LEVEL_SVS_L2>; 1252 }; 1253 1254 rpmhpd_opp_nom: opp-256 { 1255 opp-level = <RPMH_REGULATOR_LEVEL_NOM>; 1256 }; 1257 1258 rpmhpd_opp_nom_l1: opp-320 { 1259 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>; 1260 }; 1261 1262 rpmhpd_opp_nom_l2: opp-336 { 1263 opp-level = <RPMH_REGULATOR_LEVEL_NOM_L2>; 1264 }; 1265 1266 rpmhpd_opp_turbo: opp-384 { 1267 opp-level = <RPMH_REGULATOR_LEVEL_TURBO>; 1268 }; 1269 1270 rpmhpd_opp_turbo_l1: opp-416 { 1271 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>; 1272 }; 1273 1274 rpmhpd_opp_turbo_l2: opp-432 { 1275 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L2>; 1276 }; 1277 1278 rpmhpd_opp_turbo_l3: opp-448 { 1279 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L3>; 1280 }; 1281 1282 rpmhpd_opp_turbo_l4: opp-452 { 1283 opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L4>; 1284 }; 1285 1286 rpmhpd_opp_super_turbo_no_cpr: opp-480 { 1287 opp-level = <RPMH_REGULATOR_LEVEL_SUPER_TURBO_NO_CPR>; 1288 }; 1289 }; 1290 }; 1291 }; 1292 1293 epss_l3: interconnect@17d90000 { 1294 compatible = "qcom,eliza-epss-l3", "qcom,epss-l3"; 1295 reg = <0x0 0x17d90000 0x0 0x1000>; 1296 1297 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 1298 clock-names = "xo", "alternate"; 1299 1300 #interconnect-cells = <1>; 1301 }; 1302 1303 cpufreq_hw: cpufreq@17d91000 { 1304 compatible = "qcom,eliza-cpufreq-epss", "qcom,cpufreq-epss"; 1305 reg = <0x0 0x17d91000 0x0 0x1000>, 1306 <0x0 0x17d92000 0x0 0x1000>, 1307 <0x0 0x17d93000 0x0 0x1000>; 1308 reg-names = "freq-domain0", 1309 "freq-domain1", 1310 "freq-domain2"; 1311 1312 interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>, 1313 <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>, 1314 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1315 interrupt-names = "dcvsh-irq-0", 1316 "dcvsh-irq-1", 1317 "dcvsh-irq-2"; 1318 1319 clocks = <&bi_tcxo_div2>, <&gcc GCC_GPLL0>; 1320 clock-names = "xo", "alternate"; 1321 1322 #freq-domain-cells = <1>; 1323 #clock-cells = <1>; 1324 }; 1325 1326 tlmm: pinctrl@f100000 { 1327 compatible = "qcom,eliza-tlmm"; 1328 reg = <0x0 0x0f100000 0x0 0xf00000>; 1329 1330 interrupts = <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>; 1331 1332 gpio-controller; 1333 #gpio-cells = <2>; 1334 1335 interrupt-controller; 1336 #interrupt-cells = <2>; 1337 1338 gpio-ranges = <&tlmm 0 0 184>; 1339 wakeup-parent = <&pdc>; 1340 1341 qup_uart14_default: qup-uart14-default-state { 1342 /* TX, RX */ 1343 pins = "gpio18", "gpio19"; 1344 function = "qup2_se5"; 1345 drive-strength = <2>; 1346 bias-pull-up; 1347 }; 1348 }; 1349 1350 gem_noc: interconnect@24100000 { 1351 compatible = "qcom,eliza-gem-noc"; 1352 reg = <0x0 0x24100000 0x0 0x163080>; 1353 qcom,bcm-voters = <&apps_bcm_voter>; 1354 #interconnect-cells = <2>; 1355 }; 1356 1357 nsp_noc: interconnect@320c0000 { 1358 compatible = "qcom,eliza-nsp-noc"; 1359 reg = <0x0 0x320c0000 0x0 0xe080>; 1360 qcom,bcm-voters = <&apps_bcm_voter>; 1361 #interconnect-cells = <2>; 1362 }; 1363 }; 1364 1365 thermal-zones { 1366 aoss0-thermal { 1367 thermal-sensors = <&tsens0 0>; 1368 1369 trips { 1370 aoss-hot { 1371 temperature = <110000>; 1372 hysteresis = <1000>; 1373 type = "hot"; 1374 }; 1375 1376 aoss-critical { 1377 temperature = <115000>; 1378 hysteresis = <0>; 1379 type = "critical"; 1380 }; 1381 }; 1382 }; 1383 1384 aoss1-thermal { 1385 thermal-sensors = <&tsens1 0>; 1386 1387 trips { 1388 aoss-hot { 1389 temperature = <110000>; 1390 hysteresis = <1000>; 1391 type = "hot"; 1392 }; 1393 1394 aoss-critical { 1395 temperature = <115000>; 1396 hysteresis = <0>; 1397 type = "critical"; 1398 }; 1399 }; 1400 }; 1401 1402 aoss2-thermal { 1403 thermal-sensors = <&tsens2 0>; 1404 1405 trips { 1406 aoss-hot { 1407 temperature = <110000>; 1408 hysteresis = <1000>; 1409 type = "hot"; 1410 }; 1411 1412 aoss-critical { 1413 temperature = <115000>; 1414 hysteresis = <0>; 1415 type = "critical"; 1416 }; 1417 }; 1418 }; 1419 1420 camera0-thermal { 1421 thermal-sensors = <&tsens1 12>; 1422 1423 trips { 1424 camera-hot { 1425 temperature = <110000>; 1426 hysteresis = <1000>; 1427 type = "hot"; 1428 }; 1429 1430 camera-critical { 1431 temperature = <115000>; 1432 hysteresis = <0>; 1433 type = "critical"; 1434 }; 1435 }; 1436 }; 1437 1438 camera1-thermal { 1439 thermal-sensors = <&tsens1 13>; 1440 1441 trips { 1442 camera-hot { 1443 temperature = <110000>; 1444 hysteresis = <1000>; 1445 type = "hot"; 1446 }; 1447 1448 camera-critical { 1449 temperature = <115000>; 1450 hysteresis = <0>; 1451 type = "critical"; 1452 }; 1453 }; 1454 }; 1455 1456 cpu0-thermal { 1457 thermal-sensors = <&tsens1 1>; 1458 1459 trips { 1460 cpu-critical { 1461 temperature = <110000>; 1462 hysteresis = <1000>; 1463 type = "critical"; 1464 }; 1465 }; 1466 }; 1467 1468 cpu1-thermal { 1469 thermal-sensors = <&tsens1 2>; 1470 1471 trips { 1472 cpu-critical { 1473 temperature = <110000>; 1474 hysteresis = <1000>; 1475 type = "critical"; 1476 }; 1477 }; 1478 }; 1479 1480 cpu2-thermal { 1481 thermal-sensors = <&tsens1 3>; 1482 1483 trips { 1484 cpu-critical { 1485 temperature = <110000>; 1486 hysteresis = <1000>; 1487 type = "critical"; 1488 }; 1489 }; 1490 }; 1491 1492 cpu3-top-thermal { 1493 thermal-sensors = <&tsens0 3>; 1494 1495 trips { 1496 cpu-critical { 1497 temperature = <110000>; 1498 hysteresis = <1000>; 1499 type = "critical"; 1500 }; 1501 }; 1502 }; 1503 1504 cpu3-bottom-thermal { 1505 thermal-sensors = <&tsens0 4>; 1506 1507 trips { 1508 cpu-critical { 1509 temperature = <110000>; 1510 hysteresis = <1000>; 1511 type = "critical"; 1512 }; 1513 }; 1514 }; 1515 1516 cpu4-top-thermal { 1517 thermal-sensors = <&tsens0 5>; 1518 1519 trips { 1520 cpu-critical { 1521 temperature = <110000>; 1522 hysteresis = <1000>; 1523 type = "critical"; 1524 }; 1525 }; 1526 }; 1527 1528 cpu4-bottom-thermal { 1529 thermal-sensors = <&tsens0 6>; 1530 1531 trips { 1532 cpu-critical { 1533 temperature = <110000>; 1534 hysteresis = <1000>; 1535 type = "critical"; 1536 }; 1537 }; 1538 }; 1539 1540 cpu5-top-thermal { 1541 thermal-sensors = <&tsens0 7>; 1542 1543 trips { 1544 cpu-critical { 1545 temperature = <110000>; 1546 hysteresis = <1000>; 1547 type = "critical"; 1548 }; 1549 }; 1550 }; 1551 1552 cpu5-bottom-thermal { 1553 thermal-sensors = <&tsens0 8>; 1554 1555 trips { 1556 cpu-critical { 1557 temperature = <110000>; 1558 hysteresis = <1000>; 1559 type = "critical"; 1560 }; 1561 }; 1562 }; 1563 1564 cpu6-top-thermal { 1565 thermal-sensors = <&tsens0 9>; 1566 1567 trips { 1568 cpu-critical { 1569 temperature = <110000>; 1570 hysteresis = <1000>; 1571 type = "critical"; 1572 }; 1573 }; 1574 }; 1575 1576 cpu6-bottom-thermal { 1577 thermal-sensors = <&tsens0 10>; 1578 1579 trips { 1580 cpu-critical { 1581 temperature = <110000>; 1582 hysteresis = <1000>; 1583 type = "critical"; 1584 }; 1585 }; 1586 }; 1587 1588 cpu7-top-thermal { 1589 thermal-sensors = <&tsens0 11>; 1590 1591 trips { 1592 cpu-critical { 1593 temperature = <110000>; 1594 hysteresis = <1000>; 1595 type = "critical"; 1596 }; 1597 }; 1598 }; 1599 1600 cpu7-bottom-thermal { 1601 thermal-sensors = <&tsens0 12>; 1602 1603 trips { 1604 cpu-critical { 1605 temperature = <110000>; 1606 hysteresis = <1000>; 1607 type = "critical"; 1608 }; 1609 }; 1610 }; 1611 1612 cpuss0-thermal { 1613 thermal-sensors = <&tsens0 1>; 1614 1615 trips { 1616 cpuss-hot { 1617 temperature = <110000>; 1618 hysteresis = <1000>; 1619 type = "hot"; 1620 }; 1621 1622 cpuss-critical { 1623 temperature = <115000>; 1624 hysteresis = <0>; 1625 type = "critical"; 1626 }; 1627 }; 1628 }; 1629 1630 cpuss1-thermal { 1631 thermal-sensors = <&tsens0 2>; 1632 1633 trips { 1634 cpuss-hot { 1635 temperature = <110000>; 1636 hysteresis = <1000>; 1637 type = "hot"; 1638 }; 1639 1640 cpuss-critical { 1641 temperature = <115000>; 1642 hysteresis = <0>; 1643 type = "critical"; 1644 }; 1645 }; 1646 }; 1647 1648 ddr-thermal { 1649 thermal-sensors = <&tsens1 11>; 1650 1651 trips { 1652 ddr-hot { 1653 temperature = <110000>; 1654 hysteresis = <1000>; 1655 type = "hot"; 1656 }; 1657 1658 ddr-critical { 1659 temperature = <115000>; 1660 hysteresis = <0>; 1661 type = "critical"; 1662 }; 1663 }; 1664 }; 1665 1666 gpuss0-thermal { 1667 polling-delay-passive = <10>; 1668 1669 thermal-sensors = <&tsens1 8>; 1670 1671 trips { 1672 gpu-alert { 1673 temperature = <95000>; 1674 hysteresis = <1000>; 1675 type = "passive"; 1676 }; 1677 1678 gpu-hot { 1679 temperature = <110000>; 1680 hysteresis = <1000>; 1681 type = "hot"; 1682 }; 1683 1684 gpu-critical { 1685 temperature = <115000>; 1686 hysteresis = <0>; 1687 type = "critical"; 1688 }; 1689 }; 1690 }; 1691 1692 gpuss1-thermal { 1693 polling-delay-passive = <10>; 1694 1695 thermal-sensors = <&tsens1 9>; 1696 1697 trips { 1698 gpu-alert { 1699 temperature = <95000>; 1700 hysteresis = <1000>; 1701 type = "passive"; 1702 }; 1703 1704 gpu-hot { 1705 temperature = <110000>; 1706 hysteresis = <1000>; 1707 type = "hot"; 1708 }; 1709 1710 gpu-critical { 1711 temperature = <115000>; 1712 hysteresis = <0>; 1713 type = "critical"; 1714 }; 1715 }; 1716 }; 1717 1718 modem0-thermal { 1719 thermal-sensors = <&tsens2 1>; 1720 1721 trips { 1722 modem-hot { 1723 temperature = <110000>; 1724 hysteresis = <1000>; 1725 type = "hot"; 1726 }; 1727 1728 modem-critical { 1729 temperature = <115000>; 1730 hysteresis = <0>; 1731 type = "critical"; 1732 }; 1733 }; 1734 }; 1735 1736 modem1-thermal { 1737 thermal-sensors = <&tsens2 2>; 1738 1739 trips { 1740 modem-hot { 1741 temperature = <110000>; 1742 hysteresis = <1000>; 1743 type = "hot"; 1744 }; 1745 1746 modem-critical { 1747 temperature = <115000>; 1748 hysteresis = <0>; 1749 type = "critical"; 1750 }; 1751 }; 1752 }; 1753 1754 modem2-thermal { 1755 thermal-sensors = <&tsens2 3>; 1756 1757 trips { 1758 modem-hot { 1759 temperature = <110000>; 1760 hysteresis = <1000>; 1761 type = "hot"; 1762 }; 1763 1764 modem-critical { 1765 temperature = <115000>; 1766 hysteresis = <0>; 1767 type = "critical"; 1768 }; 1769 }; 1770 }; 1771 1772 modem3-thermal { 1773 thermal-sensors = <&tsens2 4>; 1774 1775 trips { 1776 modem-hot { 1777 temperature = <110000>; 1778 hysteresis = <1000>; 1779 type = "hot"; 1780 }; 1781 1782 modem-critical { 1783 temperature = <115000>; 1784 hysteresis = <0>; 1785 type = "critical"; 1786 }; 1787 }; 1788 }; 1789 1790 nsphmx0-thermal { 1791 thermal-sensors = <&tsens1 6>; 1792 1793 trips { 1794 nsphmx-hot { 1795 temperature = <110000>; 1796 hysteresis = <1000>; 1797 type = "hot"; 1798 }; 1799 1800 nsphmx-critical { 1801 temperature = <115000>; 1802 hysteresis = <0>; 1803 type = "critical"; 1804 }; 1805 }; 1806 }; 1807 1808 nsphmx1-thermal { 1809 thermal-sensors = <&tsens1 7>; 1810 1811 trips { 1812 nsphmx-hot { 1813 temperature = <110000>; 1814 hysteresis = <1000>; 1815 type = "hot"; 1816 }; 1817 1818 nsphmx-critical { 1819 temperature = <115000>; 1820 hysteresis = <0>; 1821 type = "critical"; 1822 }; 1823 }; 1824 }; 1825 1826 nsphvx0-thermal { 1827 thermal-sensors = <&tsens1 4>; 1828 1829 trips { 1830 nsphvx-hot { 1831 temperature = <110000>; 1832 hysteresis = <1000>; 1833 type = "hot"; 1834 }; 1835 1836 nsphvx-critical { 1837 temperature = <115000>; 1838 hysteresis = <0>; 1839 type = "critical"; 1840 }; 1841 }; 1842 }; 1843 1844 nsphvx1-thermal { 1845 thermal-sensors = <&tsens1 5>; 1846 1847 trips { 1848 nsphvx-hot { 1849 temperature = <110000>; 1850 hysteresis = <1000>; 1851 type = "hot"; 1852 }; 1853 1854 nsphvx-critical { 1855 temperature = <115000>; 1856 hysteresis = <0>; 1857 type = "critical"; 1858 }; 1859 }; 1860 }; 1861 1862 video-thermal { 1863 thermal-sensors = <&tsens1 10>; 1864 1865 trips { 1866 video-hot { 1867 temperature = <110000>; 1868 hysteresis = <1000>; 1869 type = "hot"; 1870 }; 1871 1872 video-critical { 1873 temperature = <115000>; 1874 hysteresis = <0>; 1875 type = "critical"; 1876 }; 1877 }; 1878 }; 1879 }; 1880 1881 timer { 1882 compatible = "arm,armv8-timer"; 1883 1884 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 1885 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 1886 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 1887 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 1888 }; 1889}; 1890