1// SPDX-License-Identifier: (GPL-2.0 OR MIT) 2/* 3 * Copyright (C) 2023 MediaTek Inc. 4 * Author: Ben Lok <ben.lok@mediatek.com> 5 * Macpaul Lin <macpaul.lin@mediatek.com> 6 */ 7/dts-v1/; 8 9#include "mt8195.dtsi" 10#include "mt6359.dtsi" 11#include <dt-bindings/gpio/gpio.h> 12#include <dt-bindings/input/input.h> 13#include <dt-bindings/interrupt-controller/irq.h> 14#include <dt-bindings/pinctrl/mt8195-pinfunc.h> 15#include <dt-bindings/regulator/mediatek,mt6360-regulator.h> 16#include <dt-bindings/spmi/spmi.h> 17#include <dt-bindings/usb/pd.h> 18 19/ { 20 aliases { 21 ethernet0 = ð 22 mmc0 = &mmc0; 23 mmc1 = &mmc1; 24 serial0 = &uart0; 25 }; 26 27 chosen { 28 stdout-path = "serial0:921600n8"; 29 }; 30 31 connector { 32 compatible = "hdmi-connector"; 33 label = "hdmi"; 34 type = "a"; 35 ddc-i2c-bus = <&hdmitx_ddc>; 36 hdmi-pwr-supply = <&hdmi_phy>; 37 38 port { 39 hdmi_connector_in: endpoint { 40 remote-endpoint = <&hdmi0_out>; 41 }; 42 }; 43 }; 44 45 firmware { 46 optee { 47 compatible = "linaro,optee-tz"; 48 method = "smc"; 49 }; 50 }; 51 52 memory@40000000 { 53 device_type = "memory"; 54 reg = <0 0x40000000 0x2 0x00000000>; 55 }; 56 57 reserved-memory { 58 #address-cells = <2>; 59 #size-cells = <2>; 60 ranges; 61 62 /* 63 * 12 MiB reserved for OP-TEE (BL32) 64 * +-----------------------+ 0x43e0_0000 65 * | SHMEM 2MiB | 66 * +-----------------------+ 0x43c0_0000 67 * | | TA_RAM 8MiB | 68 * + TZDRAM +--------------+ 0x4340_0000 69 * | | TEE_RAM 2MiB | 70 * +-----------------------+ 0x4320_0000 71 */ 72 optee_reserved: optee@43200000 { 73 no-map; 74 reg = <0 0x43200000 0 0x00c00000>; 75 }; 76 77 scp_mem: memory@50000000 { 78 compatible = "shared-dma-pool"; 79 reg = <0 0x50000000 0 0x2900000>; 80 no-map; 81 }; 82 83 vpu_mem: memory@53000000 { 84 compatible = "shared-dma-pool"; 85 reg = <0 0x53000000 0 0x1400000>; /* 20 MB */ 86 }; 87 88 /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ 89 bl31_secmon_mem: memory@54600000 { 90 no-map; 91 reg = <0 0x54600000 0x0 0x200000>; 92 }; 93 94 adsp_mem: memory@60000000 { 95 compatible = "shared-dma-pool"; 96 reg = <0 0x60000000 0 0xf00000>; 97 no-map; 98 }; 99 100 afe_dma_mem: memory@60f00000 { 101 compatible = "shared-dma-pool"; 102 reg = <0 0x60f00000 0 0x100000>; 103 no-map; 104 }; 105 106 adsp_dma_mem: memory@61000000 { 107 compatible = "shared-dma-pool"; 108 reg = <0 0x61000000 0 0x100000>; 109 no-map; 110 }; 111 112 apu_mem: memory@62000000 { 113 compatible = "shared-dma-pool"; 114 reg = <0 0x62000000 0 0x1400000>; /* 20 MB */ 115 }; 116 }; 117 118 backlight_lcm0: backlight-lcm0 { 119 compatible = "pwm-backlight"; 120 brightness-levels = <0 1023>; 121 default-brightness-level = <576>; 122 num-interpolated-steps = <1023>; 123 pwms = <&disp_pwm0 0 500000>; 124 }; 125 126 backlight_lcd1: backlight-lcd1 { 127 compatible = "pwm-backlight"; 128 pwms = <&disp_pwm1 0 500000>; 129 enable-gpios = <&pio 46 GPIO_ACTIVE_HIGH>; 130 brightness-levels = <0 1023>; 131 num-interpolated-steps = <1023>; 132 default-brightness-level = <576>; 133 status = "disabled"; 134 }; 135 136 can_clk: can-clk { 137 compatible = "fixed-clock"; 138 #clock-cells = <0>; 139 clock-frequency = <20000000>; 140 clock-output-names = "can-clk"; 141 }; 142 143 edp_panel_fixed_3v3: regulator-0 { 144 compatible = "regulator-fixed"; 145 regulator-name = "edp_panel_3v3"; 146 regulator-min-microvolt = <3300000>; 147 regulator-max-microvolt = <3300000>; 148 enable-active-high; 149 gpio = <&pio 6 GPIO_ACTIVE_HIGH>; 150 pinctrl-names = "default"; 151 pinctrl-0 = <&edp_panel_3v3_en_pins>; 152 }; 153 154 edp_panel_fixed_12v: regulator-1 { 155 compatible = "regulator-fixed"; 156 regulator-name = "edp_backlight_12v"; 157 regulator-min-microvolt = <12000000>; 158 regulator-max-microvolt = <12000000>; 159 enable-active-high; 160 gpio = <&pio 96 GPIO_ACTIVE_HIGH>; 161 pinctrl-names = "default"; 162 pinctrl-0 = <&edp_panel_12v_en_pins>; 163 }; 164 165 keys: gpio-keys { 166 compatible = "gpio-keys"; 167 168 button-volume-up { 169 wakeup-source; 170 debounce-interval = <100>; 171 gpios = <&pio 106 GPIO_ACTIVE_LOW>; 172 label = "volume_up"; 173 linux,code = <KEY_VOLUMEUP>; 174 }; 175 }; 176 177 lcm0_iovcc: regulator-vio18-lcm0 { 178 compatible = "regulator-fixed"; 179 regulator-name = "vio18_lcm0"; 180 enable-active-high; 181 gpio = <&pio 47 GPIO_ACTIVE_HIGH>; 182 pinctrl-names = "default"; 183 pinctrl-0 = <&dsi0_vreg_en_pins>; 184 vin-supply = <&mt6360_ldo2>; 185 }; 186 187 lcm0_vddp: regulator-vsys-lcm0 { 188 compatible = "regulator-fixed"; 189 regulator-name = "vsys_lcm0"; 190 regulator-always-on; 191 regulator-boot-on; 192 vin-supply = <&mt6360_ldo1>; 193 }; 194 195 wifi_fixed_3v3: regulator-2 { 196 compatible = "regulator-fixed"; 197 regulator-name = "wifi_3v3"; 198 regulator-min-microvolt = <3300000>; 199 regulator-max-microvolt = <3300000>; 200 gpio = <&pio 135 GPIO_ACTIVE_HIGH>; 201 enable-active-high; 202 regulator-always-on; 203 }; 204}; 205 206&adsp { 207 memory-region = <&adsp_dma_mem>, <&adsp_mem>; 208 status = "okay"; 209}; 210 211&afe { 212 memory-region = <&afe_dma_mem>; 213 status = "okay"; 214}; 215 216&cpu0 { 217 cpu-supply = <&mt6359_vcore_buck_reg>; 218}; 219 220&cpu1 { 221 cpu-supply = <&mt6359_vcore_buck_reg>; 222}; 223 224&cpu2 { 225 cpu-supply = <&mt6359_vcore_buck_reg>; 226}; 227 228&cpu3 { 229 cpu-supply = <&mt6359_vcore_buck_reg>; 230}; 231 232&cpu4 { 233 cpu-supply = <&mt6315_6_vbuck1>; 234}; 235 236&cpu5 { 237 cpu-supply = <&mt6315_6_vbuck1>; 238}; 239 240&cpu6 { 241 cpu-supply = <&mt6315_6_vbuck1>; 242}; 243 244&cpu7 { 245 cpu-supply = <&mt6315_6_vbuck1>; 246}; 247 248&disp_pwm0 { 249 pinctrl-names = "default"; 250 pinctrl-0 = <&disp_pwm0_pins>; 251 status = "okay"; 252}; 253 254&dither0_in { 255 remote-endpoint = <&gamma0_out>; 256}; 257 258&dither0_out { 259 remote-endpoint = <&dsi0_in>; 260}; 261 262&dmic_codec { 263 wakeup-delay-ms = <200>; 264}; 265 266&dpi1 { 267 status = "okay"; 268}; 269 270&dpi1_in { 271 remote-endpoint = <&merge5_out>; 272}; 273 274&dpi1_out { 275 remote-endpoint = <&hdmi0_in>; 276}; 277 278&dsi0 { 279 #address-cells = <1>; 280 #size-cells = <0>; 281 status = "okay"; 282 283 panel@0 { 284 compatible = "startek,kd070fhfid078", "himax,hx8279"; 285 reg = <0>; 286 backlight = <&backlight_lcm0>; 287 enable-gpios = <&pio 48 GPIO_ACTIVE_HIGH>; 288 reset-gpios = <&pio 108 GPIO_ACTIVE_HIGH>; 289 iovcc-supply = <&lcm0_iovcc>; 290 vdd-supply = <&lcm0_vddp>; 291 pinctrl-names = "default"; 292 pinctrl-0 = <&panel_default_pins>; 293 294 port { 295 dsi_panel_in: endpoint { 296 remote-endpoint = <&dsi0_out>; 297 }; 298 }; 299 }; 300 301 ports { 302 #address-cells = <1>; 303 #size-cells = <0>; 304 305 port@0 { 306 reg = <0>; 307 dsi0_in: endpoint { 308 remote-endpoint = <&dither0_out>; 309 }; 310 }; 311 312 port@1 { 313 reg = <1>; 314 dsi0_out: endpoint { 315 remote-endpoint = <&dsi_panel_in>; 316 }; 317 }; 318 }; 319}; 320 321ð { 322 phy-mode ="rgmii-rxid"; 323 phy-handle = <ð_phy0>; 324 snps,reset-gpio = <&pio 93 GPIO_ACTIVE_HIGH>; 325 snps,reset-delays-us = <0 10000 10000>; 326 mediatek,tx-delay-ps = <2030>; 327 mediatek,mac-wol; 328 pinctrl-names = "default", "sleep"; 329 pinctrl-0 = <ð_default_pins>; 330 pinctrl-1 = <ð_sleep_pins>; 331 status = "okay"; 332 333 mdio { 334 compatible = "snps,dwmac-mdio"; 335 #address-cells = <1>; 336 #size-cells = <0>; 337 eth_phy0: ethernet-phy@1 { 338 compatible = "ethernet-phy-id001c.c916"; 339 reg = <0x1>; 340 }; 341 }; 342}; 343 344ðdr0 { 345 ports { 346 #address-cells = <1>; 347 #size-cells = <0>; 348 349 port@0 { 350 #address-cells = <1>; 351 #size-cells = <0>; 352 reg = <0>; 353 354 ethdr0_in: endpoint@1 { 355 reg = <1>; 356 remote-endpoint = <&vdosys1_ep_ext>; 357 }; 358 }; 359 360 port@1 { 361 #address-cells = <1>; 362 #size-cells = <0>; 363 reg = <1>; 364 365 ethdr0_out: endpoint@1 { 366 reg = <1>; 367 remote-endpoint = <&merge5_in>; 368 }; 369 }; 370 }; 371}; 372 373&gamma0_out { 374 remote-endpoint = <&dither0_in>; 375}; 376 377&gpu { 378 mali-supply = <&mt6315_7_vbuck1>; 379 status = "okay"; 380}; 381 382&i2c0 { 383 clock-frequency = <400000>; 384 pinctrl-0 = <&i2c0_pins>; 385 pinctrl-names = "default"; 386 status = "okay"; 387}; 388 389&hdmi { 390 pinctrl-names = "default"; 391 pinctrl-0 = <&hdmi_pins>; 392 status = "okay"; 393}; 394 395&hdmi0_in { 396 remote-endpoint = <&dpi1_out>; 397}; 398 399&hdmi0_out { 400 remote-endpoint = <&hdmi_connector_in>; 401}; 402 403&hdmi_phy { 404 pinctrl-names = "default"; 405 pinctrl-0 = <&hdmi_vreg_pins>; 406 407 status = "okay"; 408}; 409 410&i2c1 { 411 clock-frequency = <400000>; 412 pinctrl-0 = <&i2c1_pins>; 413 pinctrl-names = "default"; 414 status = "okay"; 415 416 touchscreen@5d { 417 compatible = "goodix,gt9271"; 418 reg = <0x5d>; 419 interrupts-extended = <&pio 132 IRQ_TYPE_EDGE_RISING>; 420 irq-gpios = <&pio 132 GPIO_ACTIVE_HIGH>; 421 reset-gpios = <&pio 133 GPIO_ACTIVE_HIGH>; 422 AVDD28-supply = <&mt6360_ldo1>; 423 pinctrl-names = "default"; 424 pinctrl-0 = <&touch_pins>; 425 }; 426}; 427 428&i2c2 { 429 clock-frequency = <400000>; 430 pinctrl-0 = <&i2c2_pins>; 431 pinctrl-names = "default"; 432 status = "okay"; 433 434 typec-mux@48 { 435 compatible = "ite,it5205"; 436 reg = <0x48>; 437 vcc-supply = <&mt6359_vibr_ldo_reg>; 438 mode-switch; 439 orientation-switch; 440 status = "okay"; 441 442 port { 443 it5205_sbu_ep: endpoint { 444 remote-endpoint = <&mt6360_ssusb_sbu_ep>; 445 }; 446 }; 447 }; 448}; 449 450&i2c6 { 451 clock-frequency = <400000>; 452 pinctrl-0 = <&i2c6_pins>; 453 pinctrl-names = "default"; 454 #address-cells = <1>; 455 #size-cells = <0>; 456 status = "okay"; 457 458 mt6360: pmic@34 { 459 compatible = "mediatek,mt6360"; 460 reg = <0x34>; 461 interrupt-parent = <&pio>; 462 interrupts = <128 IRQ_TYPE_EDGE_FALLING>; 463 interrupt-names = "IRQB"; 464 interrupt-controller; 465 #interrupt-cells = <1>; 466 pinctrl-0 = <&mt6360_pins>; 467 468 charger { 469 compatible = "mediatek,mt6360-chg"; 470 richtek,vinovp-microvolt = <14500000>; 471 472 otg_vbus_regulator: usb-otg-vbus-regulator { 473 regulator-name = "usb-otg-vbus"; 474 regulator-min-microvolt = <4425000>; 475 regulator-max-microvolt = <5825000>; 476 }; 477 }; 478 479 regulator { 480 compatible = "mediatek,mt6360-regulator"; 481 LDO_VIN3-supply = <&mt6360_buck2>; 482 483 mt6360_buck1: buck1 { 484 regulator-name = "emi_vdd2"; 485 regulator-min-microvolt = <300000>; 486 regulator-max-microvolt = <1300000>; 487 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 488 MT6360_OPMODE_LP 489 MT6360_OPMODE_ULP>; 490 regulator-always-on; 491 }; 492 493 mt6360_buck2: buck2 { 494 regulator-name = "emi_vddq"; 495 regulator-min-microvolt = <300000>; 496 regulator-max-microvolt = <1300000>; 497 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 498 MT6360_OPMODE_LP 499 MT6360_OPMODE_ULP>; 500 regulator-always-on; 501 }; 502 503 mt6360_ldo1: ldo1 { 504 regulator-name = "tp1_p3v0"; 505 regulator-min-microvolt = <3300000>; 506 regulator-max-microvolt = <3300000>; 507 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 508 MT6360_OPMODE_LP>; 509 regulator-always-on; 510 }; 511 512 mt6360_ldo2: ldo2 { 513 regulator-name = "panel1_p1v8"; 514 regulator-min-microvolt = <1800000>; 515 regulator-max-microvolt = <1800000>; 516 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 517 MT6360_OPMODE_LP>; 518 }; 519 520 mt6360_ldo3: ldo3 { 521 regulator-name = "vmc_pmu"; 522 regulator-min-microvolt = <1200000>; 523 regulator-max-microvolt = <3600000>; 524 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 525 MT6360_OPMODE_LP>; 526 }; 527 528 mt6360_ldo5: ldo5 { 529 regulator-name = "vmch_pmu"; 530 regulator-min-microvolt = <2700000>; 531 regulator-max-microvolt = <3600000>; 532 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 533 MT6360_OPMODE_LP>; 534 }; 535 536 /* This is a measure point, which name is mt6360_ldo1 on schematic */ 537 mt6360_ldo6: ldo6 { 538 regulator-name = "mt6360_ldo1"; 539 regulator-min-microvolt = <500000>; 540 regulator-max-microvolt = <2100000>; 541 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 542 MT6360_OPMODE_LP>; 543 }; 544 545 mt6360_ldo7: ldo7 { 546 regulator-name = "emi_vmddr_en"; 547 regulator-min-microvolt = <500000>; 548 regulator-max-microvolt = <2100000>; 549 regulator-allowed-modes = <MT6360_OPMODE_NORMAL 550 MT6360_OPMODE_LP>; 551 regulator-always-on; 552 }; 553 }; 554 555 tcpc { 556 compatible = "mediatek,mt6360-tcpc"; 557 interrupts-extended = <&pio 17 IRQ_TYPE_LEVEL_LOW>; 558 interrupt-names = "PD_IRQB"; 559 560 connector { 561 compatible = "usb-c-connector"; 562 label = "USB-C"; 563 data-role = "dual"; 564 op-sink-microwatt = <10000000>; 565 power-role = "dual"; 566 try-power-role = "sink"; 567 568 source-pdos = <PDO_FIXED(5000, 1000, 569 PDO_FIXED_DUAL_ROLE | 570 PDO_FIXED_DATA_SWAP)>; 571 sink-pdos = <PDO_FIXED(5000, 2000, 572 PDO_FIXED_DUAL_ROLE | 573 PDO_FIXED_DATA_SWAP)>; 574 575 pd-revision = /bits/ 8 <0x03 0x01 0x01 0x06>; 576 577 altmodes { 578 displayport { 579 svid = /bits/ 16 <0xff01>; 580 vdo = <0x00001c46>; 581 }; 582 }; 583 584 ports { 585 #address-cells = <1>; 586 #size-cells = <0>; 587 588 port@0 { 589 reg = <0>; 590 typec_con_hs: endpoint { 591 remote-endpoint = <&mtu3_hs0_role_sw>; 592 }; 593 }; 594 595 port@1 { 596 reg = <1>; 597 typec_con_ss: endpoint { 598 remote-endpoint = <&mtu3_ss0_role_sw>; 599 }; 600 }; 601 602 port@2 { 603 reg = <2>; 604 mt6360_ssusb_sbu_ep: endpoint { 605 remote-endpoint = <&it5205_sbu_ep>; 606 }; 607 }; 608 }; 609 }; 610 }; 611 }; 612}; 613 614&merge5 { 615 ports { 616 #address-cells = <1>; 617 #size-cells = <0>; 618 619 port@0 { 620 #address-cells = <1>; 621 #size-cells = <0>; 622 reg = <0>; 623 624 merge5_in: endpoint@1 { 625 reg = <1>; 626 remote-endpoint = <ðdr0_out>; 627 }; 628 }; 629 630 port@1 { 631 #address-cells = <1>; 632 #size-cells = <0>; 633 reg = <1>; 634 635 merge5_out: endpoint@1 { 636 reg = <1>; 637 remote-endpoint = <&dpi1_in>; 638 }; 639 }; 640 }; 641}; 642 643&mfg0 { 644 domain-supply = <&mt6315_7_vbuck1>; 645}; 646 647&mfg1 { 648 domain-supply = <&mt6359_vsram_others_ldo_reg>; 649}; 650 651&mipi_tx0 { 652 status = "okay"; 653}; 654 655&mmc0 { 656 status = "okay"; 657 pinctrl-names = "default", "state_uhs"; 658 pinctrl-0 = <&mmc0_default_pins>; 659 pinctrl-1 = <&mmc0_uhs_pins>; 660 bus-width = <8>; 661 max-frequency = <200000000>; 662 cap-mmc-highspeed; 663 mmc-hs200-1_8v; 664 mmc-hs400-1_8v; 665 cap-mmc-hw-reset; 666 no-sdio; 667 no-sd; 668 hs400-ds-delay = <0x14c11>; 669 vmmc-supply = <&mt6359_vemc_1_ldo_reg>; 670 vqmmc-supply = <&mt6359_vufs_ldo_reg>; 671 non-removable; 672}; 673 674&mmc1 { 675 pinctrl-names = "default", "state_uhs"; 676 pinctrl-0 = <&mmc1_default_pins>; 677 pinctrl-1 = <&mmc1_uhs_pins>; 678 bus-width = <4>; 679 max-frequency = <200000000>; 680 cap-sd-highspeed; 681 sd-uhs-sdr50; 682 sd-uhs-sdr104; 683 no-mmc; 684 no-sdio; 685 vmmc-supply = <&mt6360_ldo5>; 686 vqmmc-supply = <&mt6360_ldo3>; 687 status = "okay"; 688 non-removable; 689}; 690 691&mt6359_vaud18_ldo_reg { 692 regulator-always-on; 693}; 694 695&mt6359_vbbck_ldo_reg { 696 regulator-always-on; 697}; 698 699/* For USB Hub */ 700&mt6359_vcamio_ldo_reg { 701 regulator-always-on; 702}; 703 704&mt6359_vcn33_2_bt_ldo_reg { 705 regulator-min-microvolt = <3300000>; 706 regulator-max-microvolt = <3300000>; 707}; 708 709&mt6359_vcore_buck_reg { 710 regulator-always-on; 711}; 712 713&mt6359_vgpu11_buck_reg { 714 regulator-always-on; 715}; 716 717&mt6359_vpu_buck_reg { 718 regulator-always-on; 719}; 720 721&mt6359_vrf12_ldo_reg { 722 regulator-always-on; 723}; 724 725/* for GPU SRAM */ 726&mt6359_vsram_others_ldo_reg { 727 regulator-min-microvolt = <750000>; 728 regulator-max-microvolt = <750000>; 729}; 730 731&mt6359codec { 732 mediatek,mic-type-0 = <1>; /* ACC */ 733 mediatek,mic-type-1 = <3>; /* DCC */ 734 mediatek,mic-type-2 = <1>; /* ACC */ 735}; 736 737&ovl0_in { 738 remote-endpoint = <&vdosys0_ep_main>; 739}; 740 741&pcie0 { 742 pinctrl-names = "default", "idle"; 743 pinctrl-0 = <&pcie0_default_pins>; 744 pinctrl-1 = <&pcie0_idle_pins>; 745 status = "okay"; 746}; 747 748&pcie1 { 749 pinctrl-names = "default"; 750 pinctrl-0 = <&pcie1_default_pins>; 751 status = "disabled"; 752}; 753 754&pciephy { 755 status = "okay"; 756}; 757 758&pio { 759 audio_default_pins: audio-default-pins { 760 pins-cmd-dat { 761 pinmux = <PINMUX_GPIO61__FUNC_DMIC1_CLK>, 762 <PINMUX_GPIO62__FUNC_DMIC1_DAT>, 763 <PINMUX_GPIO65__FUNC_PCM_DO>, 764 <PINMUX_GPIO66__FUNC_PCM_CLK>, 765 <PINMUX_GPIO67__FUNC_PCM_DI>, 766 <PINMUX_GPIO68__FUNC_PCM_SYNC>, 767 <PINMUX_GPIO69__FUNC_AUD_CLK_MOSI>, 768 <PINMUX_GPIO70__FUNC_AUD_SYNC_MOSI>, 769 <PINMUX_GPIO71__FUNC_AUD_DAT_MOSI0>, 770 <PINMUX_GPIO72__FUNC_AUD_DAT_MOSI1>, 771 <PINMUX_GPIO73__FUNC_AUD_DAT_MISO0>, 772 <PINMUX_GPIO74__FUNC_AUD_DAT_MISO1>, 773 <PINMUX_GPIO75__FUNC_AUD_DAT_MISO2>; 774 }; 775 }; 776 777 disp_pwm1_default_pins: disp-pwm1-default-pins { 778 pins1 { 779 pinmux = <PINMUX_GPIO104__FUNC_DISP_PWM1>; 780 }; 781 }; 782 783 edp_panel_12v_en_pins: edp-panel-12v-en-pins { 784 pins1 { 785 pinmux = <PINMUX_GPIO96__FUNC_GPIO96>; 786 output-high; 787 }; 788 }; 789 790 edp_panel_3v3_en_pins: edp-panel-3v3-en-pins { 791 pins1 { 792 pinmux = <PINMUX_GPIO6__FUNC_GPIO6>; 793 output-high; 794 }; 795 }; 796 797 eth_default_pins: eth-default-pins { 798 pins-cc { 799 pinmux = <PINMUX_GPIO85__FUNC_GBE_TXC>, 800 <PINMUX_GPIO86__FUNC_GBE_RXC>, 801 <PINMUX_GPIO87__FUNC_GBE_RXDV>, 802 <PINMUX_GPIO88__FUNC_GBE_TXEN>; 803 drive-strength = <8>; 804 }; 805 806 pins-mdio { 807 pinmux = <PINMUX_GPIO89__FUNC_GBE_MDC>, 808 <PINMUX_GPIO90__FUNC_GBE_MDIO>; 809 input-enable; 810 }; 811 812 pins-power { 813 pinmux = <PINMUX_GPIO91__FUNC_GPIO91>, 814 <PINMUX_GPIO92__FUNC_GPIO92>; 815 output-high; 816 }; 817 818 pins-rxd { 819 pinmux = <PINMUX_GPIO81__FUNC_GBE_RXD3>, 820 <PINMUX_GPIO82__FUNC_GBE_RXD2>, 821 <PINMUX_GPIO83__FUNC_GBE_RXD1>, 822 <PINMUX_GPIO84__FUNC_GBE_RXD0>; 823 }; 824 825 pins-txd { 826 pinmux = <PINMUX_GPIO77__FUNC_GBE_TXD3>, 827 <PINMUX_GPIO78__FUNC_GBE_TXD2>, 828 <PINMUX_GPIO79__FUNC_GBE_TXD1>, 829 <PINMUX_GPIO80__FUNC_GBE_TXD0>; 830 drive-strength = <8>; 831 }; 832 }; 833 834 eth_sleep_pins: eth-sleep-pins { 835 pins-cc { 836 pinmux = <PINMUX_GPIO85__FUNC_GPIO85>, 837 <PINMUX_GPIO86__FUNC_GPIO86>, 838 <PINMUX_GPIO87__FUNC_GPIO87>, 839 <PINMUX_GPIO88__FUNC_GPIO88>; 840 }; 841 842 pins-mdio { 843 pinmux = <PINMUX_GPIO89__FUNC_GPIO89>, 844 <PINMUX_GPIO90__FUNC_GPIO90>; 845 input-disable; 846 bias-disable; 847 }; 848 849 pins-rxd { 850 pinmux = <PINMUX_GPIO81__FUNC_GPIO81>, 851 <PINMUX_GPIO82__FUNC_GPIO82>, 852 <PINMUX_GPIO83__FUNC_GPIO83>, 853 <PINMUX_GPIO84__FUNC_GPIO84>; 854 }; 855 856 pins-txd { 857 pinmux = <PINMUX_GPIO77__FUNC_GPIO77>, 858 <PINMUX_GPIO78__FUNC_GPIO78>, 859 <PINMUX_GPIO79__FUNC_GPIO79>, 860 <PINMUX_GPIO80__FUNC_GPIO80>; 861 }; 862 }; 863 864 gpio_key_pins: gpio-keys-pins { 865 pins { 866 pinmux = <PINMUX_GPIO106__FUNC_GPIO106>; 867 bias-pull-up; 868 input-enable; 869 }; 870 }; 871 872 hdmi_vreg_pins: hdmi-vreg-pins { 873 pins-pwr { 874 pinmux = <PINMUX_GPIO31__FUNC_HDMITX20_PWR5V>; 875 bias-disable; 876 }; 877 }; 878 879 hdmi_pins: hdmi-pins { 880 pins-hotplug { 881 pinmux = <PINMUX_GPIO32__FUNC_HDMITX20_HTPLG>; 882 bias-pull-down; 883 }; 884 885 pins-ddc { 886 pinmux = <PINMUX_GPIO34__FUNC_HDMITX20_SCL>, 887 <PINMUX_GPIO35__FUNC_HDMITX20_SDA>; 888 drive-strength = <10>; 889 }; 890 891 pins-cec { 892 pinmux = <PINMUX_GPIO33__FUNC_HDMITX20_CEC>; 893 bias-disable; 894 }; 895 }; 896 897 i2c0_pins: i2c0-pins { 898 pins { 899 pinmux = <PINMUX_GPIO8__FUNC_SDA0>, 900 <PINMUX_GPIO9__FUNC_SCL0>; 901 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 902 drive-strength-microamp = <1000>; 903 }; 904 }; 905 906 i2c1_pins: i2c1-pins { 907 pins { 908 pinmux = <PINMUX_GPIO10__FUNC_SDA1>, 909 <PINMUX_GPIO11__FUNC_SCL1>; 910 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 911 drive-strength-microamp = <1000>; 912 }; 913 }; 914 915 i2c2_pins: i2c2-pins { 916 pins { 917 pinmux = <PINMUX_GPIO12__FUNC_SDA2>, 918 <PINMUX_GPIO13__FUNC_SCL2>; 919 bias-pull-up = <MTK_PULL_SET_RSEL_111>; 920 drive-strength = <6>; 921 }; 922 }; 923 924 i2c6_pins: i2c6-pins { 925 pins { 926 pinmux = <PINMUX_GPIO25__FUNC_SDA6>, 927 <PINMUX_GPIO26__FUNC_SCL6>; 928 bias-pull-up; 929 }; 930 }; 931 932 mmc0_default_pins: mmc0-default-pins { 933 pins-clk { 934 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 935 drive-strength = <6>; 936 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 937 }; 938 939 pins-cmd-dat { 940 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 941 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 942 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 943 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 944 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 945 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 946 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 947 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 948 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 949 input-enable; 950 drive-strength = <6>; 951 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 952 }; 953 954 pins-rst { 955 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 956 drive-strength = <6>; 957 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 958 }; 959 }; 960 961 mmc0_uhs_pins: mmc0-uhs-pins { 962 pins-clk { 963 pinmux = <PINMUX_GPIO122__FUNC_MSDC0_CLK>; 964 drive-strength = <8>; 965 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 966 }; 967 968 pins-cmd-dat { 969 pinmux = <PINMUX_GPIO126__FUNC_MSDC0_DAT0>, 970 <PINMUX_GPIO125__FUNC_MSDC0_DAT1>, 971 <PINMUX_GPIO124__FUNC_MSDC0_DAT2>, 972 <PINMUX_GPIO123__FUNC_MSDC0_DAT3>, 973 <PINMUX_GPIO119__FUNC_MSDC0_DAT4>, 974 <PINMUX_GPIO118__FUNC_MSDC0_DAT5>, 975 <PINMUX_GPIO117__FUNC_MSDC0_DAT6>, 976 <PINMUX_GPIO116__FUNC_MSDC0_DAT7>, 977 <PINMUX_GPIO121__FUNC_MSDC0_CMD>; 978 input-enable; 979 drive-strength = <8>; 980 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 981 }; 982 983 pins-ds { 984 pinmux = <PINMUX_GPIO127__FUNC_MSDC0_DSL>; 985 drive-strength = <8>; 986 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 987 }; 988 989 pins-rst { 990 pinmux = <PINMUX_GPIO120__FUNC_MSDC0_RSTB>; 991 drive-strength = <8>; 992 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 993 }; 994 }; 995 996 mmc1_default_pins: mmc1-default-pins { 997 pins-clk { 998 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 999 drive-strength = <8>; 1000 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1001 }; 1002 1003 pins-cmd-dat { 1004 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 1005 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 1006 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 1007 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 1008 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 1009 input-enable; 1010 drive-strength = <8>; 1011 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1012 }; 1013 }; 1014 1015 mmc1_uhs_pins: mmc1-uhs-pins { 1016 pins-clk { 1017 pinmux = <PINMUX_GPIO111__FUNC_MSDC1_CLK>; 1018 drive-strength = <8>; 1019 bias-pull-down = <MTK_PUPD_SET_R1R0_10>; 1020 }; 1021 1022 pins-cmd-dat { 1023 pinmux = <PINMUX_GPIO110__FUNC_MSDC1_CMD>, 1024 <PINMUX_GPIO112__FUNC_MSDC1_DAT0>, 1025 <PINMUX_GPIO113__FUNC_MSDC1_DAT1>, 1026 <PINMUX_GPIO114__FUNC_MSDC1_DAT2>, 1027 <PINMUX_GPIO115__FUNC_MSDC1_DAT3>; 1028 input-enable; 1029 drive-strength = <8>; 1030 bias-pull-up = <MTK_PUPD_SET_R1R0_01>; 1031 }; 1032 }; 1033 1034 mt6360_pins: mt6360-pins { 1035 pins { 1036 pinmux = <PINMUX_GPIO17__FUNC_GPIO17>, 1037 <PINMUX_GPIO128__FUNC_GPIO128>; 1038 input-enable; 1039 bias-pull-up; 1040 }; 1041 }; 1042 1043 dsi0_vreg_en_pins: dsi0-vreg-en-pins { 1044 pins-pwr-en { 1045 pinmux = <PINMUX_GPIO47__FUNC_GPIO47>; 1046 output-low; 1047 }; 1048 }; 1049 1050 panel_default_pins: panel-default-pins { 1051 pins-rst { 1052 pinmux = <PINMUX_GPIO108__FUNC_GPIO108>; 1053 output-high; 1054 }; 1055 1056 pins-en { 1057 pinmux = <PINMUX_GPIO48__FUNC_GPIO48>; 1058 output-low; 1059 }; 1060 }; 1061 1062 pcie0_default_pins: pcie0-default-pins { 1063 pins { 1064 pinmux = <PINMUX_GPIO19__FUNC_WAKEN>, 1065 <PINMUX_GPIO20__FUNC_PERSTN>, 1066 <PINMUX_GPIO21__FUNC_CLKREQN>; 1067 bias-pull-up; 1068 }; 1069 }; 1070 1071 pcie0_idle_pins: pcie0-idle-pins { 1072 pins { 1073 pinmux = <PINMUX_GPIO20__FUNC_GPIO20>; 1074 bias-disable; 1075 output-low; 1076 }; 1077 }; 1078 1079 pcie1_default_pins: pcie1-default-pins { 1080 pins { 1081 pinmux = <PINMUX_GPIO22__FUNC_PERSTN_1>, 1082 <PINMUX_GPIO23__FUNC_CLKREQN_1>, 1083 <PINMUX_GPIO24__FUNC_WAKEN_1>; 1084 bias-pull-up; 1085 }; 1086 }; 1087 1088 disp_pwm0_pins: disp-pwm0-pins { 1089 pins-disp-pwm { 1090 pinmux = <PINMUX_GPIO97__FUNC_DISP_PWM0>; 1091 }; 1092 }; 1093 1094 spi1_pins: spi1-pins { 1095 pins { 1096 pinmux = <PINMUX_GPIO136__FUNC_SPIM1_CSB>, 1097 <PINMUX_GPIO137__FUNC_SPIM1_CLK>, 1098 <PINMUX_GPIO138__FUNC_SPIM1_MO>, 1099 <PINMUX_GPIO139__FUNC_SPIM1_MI>; 1100 bias-disable; 1101 }; 1102 }; 1103 1104 spi2_pins: spi-pins { 1105 pins { 1106 pinmux = <PINMUX_GPIO140__FUNC_SPIM2_CSB>, 1107 <PINMUX_GPIO141__FUNC_SPIM2_CLK>, 1108 <PINMUX_GPIO142__FUNC_SPIM2_MO>, 1109 <PINMUX_GPIO143__FUNC_SPIM2_MI>; 1110 bias-disable; 1111 }; 1112 }; 1113 1114 touch_pins: touch-pins { 1115 pins-irq { 1116 pinmux = <PINMUX_GPIO132__FUNC_GPIO132>; 1117 input-enable; 1118 bias-disable; 1119 }; 1120 1121 pins-reset { 1122 pinmux = <PINMUX_GPIO133__FUNC_GPIO133>; 1123 output-high; 1124 }; 1125 }; 1126 1127 u3_p0_vbus: u3-p0-vbus-default-pins { 1128 pins-vbus { 1129 pinmux = <PINMUX_GPIO63__FUNC_VBUSVALID>; 1130 input-enable; 1131 }; 1132 }; 1133 1134 uart0_pins: uart0-pins { 1135 pins { 1136 pinmux = <PINMUX_GPIO98__FUNC_UTXD0>, 1137 <PINMUX_GPIO99__FUNC_URXD0>; 1138 }; 1139 }; 1140 1141 uart1_pins: uart1-pins { 1142 pins { 1143 pinmux = <PINMUX_GPIO100__FUNC_URTS1>, 1144 <PINMUX_GPIO101__FUNC_UCTS1>, 1145 <PINMUX_GPIO102__FUNC_UTXD1>, 1146 <PINMUX_GPIO103__FUNC_URXD1>; 1147 }; 1148 }; 1149}; 1150 1151&pmic { 1152 interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; 1153 1154 mt6359keys: keys { 1155 compatible = "mediatek,mt6359-keys"; 1156 mediatek,long-press-mode = <1>; 1157 power-off-time-sec = <0>; 1158 1159 power-key { 1160 linux,keycodes = <KEY_POWER>; 1161 wakeup-source; 1162 }; 1163 1164 home { 1165 linux,keycodes = <KEY_HOME>; 1166 }; 1167 }; 1168}; 1169 1170&scp { 1171 memory-region = <&scp_mem>; 1172 firmware-name = "mediatek/mt8195/scp.img"; 1173 status = "okay"; 1174}; 1175 1176&sound { 1177 compatible = "mediatek,mt8195_mt6359"; 1178 model = "mt8395-evk"; 1179 pinctrl-names = "default"; 1180 pinctrl-0 = <&audio_default_pins>; 1181 audio-routing = 1182 "Headphone", "Headphone L", 1183 "Headphone", "Headphone R"; 1184 mediatek,adsp = <&adsp>; 1185 status = "okay"; 1186 1187 headphone-dai-link { 1188 link-name = "DL_SRC_BE"; 1189 1190 codec { 1191 sound-dai = <&pmic 0>; 1192 }; 1193 }; 1194 1195 hdmi-dai-link { 1196 link-name = "ETDM3_OUT_BE"; 1197 1198 codec { 1199 sound-dai = <&hdmi 0>; 1200 }; 1201 }; 1202}; 1203 1204&spi1 { 1205 pinctrl-0 = <&spi1_pins>; 1206 pinctrl-names = "default"; 1207 mediatek,pad-select = <0>; 1208 #address-cells = <1>; 1209 #size-cells = <0>; 1210 status = "okay"; 1211 cs-gpios = <&pio 64 GPIO_ACTIVE_LOW>; 1212 1213 can0: can@0 { 1214 compatible = "microchip,mcp2518fd"; 1215 reg = <0>; 1216 clocks = <&can_clk>; 1217 spi-max-frequency = <20000000>; 1218 interrupts-extended = <&pio 16 IRQ_TYPE_LEVEL_LOW>; 1219 vdd-supply = <&mt6359_vcn33_2_bt_ldo_reg>; 1220 xceiver-supply = <&mt6359_vcn33_2_bt_ldo_reg>; 1221 }; 1222}; 1223 1224&spi2 { 1225 pinctrl-0 = <&spi2_pins>; 1226 pinctrl-names = "default"; 1227 mediatek,pad-select = <0>; 1228 #address-cells = <1>; 1229 #size-cells = <0>; 1230 status = "okay"; 1231}; 1232 1233&spmi { 1234 #address-cells = <2>; 1235 #size-cells = <0>; 1236 1237 mt6315_6: pmic@6 { 1238 compatible = "mediatek,mt6315-regulator"; 1239 reg = <0x6 SPMI_USID>; 1240 1241 regulators { 1242 mt6315_6_vbuck1: vbuck1 { 1243 regulator-name = "Vbcpu"; 1244 regulator-min-microvolt = <300000>; 1245 regulator-max-microvolt = <1193750>; 1246 regulator-enable-ramp-delay = <256>; 1247 regulator-allowed-modes = <0 1 2>; 1248 regulator-always-on; 1249 }; 1250 }; 1251 }; 1252 1253 mt6315_7: pmic@7 { 1254 compatible = "mediatek,mt6315-regulator"; 1255 reg = <0x7 SPMI_USID>; 1256 1257 regulators { 1258 mt6315_7_vbuck1: vbuck1 { 1259 regulator-name = "Vgpu"; 1260 regulator-min-microvolt = <546000>; 1261 regulator-max-microvolt = <787000>; 1262 regulator-enable-ramp-delay = <256>; 1263 regulator-allowed-modes = <0 1 2>; 1264 }; 1265 }; 1266 }; 1267}; 1268 1269&u3phy0 { 1270 status = "okay"; 1271}; 1272 1273&u3phy1 { 1274 status = "okay"; 1275 1276 u3port1: usb-phy@700 { 1277 mediatek,force-mode; 1278 }; 1279}; 1280 1281&u3phy2 { 1282 status = "okay"; 1283}; 1284 1285&u3phy3 { 1286 status = "okay"; 1287}; 1288 1289&uart0 { 1290 pinctrl-0 = <&uart0_pins>; 1291 pinctrl-names = "default"; 1292 status = "okay"; 1293}; 1294 1295&uart1 { 1296 pinctrl-0 = <&uart1_pins>; 1297 pinctrl-names = "default"; 1298 status = "okay"; 1299}; 1300 1301&ufsphy { 1302 status = "disabled"; 1303}; 1304 1305&ssusb0 { 1306 dr_mode = "otg"; 1307 pinctrl-names = "default"; 1308 pinctrl-0 = <&u3_p0_vbus>; 1309 usb-role-switch; 1310 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1311 status = "okay"; 1312 1313 ports { 1314 #address-cells = <1>; 1315 #size-cells = <0>; 1316 1317 port@0 { 1318 reg = <0>; 1319 mtu3_hs0_role_sw: endpoint { 1320 remote-endpoint = <&typec_con_hs>; 1321 }; 1322 }; 1323 1324 port@1 { 1325 reg = <1>; 1326 mtu3_ss0_role_sw: endpoint { 1327 remote-endpoint = <&typec_con_ss>; 1328 }; 1329 }; 1330 }; 1331}; 1332 1333&ssusb2 { 1334 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1335 status = "okay"; 1336}; 1337 1338&ssusb3 { 1339 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1340 status = "okay"; 1341}; 1342 1343&vdosys0 { 1344 port { 1345 #address-cells = <1>; 1346 #size-cells = <0>; 1347 1348 vdosys0_ep_main: endpoint@0 { 1349 reg = <0>; 1350 remote-endpoint = <&ovl0_in>; 1351 }; 1352 }; 1353}; 1354 1355&vdosys1 { 1356 port { 1357 #address-cells = <1>; 1358 #size-cells = <0>; 1359 1360 vdosys1_ep_ext: endpoint@1 { 1361 reg = <1>; 1362 remote-endpoint = <ðdr0_in>; 1363 }; 1364 }; 1365}; 1366 1367&xhci0 { 1368 status = "okay"; 1369}; 1370 1371&xhci1 { 1372 vusb33-supply = <&mt6359_vusb_ldo_reg>; 1373 status = "okay"; 1374}; 1375 1376&xhci2 { 1377 status = "okay"; 1378}; 1379 1380&xhci3 { 1381 status = "okay"; 1382}; 1383