1// SPDX-License-Identifier: (GPL-2.0-only OR MIT) 2/* 3 * Copyright 2025-2026 NXP 4 */ 5 6#include <dt-bindings/dma/fsl-edma.h> 7#include <dt-bindings/gpio/gpio.h> 8#include <dt-bindings/interrupt-controller/arm-gic.h> 9 10#include "imx952-clock.h" 11#include "imx952-pinfunc.h" 12#include "imx952-power.h" 13 14/ { 15 interrupt-parent = <&gic>; 16 #address-cells = <2>; 17 #size-cells = <2>; 18 19 clk_ext1: clock-ext1 { 20 compatible = "fixed-clock"; 21 #clock-cells = <0>; 22 clock-frequency = <133000000>; 23 clock-output-names = "clk_ext1"; 24 }; 25 26 clk_dummy: clock-dummy { 27 compatible = "fixed-clock"; 28 #clock-cells = <0>; 29 clock-frequency = <0>; 30 clock-output-names = "dummy"; 31 }; 32 33 clk_ldb_pll_pixel: clock-ldb-pll-div7 { 34 compatible = "fixed-factor-clock"; 35 clocks = <&scmi_clk IMX952_CLK_LDBPLL>; 36 #clock-cells = <0>; 37 clock-div = <7>; 38 clock-mult = <1>; 39 clock-output-names = "ldb_pll_div7"; 40 }; 41 42 clk_osc_24m: clock-osc-24m { 43 compatible = "fixed-clock"; 44 #clock-cells = <0>; 45 clock-frequency = <24000000>; 46 clock-output-names = "osc_24m"; 47 }; 48 49 cpus { 50 #address-cells = <1>; 51 #size-cells = <0>; 52 53 idle-states { 54 entry-method = "psci"; 55 56 cpu_pd_wait: cpu-pd-wait { 57 compatible = "arm,idle-state"; 58 arm,psci-suspend-param = <0x0010033>; 59 local-timer-stop; 60 entry-latency-us = <1000>; 61 exit-latency-us = <700>; 62 min-residency-us = <2700>; 63 wakeup-latency-us = <1500>; 64 }; 65 }; 66 67 A55_0: cpu@0 { 68 device_type = "cpu"; 69 compatible = "arm,cortex-a55"; 70 reg = <0x0>; 71 enable-method = "psci"; 72 #cooling-cells = <2>; 73 cpu-idle-states = <&cpu_pd_wait>; 74 power-domains = <&scmi_perf IMX952_PERF_A55>; 75 power-domain-names = "perf"; 76 i-cache-size = <32768>; 77 i-cache-line-size = <64>; 78 i-cache-sets = <128>; 79 d-cache-size = <32768>; 80 d-cache-line-size = <64>; 81 d-cache-sets = <128>; 82 next-level-cache = <&l2_cache_l0>; 83 }; 84 85 A55_1: cpu@100 { 86 device_type = "cpu"; 87 compatible = "arm,cortex-a55"; 88 reg = <0x100>; 89 enable-method = "psci"; 90 #cooling-cells = <2>; 91 cpu-idle-states = <&cpu_pd_wait>; 92 power-domains = <&scmi_perf IMX952_PERF_A55>; 93 power-domain-names = "perf"; 94 i-cache-size = <32768>; 95 i-cache-line-size = <64>; 96 i-cache-sets = <128>; 97 d-cache-size = <32768>; 98 d-cache-line-size = <64>; 99 d-cache-sets = <128>; 100 next-level-cache = <&l2_cache_l1>; 101 }; 102 103 A55_2: cpu@200 { 104 device_type = "cpu"; 105 compatible = "arm,cortex-a55"; 106 reg = <0x200>; 107 enable-method = "psci"; 108 #cooling-cells = <2>; 109 cpu-idle-states = <&cpu_pd_wait>; 110 power-domains = <&scmi_perf IMX952_PERF_A55>; 111 power-domain-names = "perf"; 112 i-cache-size = <32768>; 113 i-cache-line-size = <64>; 114 i-cache-sets = <128>; 115 d-cache-size = <32768>; 116 d-cache-line-size = <64>; 117 d-cache-sets = <128>; 118 next-level-cache = <&l2_cache_l2>; 119 }; 120 121 A55_3: cpu@300 { 122 device_type = "cpu"; 123 compatible = "arm,cortex-a55"; 124 reg = <0x300>; 125 enable-method = "psci"; 126 #cooling-cells = <2>; 127 cpu-idle-states = <&cpu_pd_wait>; 128 power-domains = <&scmi_perf IMX952_PERF_A55>; 129 power-domain-names = "perf"; 130 i-cache-size = <32768>; 131 i-cache-line-size = <64>; 132 i-cache-sets = <128>; 133 d-cache-size = <32768>; 134 d-cache-line-size = <64>; 135 d-cache-sets = <128>; 136 next-level-cache = <&l2_cache_l3>; 137 }; 138 139 l2_cache_l0: l2-cache-l0 { 140 compatible = "cache"; 141 cache-size = <65536>; 142 cache-line-size = <64>; 143 cache-sets = <256>; 144 cache-level = <2>; 145 cache-unified; 146 next-level-cache = <&l3_cache>; 147 }; 148 149 l2_cache_l1: l2-cache-l1 { 150 compatible = "cache"; 151 cache-size = <65536>; 152 cache-line-size = <64>; 153 cache-sets = <256>; 154 cache-level = <2>; 155 cache-unified; 156 next-level-cache = <&l3_cache>; 157 }; 158 159 l2_cache_l2: l2-cache-l2 { 160 compatible = "cache"; 161 cache-size = <65536>; 162 cache-line-size = <64>; 163 cache-sets = <256>; 164 cache-level = <2>; 165 cache-unified; 166 next-level-cache = <&l3_cache>; 167 }; 168 169 l2_cache_l3: l2-cache-l3 { 170 compatible = "cache"; 171 cache-size = <65536>; 172 cache-line-size = <64>; 173 cache-sets = <256>; 174 cache-level = <2>; 175 cache-unified; 176 next-level-cache = <&l3_cache>; 177 }; 178 179 l3_cache: l3-cache { 180 compatible = "cache"; 181 cache-size = <524288>; 182 cache-line-size = <64>; 183 cache-sets = <512>; 184 cache-level = <3>; 185 cache-unified; 186 }; 187 188 cpu-map { 189 cluster0 { 190 core0 { 191 cpu = <&A55_0>; 192 }; 193 194 core1 { 195 cpu = <&A55_1>; 196 }; 197 198 core2 { 199 cpu = <&A55_2>; 200 }; 201 202 core3 { 203 cpu = <&A55_3>; 204 }; 205 }; 206 }; 207 }; 208 209 firmware { 210 scmi { 211 compatible = "arm,scmi"; 212 mboxes = <&mu2 5 0>, <&mu2 3 0>, <&mu2 3 1>, <&mu2 5 1>; 213 shmem = <&scmi_buf0>, <&scmi_buf1>; 214 #address-cells = <1>; 215 #size-cells = <0>; 216 arm,max-rx-timeout-ms = <5000>; 217 218 scmi_devpd: protocol@11 { 219 reg = <0x11>; 220 #power-domain-cells = <1>; 221 }; 222 223 scmi_sys_power: protocol@12 { 224 reg = <0x12>; 225 }; 226 227 scmi_perf: protocol@13 { 228 reg = <0x13>; 229 #power-domain-cells = <1>; 230 }; 231 232 scmi_clk: protocol@14 { 233 reg = <0x14>; 234 #clock-cells = <1>; 235 }; 236 237 scmi_sensor: protocol@15 { 238 reg = <0x15>; 239 #thermal-sensor-cells = <1>; 240 }; 241 242 scmi_iomuxc: protocol@19 { 243 reg = <0x19>; 244 }; 245 246 scmi_lmm: protocol@80 { 247 reg = <0x80>; 248 }; 249 250 scmi_bbm: protocol@81 { 251 reg = <0x81>; 252 }; 253 254 scmi_cpu: protocol@82 { 255 reg = <0x82>; 256 }; 257 258 scmi_misc: protocol@84 { 259 reg = <0x84>; 260 }; 261 }; 262 }; 263 264 gic: interrupt-controller@48000000 { 265 compatible = "arm,gic-v3"; 266 reg = <0 0x48000000 0 0x10000>, 267 <0 0x48060000 0 0xc0000>; 268 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>; 269 interrupt-parent = <&gic>; 270 interrupt-controller; 271 #interrupt-cells = <3>; 272 dma-noncoherent; 273 #address-cells = <2>; 274 #size-cells = <2>; 275 ranges; 276 277 its: msi-controller@48040000 { 278 compatible = "arm,gic-v3-its"; 279 reg = <0 0x48040000 0 0x20000>; 280 msi-controller; 281 #msi-cells = <1>; 282 dma-noncoherent; 283 }; 284 }; 285 286 pmu { 287 compatible = "arm,cortex-a55-pmu"; 288 interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; 289 }; 290 291 psci { 292 compatible = "arm,psci-1.0"; 293 method = "smc"; 294 }; 295 296 timer { 297 compatible = "arm,armv8-timer"; 298 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_LOW>, 299 <GIC_PPI 14 IRQ_TYPE_LEVEL_LOW>, 300 <GIC_PPI 11 IRQ_TYPE_LEVEL_LOW>, 301 <GIC_PPI 10 IRQ_TYPE_LEVEL_LOW>; 302 clock-frequency = <24000000>; 303 arm,no-tick-in-suspend; 304 interrupt-parent = <&gic>; 305 }; 306 307 usbphynop1: usbphynop1 { 308 compatible = "usb-nop-xceiv"; 309 #phy-cells = <0>; 310 clocks = <&clk_dummy>; 311 clock-names = "main_clk"; 312 }; 313 314 usbphynop2: usbphynop2 { 315 compatible = "usb-nop-xceiv"; 316 #phy-cells = <0>; 317 clocks = <&clk_dummy>; 318 clock-names = "main_clk"; 319 }; 320 321 soc { 322 compatible = "simple-bus"; 323 #address-cells = <2>; 324 #size-cells = <2>; 325 ranges = <0x0 0x0 0x0 0x0 0x0 0x80000000>, 326 <0x0 0x28000000 0x0 0x28000000 0x0 0x10000000>; 327 328 aips2: bus@42000000 { 329 compatible = "fsl,aips-bus", "simple-bus"; 330 reg = <0x0 0x42000000 0x0 0x800000>; 331 ranges = <0x42000000 0x0 0x42000000 0x8000000>, 332 <0x28000000 0x0 0x28000000 0x10000000>; 333 #address-cells = <1>; 334 #size-cells = <1>; 335 336 mu7: mailbox@42050000 { 337 compatible = "fsl,imx95-mu"; 338 reg = <0x42050000 0x10000>; 339 interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; 340 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; 341 #mbox-cells = <2>; 342 status = "disabled"; 343 }; 344 345 wdog3: watchdog@420b0000 { 346 compatible = "fsl,imx93-wdt"; 347 reg = <0x420b0000 0x10000>; 348 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>; 349 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; 350 timeout-sec = <40>; 351 status = "disabled"; 352 }; 353 354 tpm3: pwm@42100000 { 355 compatible = "fsl,imx7ulp-pwm"; 356 reg = <0x42100000 0x1000>; 357 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; 358 #pwm-cells = <3>; 359 status = "disabled"; 360 }; 361 362 tpm4: pwm@42110000 { 363 compatible = "fsl,imx7ulp-pwm"; 364 reg = <0x42110000 0x1000>; 365 clocks = <&scmi_clk IMX952_CLK_TPM4>; 366 #pwm-cells = <3>; 367 status = "disabled"; 368 }; 369 370 tpm5: pwm@42120000 { 371 compatible = "fsl,imx7ulp-pwm"; 372 reg = <0x42120000 0x1000>; 373 clocks = <&scmi_clk IMX952_CLK_TPM5>; 374 #pwm-cells = <3>; 375 status = "disabled"; 376 }; 377 378 tpm6: pwm@42130000 { 379 compatible = "fsl,imx7ulp-pwm"; 380 reg = <0x42130000 0x1000>; 381 clocks = <&scmi_clk IMX952_CLK_TPM6>; 382 #pwm-cells = <3>; 383 status = "disabled"; 384 }; 385 386 i3c2: i3c@42140000 { 387 compatible = "silvaco,i3c-master-v1"; 388 reg = <0x42140000 0x10000>; 389 interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>; 390 #address-cells = <3>; 391 #size-cells = <0>; 392 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 393 <&scmi_clk IMX952_CLK_I3C2SLOW>, 394 <&clk_dummy>; 395 clock-names = "pclk", "fast_clk", "slow_clk"; 396 status = "disabled"; 397 }; 398 399 lpi2c3: i2c@42150000 { 400 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 401 reg = <0x42150000 0x10000>; 402 interrupts = <GIC_SPI 58 IRQ_TYPE_LEVEL_HIGH>; 403 clocks = <&scmi_clk IMX952_CLK_LPI2C3>, 404 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 405 clock-names = "per", "ipg"; 406 #address-cells = <1>; 407 #size-cells = <0>; 408 dmas = <&edma2 8 0 0>, <&edma2 9 0 FSL_EDMA_RX>; 409 dma-names = "tx", "rx"; 410 status = "disabled"; 411 }; 412 413 lpi2c4: i2c@42160000 { 414 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 415 reg = <0x42160000 0x10000>; 416 interrupts = <GIC_SPI 59 IRQ_TYPE_LEVEL_HIGH>; 417 clocks = <&scmi_clk IMX952_CLK_LPI2C4>, 418 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 419 clock-names = "per", "ipg"; 420 #address-cells = <1>; 421 #size-cells = <0>; 422 dmas = <&edma2 10 0 0>, <&edma2 11 0 FSL_EDMA_RX>; 423 dma-names = "tx", "rx"; 424 status = "disabled"; 425 }; 426 427 lpspi3: spi@42170000 { 428 #address-cells = <1>; 429 #size-cells = <0>; 430 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 431 reg = <0x42170000 0x10000>; 432 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>; 433 clocks = <&scmi_clk IMX952_CLK_LPSPI3>, 434 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 435 clock-names = "per", "ipg"; 436 dmas = <&edma2 12 0 0>, <&edma2 13 0 FSL_EDMA_RX>; 437 dma-names = "tx", "rx"; 438 status = "disabled"; 439 }; 440 441 lpspi4: spi@42180000 { 442 #address-cells = <1>; 443 #size-cells = <0>; 444 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 445 reg = <0x42180000 0x10000>; 446 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>; 447 clocks = <&scmi_clk IMX952_CLK_LPSPI4>, 448 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 449 clock-names = "per", "ipg"; 450 dmas = <&edma2 14 0 0>, <&edma2 15 0 FSL_EDMA_RX>; 451 dma-names = "tx", "rx"; 452 status = "disabled"; 453 }; 454 455 lpuart3: serial@42190000 { 456 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 457 "fsl,imx7ulp-lpuart"; 458 reg = <0x42190000 0x1000>; 459 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>; 460 clocks = <&scmi_clk IMX952_CLK_LPUART3>; 461 clock-names = "ipg"; 462 dmas = <&edma2 18 0 FSL_EDMA_RX>, <&edma2 17 0 0>; 463 dma-names = "rx", "tx"; 464 status = "disabled"; 465 }; 466 467 lpuart4: serial@421a0000 { 468 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 469 "fsl,imx7ulp-lpuart"; 470 reg = <0x421a0000 0x1000>; 471 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>; 472 clocks = <&scmi_clk IMX952_CLK_LPUART4>; 473 clock-names = "ipg"; 474 dmas = <&edma2 20 0 FSL_EDMA_RX>, <&edma2 19 0 0>; 475 dma-names = "rx", "tx"; 476 status = "disabled"; 477 }; 478 479 lpuart5: serial@421b0000 { 480 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 481 "fsl,imx7ulp-lpuart"; 482 reg = <0x421b0000 0x1000>; 483 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>; 484 clocks = <&scmi_clk IMX952_CLK_LPUART5>; 485 clock-names = "ipg"; 486 dmas = <&edma2 22 0 FSL_EDMA_RX>, <&edma2 21 0 0>; 487 dma-names = "rx", "tx"; 488 status = "disabled"; 489 }; 490 491 lpuart6: serial@421c0000 { 492 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 493 "fsl,imx7ulp-lpuart"; 494 reg = <0x421c0000 0x1000>; 495 interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>; 496 clocks = <&scmi_clk IMX952_CLK_LPUART6>; 497 clock-names = "ipg"; 498 dmas = <&edma2 24 0 FSL_EDMA_RX>, <&edma2 23 0 0>; 499 dma-names = "rx", "tx"; 500 status = "disabled"; 501 }; 502 503 flexcan2: can@421d0000 { 504 compatible = "fsl,imx95-flexcan"; 505 reg = <0x421d0000 0x10000>; 506 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; 507 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 508 <&scmi_clk IMX952_CLK_CAN2>; 509 clock-names = "ipg", "per"; 510 assigned-clocks = <&scmi_clk IMX952_CLK_CAN2>; 511 assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; 512 assigned-clock-rates = <40000000>; 513 fsl,clk-source = /bits/ 8 <0>; 514 status = "disabled"; 515 }; 516 517 flexcan3: can@42220000 { 518 compatible = "fsl,imx95-flexcan"; 519 reg = <0x42220000 0x10000>; 520 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; 521 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 522 <&scmi_clk IMX952_CLK_CAN3>; 523 clock-names = "ipg", "per"; 524 assigned-clocks = <&scmi_clk IMX952_CLK_CAN3>; 525 assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; 526 assigned-clock-rates = <40000000>; 527 fsl,clk-source = /bits/ 8 <0>; 528 status = "disabled"; 529 }; 530 531 lpuart7: serial@422b0000 { 532 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 533 "fsl,imx7ulp-lpuart"; 534 reg = <0x422b0000 0x1000>; 535 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>; 536 clocks = <&scmi_clk IMX952_CLK_LPUART7>; 537 clock-names = "ipg"; 538 dmas = <&edma2 88 0 FSL_EDMA_RX>, <&edma2 87 0 0>; 539 dma-names = "rx", "tx"; 540 status = "disabled"; 541 }; 542 543 lpuart8: serial@422c0000 { 544 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 545 "fsl,imx7ulp-lpuart"; 546 reg = <0x422c0000 0x1000>; 547 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>; 548 clocks = <&scmi_clk IMX952_CLK_LPUART8>; 549 clock-names = "ipg"; 550 dmas = <&edma2 90 0 FSL_EDMA_RX>, <&edma2 89 0 0>; 551 dma-names = "rx", "tx"; 552 status = "disabled"; 553 }; 554 555 lpi2c5: i2c@422d0000 { 556 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 557 reg = <0x422d0000 0x10000>; 558 interrupts = <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>; 559 clocks = <&scmi_clk IMX952_CLK_LPI2C5>, 560 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 561 clock-names = "per", "ipg"; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 dmas = <&edma2 71 0 0>, <&edma2 72 0 FSL_EDMA_RX>; 565 dma-names = "tx", "rx"; 566 status = "disabled"; 567 }; 568 569 lpi2c6: i2c@422e0000 { 570 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 571 reg = <0x422e0000 0x10000>; 572 interrupts = <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>; 573 clocks = <&scmi_clk IMX952_CLK_LPI2C6>, 574 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 575 clock-names = "per", "ipg"; 576 #address-cells = <1>; 577 #size-cells = <0>; 578 dmas = <&edma2 73 0 0>, <&edma2 74 0 FSL_EDMA_RX>; 579 dma-names = "tx", "rx"; 580 status = "disabled"; 581 }; 582 583 lpi2c7: i2c@422f0000 { 584 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 585 reg = <0x422f0000 0x10000>; 586 interrupts = <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>; 587 clocks = <&scmi_clk IMX952_CLK_LPI2C7>, 588 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 589 clock-names = "per", "ipg"; 590 #address-cells = <1>; 591 #size-cells = <0>; 592 dmas = <&edma2 75 0 0>, <&edma2 76 0 FSL_EDMA_RX>; 593 dma-names = "tx", "rx"; 594 status = "disabled"; 595 }; 596 597 lpi2c8: i2c@42300000 { 598 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 599 reg = <0x42300000 0x10000>; 600 interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>; 601 clocks = <&scmi_clk IMX952_CLK_LPI2C8>, 602 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 603 clock-names = "per", "ipg"; 604 #address-cells = <1>; 605 #size-cells = <0>; 606 dmas = <&edma2 77 0 0>, <&edma2 78 0 FSL_EDMA_RX>; 607 dma-names = "tx", "rx"; 608 status = "disabled"; 609 }; 610 611 lpspi5: spi@42310000 { 612 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 613 reg = <0x42310000 0x10000>; 614 interrupts = <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>; 615 #address-cells = <1>; 616 #size-cells = <0>; 617 clocks = <&scmi_clk IMX952_CLK_LPSPI5>, 618 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 619 clock-names = "per", "ipg"; 620 dmas = <&edma2 79 0 0>, <&edma2 80 0 FSL_EDMA_RX>; 621 dma-names = "tx", "rx"; 622 status = "disabled"; 623 }; 624 625 lpspi6: spi@42320000 { 626 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 627 reg = <0x42320000 0x10000>; 628 interrupts = <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>; 629 #address-cells = <1>; 630 #size-cells = <0>; 631 clocks = <&scmi_clk IMX952_CLK_LPSPI6>, 632 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 633 clock-names = "per", "ipg"; 634 dmas = <&edma2 81 0 0>, <&edma2 82 0 FSL_EDMA_RX>; 635 dma-names = "tx", "rx"; 636 status = "disabled"; 637 }; 638 639 lpspi7: spi@42330000 { 640 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 641 reg = <0x42330000 0x10000>; 642 interrupts = <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>; 643 #address-cells = <1>; 644 #size-cells = <0>; 645 clocks = <&scmi_clk IMX952_CLK_LPSPI7>, 646 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 647 clock-names = "per", "ipg"; 648 dmas = <&edma2 83 0 0>, <&edma2 84 0 FSL_EDMA_RX>; 649 dma-names = "tx", "rx"; 650 status = "disabled"; 651 }; 652 653 lpspi8: spi@42340000 { 654 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 655 reg = <0x42340000 0x10000>; 656 interrupts = <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>; 657 #address-cells = <1>; 658 #size-cells = <0>; 659 clocks = <&scmi_clk IMX952_CLK_LPSPI8>, 660 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 661 clock-names = "per", "ipg"; 662 dmas = <&edma2 85 0 0>, <&edma2 86 0 FSL_EDMA_RX>; 663 dma-names = "tx", "rx"; 664 status = "disabled"; 665 }; 666 667 mu8: mailbox@42350000 { 668 compatible = "fsl,imx95-mu"; 669 reg = <0x42350000 0x10000>; 670 interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; 671 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; 672 #mbox-cells = <2>; 673 status = "disabled"; 674 }; 675 676 xspi1: spi@42400000 { 677 compatible = "nxp,imx952-xspi", "nxp,imx94-xspi"; 678 reg = <0x42400000 0x50000>, <0x28000000 0x8000000>; 679 reg-names = "base", "mmap"; 680 interrupts = <GIC_SPI 400 IRQ_TYPE_LEVEL_HIGH>, 681 <GIC_SPI 401 IRQ_TYPE_LEVEL_HIGH>, 682 <GIC_SPI 402 IRQ_TYPE_LEVEL_HIGH>, 683 <GIC_SPI 403 IRQ_TYPE_LEVEL_HIGH>, 684 <GIC_SPI 404 IRQ_TYPE_LEVEL_HIGH>; 685 #address-cells = <1>; 686 #size-cells = <0>; 687 clocks = <&scmi_clk IMX952_CLK_XSPI1>; 688 clock-names = "per"; 689 assigned-clocks = <&scmi_clk IMX952_CLK_XSPI1>; 690 assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; 691 assigned-clock-rates = <200000000>; 692 status = "disabled"; 693 }; 694 }; 695 696 aips3: bus@42800000 { 697 compatible = "fsl,aips-bus", "simple-bus"; 698 reg = <0 0x42800000 0 0x800000>; 699 #address-cells = <1>; 700 #size-cells = <1>; 701 ranges = <0x42800000 0x0 0x42800000 0x800000>; 702 703 edma2: dma-controller@42800000 { 704 compatible = "fsl,imx95-edma5"; 705 reg = <0x42800000 0x210000>; 706 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>; 707 clock-names = "dma"; 708 #dma-cells = <3>; 709 dma-channels = <64>; 710 interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 711 <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH>, 712 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 713 <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH>, 714 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 715 <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>, 716 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 717 <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, 718 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 719 <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>, 720 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 721 <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>, 722 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 723 <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>, 724 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 725 <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, 726 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 727 <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>, 728 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 729 <GIC_SPI 137 IRQ_TYPE_LEVEL_HIGH>, 730 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 731 <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>, 732 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 733 <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>, 734 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 735 <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>, 736 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 737 <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, 738 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 739 <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, 740 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 741 <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, 742 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 743 <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>, 744 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 745 <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>, 746 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 747 <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, 748 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 749 <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, 750 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 751 <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, 752 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 753 <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, 754 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 755 <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, 756 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 757 <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, 758 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 759 <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, 760 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 761 <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, 762 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 763 <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, 764 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 765 <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, 766 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 767 <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, 768 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 769 <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, 770 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 771 <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, 772 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 773 <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, 774 <GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>; //error irq 775 }; 776 777 usdhc1: mmc@42c20000 { 778 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 779 reg = <0x42c20000 0x10000>; 780 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; 781 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 782 <&scmi_clk IMX952_CLK_WAKEUPAXI>, 783 <&scmi_clk IMX952_CLK_USDHC1>; 784 clock-names = "ipg", "ahb", "per"; 785 assigned-clocks = <&scmi_clk IMX952_CLK_USDHC1>; 786 assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; 787 assigned-clock-rates = <400000000>; 788 bus-width = <8>; 789 fsl,tuning-start-tap = <1>; 790 fsl,tuning-step= <2>; 791 status = "disabled"; 792 }; 793 794 usdhc2: mmc@42c30000 { 795 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 796 reg = <0x42c30000 0x10000>; 797 interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>; 798 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 799 <&scmi_clk IMX952_CLK_WAKEUPAXI>, 800 <&scmi_clk IMX952_CLK_USDHC2>; 801 clock-names = "ipg", "ahb", "per"; 802 assigned-clocks = <&scmi_clk IMX952_CLK_USDHC2>; 803 assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1>; 804 assigned-clock-rates = <200000000>; 805 bus-width = <4>; 806 fsl,tuning-start-tap = <1>; 807 fsl,tuning-step= <2>; 808 status = "disabled"; 809 }; 810 811 usdhc3: mmc@42c40000 { 812 compatible = "fsl,imx95-usdhc", "fsl,imx8mm-usdhc"; 813 reg = <0x42c40000 0x10000>; 814 interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>; 815 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 816 <&scmi_clk IMX952_CLK_WAKEUPAXI>, 817 <&scmi_clk IMX952_CLK_USDHC3>; 818 clock-names = "ipg", "ahb", "per"; 819 bus-width = <4>; 820 fsl,tuning-start-tap = <1>; 821 fsl,tuning-step = <2>; 822 status = "disabled"; 823 }; 824 }; 825 826 aips5: bus@43000000 { 827 compatible = "fsl,aips-bus", "simple-bus"; 828 reg = <0 0x43000000 0 0x800000>; 829 #address-cells = <1>; 830 #size-cells = <1>; 831 ranges = <0x43000000 0x0 0x43000000 0x800000>; 832 833 asrc1: asrc@43000000 { 834 compatible = "fsl,imx952-asrc"; 835 reg = <0x43000000 0x10000>; 836 interrupts = <GIC_SPI 376 IRQ_TYPE_LEVEL_HIGH>; 837 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 838 <&scmi_clk IMX952_CLK_BUSWAKEUP>, 839 <&scmi_clk IMX952_CLK_ASRC1>, 840 <&scmi_clk IMX952_CLK_ASRC2>, 841 <&clk_dummy>, 842 <&clk_dummy>, 843 <&clk_dummy>, 844 <&clk_dummy>, 845 <&clk_dummy>, 846 <&clk_dummy>, 847 <&clk_dummy>, 848 <&clk_dummy>, 849 <&clk_dummy>, 850 <&clk_dummy>, 851 <&clk_dummy>, 852 <&clk_dummy>, 853 <&clk_dummy>, 854 <&clk_dummy>, 855 <&clk_dummy>; 856 clock-names = "mem", "ipg", 857 "asrck_0", "asrck_1", "asrck_2", "asrck_3", 858 "asrck_4", "asrck_5", "asrck_6", "asrck_7", 859 "asrck_8", "asrck_9", "asrck_a", "asrck_b", 860 "asrck_c", "asrck_d", "asrck_e", "asrck_f", 861 "spba"; 862 dmas = <&edma2 97 0 0>, <&edma2 98 0 0>, <&edma2 99 0 0>, 863 <&edma2 100 0 FSL_EDMA_RX>, <&edma2 101 0 FSL_EDMA_RX>, 864 <&edma2 102 0 FSL_EDMA_RX>; 865 /* tx* is output channel of asrc, it is rx channel for eDMA */ 866 dma-names = "rxa", "rxb", "rxc", 867 "txa", "txb", "txc"; 868 #sound-dai-cells = <0>; 869 fsl,asrc-rate = <8000>; 870 fsl,asrc-width = <16>; 871 status = "disabled"; 872 }; 873 874 asrc2: asrc@430f0000 { 875 compatible = "fsl,imx952-asrc"; 876 reg = <0x430f0000 0x10000>; 877 interrupts = <GIC_SPI 384 IRQ_TYPE_LEVEL_HIGH>; 878 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 879 <&scmi_clk IMX952_CLK_BUSWAKEUP>, 880 <&scmi_clk IMX952_CLK_ASRC1>, 881 <&scmi_clk IMX952_CLK_ASRC2>, 882 <&clk_dummy>, 883 <&clk_dummy>, 884 <&clk_dummy>, 885 <&clk_dummy>, 886 <&clk_dummy>, 887 <&clk_dummy>, 888 <&clk_dummy>, 889 <&clk_dummy>, 890 <&clk_dummy>, 891 <&clk_dummy>, 892 <&clk_dummy>, 893 <&clk_dummy>, 894 <&clk_dummy>, 895 <&clk_dummy>, 896 <&clk_dummy>; 897 clock-names = "mem", "ipg", 898 "asrck_0", "asrck_1", "asrck_2", "asrck_3", 899 "asrck_4", "asrck_5", "asrck_6", "asrck_7", 900 "asrck_8", "asrck_9", "asrck_a", "asrck_b", 901 "asrck_c", "asrck_d", "asrck_e", "asrck_f", 902 "spba"; 903 dmas = <&edma2 103 0 0>, <&edma2 104 0 0>, <&edma2 105 0 0>, 904 <&edma2 106 0 FSL_EDMA_RX>, <&edma2 107 0 FSL_EDMA_RX>, 905 <&edma2 108 0 FSL_EDMA_RX>; 906 /* tx* is output channel of asrc, it is rx channel for eDMA */ 907 dma-names = "rxa", "rxb", "rxc", 908 "txa", "txb", "txc"; 909 #sound-dai-cells = <0>; 910 fsl,asrc-rate = <8000>; 911 fsl,asrc-width = <16>; 912 status = "disabled"; 913 }; 914 915 amix: amix@431f0000 { 916 compatible = "fsl,imx952-audmix"; 917 reg = <0x431f0000 0x10000>; 918 clocks = <&scmi_clk IMX952_CLK_AUDMIX1>; 919 clock-names = "ipg"; 920 status = "disabled"; 921 }; 922 923 sai3: sai@433e0000 { 924 compatible = "fsl,imx952-sai", "fsl,imx95-sai"; 925 reg = <0x433e0000 0x10000>; 926 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>; 927 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, 928 <&scmi_clk IMX952_CLK_SAI3>, <&clk_dummy>, 929 <&clk_dummy>; 930 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 931 dmas = <&edma2 61 0 FSL_EDMA_RX>, <&edma2 60 0 0>; 932 dma-names = "rx", "tx"; 933 #sound-dai-cells = <0>; 934 status = "disabled"; 935 }; 936 937 sai4: sai@433f0000 { 938 compatible = "fsl,imx952-sai", "fsl,imx95-sai"; 939 reg = <0x433f0000 0x10000>; 940 interrupts = <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>; 941 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, 942 <&scmi_clk IMX952_CLK_SAI4>, <&clk_dummy>, 943 <&clk_dummy>; 944 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 945 dmas = <&edma2 68 0 FSL_EDMA_RX>, <&edma2 67 0 0>; 946 dma-names = "rx", "tx"; 947 #sound-dai-cells = <0>; 948 status = "disabled"; 949 }; 950 951 sai5: sai@43400000 { 952 compatible = "fsl,imx952-sai", "fsl,imx95-sai"; 953 reg = <0x43400000 0x10000>; 954 interrupts = <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>; 955 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, 956 <&scmi_clk IMX952_CLK_SAI5>, <&clk_dummy>, 957 <&clk_dummy>; 958 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 959 dmas = <&edma2 70 0 FSL_EDMA_RX>, <&edma2 69 0 0>; 960 dma-names = "rx", "tx"; 961 #sound-dai-cells = <0>; 962 status = "disabled"; 963 }; 964 965 sai6: sai@43410000 { 966 compatible = "fsl,imx952-sai", "fsl,imx95-sai"; 967 reg = <0x43410000 0x10000>; 968 interrupts = <GIC_SPI 399 IRQ_TYPE_LEVEL_HIGH>; 969 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, <&clk_dummy>, 970 <&scmi_clk IMX952_CLK_SAI3>, <&clk_dummy>, 971 <&clk_dummy>; 972 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 973 dmas = <&edma2 96 0 FSL_EDMA_RX>, <&edma2 95 0 0>; 974 dma-names = "rx", "tx"; 975 #sound-dai-cells = <0>; 976 status = "disabled"; 977 }; 978 }; 979 980 gpio2: gpio@43810000 { 981 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 982 reg = <0x0 0x43810000 0x0 0x1000>; 983 gpio-controller; 984 #gpio-cells = <2>; 985 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>, 986 <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>; 987 interrupt-controller; 988 #interrupt-cells = <2>; 989 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 990 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 991 clock-names = "gpio", "port"; 992 gpio-ranges = <&scmi_iomuxc 0 4 32>; 993 ngpios = <32>; 994 }; 995 996 gpio3: gpio@43820000 { 997 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 998 reg = <0x0 0x43820000 0x0 0x1000>; 999 gpio-controller; 1000 #gpio-cells = <2>; 1001 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>, 1002 <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>; 1003 interrupt-controller; 1004 #interrupt-cells = <2>; 1005 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 1006 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 1007 clock-names = "gpio", "port"; 1008 gpio-ranges = <&scmi_iomuxc 0 115 8>, <&scmi_iomuxc 8 85 18>, 1009 <&scmi_iomuxc 26 53 2>, <&scmi_iomuxc 28 0 4>; 1010 ngpios = <32>; 1011 }; 1012 1013 gpio4: gpio@43840000 { 1014 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1015 reg = <0x0 0x43840000 0x0 0x1000>; 1016 gpio-controller; 1017 #gpio-cells = <2>; 1018 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>, 1019 <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>; 1020 interrupt-controller; 1021 #interrupt-cells = <2>; 1022 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 1023 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 1024 clock-names = "gpio", "port"; 1025 gpio-ranges = <&scmi_iomuxc 0 57 28>, <&scmi_iomuxc 28 55 2>; 1026 ngpios = <30>; 1027 }; 1028 1029 gpio5: gpio@43850000 { 1030 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1031 reg = <0x0 0x43850000 0x0 0x1000>; 1032 gpio-controller; 1033 #gpio-cells = <2>; 1034 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>, 1035 <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; 1036 interrupt-controller; 1037 #interrupt-cells = <2>; 1038 clocks = <&scmi_clk IMX952_CLK_BUSWAKEUP>, 1039 <&scmi_clk IMX952_CLK_BUSWAKEUP>; 1040 clock-names = "gpio", "port"; 1041 gpio-ranges = <&scmi_iomuxc 0 103 12>, <&scmi_iomuxc 12 36 6>; 1042 ngpios = <18>; 1043 }; 1044 1045 aips1: bus@44000000 { 1046 compatible = "fsl,aips-bus", "simple-bus"; 1047 reg = <0x0 0x44000000 0x0 0x800000>; 1048 ranges = <0x44000000 0x0 0x44000000 0x800000>; 1049 #address-cells = <1>; 1050 #size-cells = <1>; 1051 1052 edma1: dma-controller@44000000 { 1053 compatible = "fsl,imx93-edma3"; 1054 reg = <0x44000000 0x210000>; 1055 clocks = <&scmi_clk IMX952_CLK_BUSAON>; 1056 clock-names = "dma"; 1057 #dma-cells = <3>; 1058 dma-channels = <32>; 1059 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>, 1060 <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>, 1061 <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>, 1062 <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>, 1063 <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>, 1064 <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>, 1065 <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>, 1066 <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>, 1067 <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>, 1068 <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>, 1069 <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>, 1070 <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>, 1071 <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, 1072 <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, 1073 <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, 1074 <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, 1075 <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>, 1076 <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, 1077 <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, 1078 <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, 1079 <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, 1080 <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>, 1081 <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>, 1082 <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>, 1083 <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>, 1084 <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>, 1085 <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>, 1086 <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>, 1087 <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>, 1088 <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>, 1089 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1090 <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>, 1091 <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; //error irq 1092 }; 1093 1094 mu1: mailbox@44220000 { 1095 compatible = "fsl,imx95-mu"; 1096 reg = <0x44220000 0x10000>; 1097 interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>; 1098 clocks = <&scmi_clk IMX952_CLK_BUSAON>; 1099 #mbox-cells = <2>; 1100 status = "disabled"; 1101 }; 1102 1103 system_counter: timer@44290000 { 1104 compatible = "nxp,imx95-sysctr-timer"; 1105 reg = <0x44290000 0x30000>; 1106 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; 1107 clocks = <&clk_osc_24m>; 1108 clock-names = "per"; 1109 nxp,no-divider; 1110 }; 1111 1112 i3c1: i3c@44330000 { 1113 compatible = "silvaco,i3c-master-v1"; 1114 reg = <0x44330000 0x10000>; 1115 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>; 1116 #address-cells = <3>; 1117 #size-cells = <0>; 1118 clocks = <&scmi_clk IMX952_CLK_BUSAON>, 1119 <&scmi_clk IMX952_CLK_I3C1SLOW>, 1120 <&clk_dummy>; 1121 clock-names = "pclk", "fast_clk", "slow_clk"; 1122 status = "disabled"; 1123 }; 1124 1125 lpi2c1: i2c@44340000 { 1126 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1127 reg = <0x44340000 0x10000>; 1128 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>; 1129 clocks = <&scmi_clk IMX952_CLK_LPI2C1>, 1130 <&scmi_clk IMX952_CLK_BUSAON>; 1131 clock-names = "per", "ipg"; 1132 #address-cells = <1>; 1133 #size-cells = <0>; 1134 dmas = <&edma1 12 0 0>, <&edma1 13 0 FSL_EDMA_RX> ; 1135 dma-names = "tx", "rx"; 1136 status = "disabled"; 1137 }; 1138 1139 lpi2c2: i2c@44350000 { 1140 compatible = "fsl,imx95-lpi2c", "fsl,imx7ulp-lpi2c"; 1141 reg = <0x44350000 0x10000>; 1142 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>; 1143 clocks = <&scmi_clk IMX952_CLK_LPI2C2>, 1144 <&scmi_clk IMX952_CLK_BUSAON>; 1145 clock-names = "per", "ipg"; 1146 #address-cells = <1>; 1147 #size-cells = <0>; 1148 dmas = <&edma1 14 0 0>, <&edma1 15 0 FSL_EDMA_RX> ; 1149 dma-names = "tx", "rx"; 1150 status = "disabled"; 1151 }; 1152 1153 lpspi1: spi@44360000 { 1154 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1155 reg = <0x44360000 0x10000>; 1156 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>; 1157 clocks = <&scmi_clk IMX952_CLK_LPSPI1>, 1158 <&scmi_clk IMX952_CLK_BUSAON>; 1159 clock-names = "per", "ipg"; 1160 #address-cells = <1>; 1161 #size-cells = <0>; 1162 dmas = <&edma1 16 0 FSL_EDMA_RX>, <&edma1 17 0 0> ; 1163 dma-names = "tx", "rx"; 1164 status = "disabled"; 1165 }; 1166 1167 lpspi2: spi@44370000 { 1168 compatible = "fsl,imx95-spi", "fsl,imx7ulp-spi"; 1169 reg = <0x44370000 0x10000>; 1170 interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; 1171 clocks = <&scmi_clk IMX952_CLK_LPSPI2>, 1172 <&scmi_clk IMX952_CLK_BUSAON>; 1173 clock-names = "per", "ipg"; 1174 #address-cells = <1>; 1175 #size-cells = <0>; 1176 dmas = <&edma1 18 0 FSL_EDMA_RX>, <&edma1 19 0 0> ; 1177 dma-names = "tx", "rx"; 1178 status = "disabled"; 1179 }; 1180 1181 lpuart1: serial@44380000 { 1182 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1183 "fsl,imx7ulp-lpuart"; 1184 reg = <0x44380000 0x1000>; 1185 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; 1186 clocks = <&scmi_clk IMX952_CLK_LPUART1>; 1187 clock-names = "ipg"; 1188 dmas = <&edma1 21 0 FSL_EDMA_RX>, <&edma1 20 0 0>; 1189 dma-names = "rx", "tx"; 1190 status = "disabled"; 1191 }; 1192 1193 lpuart2: serial@44390000 { 1194 compatible = "fsl,imx95-lpuart", "fsl,imx8ulp-lpuart", 1195 "fsl,imx7ulp-lpuart"; 1196 reg = <0x44390000 0x1000>; 1197 interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>; 1198 clocks = <&scmi_clk IMX952_CLK_LPUART2>; 1199 clock-names = "ipg"; 1200 dmas = <&edma1 23 0 FSL_EDMA_RX>, <&edma1 22 0 0>; 1201 dma-names = "rx", "tx"; 1202 status = "disabled"; 1203 }; 1204 1205 flexcan1: can@443a0000 { 1206 compatible = "fsl,imx95-flexcan"; 1207 reg = <0x443a0000 0x10000>; 1208 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>; 1209 clocks = <&scmi_clk IMX952_CLK_BUSAON>, 1210 <&scmi_clk IMX952_CLK_CAN1>; 1211 clock-names = "ipg", "per"; 1212 assigned-clocks = <&scmi_clk IMX952_CLK_CAN1>; 1213 assigned-clock-parents = <&scmi_clk IMX952_CLK_SYSPLL1_PFD1_DIV2>; 1214 assigned-clock-rates = <40000000>; 1215 fsl,clk-source = /bits/ 8 <0>; 1216 status = "disabled"; 1217 }; 1218 1219 sai1: sai@443b0000 { 1220 compatible = "fsl,imx952-sai", "fsl,imx95-sai"; 1221 reg = <0x443b0000 0x10000>; 1222 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; 1223 clocks = <&scmi_clk IMX952_CLK_BUSAON>, <&clk_dummy>, 1224 <&scmi_clk IMX952_CLK_SAI1>, <&clk_dummy>, 1225 <&clk_dummy>; 1226 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1227 dmas = <&edma1 25 0 FSL_EDMA_RX>, <&edma1 24 0 0>; 1228 dma-names = "rx", "tx"; 1229 #sound-dai-cells = <0>; 1230 status = "disabled"; 1231 }; 1232 1233 micfil: micfil@44520000 { 1234 compatible = "fsl,imx943-micfil"; 1235 reg = <0x44520000 0x10000>; 1236 interrupts = <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, 1237 <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, 1238 <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, 1239 <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>; 1240 clocks = <&scmi_clk IMX952_CLK_BUSAON>, 1241 <&scmi_clk IMX952_CLK_PDM>, 1242 <&scmi_clk IMX952_CLK_AUDIOPLL1>, 1243 <&scmi_clk IMX952_CLK_AUDIOPLL2>, 1244 <&clk_dummy>; 1245 clock-names = "ipg_clk", "ipg_clk_app", 1246 "pll8k", "pll11k", "clkext3"; 1247 dmas = <&edma1 6 0 (FSL_EDMA_MULTI_FIFO | FSL_EDMA_RX)>; 1248 dma-names = "rx"; 1249 #sound-dai-cells = <0>; 1250 status = "disabled"; 1251 }; 1252 1253 adc1: adc@44530000 { 1254 compatible = "nxp,imx93-adc"; 1255 reg = <0x44530000 0x10000>; 1256 interrupts = <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, 1257 <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, 1258 <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>; 1259 clocks = <&scmi_clk IMX952_CLK_ADC>; 1260 clock-names = "ipg"; 1261 #io-channel-cells = <1>; 1262 status = "disabled"; 1263 }; 1264 1265 mu2: mailbox@445b0000 { 1266 compatible = "fsl,imx95-mu"; 1267 reg = <0x445b0000 0x1000>; 1268 ranges; 1269 interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>; 1270 #address-cells = <1>; 1271 #size-cells = <1>; 1272 #mbox-cells = <2>; 1273 1274 sram0: sram@445b1000 { 1275 compatible = "mmio-sram"; 1276 reg = <0x445b1000 0x400>; 1277 ranges = <0x0 0x445b1000 0x400>; 1278 #address-cells = <1>; 1279 #size-cells = <1>; 1280 1281 scmi_buf0: scmi-sram-section@0 { 1282 compatible = "arm,scmi-shmem"; 1283 reg = <0x0 0x80>; 1284 }; 1285 1286 scmi_buf1: scmi-sram-section@80 { 1287 compatible = "arm,scmi-shmem"; 1288 reg = <0x80 0x80>; 1289 }; 1290 }; 1291 1292 }; 1293 1294 mu3: mailbox@445d0000 { 1295 compatible = "fsl,imx95-mu"; 1296 reg = <0x445d0000 0x10000>; 1297 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>; 1298 clocks = <&scmi_clk IMX952_CLK_BUSAON>; 1299 #mbox-cells = <2>; 1300 status = "disabled"; 1301 }; 1302 1303 mu4: mailbox@445f0000 { 1304 compatible = "fsl,imx95-mu"; 1305 reg = <0x445f0000 0x10000>; 1306 interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>; 1307 clocks = <&scmi_clk IMX952_CLK_BUSAON>; 1308 #mbox-cells = <2>; 1309 status = "disabled"; 1310 }; 1311 1312 mu5: mailbox@44610000 { 1313 compatible = "fsl,imx95-mu"; 1314 reg = <0x44610000 0x10000>; 1315 interrupts = <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>; 1316 clocks = <&scmi_clk IMX952_CLK_BUSAON>; 1317 #mbox-cells = <2>; 1318 status = "disabled"; 1319 }; 1320 1321 mu6: mailbox@44630000 { 1322 compatible = "fsl,imx95-mu"; 1323 reg = <0x44630000 0x10000>; 1324 interrupts = <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>; 1325 clocks = <&scmi_clk IMX952_CLK_BUSAON>; 1326 #mbox-cells = <2>; 1327 status = "disabled"; 1328 }; 1329 }; 1330 1331 v2x_mu0: mailbox@47300000 { 1332 compatible = "fsl,imx95-mu-v2x"; 1333 reg = <0x0 0x47300000 0x0 0x10000>; 1334 interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>; 1335 #mbox-cells = <2>; 1336 }; 1337 1338 v2x_mu2: mailbox@47320000 { 1339 compatible = "fsl,imx95-mu-v2x"; 1340 reg = <0x0 0x47320000 0x0 0x10000>; 1341 interrupts = <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; 1342 #mbox-cells = <2>; 1343 }; 1344 1345 v2x_mu3: mailbox@47330000 { 1346 compatible = "fsl,imx95-mu-v2x"; 1347 reg = <0x0 0x47330000 0x0 0x10000>; 1348 interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; 1349 #mbox-cells = <2>; 1350 }; 1351 1352 v2x_mu4: mailbox@47340000 { 1353 compatible = "fsl,imx95-mu-v2x"; 1354 reg = <0x0 0x47340000 0x0 0x10000>; 1355 interrupts = <GIC_SPI 239 IRQ_TYPE_LEVEL_HIGH>; 1356 #mbox-cells = <2>; 1357 }; 1358 1359 v2x_mu: mailbox@47350000 { 1360 compatible = "fsl,imx95-mu-v2x"; 1361 reg = <0x0 0x47350000 0x0 0x10000>; 1362 interrupts = <GIC_SPI 255 IRQ_TYPE_LEVEL_HIGH>; 1363 #mbox-cells = <2>; 1364 }; 1365 1366 /* GPIO1 is under exclusive control of System Manager */ 1367 gpio1: gpio@47400000 { 1368 compatible = "fsl,imx95-gpio", "fsl,imx8ulp-gpio"; 1369 reg = <0x0 0x47400000 0x0 0x1000>; 1370 gpio-controller; 1371 #gpio-cells = <2>; 1372 interrupts = <GIC_SPI 10 IRQ_TYPE_LEVEL_HIGH>, 1373 <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>; 1374 interrupt-controller; 1375 #interrupt-cells = <2>; 1376 clocks = <&scmi_clk IMX952_CLK_M33>, 1377 <&scmi_clk IMX952_CLK_M33>; 1378 clock-names = "gpio", "port"; 1379 gpio-ranges = <&scmi_iomuxc 0 123 16>; 1380 ngpios = <16>; 1381 status = "disabled"; 1382 }; 1383 1384 elemu0: mailbox@47520000 { 1385 compatible = "fsl,imx95-mu-ele"; 1386 reg = <0x0 0x47520000 0x0 0x10000>; 1387 interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; 1388 #mbox-cells = <2>; 1389 status = "disabled"; 1390 }; 1391 1392 elemu1: mailbox@47530000 { 1393 compatible = "fsl,imx95-mu-ele"; 1394 reg = <0x0 0x47530000 0x0 0x10000>; 1395 interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; 1396 #mbox-cells = <2>; 1397 status = "disabled"; 1398 }; 1399 1400 elemu2: mailbox@47540000 { 1401 compatible = "fsl,imx95-mu-ele"; 1402 reg = <0x0 0x47540000 0x0 0x10000>; 1403 interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>; 1404 #mbox-cells = <2>; 1405 status = "disabled"; 1406 }; 1407 1408 elemu3: mailbox@47550000 { 1409 compatible = "fsl,imx95-mu-ele"; 1410 reg = <0x0 0x47550000 0x0 0x10000>; 1411 interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>; 1412 #mbox-cells = <2>; 1413 }; 1414 1415 elemu4: mailbox@47560000 { 1416 compatible = "fsl,imx95-mu-ele"; 1417 reg = <0x0 0x47560000 0x0 0x10000>; 1418 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; 1419 #mbox-cells = <2>; 1420 status = "disabled"; 1421 }; 1422 1423 elemu5: mailbox@47570000 { 1424 compatible = "fsl,imx95-mu-ele"; 1425 reg = <0x0 0x47570000 0x0 0x10000>; 1426 interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; 1427 #mbox-cells = <2>; 1428 status = "disabled"; 1429 }; 1430 1431 usb1: usb@4c100000 { 1432 compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1433 reg = <0x0 0x4c100000 0x0 0x200>; 1434 interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, 1435 <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>; 1436 clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, 1437 <&scmi_clk IMX952_CLK_OSC32K>; 1438 clock-names = "usb_ctrl_root", "usb_wakeup"; 1439 power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; 1440 phys = <&usbphynop1>; 1441 fsl,usbmisc = <&usbmisc1 0>; 1442 status = "disabled"; 1443 }; 1444 1445 usbmisc1: usbmisc@4c100200 { 1446 compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1447 #index-cells = <1>; 1448 reg = <0x0 0x4c100200 0x0 0x200>, 1449 <0x0 0x4c010010 0x0 0x4>; 1450 }; 1451 1452 usb2: usb@4c200000 { 1453 compatible = "fsl,imx95-usb", "fsl,imx7d-usb", "fsl,imx27-usb"; 1454 reg = <0x0 0x4c200000 0x0 0x200>; 1455 interrupts = <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, 1456 <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>; 1457 clocks = <&scmi_clk IMX952_CLK_CGC_HSIOUSB>, 1458 <&scmi_clk IMX952_CLK_OSC32K>; 1459 clock-names = "usb_ctrl_root", "usb_wakeup"; 1460 power-domains = <&scmi_devpd IMX952_PD_HSIO_TOP>; 1461 phys = <&usbphynop2>; 1462 fsl,usbmisc = <&usbmisc2 0>; 1463 status = "disabled"; 1464 }; 1465 1466 usbmisc2: usbmisc@4c200200 { 1467 compatible = "fsl,imx95-usbmisc", "fsl,imx7d-usbmisc", "fsl,imx6q-usbmisc"; 1468 #index-cells = <1>; 1469 reg = <0x0 0x4c200200 0x0 0x200>, 1470 <0x0 0x4c010014 0x0 0x4>; 1471 }; 1472 1473 sai2: sai@4c880000 { 1474 compatible = "fsl,imx952-sai", "fsl,imx95-sai"; 1475 reg = <0x0 0x4c880000 0x0 0x10000>; 1476 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>; 1477 clocks = <&scmi_clk IMX952_CLK_BUSNETCMIX>, <&clk_dummy>, 1478 <&scmi_clk IMX952_CLK_SAI2>, <&clk_dummy>, 1479 <&clk_dummy>; 1480 clock-names = "bus", "mclk0", "mclk1", "mclk2", "mclk3"; 1481 dmas = <&edma2 59 0 FSL_EDMA_RX>, <&edma2 58 0 0>; 1482 dma-names = "rx", "tx"; 1483 #sound-dai-cells = <0>; 1484 power-domains = <&scmi_devpd IMX952_PD_NETC>; 1485 status = "disabled"; 1486 }; 1487 }; 1488}; 1489