1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025-2026 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/pwm/pwm.h> 9#include <dt-bindings/usb/pd.h> 10#include "imx952.dtsi" 11 12#define FALLING_EDGE BIT(0) 13#define RISING_EDGE BIT(1) 14 15#define BRD_SM_CTRL_SD3_WAKE 0x8000U /*!< PCAL6408A-0 */ 16#define BRD_SM_CTRL_M2E_WAKE 0x8001U /*!< PCAL6408A-4 */ 17#define BRD_SM_CTRL_BT_WAKE 0x8002U /*!< PCAL6408A-5 */ 18#define BRD_SM_CTRL_M2M_WAKE 0x8003U /*!< PCAL6408A-6 */ 19#define BRD_SM_CTRL_BUTTON 0x8004U /*!< PCAL6408A-7 */ 20 21/ { 22 model = "NXP i.MX952 EVK board"; 23 compatible = "fsl,imx952-evk", "fsl,imx952"; 24 25 aliases { 26 gpio0 = &gpio1; 27 gpio1 = &gpio2; 28 gpio2 = &gpio3; 29 gpio3 = &gpio4; 30 gpio4 = &gpio5; 31 i2c0 = &lpi2c1; 32 i2c1 = &lpi2c2; 33 i2c2 = &lpi2c3; 34 i2c3 = &lpi2c4; 35 i2c4 = &lpi2c5; 36 i2c5 = &lpi2c6; 37 i2c6 = &lpi2c7; 38 i2c7 = &lpi2c8; 39 mmc0 = &usdhc1; 40 mmc1 = &usdhc2; 41 serial0 = &lpuart1; 42 serial4 = &lpuart5; 43 spi6 = &lpspi7; 44 }; 45 46 bt_sco_codec: audio-codec-bt-sco { 47 #sound-dai-cells = <1>; 48 compatible = "linux,bt-sco"; 49 }; 50 51 chosen { 52 stdout-path = &lpuart1; 53 }; 54 55 dmic: dmic { 56 compatible = "dmic-codec"; 57 #sound-dai-cells = <0>; 58 num-channels = <2>; 59 }; 60 61 memory@80000000 { 62 device_type = "memory"; 63 reg = <0x0 0x80000000 0 0x80000000>; 64 }; 65 66 fan0: pwm-fan { 67 compatible = "pwm-fan"; 68 #cooling-cells = <2>; 69 pwms = <&tpm6 2 4000000 PWM_POLARITY_INVERTED>; 70 cooling-levels = <64 128 192 255>; 71 }; 72 73 reserved-memory { 74 #address-cells = <2>; 75 #size-cells = <2>; 76 ranges; 77 78 linux_cma: linux,cma { 79 compatible = "shared-dma-pool"; 80 alloc-ranges = <0 0x80000000 0 0x7f000000>; 81 size = <0 0x3c000000>; 82 linux,cma-default; 83 reusable; 84 }; 85 }; 86 87 flexcan1_phy: can-phy0 { 88 compatible = "nxp,tjr1443"; 89 #phy-cells = <0>; 90 max-bitrate = <8000000>; 91 enable-gpios = <&pcal6416 6 GPIO_ACTIVE_HIGH>; 92 standby-gpios = <&pcal6416 5 GPIO_ACTIVE_LOW>; 93 }; 94 95 flexcan2_phy: can-phy1 { 96 compatible = "nxp,tjr1443"; 97 #phy-cells = <0>; 98 max-bitrate = <8000000>; 99 enable-gpios = <&i2c4_pcal6408 4 GPIO_ACTIVE_HIGH>; 100 standby-gpios = <&i2c4_pcal6408 3 GPIO_ACTIVE_LOW>; 101 }; 102 103 reg_3p3v: regulator-3p3v { 104 compatible = "regulator-fixed"; 105 regulator-max-microvolt = <3300000>; 106 regulator-min-microvolt = <3300000>; 107 regulator-name = "+V3.3_SW"; 108 }; 109 110 reg_1p8v: regulator-1p8v { 111 compatible = "regulator-fixed"; 112 regulator-max-microvolt = <1800000>; 113 regulator-min-microvolt = <1800000>; 114 regulator-name = "+V1.8_SW"; 115 }; 116 117 reg_vref_1v8: regulator-adc-vref { 118 compatible = "regulator-fixed"; 119 regulator-name = "vref_1v8"; 120 regulator-min-microvolt = <1800000>; 121 regulator-max-microvolt = <1800000>; 122 }; 123 124 reg_audio_pwr: regulator-audio-pwr { 125 compatible = "regulator-fixed"; 126 regulator-name = "audio-pwr"; 127 regulator-max-microvolt = <3300000>; 128 regulator-min-microvolt = <3300000>; 129 gpio = <&i2c4_pcal6408 1 GPIO_ACTIVE_HIGH>; 130 enable-active-high; 131 }; 132 133 reg_usdhc2_vmmc: regulator-usdhc2 { 134 compatible = "regulator-fixed"; 135 pinctrl-names = "default"; 136 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 137 regulator-name = "VDD_SD2_3V3"; 138 regulator-min-microvolt = <3300000>; 139 regulator-max-microvolt = <3300000>; 140 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 141 enable-active-high; 142 off-on-delay-us = <12000>; 143 }; 144 145 reg_usb_vbus: regulator-vbus { 146 compatible = "regulator-fixed"; 147 regulator-name = "USB_VBUS"; 148 regulator-min-microvolt = <5000000>; 149 regulator-max-microvolt = <5000000>; 150 gpio = <&pcal6524 3 GPIO_ACTIVE_HIGH>; 151 enable-active-high; 152 }; 153 154 sound-bt-sco { 155 compatible = "simple-audio-card"; 156 simple-audio-card,bitclock-inversion; 157 simple-audio-card,bitclock-master = <&btcpu>; 158 simple-audio-card,format = "dsp_a"; 159 simple-audio-card,frame-master = <&btcpu>; 160 simple-audio-card,name = "bt-sco-audio"; 161 162 simple-audio-card,codec { 163 sound-dai = <&bt_sco_codec 1>; 164 }; 165 166 btcpu: simple-audio-card,cpu { 167 dai-tdm-slot-num = <2>; 168 dai-tdm-slot-width = <16>; 169 sound-dai = <&sai1>; 170 }; 171 }; 172 173 sound-micfil { 174 compatible = "fsl,imx-audio-card"; 175 model = "micfil-audio"; 176 177 pri-dai-link { 178 format = "i2s"; 179 link-name = "micfil hifi"; 180 181 codec { 182 sound-dai = <&dmic>; 183 }; 184 185 cpu { 186 sound-dai = <&micfil>; 187 }; 188 }; 189 }; 190 191 sound-wm8962 { 192 compatible = "fsl,imx-audio-wm8962"; 193 audio-asrc = <&asrc1>; 194 audio-codec = <&wm8962>; 195 audio-cpu = <&sai3>; 196 audio-routing = "Headphone Jack", "HPOUTL", 197 "Headphone Jack", "HPOUTR", 198 "Ext Spk", "SPKOUTL", 199 "Ext Spk", "SPKOUTR", 200 "AMIC", "MICBIAS", 201 "IN3R", "AMIC", 202 "IN1R", "AMIC"; 203 hp-det-gpio = <&gpio2 11 GPIO_ACTIVE_HIGH>; 204 model = "wm8962-audio"; 205 pinctrl-0 = <&pinctrl_hp>; 206 pinctrl-names = "default"; 207 }; 208}; 209 210&asrc1 { 211 assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, 212 <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, 213 <&scmi_clk IMX952_CLK_AUDIOPLL1>, 214 <&scmi_clk IMX952_CLK_AUDIOPLL2>, 215 <&scmi_clk IMX952_CLK_ASRC1>; 216 assigned-clock-parents = <0>, <0>, <0>, <0>, 217 <&scmi_clk IMX952_CLK_AUDIOPLL1>; 218 assigned-clock-rates = <3932160000>, <3612672000>, 219 <393216000>, <361267200>, <49152000>; 220 fsl,asrc-rate = <48000>; 221 status = "okay"; 222}; 223 224&asrc2 { 225 assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, 226 <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, 227 <&scmi_clk IMX952_CLK_AUDIOPLL1>, 228 <&scmi_clk IMX952_CLK_AUDIOPLL2>, 229 <&scmi_clk IMX952_CLK_ASRC2>; 230 assigned-clock-parents = <0>, <0>, <0>, <0>, 231 <&scmi_clk IMX952_CLK_AUDIOPLL1>; 232 assigned-clock-rates = <3932160000>, <3612672000>, 233 <393216000>, <361267200>, <49152000>; 234 fsl,asrc-rate = <48000>; 235 status = "okay"; 236}; 237 238/* pin conflict with PDM */ 239&flexcan1 { 240 pinctrl-names = "default"; 241 pinctrl-0 = <&pinctrl_flexcan1>; 242 phys = <&flexcan1_phy>; 243 status = "disabled"; 244}; 245 246&flexcan2 { 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_flexcan2>; 249 phys = <&flexcan2_phy>; 250 status = "okay"; 251}; 252 253&lpi2c2 { 254 clock-frequency = <400000>; 255 pinctrl-names = "default"; 256 pinctrl-0 = <&pinctrl_lpi2c2>; 257 status = "okay"; 258 259 adp5585: io-expander@34 { 260 compatible = "adi,adp5585-00", "adi,adp5585"; 261 reg = <0x34>; 262 gpio-controller; 263 #gpio-cells = <2>; 264 gpio-reserved-ranges = <5 1>; 265 #pwm-cells = <3>; 266 }; 267}; 268 269&lpi2c3 { 270 clock-frequency = <400000>; 271 pinctrl-names = "default"; 272 pinctrl-0 = <&pinctrl_lpi2c3>; 273 status = "okay"; 274 275 i2c3_pcal6408: gpio@20 { 276 compatible = "nxp,pcal6408"; 277 reg = <0x20>; 278 #gpio-cells = <2>; 279 gpio-controller; 280 vcc-supply = <®_3p3v>; 281 }; 282}; 283 284&lpi2c4 { 285 clock-frequency = <400000>; 286 pinctrl-names = "default"; 287 pinctrl-0 = <&pinctrl_lpi2c4>; 288 status = "okay"; 289 290 wm8962: audio-codec@1a { 291 compatible = "wlf,wm8962"; 292 reg = <0x1a>; 293 clocks = <&scmi_clk IMX952_CLK_SAI3>; 294 AVDD-supply = <®_audio_pwr>; 295 CPVDD-supply = <®_audio_pwr>; 296 DBVDD-supply = <®_audio_pwr>; 297 DCVDD-supply = <®_audio_pwr>; 298 gpio-cfg = < 0x0000 /* 0:Default */ 299 0x0000 /* 1:Default */ 300 0x0000 /* 2:FN_DMICCLK */ 301 0x0000 /* 3:Default */ 302 0x0000 /* 4:FN_DMICCDAT */ 303 0x0000 /* 5:Default */ 304 >; 305 MICVDD-supply = <®_audio_pwr>; 306 PLLVDD-supply = <®_audio_pwr>; 307 SPKVDD1-supply = <®_audio_pwr>; 308 SPKVDD2-supply = <®_audio_pwr>; 309 }; 310 311 i2c4_pcal6408: gpio@21 { 312 compatible = "nxp,pcal6408"; 313 reg = <0x21>; 314 #gpio-cells = <2>; 315 gpio-controller; 316 interrupt-controller; 317 #interrupt-cells = <2>; 318 interrupt-parent = <&gpio2>; 319 interrupts = <18 IRQ_TYPE_LEVEL_LOW>; 320 pinctrl-names = "default"; 321 pinctrl-0 = <&pinctrl_i2c4_pcal6408>; 322 vcc-supply = <®_3p3v>; 323 }; 324}; 325 326&lpi2c6 { 327 clock-frequency = <100000>; 328 pinctrl-names = "default"; 329 pinctrl-0 = <&pinctrl_lpi2c6>; 330 status = "okay"; 331 332 pcal6416: gpio@21 { 333 compatible = "nxp,pcal6416"; 334 #gpio-cells = <2>; 335 gpio-controller; 336 reg = <0x21>; 337 interrupt-controller; 338 #interrupt-cells = <2>; 339 interrupt-parent = <&gpio2>; 340 interrupts = <10 IRQ_TYPE_LEVEL_LOW>; 341 pinctrl-names = "default"; 342 pinctrl-0 = <&pinctrl_pcal6416>; 343 vcc-supply = <®_3p3v>; 344 345 pdm-can-sel-hog { 346 gpio-hog; 347 gpios = <10 GPIO_ACTIVE_HIGH>; 348 output-low; 349 }; 350 351 mqs-en-hog { 352 gpio-hog; 353 gpios = <15 GPIO_ACTIVE_HIGH>; 354 output-low; 355 }; 356 }; 357}; 358 359&lpi2c7 { 360 clock-frequency = <1000000>; 361 pinctrl-names = "default"; 362 pinctrl-0 = <&pinctrl_lpi2c7>; 363 status = "okay"; 364 365 pcal6524: gpio@22 { 366 compatible = "nxp,pcal6524"; 367 reg = <0x22>; 368 pinctrl-names = "default"; 369 pinctrl-0 = <&pinctrl_pcal6524>; 370 gpio-controller; 371 #gpio-cells = <2>; 372 interrupt-controller; 373 #interrupt-cells = <2>; 374 interrupt-parent = <&gpio5>; 375 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 376 }; 377 378 ptn5110: tcpc@50 { 379 compatible = "nxp,ptn5110", "tcpci"; 380 reg = <0x50>; 381 interrupt-parent = <&gpio5>; 382 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 383 pinctrl-names = "default"; 384 pinctrl-0 = <&pinctrl_ptn5110>; 385 386 typec_con: connector { 387 compatible = "usb-c-connector"; 388 label = "USB-C"; 389 power-role = "dual"; 390 data-role = "dual"; 391 try-power-role = "sink"; 392 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 393 sink-pdos = <PDO_FIXED(5000, 0, PDO_FIXED_USB_COMM)>; 394 op-sink-microwatt = <0>; 395 self-powered; 396 397 ports { 398 #address-cells = <1>; 399 #size-cells = <0>; 400 401 port@0 { 402 reg = <0>; 403 404 typec1_dr_sw: endpoint { 405 remote-endpoint = <&usb1_drd_sw>; 406 }; 407 }; 408 }; 409 }; 410 }; 411}; 412 413&lpuart1 { 414 /* console */ 415 pinctrl-names = "default"; 416 pinctrl-0 = <&pinctrl_uart1>; 417 status = "okay"; 418}; 419 420&lpuart5 { 421 /* BT */ 422 pinctrl-names = "default"; 423 pinctrl-0 = <&pinctrl_uart5>; 424 status = "okay"; 425 426 bluetooth { 427 compatible = "nxp,88w8987-bt"; 428 }; 429}; 430 431&lpspi7 { 432 cs-gpios = <&gpio2 4 GPIO_ACTIVE_LOW>; 433 pinctrl-names = "default"; 434 pinctrl-0 = <&pinctrl_lpspi7>; 435 status = "okay"; 436}; 437 438&micfil { 439 assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, 440 <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, 441 <&scmi_clk IMX952_CLK_AUDIOPLL1>, 442 <&scmi_clk IMX952_CLK_AUDIOPLL2>, 443 <&scmi_clk IMX952_CLK_PDM>; 444 assigned-clock-parents = <0>, <0>, <0>, <0>, 445 <&scmi_clk IMX952_CLK_AUDIOPLL1>; 446 assigned-clock-rates = <3932160000>, <3612672000>, 447 <393216000>, <361267200>, <49152000>; 448 pinctrl-0 = <&pinctrl_pdm>; 449 pinctrl-1 = <&pinctrl_pdm_sleep>; 450 pinctrl-names = "default", "sleep"; 451 status = "okay"; 452}; 453 454&sai1 { 455 assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, 456 <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, 457 <&scmi_clk IMX952_CLK_AUDIOPLL1>, 458 <&scmi_clk IMX952_CLK_AUDIOPLL2>, 459 <&scmi_clk IMX952_CLK_SAI1>; 460 assigned-clock-parents = <0>, <0>, <0>, <0>, 461 <&scmi_clk IMX952_CLK_AUDIOPLL1>; 462 assigned-clock-rates = <3932160000>, <3612672000>, 463 <393216000>, <361267200>, <12288000>; 464 pinctrl-0 = <&pinctrl_sai1>; 465 pinctrl-1 = <&pinctrl_sai1_sleep>; 466 pinctrl-names = "default", "sleep"; 467 fsl,sai-mclk-direction-output; 468 status = "okay"; 469}; 470 471&sai3 { 472 assigned-clocks = <&scmi_clk IMX952_CLK_AUDIOPLL1_VCO>, 473 <&scmi_clk IMX952_CLK_AUDIOPLL2_VCO>, 474 <&scmi_clk IMX952_CLK_AUDIOPLL1>, 475 <&scmi_clk IMX952_CLK_AUDIOPLL2>, 476 <&scmi_clk IMX952_CLK_SAI3>; 477 assigned-clock-parents = <0>, <0>, <0>, <0>, 478 <&scmi_clk IMX952_CLK_AUDIOPLL1>; 479 assigned-clock-rates = <3932160000>, <3612672000>, 480 <393216000>, <361267200>, <12288000>; 481 pinctrl-0 = <&pinctrl_sai3>; 482 pinctrl-1 = <&pinctrl_sai3_sleep>; 483 pinctrl-names = "default", "sleep"; 484 fsl,sai-amix-mode = "bypass"; 485 fsl,sai-mclk-direction-output; 486 status = "okay"; 487}; 488 489&scmi_misc { 490 nxp,ctrl-ids = <BRD_SM_CTRL_SD3_WAKE 1 491 BRD_SM_CTRL_M2E_WAKE 1 492 BRD_SM_CTRL_BT_WAKE 1 493 BRD_SM_CTRL_M2M_WAKE 1 494 BRD_SM_CTRL_BUTTON 1>; 495}; 496 497&tpm3 { 498 pinctrl-names = "default"; 499 pinctrl-0 = <&pinctrl_tpm3>; 500 status = "okay"; 501}; 502 503&tpm6 { 504 pinctrl-names = "default"; 505 pinctrl-0 = <&pinctrl_tpm6>; 506 status = "okay"; 507}; 508 509&usb1 { 510 dr_mode = "otg"; 511 hnp-disable; 512 srp-disable; 513 adp-disable; 514 usb-role-switch; 515 disable-over-current; 516 samsung,picophy-pre-emp-curr-control = <3>; 517 samsung,picophy-dc-vol-level-adjust = <7>; 518 status = "okay"; 519 520 port { 521 usb1_drd_sw: endpoint { 522 remote-endpoint = <&typec1_dr_sw>; 523 }; 524 }; 525}; 526 527&usb2 { 528 dr_mode = "host"; 529 disable-over-current; 530 vbus-supply = <®_usb_vbus>; 531 status = "okay"; 532}; 533 534&usdhc1 { 535 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 536 pinctrl-0 = <&pinctrl_usdhc1>; 537 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 538 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 539 pinctrl-3 = <&pinctrl_usdhc1>; 540 bus-width = <8>; 541 non-removable; 542 no-sdio; 543 no-sd; 544 status = "okay"; 545}; 546 547&usdhc2 { 548 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 549 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 550 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 551 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 552 pinctrl-3 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 553 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 554 vmmc-supply = <®_usdhc2_vmmc>; 555 bus-width = <4>; 556 status = "okay"; 557}; 558 559&wdog3 { 560 fsl,ext-reset-output; 561 status = "okay"; 562}; 563 564&scmi_iomuxc { 565 pinctrl_flexcan1: flexcan1grp { 566 fsl,pins = < 567 IMX952_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e 568 IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e 569 >; 570 }; 571 572 pinctrl_flexcan2: flexcan2grp { 573 fsl,pins = < 574 IMX952_PAD_GPIO_IO25__WAKEUPMIX_TOP_CAN2_TX 0x39e 575 IMX952_PAD_GPIO_IO27__WAKEUPMIX_TOP_CAN2_RX 0x39e 576 >; 577 }; 578 579 pinctrl_hp: hpgrp { 580 fsl,pins = < 581 IMX952_PAD_GPIO_IO11__WAKEUPMIX_TOP_GPIO2_IO_11 0x31e 582 >; 583 }; 584 585 pinctrl_lpi2c2: lpi2c2grp { 586 fsl,pins = < 587 IMX952_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40000b9e 588 IMX952_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40000b9e 589 >; 590 }; 591 592 pinctrl_lpi2c3: lpi2c3grp { 593 fsl,pins = < 594 IMX952_PAD_GPIO_IO00__WAKEUPMIX_TOP_LPI2C3_SDA 0x40000b9e 595 IMX952_PAD_GPIO_IO01__WAKEUPMIX_TOP_LPI2C3_SCL 0x40000b9e 596 >; 597 }; 598 599 pinctrl_lpi2c4: lpi2c4grp { 600 fsl,pins = < 601 IMX952_PAD_GPIO_IO30__WAKEUPMIX_TOP_LPI2C4_SDA 0x40000b9e 602 IMX952_PAD_GPIO_IO31__WAKEUPMIX_TOP_LPI2C4_SCL 0x40000b9e 603 >; 604 }; 605 606 pinctrl_i2c4_pcal6408: i2c4pcal6408grp { 607 fsl,pins = < 608 IMX952_PAD_GPIO_IO18__WAKEUPMIX_TOP_GPIO2_IO_18 0x31e 609 >; 610 }; 611 612 pinctrl_lpi2c6: lpi2c6grp { 613 fsl,pins = < 614 IMX952_PAD_GPIO_IO02__WAKEUPMIX_TOP_LPI2C6_SDA 0x40000b9e 615 IMX952_PAD_GPIO_IO03__WAKEUPMIX_TOP_LPI2C6_SCL 0x40000b9e 616 >; 617 }; 618 619 pinctrl_lpi2c7: lpi2c7grp { 620 fsl,pins = < 621 IMX952_PAD_GPIO_IO08__WAKEUPMIX_TOP_LPI2C7_SDA 0x40000b9e 622 IMX952_PAD_GPIO_IO09__WAKEUPMIX_TOP_LPI2C7_SCL 0x40000b9e 623 >; 624 }; 625 626 pinctrl_lpspi7: lpspi7grp { 627 fsl,pins = < 628 IMX952_PAD_GPIO_IO04__WAKEUPMIX_TOP_GPIO2_IO_4 0x39e 629 IMX952_PAD_GPIO_IO05__WAKEUPMIX_TOP_LPSPI7_SIN 0x39e 630 IMX952_PAD_GPIO_IO06__WAKEUPMIX_TOP_LPSPI7_SOUT 0x39e 631 IMX952_PAD_GPIO_IO07__WAKEUPMIX_TOP_LPSPI7_SCK 0x39e 632 >; 633 }; 634 635 pinctrl_pcal6416: pcal6416grp { 636 fsl,pins = < 637 IMX952_PAD_GPIO_IO10__WAKEUPMIX_TOP_GPIO2_IO_10 0x31e 638 >; 639 }; 640 641 pinctrl_pcal6524: pcal6524grp { 642 fsl,pins = < 643 IMX952_PAD_GPIO_IO36__WAKEUPMIX_TOP_GPIO5_IO_16 0x31e 644 >; 645 }; 646 647 pinctrl_pdm: pdmgrp { 648 fsl,pins = < 649 IMX952_PAD_PDM_CLK__AONMIX_TOP_PDM_CLK 0x31e 650 IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_PDM_BIT_STREAM_0 0x31e 651 >; 652 }; 653 654 pinctrl_pdm_sleep: pdmsleepgrp { 655 fsl,pins = < 656 IMX952_PAD_PDM_CLK__AONMIX_TOP_GPIO1_IO_8 0x31e 657 IMX952_PAD_PDM_BIT_STREAM0__AONMIX_TOP_GPIO1_IO_9 0x31e 658 >; 659 }; 660 661 pinctrl_ptn5110: ptn5110grp { 662 fsl,pins = < 663 IMX952_PAD_GPIO_IO34__WAKEUPMIX_TOP_GPIO5_IO_14 0x31e 664 >; 665 }; 666 667 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 668 fsl,pins = < 669 IMX952_PAD_SD2_RESET_B__WAKEUPMIX_TOP_GPIO3_IO_7 0x31e 670 >; 671 }; 672 673 pinctrl_sai1: sai1grp { 674 fsl,pins = < 675 IMX952_PAD_SAI1_RXD0__AONMIX_TOP_SAI1_RX_DATA_0 0x31e 676 IMX952_PAD_SAI1_TXC__AONMIX_TOP_SAI1_TX_BCLK 0x31e 677 IMX952_PAD_SAI1_TXFS__AONMIX_TOP_SAI1_TX_SYNC 0x31e 678 IMX952_PAD_SAI1_TXD0__AONMIX_TOP_SAI1_TX_DATA_0 0x31e 679 >; 680 }; 681 682 pinctrl_sai1_sleep: sai1sleepgrp { 683 fsl,pins = < 684 IMX952_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_14 0x51e 685 IMX952_PAD_SAI1_TXC__AONMIX_TOP_GPIO1_IO_12 0x51e 686 IMX952_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_11 0x51e 687 IMX952_PAD_SAI1_TXD0__AONMIX_TOP_GPIO1_IO_13 0x51e 688 >; 689 }; 690 691 pinctrl_sai3: sai3grp { 692 fsl,pins = < 693 IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_SAI3_MCLK 0x31e 694 IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXBCLK 0x31e 695 IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXSYNC 0x31e 696 IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_SAI3_RX_DATA_0 0x31e 697 IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_AUDMIX_TDM_OUT_TXDATA 0x31e 698 >; 699 }; 700 701 pinctrl_sai3_sleep: sai3sleepgrp { 702 fsl,pins = < 703 IMX952_PAD_GPIO_IO17__WAKEUPMIX_TOP_GPIO2_IO_17 0x31e 704 IMX952_PAD_GPIO_IO16__WAKEUPMIX_TOP_GPIO2_IO_16 0x31e 705 IMX952_PAD_GPIO_IO26__WAKEUPMIX_TOP_GPIO2_IO_26 0x31e 706 IMX952_PAD_GPIO_IO20__WAKEUPMIX_TOP_GPIO2_IO_20 0x31e 707 IMX952_PAD_GPIO_IO21__WAKEUPMIX_TOP_GPIO2_IO_21 0x31e 708 >; 709 }; 710 711 pinctrl_tpm3: tpm3grp { 712 fsl,pins = < 713 IMX952_PAD_GPIO_IO12__WAKEUPMIX_TOP_TPM3_CH2 0x51e 714 >; 715 }; 716 717 pinctrl_tpm6: tpm6grp { 718 fsl,pins = < 719 IMX952_PAD_GPIO_IO19__WAKEUPMIX_TOP_TPM6_CH2 0x51e 720 >; 721 }; 722 723 pinctrl_uart1: uart1grp { 724 fsl,pins = < 725 IMX952_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e 726 IMX952_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e 727 >; 728 }; 729 730 pinctrl_uart5: uart5grp { 731 fsl,pins = < 732 IMX952_PAD_DAP_TDO_TRACESWO__WAKEUPMIX_TOP_LPUART5_TX 0x31e 733 IMX952_PAD_DAP_TDI__WAKEUPMIX_TOP_LPUART5_RX 0x31e 734 IMX952_PAD_DAP_TMS_SWDIO__WAKEUPMIX_TOP_LPUART5_RTS_B 0x31e 735 IMX952_PAD_DAP_TCLK_SWCLK__WAKEUPMIX_TOP_LPUART5_CTS_B 0x31e 736 >; 737 }; 738 739 pinctrl_usdhc1: usdhc1grp { 740 fsl,pins = < 741 IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e 742 IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e 743 IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e 744 IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e 745 IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e 746 IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e 747 IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e 748 IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e 749 IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e 750 IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e 751 IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e 752 >; 753 }; 754 755 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 756 fsl,pins = < 757 IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x158e 758 IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x138e 759 IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x138e 760 IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x138e 761 IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x138e 762 IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x138e 763 IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x138e 764 IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x138e 765 IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x138e 766 IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x138e 767 IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x158e 768 >; 769 }; 770 771 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 772 fsl,pins = < 773 IMX952_PAD_SD1_CLK__WAKEUPMIX_TOP_USDHC1_CLK 0x159e 774 IMX952_PAD_SD1_CMD__WAKEUPMIX_TOP_USDHC1_CMD 0x139e 775 IMX952_PAD_SD1_DATA0__WAKEUPMIX_TOP_USDHC1_DATA0 0x139e 776 IMX952_PAD_SD1_DATA1__WAKEUPMIX_TOP_USDHC1_DATA1 0x139e 777 IMX952_PAD_SD1_DATA2__WAKEUPMIX_TOP_USDHC1_DATA2 0x139e 778 IMX952_PAD_SD1_DATA3__WAKEUPMIX_TOP_USDHC1_DATA3 0x139e 779 IMX952_PAD_SD1_DATA4__WAKEUPMIX_TOP_USDHC1_DATA4 0x139e 780 IMX952_PAD_SD1_DATA5__WAKEUPMIX_TOP_USDHC1_DATA5 0x139e 781 IMX952_PAD_SD1_DATA6__WAKEUPMIX_TOP_USDHC1_DATA6 0x139e 782 IMX952_PAD_SD1_DATA7__WAKEUPMIX_TOP_USDHC1_DATA7 0x139e 783 IMX952_PAD_SD1_STROBE__WAKEUPMIX_TOP_USDHC1_STROBE 0x159e 784 >; 785 }; 786 787 pinctrl_usdhc2: usdhc2grp { 788 fsl,pins = < 789 IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e 790 IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e 791 IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e 792 IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e 793 IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e 794 IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e 795 IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e 796 >; 797 }; 798 799 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 800 fsl,pins = < 801 IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e 802 IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e 803 IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e 804 IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e 805 IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e 806 IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e 807 IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e 808 >; 809 }; 810 811 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 812 fsl,pins = < 813 IMX952_PAD_SD2_CLK__WAKEUPMIX_TOP_USDHC2_CLK 0x158e 814 IMX952_PAD_SD2_CMD__WAKEUPMIX_TOP_USDHC2_CMD 0x138e 815 IMX952_PAD_SD2_DATA0__WAKEUPMIX_TOP_USDHC2_DATA0 0x138e 816 IMX952_PAD_SD2_DATA1__WAKEUPMIX_TOP_USDHC2_DATA1 0x138e 817 IMX952_PAD_SD2_DATA2__WAKEUPMIX_TOP_USDHC2_DATA2 0x138e 818 IMX952_PAD_SD2_DATA3__WAKEUPMIX_TOP_USDHC2_DATA3 0x138e 819 IMX952_PAD_SD2_VSELECT__WAKEUPMIX_TOP_USDHC2_VSELECT 0x51e 820 >; 821 }; 822 823 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 824 fsl,pins = < 825 IMX952_PAD_SD2_CD_B__WAKEUPMIX_TOP_GPIO3_IO_0 0x31e 826 >; 827 }; 828 829 pinctrl_xspi1: xspi1grp { 830 fsl,pins = < 831 IMX952_PAD_XSPI1_DATA0__WAKEUPMIX_TOP_XSPI1_A_DATA_0 0x39e 832 IMX952_PAD_XSPI1_DATA1__WAKEUPMIX_TOP_XSPI1_A_DATA_1 0x39e 833 IMX952_PAD_XSPI1_DATA2__WAKEUPMIX_TOP_XSPI1_A_DATA_2 0x39e 834 IMX952_PAD_XSPI1_DATA3__WAKEUPMIX_TOP_XSPI1_A_DATA_3 0x39e 835 IMX952_PAD_XSPI1_DATA4__WAKEUPMIX_TOP_XSPI1_A_DATA_4 0x39e 836 IMX952_PAD_XSPI1_DATA5__WAKEUPMIX_TOP_XSPI1_A_DATA_5 0x39e 837 IMX952_PAD_XSPI1_DATA6__WAKEUPMIX_TOP_XSPI1_A_DATA_6 0x39e 838 IMX952_PAD_XSPI1_DATA7__WAKEUPMIX_TOP_XSPI1_A_DATA_7 0x39e 839 IMX952_PAD_XSPI1_DQS__WAKEUPMIX_TOP_XSPI1_A_DQS 0x39e 840 IMX952_PAD_XSPI1_SCLK__WAKEUPMIX_TOP_XSPI1_A_SCLK 0x39e 841 IMX952_PAD_XSPI1_SS0_B__WAKEUPMIX_TOP_XSPI1_A_SS0_B 0x39e 842 >; 843 }; 844 845 pinctrl_xspi1_reset: xspi1-reset-grp { 846 fsl,pins = < 847 IMX952_PAD_XSPI1_SS1_B__WAKEUPMIX_TOP_GPIO5_IO_11 0x39e 848 >; 849 }; 850}; 851 852&xspi1 { 853 pinctrl-names = "default"; 854 pinctrl-0 = <&pinctrl_xspi1>; 855 status = "okay"; 856 857 mt35xu01gbba: flash@0 { 858 compatible = "jedec,spi-nor"; 859 reg = <0>; 860 pinctrl-names = "default"; 861 pinctrl-0 = <&pinctrl_xspi1_reset>; 862 reset-gpios = <&gpio5 11 GPIO_ACTIVE_LOW>; 863 #address-cells = <1>; 864 #size-cells = <1>; 865 spi-max-frequency = <200000000>; 866 spi-tx-bus-width = <8>; 867 spi-rx-bus-width = <8>; 868 }; 869}; 870