1// SPDX-License-Identifier: GPL-2.0-or-later OR MIT 2/* 3 * Copyright (C) 2025 Toradex 4 * 5 * https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95 6 */ 7 8#include <dt-bindings/input/input.h> 9#include <dt-bindings/net/ti-dp83867.h> 10#include "imx95.dtsi" 11 12/ { 13 aliases { 14 can0 = &flexcan1; 15 can1 = &flexcan2; 16 ethernet0 = &enetc_port0; 17 ethernet1 = &enetc_port1; 18 mmc0 = &usdhc1; 19 mmc1 = &usdhc2; 20 mmc2 = &usdhc3; 21 rtc0 = &rtc_i2c; 22 rtc1 = &scmi_bbm; 23 serial0 = &lpuart2; 24 serial1 = &lpuart1; 25 serial3 = &lpuart3; 26 }; 27 28 chosen { 29 stdout-path = "serial1:115200n8"; 30 }; 31 32 clk_dsi2dp_bridge: clock-dsi2dp-bridge { 33 compatible = "fixed-clock"; 34 #clock-cells = <0>; 35 clock-frequency = <27000000>; 36 }; 37 38 clk_serdes_eth_ref: clock-eth-ref { 39 compatible = "gpio-gate-clock"; 40 #clock-cells = <0>; 41 /* CTRL_ETH_REF_CLK_STBY# */ 42 enable-gpios = <&som_gpio_expander_1 13 GPIO_ACTIVE_HIGH>; 43 }; 44 45 connector { 46 compatible = "gpio-usb-b-connector", "usb-b-connector"; 47 /* SMARC P64 - USB0_OTG_ID */ 48 id-gpios = <&som_gpio_expander_0 3 GPIO_ACTIVE_HIGH>; 49 label = "USB0"; 50 self-powered; 51 type = "micro"; 52 vbus-supply = <®_usb0_vbus>; 53 54 port { 55 usb_dr_connector: endpoint { 56 remote-endpoint = <&usb0_otg_id>; 57 }; 58 }; 59 }; 60 61 gpio-keys { 62 compatible = "gpio-keys"; 63 64 smarc_key_sleep: key-sleep { 65 gpios = <&som_ec_gpio_expander 4 GPIO_ACTIVE_LOW>; 66 label = "SMARC_SLEEP#"; 67 wakeup-source; 68 linux,code = <KEY_SLEEP>; 69 }; 70 71 smarc_switch_lid: switch-lid { 72 gpios = <&som_ec_gpio_expander 2 GPIO_ACTIVE_LOW>; 73 label = "SMARC_LID#"; 74 linux,code = <SW_LID>; 75 linux,input-type = <EV_SW>; 76 }; 77 }; 78 79 reg_module_1p8v: regulator-module-1p8v { 80 compatible = "regulator-fixed"; 81 regulator-max-microvolt = <1800000>; 82 regulator-min-microvolt = <1800000>; 83 regulator-name = "On-module +V1.8"; 84 }; 85 86 /* Non PMIC On-module Supplies */ 87 reg_module_dp_1p2v: regulator-module-dp-1p2v { 88 compatible = "regulator-fixed"; 89 regulator-max-microvolt = <1200000>; 90 regulator-min-microvolt = <1200000>; 91 regulator-name = "On-module +V1.2_DP"; 92 vin-supply = <®_module_1p8v>; 93 }; 94 95 reg_usb0_vbus: regulator-usb0-vbus { 96 compatible = "regulator-fixed"; 97 /* SMARC P62 - USB0_EN_OC# */ 98 gpios = <&som_gpio_expander_0 4 GPIO_ACTIVE_HIGH>; 99 enable-active-high; 100 regulator-name = "USB0_EN_OC#"; 101 }; 102 103 reg_usb1_vbus: regulator-usb1-vbus { 104 compatible = "regulator-fixed"; 105 /* CTRL_V_BUS_USB_HUB or SMARC P71 - USB2_EN_OC# */ 106 gpios = <&som_gpio_expander_0 6 GPIO_ACTIVE_HIGH>; 107 enable-active-high; 108 regulator-name = "CTRL_V_BUS_USB_HUB"; 109 }; 110 111 reg_usdhc2_vmmc: regulator-vmmc-usdhc2 { 112 compatible = "regulator-fixed"; 113 pinctrl-names = "default"; 114 pinctrl-0 = <&pinctrl_usdhc2_pwr_en>; 115 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 116 enable-active-high; 117 off-on-delay-us = <100000>; 118 regulator-max-microvolt = <3300000>; 119 regulator-min-microvolt = <3300000>; 120 regulator-name = "SDIO_PWR_EN"; 121 startup-delay-us = <20000>; 122 }; 123 124 reg_usdhc2_vqmmc: regulator-usdhc2-vqmmc { 125 compatible = "regulator-gpio"; 126 pinctrl-names = "default"; 127 pinctrl-0 = <&pinctrl_usdhc2_vsel>; 128 gpios = <&gpio3 19 GPIO_ACTIVE_HIGH>; 129 regulator-max-microvolt = <3300000>; 130 regulator-min-microvolt = <1800000>; 131 states = <1800000 0x1>, 132 <3300000 0x0>; 133 regulator-name = "PMIC_SD2_VSEL"; 134 }; 135 136 reg_wifi_en: regulator-wifi-en { 137 compatible = "regulator-fixed"; 138 /* CTRL_EN_WIFI */ 139 gpios = <&som_gpio_expander_1 7 GPIO_ACTIVE_HIGH>; 140 enable-active-high; 141 regulator-max-microvolt = <3300000>; 142 regulator-min-microvolt = <3300000>; 143 regulator-name = "CTRL_EN_WIFI"; 144 startup-delay-us = <2000>; 145 }; 146 147 remoteproc-cm7 { 148 compatible = "fsl,imx95-cm7"; 149 mboxes = <&mu7 0 1 &mu7 1 1 &mu7 3 1>; 150 mbox-names = "tx", "rx", "rxdb"; 151 memory-region = <&vdevbuffer>, <&vdev0vring0>, <&vdev0vring1>, 152 <&vdev1vring0>, <&vdev1vring1>, <&rsc_table>, <&m7_reserved>; 153 }; 154 155 reserved-memory { 156 #address-cells = <2>; 157 #size-cells = <2>; 158 ranges; 159 160 linux_cma: linux,cma { 161 compatible = "shared-dma-pool"; 162 reusable; 163 size = <0 0x3c000000>; 164 alloc-ranges = <0 0x80000000 0 0x7f000000>; 165 linux,cma-default; 166 }; 167 168 m7_reserved: memory@80000000 { 169 reg = <0 0x80000000 0 0x1000000>; 170 no-map; 171 }; 172 173 rsc_table: rsc-table@88220000 { 174 reg = <0 0x88220000 0 0x1000>; 175 no-map; 176 }; 177 178 vdev0vring0: vdev0vring0@88000000 { 179 reg = <0 0x88000000 0 0x8000>; 180 no-map; 181 }; 182 183 vdev0vring1: vdev0vring1@88008000 { 184 reg = <0 0x88008000 0 0x8000>; 185 no-map; 186 }; 187 188 vdev1vring0: vdev1vring0@88010000 { 189 reg = <0 0x88010000 0 0x8000>; 190 no-map; 191 }; 192 193 vdev1vring1: vdev1vring1@88018000 { 194 reg = <0 0x88018000 0 0x8000>; 195 no-map; 196 }; 197 198 vdevbuffer: vdevbuffer@88020000 { 199 compatible = "shared-dma-pool"; 200 reg = <0 0x88020000 0 0x100000>; 201 no-map; 202 }; 203 }; 204}; 205 206/* SMARC GBE0 */ 207&enetc_port0 { 208 pinctrl-names = "default"; 209 pinctrl-0 = <&pinctrl_enetc0>, <&pinctrl_enetc0_1588_tmr>; 210 phy-handle = <ðphy1>; 211 phy-mode = "rgmii-id"; 212}; 213 214/* SMARC GBE1 */ 215&enetc_port1 { 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_enetc1>, <&pinctrl_enetc1_1588_tmr>; 218 phy-handle = <ðphy2>; 219 phy-mode = "rgmii-id"; 220}; 221 222/* SMARC CAN0 */ 223&flexcan1 { 224 pinctrl-names = "default"; 225 pinctrl-0 = <&pinctrl_flexcan1>; 226}; 227 228/* SMARC CAN1 */ 229&flexcan2 { 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_flexcan2>; 232}; 233 234&gpio1 { 235 gpio-line-names = "", /* 0 */ 236 "", 237 "SMARC_I2C_GP_CK", 238 "SMARC_I2C_GP_DAT", 239 "", 240 "", 241 "", 242 "", 243 "", 244 "", 245 "", /* 10 */ 246 "", 247 "", 248 "", 249 "CTRL_IO_EXP_INT_B"; 250 status = "okay"; 251}; 252 253&gpio2 { 254 gpio-line-names = "SMARC_SPI0_CS0#", /* 0 */ 255 "", 256 "", 257 "", 258 "", 259 "", 260 "SMARC_GPIO5", 261 "", 262 "I2C_CAM_DAT", 263 "I2C_CAM_CK", 264 "SMARC_GPIO12", /* 10 */ 265 "SMARC_GPIO13", 266 "", 267 "", 268 "", 269 "", 270 "", 271 "", 272 "SMARC_SPI1_CS0#", 273 "", 274 "", /* 20 */ 275 "", 276 "SMARC_I2C_LCD_DAT", 277 "SMARC_I2C_LCD_CK", 278 "SMARC_SPI0_CS1#", 279 "", 280 "", 281 "", 282 "SMARC_I2C_PM_DAT", 283 "SMARC_I2C_PM_CK", 284 "I2C_SOM_DAT", /* 30 */ 285 "I2C_SOM_CK"; 286 status = "okay"; 287}; 288 289&gpio3 { 290 gpio-line-names = "SMARC_SDIO_CD#", /* 0 */ 291 "", 292 "", 293 "", 294 "", 295 "", 296 "", 297 "SMARC_SDIO_PWR_EN", 298 "", 299 "", 300 "", /* 10 */ 301 "", 302 "", 303 "", 304 "", 305 "", 306 "", 307 "", 308 "", 309 "PMIC_SD2_VSEL"; 310 status = "okay"; 311}; 312 313&gpio4 { 314 gpio-line-names = "", /* 0 */ 315 "", 316 "", 317 "", 318 "", 319 "", 320 "", 321 "", 322 "", 323 "", 324 "", /* 10 */ 325 "", 326 "", 327 "", 328 "SMARC_GPIO11", 329 "SMARC_GPIO10", 330 "", 331 "", 332 "", 333 "", 334 "", /* 20 */ 335 "", 336 "", 337 "", 338 "", 339 "", 340 "", 341 "", 342 "SMARC_SMB_ALERT#"; 343 status = "okay"; 344}; 345 346&gpio5 { 347 gpio-line-names = "SMARC_GPIO2", /* 0 */ 348 "SMARC_GPIO3", 349 "SMARC_GPIO4", 350 "SMARC_GPIO6", 351 "", 352 "", 353 "", 354 "", 355 "SMARC_GPIO9", 356 "SMARC_GPIO7", 357 "SMARC_GPIO8", /* 10 */ 358 "SMARC_SPI1_CS1#", 359 "", 360 "SPI1_TPM_CS#"; 361 status = "okay"; 362}; 363 364/* SMARC I2C_GP */ 365&lpi2c2 { 366 pinctrl-names = "default", "gpio"; 367 pinctrl-0 = <&pinctrl_lpi2c2>; 368 pinctrl-1 = <&pinctrl_lpi2c2_gpio>; 369 #address-cells = <1>; 370 #size-cells = <0>; 371 clock-frequency = <400000>; 372 scl-gpios = <&gpio1 2 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 373 sda-gpios = <&gpio1 3 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 374 status = "okay"; 375 376 eeprom@50 { 377 compatible = "st,24c32", "atmel,24c32"; 378 reg = <0x50>; 379 pagesize = <32>; 380 }; 381}; 382 383/* SMARC I2C_PM */ 384&lpi2c3 { 385 pinctrl-names = "default", "gpio"; 386 pinctrl-0 = <&pinctrl_lpi2c3>; 387 pinctrl-1 = <&pinctrl_lpi2c3_gpio>; 388 #address-cells = <1>; 389 #size-cells = <0>; 390 clock-frequency = <400000>; 391 scl-gpios = <&gpio2 29 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 392 sda-gpios = <&gpio2 28 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 393}; 394 395/* I2C_SOM */ 396&lpi2c4 { 397 pinctrl-names = "default", "gpio"; 398 pinctrl-0 = <&pinctrl_lpi2c4>, <&pinctrl_ctrl_io_exp_int_b>; 399 pinctrl-1 = <&pinctrl_lpi2c4_gpio>, <&pinctrl_ctrl_io_exp_int_b>; 400 #address-cells = <1>; 401 #size-cells = <0>; 402 clock-frequency = <400000>; 403 scl-gpios = <&gpio2 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 404 sda-gpios = <&gpio2 30 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 405 status = "okay"; 406 407 som_gpio_expander_0: gpio@20 { 408 compatible = "nxp,pcal6408"; 409 reg = <0x20>; 410 #interrupt-cells = <2>; 411 interrupt-controller; 412 interrupt-parent = <&gpio1>; 413 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 414 #gpio-cells = <2>; 415 gpio-controller; 416 gpio-line-names = 417 "SMARC_PCIE_WAKE#", /* 0 */ 418 "SMARC_PCIE_B_RST#", 419 "SMARC_PCIE_A_RST#", 420 "SMARC_USB0_OTG_ID", 421 "SMARC_USB0_EN", /* SMARC USB0_EN_OC# - Open Drain Output */ 422 "SMARC_USB0_OC#", /* SMARC USB0_EN_OC# - Over-Current Sense Input */ 423 "", 424 "SMARC_PCIE_C_RST#"; 425 }; 426 427 som_gpio_expander_1: gpio@21 { 428 compatible = "nxp,pcal6416"; 429 reg = <0x21>; 430 #interrupt-cells = <2>; 431 interrupt-controller; 432 interrupt-parent = <&gpio1>; 433 interrupts = <14 IRQ_TYPE_LEVEL_LOW>; 434 #gpio-cells = <2>; 435 gpio-controller; 436 gpio-line-names = 437 "SMARC_GPIO0", /* 0 */ 438 "SMARC_GPIO1", 439 "SMARC_LCD0_VDD_EN", 440 "SMARC_LCD0_BKLT_EN", 441 "SMARC_LCD1_VDD_EN", 442 "SMARC_LCD1_BKLT_EN", 443 "", 444 "", 445 "", 446 "", 447 "", /* 10 */ 448 "", 449 "", 450 "", 451 "", 452 "SMARC_SDIO_WP"; 453 }; 454 455 embedded-controller@28 { 456 compatible = "toradex,smarc-imx95-ec", "toradex,smarc-ec"; 457 reg = <0x28>; 458 }; 459 460 som_ec_gpio_expander: gpio@29 { 461 compatible = "toradex,ecgpiol16", "nxp,pcal6416"; 462 reg = <0x29>; 463 pinctrl-names = "default"; 464 pinctrl-0 = <&pinctrl_ec_int>; 465 #interrupt-cells = <2>; 466 interrupt-controller; 467 interrupt-parent = <&gpio1>; 468 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 469 #gpio-cells = <2>; 470 gpio-controller; 471 gpio-line-names = 472 "SMARC_CHARGER_PRSNT#", 473 "SMARC_CHARGING#", 474 "SMARC_LID#", 475 "SMARC_BATLOW#", 476 "SMARC_SLEEP#"; 477 }; 478 479 /* SMARC DP0 */ 480 som_dsi2dp_bridge: bridge@2c { 481 compatible = "ti,sn65dsi86"; 482 reg = <0x2c>; 483 clocks = <&clk_dsi2dp_bridge>; 484 clock-names = "refclk"; 485 vcc-supply = <®_module_dp_1p2v>; 486 vcca-supply = <®_module_dp_1p2v>; 487 vccio-supply = <®_module_1p8v>; 488 vpll-supply = <®_module_1p8v>; 489 status = "disabled"; 490 491 ports { 492 #address-cells = <1>; 493 #size-cells = <0>; 494 495 port@0 { 496 reg = <0>; 497 498 sn65dsi86_in: endpoint { 499 }; 500 }; 501 502 port@1 { 503 reg = <1>; 504 505 sn65dsi86_out: endpoint { 506 data-lanes = <3 2 1 0>; 507 }; 508 }; 509 }; 510 }; 511 512 rtc_i2c: rtc@32 { 513 compatible = "epson,rx8130"; 514 reg = <0x32>; 515 }; 516 517 temperature-sensor@48 { 518 compatible = "ti,tmp1075"; 519 reg = <0x48>; 520 }; 521 522 eeprom@50 { 523 compatible = "st,24c02", "atmel,24c02"; 524 reg = <0x50>; 525 pagesize = <16>; 526 }; 527}; 528 529/* SMARC I2C_LCD */ 530&lpi2c5 { 531 pinctrl-names = "default", "gpio"; 532 pinctrl-0 = <&pinctrl_lpi2c5>; 533 pinctrl-1 = <&pinctrl_lpi2c5_gpio>; 534 #address-cells = <1>; 535 #size-cells = <0>; 536 clock-frequency = <100000>; 537 scl-gpios = <&gpio2 23 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 538 sda-gpios = <&gpio2 22 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 539}; 540 541/* I2C_CAM */ 542&lpi2c7 { 543 pinctrl-names = "default", "gpio"; 544 pinctrl-0 = <&pinctrl_lpi2c7>; 545 pinctrl-1 = <&pinctrl_lpi2c7_gpio>; 546 #address-cells = <1>; 547 #size-cells = <0>; 548 clock-frequency = <400000>; 549 scl-gpios = <&gpio2 9 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 550 sda-gpios = <&gpio2 8 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; 551 status = "okay"; 552 553 i2c-mux@70 { 554 compatible = "nxp,pca9543"; 555 reg = <0x70>; 556 #address-cells = <1>; 557 #size-cells = <0>; 558 559 /* SMARC I2C_CAM0 */ 560 i2c_cam0: i2c@0 { 561 reg = <0>; 562 #address-cells = <1>; 563 #size-cells = <0>; 564 }; 565 566 /* SMARC I2C_CAM1 */ 567 i2c_cam1: i2c@1 { 568 reg = <1>; 569 #address-cells = <1>; 570 #size-cells = <0>; 571 }; 572 }; 573}; 574 575/* SMARC SPI1 */ 576&lpspi4 { 577 pinctrl-names = "default"; 578 pinctrl-0 = <&pinctrl_lpspi4>; 579 cs-gpios = <&gpio2 18 GPIO_ACTIVE_LOW>, 580 <&gpio5 11 GPIO_ACTIVE_LOW>, 581 <&gpio5 13 GPIO_ACTIVE_LOW>; 582 status = "okay"; 583 584 som_tpm: tpm@2 { 585 compatible = "infineon,slb9670", "tcg,tpm_tis-spi"; 586 reg = <0x2>; 587 spi-max-frequency = <18500000>; 588 }; 589}; 590 591/* SMARC SPI0 */ 592&lpspi6 { 593 pinctrl-names = "default"; 594 pinctrl-0 = <&pinctrl_lpspi6>; 595 cs-gpios = <&gpio2 0 GPIO_ACTIVE_LOW>, 596 <&gpio2 24 GPIO_ACTIVE_LOW>; 597}; 598 599/* SMARC SER1, used as the Linux Console */ 600&lpuart1 { 601 pinctrl-names = "default"; 602 pinctrl-0 = <&pinctrl_uart1>; 603}; 604 605/* SMARC SER0 */ 606&lpuart2 { 607 pinctrl-names = "default"; 608 pinctrl-0 = <&pinctrl_uart2>; 609 uart-has-rtscts; 610}; 611 612/* SMARC SER3 */ 613&lpuart3 { 614 pinctrl-names = "default"; 615 pinctrl-0 = <&pinctrl_uart3>; 616}; 617 618&mu7 { 619 status = "okay"; 620}; 621 622/* SMARC MDIO, shared between all ethernet ports */ 623&netc_emdio { 624 pinctrl-names = "default"; 625 pinctrl-0 = <&pinctrl_emdio>; 626 627 ethphy1: ethernet-phy@1 { 628 reg = <1>; 629 interrupt-parent = <&som_gpio_expander_1>; 630 interrupts = <6 IRQ_TYPE_EDGE_FALLING>; 631 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 632 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 633 }; 634 635 ethphy2: ethernet-phy@2 { 636 reg = <2>; 637 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 638 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; 639 }; 640}; 641 642&netcmix_blk_ctrl { 643 status = "okay"; 644}; 645 646&netc_blk_ctrl { 647 status = "okay"; 648}; 649 650&netc_timer { 651 status = "okay"; 652}; 653 654/* SMARC PCIE_A */ 655&pcie0 { 656 pinctrl-0 = <&pinctrl_pcie0>; 657 pinctrl-names = "default"; 658 reset-gpios = <&som_gpio_expander_0 2 GPIO_ACTIVE_LOW>; 659}; 660 661/* SMARC PCIE_B */ 662&pcie1 { 663 pinctrl-0 = <&pinctrl_pcie1>; 664 pinctrl-names = "default"; 665 reset-gpios = <&som_gpio_expander_0 1 GPIO_ACTIVE_LOW>; 666}; 667 668/* SMARC I2S0 */ 669&sai3 { 670 #sound-dai-cells = <0>; 671 assigned-clocks = <&scmi_clk IMX95_CLK_AUDIOPLL1_VCO>, 672 <&scmi_clk IMX95_CLK_AUDIOPLL2_VCO>, 673 <&scmi_clk IMX95_CLK_AUDIOPLL1>, 674 <&scmi_clk IMX95_CLK_AUDIOPLL2>, 675 <&scmi_clk IMX95_CLK_SAI3>; 676 assigned-clock-parents = <0>, <0>, <0>, <0>, 677 <&scmi_clk IMX95_CLK_AUDIOPLL1>; 678 assigned-clock-rates = <3932160000>, 679 <3612672000>, <393216000>, 680 <361267200>, <12288000>; 681 fsl,sai-mclk-direction-output; 682}; 683 684&thermal_zones { 685 /* PF09 Main PMIC */ 686 pf09-thermal { 687 polling-delay = <2000>; 688 polling-delay-passive = <250>; 689 thermal-sensors = <&scmi_sensor 2>; 690 691 trips { 692 trip0 { 693 hysteresis = <2000>; 694 temperature = <155000>; 695 type = "critical"; 696 }; 697 }; 698 }; 699 700 /* PF53 VDD_ARM PMIC */ 701 pf53-arm-thermal { 702 polling-delay = <2000>; 703 polling-delay-passive = <250>; 704 thermal-sensors = <&scmi_sensor 4>; 705 706 trips { 707 trip0 { 708 hysteresis = <2000>; 709 temperature = <155000>; 710 type = "critical"; 711 }; 712 }; 713 }; 714 715 /* PF53 VDD_SOC PMIC */ 716 pf53-soc-thermal { 717 polling-delay = <2000>; 718 polling-delay-passive = <250>; 719 thermal-sensors = <&scmi_sensor 3>; 720 721 trips { 722 trip0 { 723 hysteresis = <2000>; 724 temperature = <155000>; 725 type = "critical"; 726 }; 727 }; 728 }; 729}; 730 731/* SMARC LCD0_BKLT_PWM */ 732&tpm3 { 733 pinctrl-names = "default"; 734 pinctrl-0 = <&pinctrl_lcd0_bklt_pwm>; 735}; 736 737/* SMARC LCD1_BKLT_PWM */ 738&tpm4 { 739 pinctrl-names = "default"; 740 pinctrl-0 = <&pinctrl_lcd1_bklt_pwm>; 741}; 742 743/* SMARC GPIO5 as PWM */ 744&tpm5 { 745 pinctrl-names = "default"; 746 pinctrl-0 = <&pinctrl_gpio5_pwm>; 747}; 748 749/* SMARC USB0 */ 750&usb2 { 751 adp-disable; 752 dr_mode = "otg"; 753 hnp-disable; 754 srp-disable; 755 usb-role-switch; 756 vbus-supply = <®_usb0_vbus>; 757 758 port { 759 usb0_otg_id: endpoint { 760 remote-endpoint = <&usb_dr_connector>; 761 }; 762 }; 763}; 764 765&usb3 { 766 fsl,disable-port-power-control; 767}; 768 769/* SMARC USB1..4 */ 770&usb3_dwc3 { 771 dr_mode = "host"; 772}; 773 774&usb3_phy { 775 vbus-supply = <®_usb1_vbus>; 776}; 777 778/* On-module eMMC */ 779&usdhc1 { 780 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 781 pinctrl-0 = <&pinctrl_usdhc1>; 782 pinctrl-1 = <&pinctrl_usdhc1>; 783 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 784 bus-width = <8>; 785 non-removable; 786 no-sdio; 787 no-sd; 788 status = "okay"; 789}; 790 791/* SMARC SDIO */ 792&usdhc2 { 793 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 794 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 795 pinctrl-1 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_cd>; 796 pinctrl-2 = <&pinctrl_usdhc2_200mhz>,<&pinctrl_usdhc2_cd>; 797 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_cd>; 798 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 799 vmmc-supply = <®_usdhc2_vmmc>; 800 vqmmc-supply = <®_usdhc2_vqmmc>; 801 wp-gpios = <&som_gpio_expander_1 15 GPIO_ACTIVE_HIGH>; 802}; 803 804/* On-module Wi-Fi */ 805&usdhc3 { 806 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 807 pinctrl-0 = <&pinctrl_usdhc3>; 808 pinctrl-1 = <&pinctrl_usdhc3>; 809 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 810 keep-power-in-suspend; 811 non-removable; 812 vmmc-supply = <®_wifi_en>; 813}; 814 815&scmi_bbm { 816 linux,code = <KEY_POWER>; 817}; 818 819&wdog3 { 820 fsl,ext-reset-output; 821 status = "okay"; 822}; 823 824&scmi_iomuxc { 825 /* SMARC CAM_MCK */ 826 pinctrl_cam_mck: cammckgrp { 827 fsl,pins = <IMX95_PAD_CCM_CLKO1__CCMSRCGPCMIX_TOP_CLKO_1 0x51e>; /* SMARC S6 - CAM_MCK */ 828 }; 829 830 pinctrl_ec_int: ecintgrp { 831 fsl,pins = <IMX95_PAD_SAI1_TXFS__AONMIX_TOP_GPIO1_IO_BIT11 0x31e>; /* SAI1_TXFS - EC_MCU_INT# */ 832 }; 833 834 /* SMARC MDIO, shared between all ethernet ports */ 835 pinctrl_emdio: emdiogrp { 836 fsl,pins = <IMX95_PAD_ENET1_MDC__NETCMIX_TOP_NETC_MDC 0x50e>, /* SMARC S45 - MDIO_CLK */ 837 <IMX95_PAD_ENET1_MDIO__NETCMIX_TOP_NETC_MDIO 0x90e>; /* SMARC S46 - MDIO_DAT */ 838 }; 839 840 /* SMARC GBE0 */ 841 pinctrl_enetc0: enetc0grp { 842 fsl,pins = <IMX95_PAD_ENET1_TX_CTL__NETCMIX_TOP_ETH0_RGMII_TX_CTL 0x57e>, /* ENET1_TX_CTL */ 843 <IMX95_PAD_ENET1_TXC__NETCMIX_TOP_ETH0_RGMII_TX_CLK 0x58e>, /* ENET1_TXC */ 844 <IMX95_PAD_ENET1_TD0__NETCMIX_TOP_ETH0_RGMII_TD0 0x50e>, /* ENET1_TDO */ 845 <IMX95_PAD_ENET1_TD1__NETCMIX_TOP_ETH0_RGMII_TD1 0x50e>, /* ENET1_TD1 */ 846 <IMX95_PAD_ENET1_TD2__NETCMIX_TOP_ETH0_RGMII_TD2 0x50e>, /* ENET1_TD2 */ 847 <IMX95_PAD_ENET1_TD3__NETCMIX_TOP_ETH0_RGMII_TD3 0x50e>, /* ENET1_TD3 */ 848 <IMX95_PAD_ENET1_RX_CTL__NETCMIX_TOP_ETH0_RGMII_RX_CTL 0x57e>, /* ENET1_RX_CTL */ 849 <IMX95_PAD_ENET1_RXC__NETCMIX_TOP_ETH0_RGMII_RX_CLK 0x58e>, /* ENET1_RXC */ 850 <IMX95_PAD_ENET1_RD0__NETCMIX_TOP_ETH0_RGMII_RD0 0x57e>, /* ENET1_RD0 */ 851 <IMX95_PAD_ENET1_RD1__NETCMIX_TOP_ETH0_RGMII_RD1 0x57e>, /* ENET1_RD1 */ 852 <IMX95_PAD_ENET1_RD2__NETCMIX_TOP_ETH0_RGMII_RD2 0x57e>, /* ENET1_RD2 */ 853 <IMX95_PAD_ENET1_RD3__NETCMIX_TOP_ETH0_RGMII_RD3 0x57e>; /* ENET1_RD3 */ 854 }; 855 856 /* SMARC GBE0_SDP */ 857 pinctrl_enetc0_1588_tmr: enetc01588tmrgrp { 858 fsl,pins = <IMX95_PAD_CCM_CLKO2__NETCMIX_TOP_NETC_TMR_1588_PP1 0x51e>; /* SMARC P6 - GBE0_SDP */ 859 }; 860 861 /* SMARC GBE1 */ 862 pinctrl_enetc1: enetc1grp { 863 fsl,pins = <IMX95_PAD_ENET2_TX_CTL__NETCMIX_TOP_ETH1_RGMII_TX_CTL 0x57e>, /* ENET2_TX_CTL */ 864 <IMX95_PAD_ENET2_TXC__NETCMIX_TOP_ETH1_RGMII_TX_CLK 0x58e>, /* ENET2_TXC */ 865 <IMX95_PAD_ENET2_TD0__NETCMIX_TOP_ETH1_RGMII_TD0 0x50e>, /* ENET2_TD0 */ 866 <IMX95_PAD_ENET2_TD1__NETCMIX_TOP_ETH1_RGMII_TD1 0x50e>, /* ENET2_TD1 */ 867 <IMX95_PAD_ENET2_TD2__NETCMIX_TOP_ETH1_RGMII_TD2 0x50e>, /* ENET2_TD2 */ 868 <IMX95_PAD_ENET2_TD3__NETCMIX_TOP_ETH1_RGMII_TD3 0x50e>, /* ENET2_TD3 */ 869 <IMX95_PAD_ENET2_RX_CTL__NETCMIX_TOP_ETH1_RGMII_RX_CTL 0x57e>, /* ENET2_RX_CTL */ 870 <IMX95_PAD_ENET2_RXC__NETCMIX_TOP_ETH1_RGMII_RX_CLK 0x58e>, /* ENET2_RXC */ 871 <IMX95_PAD_ENET2_RD0__NETCMIX_TOP_ETH1_RGMII_RD0 0x57e>, /* ENET2_RD0 */ 872 <IMX95_PAD_ENET2_RD1__NETCMIX_TOP_ETH1_RGMII_RD1 0x57e>, /* ENET2_RD1 */ 873 <IMX95_PAD_ENET2_RD2__NETCMIX_TOP_ETH1_RGMII_RD2 0x57e>, /* ENET2_RD2 */ 874 <IMX95_PAD_ENET2_RD3__NETCMIX_TOP_ETH1_RGMII_RD3 0x57e>; /* ENET2_RD3 */ 875 }; 876 877 /* SMARC GBE1_SDP */ 878 pinctrl_enetc1_1588_tmr: enetc11588tmrgrp { 879 fsl,pins = <IMX95_PAD_CCM_CLKO4__NETCMIX_TOP_NETC_TMR_1588_PP2 0x51e>; /* SMARC P5 - GBE1_SDP */ 880 }; 881 882 /* SMARC CAN0 */ 883 pinctrl_flexcan1: flexcan1grp { 884 fsl,pins = <IMX95_PAD_PDM_CLK__AONMIX_TOP_CAN1_TX 0x39e>, /* SMARC P143 - CAN0_TX */ 885 <IMX95_PAD_PDM_BIT_STREAM0__AONMIX_TOP_CAN1_RX 0x39e>; /* SMARC P144 - CAN0_RX */ 886 }; 887 888 /* SMARC CAN1 */ 889 pinctrl_flexcan2: flexcan2grp { 890 fsl,pins = <IMX95_PAD_GPIO_IO25__CAN2_TX 0x39e>, /* SMARC P145 - CAN1_TX */ 891 <IMX95_PAD_GPIO_IO27__CAN2_RX 0x39e>; /* SMARC P146 - CAN1_RX */ 892 }; 893 894 /* SMARC GPIO2 */ 895 pinctrl_gpio2: gpio2grp { 896 fsl,pins = <IMX95_PAD_XSPI1_DATA0__GPIO5_IO_BIT0 0x31e>; /* SMARC P110 - GPIO2 */ 897 }; 898 899 /* SMARC GPIO3 */ 900 pinctrl_gpio3: gpio3grp { 901 fsl,pins = <IMX95_PAD_XSPI1_DATA1__GPIO5_IO_BIT1 0x31e>; /* SMARC P111 - GPIO3 */ 902 }; 903 904 /* SMARC GPIO4 */ 905 pinctrl_gpio4: gpio4grp { 906 fsl,pins = <IMX95_PAD_XSPI1_DATA2__GPIO5_IO_BIT2 0x31e>; /* SMARC P112 - GPIO4 */ 907 }; 908 909 /* SMARC GPIO5 */ 910 pinctrl_gpio5: gpio5grp { 911 fsl,pins = <IMX95_PAD_GPIO_IO06__GPIO2_IO_BIT6 0x31e>; /* SMARC P113 - GPIO5 */ 912 }; 913 914 /* SMARC GPIO5 as PWM */ 915 pinctrl_gpio5_pwm: gpio5pwmgrp { 916 fsl,pins = <IMX95_PAD_GPIO_IO06__TPM5_CH0 0x11e>; /* SMARC P113 - PWM_OUT */ 917 }; 918 919 /* SMARC GPIO6 */ 920 pinctrl_gpio6: gpio6grp { 921 fsl,pins = <IMX95_PAD_XSPI1_DATA3__GPIO5_IO_BIT3 0x31e>; /* SMARC P114 - GPIO6 */ 922 }; 923 924 /* SMARC GPIO7 */ 925 pinctrl_gpio7: gpio7grp { 926 fsl,pins = <IMX95_PAD_XSPI1_SCLK__GPIO5_IO_BIT9 0x31e>; /* SMARC P115 - GPIO7 */ 927 }; 928 929 /* SMARC GPIO8 */ 930 pinctrl_gpio8: gpio8grp { 931 fsl,pins = <IMX95_PAD_XSPI1_SS0_B__GPIO5_IO_BIT10 0x31e>; /* SMARC P116 - GPIO8 */ 932 }; 933 934 /* SMARC GPIO9 */ 935 pinctrl_gpio9: gpio9grp { 936 fsl,pins = <IMX95_PAD_XSPI1_DQS__GPIO5_IO_BIT8 0x31e>; /* SMARC P117 - GPIO9 */ 937 }; 938 939 /* SMARC GPIO10 */ 940 pinctrl_gpio10: gpio10grp { 941 fsl,pins = <IMX95_PAD_ENET2_MDIO__GPIO4_IO_BIT15 0x31e>; /* SMARC P118 - GPIO10 */ 942 }; 943 944 /* SMARC GPIO11 */ 945 pinctrl_gpio11: gpio11grp { 946 fsl,pins = <IMX95_PAD_ENET2_MDC__GPIO4_IO_BIT14 0x31e>; /* SMARC P119 - GPIO11 */ 947 }; 948 949 /* SMARC GPIO12 */ 950 pinctrl_gpio12: gpio12grp { 951 fsl,pins = <IMX95_PAD_GPIO_IO10__GPIO2_IO_BIT10 0x31e>; /* SMARC S142 - GPIO12 */ 952 }; 953 954 /* SMARC GPIO13 */ 955 pinctrl_gpio13: gpio13grp { 956 fsl,pins = <IMX95_PAD_GPIO_IO11__GPIO2_IO_BIT11 0x31e>; /* SMARC S123 - GPIO13 */ 957 }; 958 959 pinctrl_ctrl_io_exp_int_b: ioexpintgrp { 960 fsl,pins = <IMX95_PAD_SAI1_RXD0__AONMIX_TOP_GPIO1_IO_BIT14 0x31e>; /* CTRL_IO_EXP_INT_B */ 961 }; 962 963 /* SMARC LCD0_BKLT_PWM */ 964 pinctrl_lcd0_bklt_pwm: lcd0bkltpwmgrp { 965 fsl,pins = <IMX95_PAD_GPIO_IO12__TPM3_CH2 0x51e>; /* SMARC S141 - LCD0_BKLT_PWM */ 966 }; 967 968 /* SMARC LCD1_BKLT_PWM */ 969 pinctrl_lcd1_bklt_pwm: lcd1bkltpwmgrp { 970 fsl,pins = <IMX95_PAD_GPIO_IO13__TPM4_CH2 0x51e>; /* SMARC S122 - LCD1_BKLT_PWM */ 971 }; 972 973 /* SMARC I2C_GP */ 974 pinctrl_lpi2c2: lpi2c2grp { 975 fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_LPI2C2_SCL 0x40001b9e>, /* SMARC S48 - I2C_GP_CK */ 976 <IMX95_PAD_I2C2_SDA__AONMIX_TOP_LPI2C2_SDA 0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */ 977 }; 978 979 /* SMARC I2C_GP as GPIOs */ 980 pinctrl_lpi2c2_gpio: lpi2c2gpiogrp { 981 fsl,pins = <IMX95_PAD_I2C2_SCL__AONMIX_TOP_GPIO1_IO_BIT2 0x40001b9e>, /* SMARC S48 - I2C_GP_CK */ 982 <IMX95_PAD_I2C2_SDA__AONMIX_TOP_GPIO1_IO_BIT3 0x40001b9e>; /* SMARC S49 - I2C_GP_DAT */ 983 }; 984 985 /* SMARC I2C_PM */ 986 pinctrl_lpi2c3: lpi2c3grp { 987 fsl,pins = <IMX95_PAD_GPIO_IO28__LPI2C3_SDA 0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */ 988 <IMX95_PAD_GPIO_IO29__LPI2C3_SCL 0x40001b9e>; /* SMARC P121 - I2C_PM_CK */ 989 }; 990 991 /* SMARC I2C_PM as GPIOs */ 992 pinctrl_lpi2c3_gpio: lpi2c3gpiogrp { 993 fsl,pins = <IMX95_PAD_GPIO_IO28__GPIO2_IO_BIT28 0x40001b9e>, /* SMARC P122 - I2C_PM_DAT */ 994 <IMX95_PAD_GPIO_IO29__GPIO2_IO_BIT29 0x40001b9e>; /* SMARC P121 - I2C_PM_CK */ 995 }; 996 997 /* I2C_SOM */ 998 pinctrl_lpi2c4: lpi2c4grp { 999 fsl,pins = <IMX95_PAD_GPIO_IO31__LPI2C4_SCL 0x40001b9e>, /* I2C_SOM_CK */ 1000 <IMX95_PAD_GPIO_IO30__LPI2C4_SDA 0x40001b9e>; /* I2C_SOM_DAT */ 1001 }; 1002 1003 /* I2C_SOM as GPIOs */ 1004 pinctrl_lpi2c4_gpio: lpi2c4gpiogrp { 1005 fsl,pins = <IMX95_PAD_GPIO_IO31__GPIO2_IO_BIT31 0x40001b9e>, /* I2C_SOM_CK */ 1006 <IMX95_PAD_GPIO_IO30__GPIO2_IO_BIT30 0x40001b9e>; /* I2C_SOM_DAT */ 1007 }; 1008 1009 /* SMARC I2C_LCD */ 1010 pinctrl_lpi2c5: lpi2c5grp { 1011 fsl,pins = <IMX95_PAD_GPIO_IO22__LPI2C5_SDA 0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */ 1012 <IMX95_PAD_GPIO_IO23__LPI2C5_SCL 0x40001b9e>; /* SMARC S139 - I2C_LCD_CK */ 1013 }; 1014 1015 /* SMARC I2C_LCD as GPIOs */ 1016 pinctrl_lpi2c5_gpio: lpi2c5gpiogrp { 1017 fsl,pins = <IMX95_PAD_GPIO_IO22__GPIO2_IO_BIT22 0x40001b9e>, /* SMARC S140 - I2C_LCD_DAT */ 1018 <IMX95_PAD_GPIO_IO23__GPIO2_IO_BIT23 0x40001b9e>; /* SMARC S139 - I2C_LCD_CK */ 1019 }; 1020 1021 /* I2C_CAM */ 1022 pinctrl_lpi2c7: lpi2c7grp { 1023 fsl,pins = <IMX95_PAD_GPIO_IO08__LPI2C7_SDA 0x40001b9e>, /* I2C_CAM_DAT */ 1024 <IMX95_PAD_GPIO_IO09__LPI2C7_SCL 0x40001b9e>; /* I2C_CAM_CK */ 1025 }; 1026 1027 /* I2C_CAM as GPIOs */ 1028 pinctrl_lpi2c7_gpio: lpi2c7gpiogrp { 1029 fsl,pins = <IMX95_PAD_GPIO_IO08__GPIO2_IO_BIT8 0x40001b9e>, /* I2C_CAM_DAT */ 1030 <IMX95_PAD_GPIO_IO09__GPIO2_IO_BIT9 0x40001b9e>; /* I2C_CAM_CK */ 1031 }; 1032 1033 /* SMARC SPI1 */ 1034 pinctrl_lpspi4: lpspi4grp { 1035 fsl,pins = <IMX95_PAD_GPIO_IO37__LPSPI4_SCK 0x3fe>, /* SMARC P56 - SPI1_CK */ 1036 <IMX95_PAD_GPIO_IO36__LPSPI4_SOUT 0x3fe>, /* SMARC P58 - SPI1_DO */ 1037 <IMX95_PAD_GPIO_IO19__LPSPI4_SIN 0x3fe>, /* SMARC P57 - SPI1_DIN */ 1038 <IMX95_PAD_GPIO_IO33__GPIO5_IO_BIT13 0x3fe>, /* SPI1_TPM_CS# */ 1039 <IMX95_PAD_GPIO_IO18__GPIO2_IO_BIT18 0x3fe>, /* SMARC P54 - SPI1_CS0# */ 1040 <IMX95_PAD_XSPI1_SS1_B__GPIO5_IO_BIT11 0x3fe>; /* SMARC P55 - SPI1_CS1# */ 1041 }; 1042 1043 /* SMARC SPI0 */ 1044 pinctrl_lpspi6: lpspi6grp { 1045 fsl,pins = <IMX95_PAD_GPIO_IO00__GPIO2_IO_BIT0 0x3fe>, /* SMARC P43 - SPI0_CS0# */ 1046 <IMX95_PAD_GPIO_IO24__GPIO2_IO_BIT24 0x3fe>, /* SMARC P31 - SPI0_CS1# */ 1047 <IMX95_PAD_GPIO_IO01__LPSPI6_SIN 0x3fe>, /* SMARC P45 - SPI0_DIN */ 1048 <IMX95_PAD_GPIO_IO02__LPSPI6_SOUT 0x3fe>, /* SMARC P46 - SPI0_DO */ 1049 <IMX95_PAD_GPIO_IO03__LPSPI6_SCK 0x3fe>; /* SMARC P44 - SPI0_CK */ 1050 }; 1051 1052 /* SMARC PCIE_A */ 1053 pinctrl_pcie0: pcie0grp { 1054 fsl,pins = <IMX95_PAD_GPIO_IO32__HSIOMIX_TOP_PCIE1_CLKREQ_B 0x40001b1e>; /* SMARC P78 - PCIE_A_CKREQ# */ 1055 }; 1056 1057 /* SMARC PCIE_B */ 1058 pinctrl_pcie1: pcie1grp { 1059 fsl,pins = <IMX95_PAD_GPIO_IO35__HSIOMIX_TOP_PCIE2_CLKREQ_B 0x40001b1e>; /* SMARC P77 - PCIE_B_CKREQ# */ 1060 }; 1061 1062 /* SMARC I2S0 */ 1063 pinctrl_sai3: sai3grp { 1064 fsl,pins = <IMX95_PAD_GPIO_IO16__SAI3_TX_BCLK 0x11e>, /* SMARC S38 - I2S0_CK */ 1065 <IMX95_PAD_GPIO_IO20__SAI3_RX_DATA_BIT0 0x11e>, /* SMARC S41 - I2S0_SDIN */ 1066 <IMX95_PAD_GPIO_IO21__SAI3_TX_DATA_BIT0 0x11e>, /* SMARC S40 - I2S0_SDOUT */ 1067 <IMX95_PAD_GPIO_IO26__SAI3_TX_SYNC 0x11e>; /* SMARC S39 - I2S0_LRCK */ 1068 }; 1069 1070 /* SMARC AUDIO_MCK */ 1071 pinctrl_sai3_mclk: sai3mclkgrp { 1072 fsl,pins = <IMX95_PAD_GPIO_IO17__SAI3_MCLK 0x31e>; /* SMARC S42 - AUDIO_MCK */ 1073 }; 1074 1075 /* SMARC I2S2 */ 1076 pinctrl_sai5: sai5grp { 1077 fsl,pins = <IMX95_PAD_XSPI1_DATA6__SAI5_TX_BCLK 0x11e>, /* SMARC S53 - I2S2_CK */ 1078 <IMX95_PAD_XSPI1_DATA4__SAI5_TX_DATA_BIT0 0x11e>, /* SMARC S51 - I2S2_SDOUT */ 1079 <IMX95_PAD_XSPI1_DATA7__SAI5_RX_DATA_BIT0 0x11e>, /* SMARC S52 - I2S2_SDIN */ 1080 <IMX95_PAD_XSPI1_DATA5__SAI5_TX_SYNC 0x11e>; /* SMARC S50 - I2S2_LRCK */ 1081 }; 1082 1083 /* SMARC SMB_ALERT# */ 1084 pinctrl_smb_alert_gpio: smbalertgrp { 1085 fsl,pins = <IMX95_PAD_CCM_CLKO3__GPIO4_IO_BIT28 0x31e>; /* SMARC P1 - SMB_ALERT# */ 1086 }; 1087 1088 /* SMARC SER1, used as the Linux Console */ 1089 pinctrl_uart1: uart1grp { 1090 fsl,pins = <IMX95_PAD_UART1_TXD__AONMIX_TOP_LPUART1_TX 0x31e>, /* SMARC P134 - SER1_TX */ 1091 <IMX95_PAD_UART1_RXD__AONMIX_TOP_LPUART1_RX 0x31e>; /* SMARC P135 - SER1_RX */ 1092 }; 1093 1094 /* SMARC SER0 */ 1095 pinctrl_uart2: uart2grp { 1096 fsl,pins = <IMX95_PAD_SAI1_TXC__AONMIX_TOP_LPUART2_CTS_B 0x31e>, /* SMARC P132 - SER0_CTS# */ 1097 <IMX95_PAD_SAI1_TXD0__AONMIX_TOP_LPUART2_RTS_B 0x31e>, /* SMARC P131 - SER0_RTS# */ 1098 <IMX95_PAD_UART2_RXD__AONMIX_TOP_LPUART2_RX 0x31e>, /* SMARC P130 - SER0_RX */ 1099 <IMX95_PAD_UART2_TXD__AONMIX_TOP_LPUART2_TX 0x31e>; /* SMARC P129 - SER0_TX */ 1100 }; 1101 1102 /* SMARC SER3 */ 1103 pinctrl_uart3: uart3grp { 1104 fsl,pins = <IMX95_PAD_GPIO_IO14__LPUART3_TX 0x31e>, /* SMARC P140 - SER3_TX */ 1105 <IMX95_PAD_GPIO_IO15__LPUART3_RX 0x31e>; /* SMARC P141 - SER3_RX */ 1106 }; 1107 1108 /* On-module eMMC */ 1109 pinctrl_usdhc1: usdhc1grp { 1110 fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x158e>, /* SD1_CLK */ 1111 <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x138e>, /* SD1_CMD */ 1112 <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x138e>, /* SD1_DATA0 */ 1113 <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x138e>, /* SD1_DATA1 */ 1114 <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x138e>, /* SD1_DATA2 */ 1115 <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x138e>, /* SD1_DATA3 */ 1116 <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x138e>, /* SD1_DATA4 */ 1117 <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x138e>, /* SD1_DATA5 */ 1118 <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x138e>, /* SD1_DATA6 */ 1119 <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x138e>, /* SD1_DATA7 */ 1120 <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x158e>; /* SD1_STROBE */ 1121 }; 1122 1123 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 1124 fsl,pins = <IMX95_PAD_SD1_CLK__USDHC1_CLK 0x15fe>, /* SD1_CLK */ 1125 <IMX95_PAD_SD1_CMD__USDHC1_CMD 0x13fe>, /* SD1_CMD */ 1126 <IMX95_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe>, /* SD1_DATA0 */ 1127 <IMX95_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe>, /* SD1_DATA1 */ 1128 <IMX95_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe>, /* SD1_DATA2 */ 1129 <IMX95_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe>, /* SD1_DATA3 */ 1130 <IMX95_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe>, /* SD1_DATA4 */ 1131 <IMX95_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe>, /* SD1_DATA5 */ 1132 <IMX95_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe>, /* SD1_DATA6 */ 1133 <IMX95_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe>, /* SD1_DATA7 */ 1134 <IMX95_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe>; /* SD1_STROBE */ 1135 }; 1136 1137 /* SMARC SDIO */ 1138 pinctrl_usdhc2: usdhc2grp { 1139 fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x158e>, /* SMARC P36 - SDIO_CK */ 1140 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x138e>, /* SMARC P34 - SDIO_CMD */ 1141 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x138e>, /* SMARC P39 - SDIO_D0 */ 1142 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x138e>, /* SMARC P40 - SDIO_D1 */ 1143 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x138e>, /* SMARC P41 - SDIO_D2 */ 1144 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x138e>; /* SMARC P42 - SDIO_D3 */ 1145 }; 1146 1147 /* SMARC SDIO */ 1148 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 1149 fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x15fe>, /* SMARC P36 - SDIO_CK */ 1150 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x13fe>, /* SMARC P34 - SDIO_CMD */ 1151 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe>, /* SMARC P39 - SDIO_D0 */ 1152 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe>, /* SMARC P40 - SDIO_D1 */ 1153 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe>, /* SMARC P41 - SDIO_D2 */ 1154 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe>; /* SMARC P42 - SDIO_D3 */ 1155 }; 1156 1157 /* SMARC SDIO */ 1158 pinctrl_usdhc2_sleep: usdhc2-sleepgrp { 1159 fsl,pins = <IMX95_PAD_SD2_CLK__USDHC2_CLK 0x400>, /* SMARC P36 - SDIO_CK */ 1160 <IMX95_PAD_SD2_CMD__USDHC2_CMD 0x400>, /* SMARC P34 - SDIO_CMD */ 1161 <IMX95_PAD_SD2_DATA0__USDHC2_DATA0 0x400>, /* SMARC P39 - SDIO_D0 */ 1162 <IMX95_PAD_SD2_DATA1__USDHC2_DATA1 0x400>, /* SMARC P40 - SDIO_D1 */ 1163 <IMX95_PAD_SD2_DATA2__USDHC2_DATA2 0x400>, /* SMARC P41 - SDIO_D2 */ 1164 <IMX95_PAD_SD2_DATA3__USDHC2_DATA3 0x400>; /* SMARC P42 - SDIO_D3 */ 1165 }; 1166 1167 /* SMARC SDIO_CD# */ 1168 pinctrl_usdhc2_cd: usdhc2-cdgrp { 1169 fsl,pins = <IMX95_PAD_SD2_CD_B__GPIO3_IO_BIT0 0x1100>; /* SMARC P35 - SDIO_CD# */ 1170 }; 1171 1172 /* SMARC SDIO_PWR_EN */ 1173 pinctrl_usdhc2_pwr_en: usdhc2-pwrengrp { 1174 fsl,pins = <IMX95_PAD_SD2_RESET_B__GPIO3_IO_BIT7 0x11e>; /* SMARC P37 - SDIO_PWR_EN */ 1175 }; 1176 1177 pinctrl_usdhc2_vsel: usdhc2-vselgrp { 1178 fsl,pins = <IMX95_PAD_SD2_VSELECT__GPIO3_IO_BIT19 0x4>; /* PMIC_SD2_VSEL */ 1179 }; 1180 1181 /* On-module Wi-Fi */ 1182 pinctrl_usdhc3: usdhc3grp { 1183 fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x158e>, /* SD3_CLK */ 1184 <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x138e>, /* SD3_CMD */ 1185 <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x138e>, /* SD3_DATA0 */ 1186 <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x138e>, /* SD3_DATA1 */ 1187 <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x138e>, /* SD3_DATA2 */ 1188 <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x138e>; /* SD3_DATA3 */ 1189 }; 1190 1191 /* On-module Wi-Fi */ 1192 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 1193 fsl,pins = <IMX95_PAD_SD3_CLK__USDHC3_CLK 0x15fe>, /* SD3_CLK */ 1194 <IMX95_PAD_SD3_CMD__USDHC3_CMD 0x13fe>, /* SD3_CMD */ 1195 <IMX95_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe>, /* SD3_DATA1 */ 1196 <IMX95_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe>, /* SD3_DATA2 */ 1197 <IMX95_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe>, /* SD3_DATA3 */ 1198 <IMX95_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe>; /* SD3_DATA4 */ 1199 }; 1200}; 1201