1// SPDX-License-Identifier: (GPL-2.0-or-later OR MIT) 2/* 3 * Copyright (c) 2022-2025 TQ-Systems GmbH <linux@ew.tq-group.com>, 4 * D-82229 Seefeld, Germany. 5 * Author: Markus Niebel 6 * Author: Alexander Stein 7 */ 8/dts-v1/; 9 10#include <dt-bindings/input/input.h> 11#include <dt-bindings/leds/common.h> 12#include <dt-bindings/net/ti-dp83867.h> 13#include <dt-bindings/pwm/pwm.h> 14#include <dt-bindings/usb/pd.h> 15#include "imx93-tqma9352.dtsi" 16 17/{ 18 model = "TQ-Systems i.MX93 TQMa93xxLA/TQMa93xxCA on MBa91xxCA starter kit"; 19 compatible = "tq,imx93-tqma9352-mba91xxca", "tq,imx93-tqma9352", "fsl,imx93"; 20 chassis-type = "embedded"; 21 22 chosen { 23 stdout-path = &lpuart1; 24 }; 25 26 aliases { 27 eeprom0 = &eeprom0; 28 ethernet0 = &eqos; 29 ethernet1 = &fec; 30 rtc0 = &pcf85063; 31 rtc1 = &bbnsm_rtc; 32 }; 33 34 backlight: backlight { 35 compatible = "pwm-backlight"; 36 pwms = <&tpm2 2 5000000 0>; 37 brightness-levels = <0 4 8 16 32 64 128 255>; 38 default-brightness-level = <7>; 39 power-supply = <®_12v0>; 40 enable-gpios = <&expander2 2 GPIO_ACTIVE_HIGH>; 41 status = "disabled"; 42 }; 43 44 display: display { 45 /* 46 * Display is not fixed, so compatible has to be added from 47 * DT overlay 48 */ 49 power-supply = <®_3v3>; 50 enable-gpios = <&expander2 1 GPIO_ACTIVE_HIGH>; 51 backlight = <&backlight>; 52 status = "disabled"; 53 54 port { 55 panel_in: endpoint { 56 }; 57 }; 58 }; 59 60 fan0: gpio-fan { 61 compatible = "gpio-fan"; 62 gpios = <&expander2 4 GPIO_ACTIVE_HIGH>; 63 gpio-fan,speed-map = <0 0>, <10000 1>; 64 fan-supply = <®_12v0>; 65 #cooling-cells = <2>; 66 }; 67 68 gpio-keys { 69 compatible = "gpio-keys"; 70 autorepeat; 71 72 switch-a { 73 label = "switcha"; 74 linux,code = <BTN_0>; 75 gpios = <&expander0 6 GPIO_ACTIVE_LOW>; 76 wakeup-source; 77 }; 78 79 switch-b { 80 label = "switchb"; 81 linux,code = <BTN_1>; 82 gpios = <&expander0 7 GPIO_ACTIVE_LOW>; 83 wakeup-source; 84 }; 85 }; 86 87 gpio-leds { 88 compatible = "gpio-leds"; 89 90 led-1 { 91 color = <LED_COLOR_ID_GREEN>; 92 function = LED_FUNCTION_STATUS; 93 gpios = <&expander2 6 GPIO_ACTIVE_HIGH>; 94 linux,default-trigger = "default-on"; 95 }; 96 97 led-2 { 98 color = <LED_COLOR_ID_AMBER>; 99 function = LED_FUNCTION_HEARTBEAT; 100 gpios = <&expander2 7 GPIO_ACTIVE_HIGH>; 101 linux,default-trigger = "heartbeat"; 102 }; 103 }; 104 105 iio-hwmon { 106 compatible = "iio-hwmon"; 107 io-channels = <&adc1 0>, <&adc1 1>, <&adc1 2>, <&adc1 3>; 108 }; 109 110 lvds_encoder: lvds-encoder { 111 compatible = "ti,sn75lvds83", "lvds-encoder"; 112 powerdown-gpios = <&expander2 3 GPIO_ACTIVE_LOW>; 113 power-supply = <®_3v3>; 114 status = "disabled"; 115 116 ports { 117 #address-cells = <1>; 118 #size-cells = <0>; 119 120 port@0 { 121 reg = <0>; 122 123 lvds_encoder_input: endpoint { 124 }; 125 }; 126 127 port@1 { 128 reg = <1>; 129 130 lvds_encoder_output: endpoint { 131 }; 132 }; 133 }; 134 }; 135 136 reg_3v3: regulator-3v3 { 137 compatible = "regulator-fixed"; 138 regulator-name = "V_3V3_MB"; 139 regulator-min-microvolt = <3300000>; 140 regulator-max-microvolt = <3300000>; 141 }; 142 143 reg_5v0: regulator-5v0 { 144 compatible = "regulator-fixed"; 145 regulator-name = "V_5V0_MB"; 146 regulator-min-microvolt = <5000000>; 147 regulator-max-microvolt = <5000000>; 148 }; 149 150 reg_12v0: regulator-12v0 { 151 compatible = "regulator-fixed"; 152 regulator-name = "V_12V"; 153 regulator-min-microvolt = <12000000>; 154 regulator-max-microvolt = <12000000>; 155 gpio = <&expander1 7 GPIO_ACTIVE_HIGH>; 156 enable-active-high; 157 }; 158 159 reg_mpcie_1v5: regulator-mpcie-1v5 { 160 compatible = "regulator-fixed"; 161 regulator-name = "V_1V5_MPCIE"; 162 regulator-min-microvolt = <1500000>; 163 regulator-max-microvolt = <1500000>; 164 gpio = <&expander0 2 GPIO_ACTIVE_HIGH>; 165 enable-active-high; 166 regulator-always-on; 167 }; 168 169 reg_mpcie_3v3: regulator-mpcie-3v3 { 170 compatible = "regulator-fixed"; 171 regulator-name = "V_3V3_MPCIE"; 172 regulator-min-microvolt = <3300000>; 173 regulator-max-microvolt = <3300000>; 174 gpio = <&expander0 3 GPIO_ACTIVE_HIGH>; 175 enable-active-high; 176 regulator-always-on; 177 }; 178 179 thermal-zones { 180 cpu-thermal { 181 trips { 182 cpu_active: trip-active0 { 183 temperature = <40000>; 184 hysteresis = <5000>; 185 type = "active"; 186 }; 187 }; 188 189 cooling-maps { 190 map1 { 191 trip = <&cpu_active>; 192 cooling-device = <&fan0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 193 }; 194 }; 195 }; 196 }; 197}; 198 199&adc1 { 200 status = "okay"; 201}; 202 203&eqos { 204 pinctrl-names = "default"; 205 pinctrl-0 = <&pinctrl_eqos>; 206 phy-mode = "rgmii-id"; 207 phy-handle = <ðphy_eqos>; 208 status = "okay"; 209 210 mdio { 211 compatible = "snps,dwmac-mdio"; 212 #address-cells = <1>; 213 #size-cells = <0>; 214 215 ethphy_eqos: ethernet-phy@0 { 216 compatible = "ethernet-phy-ieee802.3-c22"; 217 reg = <0>; 218 pinctrl-names = "default"; 219 pinctrl-0 = <&pinctrl_eqos_phy>; 220 reset-gpios = <&expander1 0 GPIO_ACTIVE_LOW>; 221 reset-assert-us = <500000>; 222 reset-deassert-us = <50000>; 223 interrupt-parent = <&gpio3>; 224 interrupts = <26 IRQ_TYPE_EDGE_FALLING>; 225 enet-phy-lane-no-swap; 226 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 227 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 228 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 229 ti,dp83867-rxctrl-strap-quirk; 230 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 231 }; 232 }; 233}; 234 235&fec { 236 pinctrl-names = "default"; 237 pinctrl-0 = <&pinctrl_fec>; 238 phy-mode = "rgmii-id"; 239 phy-handle = <ðphy_fec>; 240 fsl,magic-packet; 241 status = "okay"; 242 243 mdio { 244 #address-cells = <1>; 245 #size-cells = <0>; 246 clock-frequency = <5000000>; 247 248 ethphy_fec: ethernet-phy@0 { 249 compatible = "ethernet-phy-ieee802.3-c22"; 250 reg = <0>; 251 pinctrl-names = "default"; 252 pinctrl-0 = <&pinctrl_fec_phy>; 253 reset-gpios = <&expander1 1 GPIO_ACTIVE_LOW>; 254 reset-assert-us = <500000>; 255 reset-deassert-us = <50000>; 256 interrupt-parent = <&gpio3>; 257 interrupts = <27 IRQ_TYPE_EDGE_FALLING>; 258 enet-phy-lane-no-swap; 259 ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 260 ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_25_NS>; 261 ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>; 262 ti,dp83867-rxctrl-strap-quirk; 263 ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; 264 }; 265 }; 266}; 267 268&flexcan1 { 269 pinctrl-names = "default"; 270 pinctrl-0 = <&pinctrl_flexcan1>; 271 xceiver-supply = <®_3v3>; 272 status = "okay"; 273}; 274 275&gpio1 { 276 gpio-line-names = 277 /* 00 */ "", "", "", "PMIC_IRQ#", 278 /* 04 */ "", "", "", "", 279 /* 08 */ "", "", "USB_C_ALERT#", "BM2_LCD_INT#", 280 /* 12 */ "PEX_INT#", "", "RTC_EVENT#", "", 281 /* 16 */ "", "", "", "", 282 /* 20 */ "", "", "", "", 283 /* 24 */ "", "", "", "", 284 /* 28 */ "", "", "", ""; 285}; 286 287&gpio2 { 288 gpio-line-names = 289 /* 00 */ "", "", "", "", 290 /* 04 */ "", "", "", "", 291 /* 08 */ "", "", "", "", 292 /* 12 */ "", "", "", "", 293 /* 16 */ "", "", "", "", 294 /* 20 */ "", "", "", "", 295 /* 24 */ "", "", "", "", 296 /* 28 */ "", "", "", ""; 297}; 298 299&gpio3 { 300 gpio-line-names = 301 /* 00 */ "SD2_CD#", "", "", "", 302 /* 04 */ "", "", "", "SD2_RST#", 303 /* 08 */ "", "", "", "", 304 /* 12 */ "", "", "", "", 305 /* 16 */ "", "", "", "", 306 /* 20 */ "", "", "", "", 307 /* 24 */ "", "", "ENET1_INT#", "ENET2_INT#", 308 /* 28 */ "", "", "", ""; 309}; 310 311&gpio4 { 312 gpio-line-names = 313 /* 00 */ "", "", "", "", 314 /* 04 */ "", "", "", "", 315 /* 08 */ "", "", "", "", 316 /* 12 */ "", "", "", "", 317 /* 16 */ "", "", "", "", 318 /* 20 */ "", "", "", "", 319 /* 24 */ "", "", "", "", 320 /* 28 */ "", "", "", ""; 321}; 322 323&lpi2c3 { 324 #address-cells = <1>; 325 #size-cells = <0>; 326 clock-frequency = <400000>; 327 pinctrl-names = "default", "sleep"; 328 pinctrl-0 = <&pinctrl_lpi2c3>; 329 pinctrl-1 = <&pinctrl_lpi2c3>; 330 status = "okay"; 331 332 temperature-sensor@1c { 333 compatible = "nxp,se97b", "jedec,jc-42.4-temp"; 334 reg = <0x1c>; 335 }; 336 337 ptn5110: usb-typec@50 { 338 compatible = "nxp,ptn5110", "tcpci"; 339 reg = <0x50>; 340 pinctrl-names = "default"; 341 pinctrl-0 = <&pinctrl_typec>; 342 interrupt-parent = <&gpio1>; 343 interrupts = <10 IRQ_TYPE_EDGE_FALLING>; 344 345 connector { 346 compatible = "usb-c-connector"; 347 label = "X17"; 348 power-role = "dual"; 349 data-role = "dual"; 350 try-power-role = "sink"; 351 typec-power-opmode = "default"; 352 pd-disable; 353 self-powered; 354 355 port { 356 typec_con_hs: endpoint { 357 remote-endpoint = <&typec_hs>; 358 }; 359 }; 360 }; 361 }; 362 363 eeprom2: eeprom@54 { 364 compatible = "nxp,se97b", "atmel,24c02"; 365 reg = <0x54>; 366 pagesize = <16>; 367 vcc-supply = <®_3v3>; 368 }; 369 370 expander0: gpio@70 { 371 compatible = "nxp,pca9538"; 372 reg = <0x70>; 373 pinctrl-names = "default"; 374 pinctrl-0 = <&pinctrl_pexp_irq>; 375 gpio-controller; 376 #gpio-cells = <2>; 377 interrupt-controller; 378 #interrupt-cells = <2>; 379 interrupt-parent = <&gpio1>; 380 interrupts = <12 IRQ_TYPE_LEVEL_LOW>; 381 vcc-supply = <®_3v3>; 382 gpio-line-names = "TEMP_EVENT_MOD#", "MPCIE_WAKE#", 383 "MPCIE_1V5_EN", "MPCIE_3V3_EN", 384 "MPCIE_PERST#", "MPCIE_WDISABLE#", 385 "BUTTON_A#", "BUTTON_B#"; 386 387 temp-event-mod-hog { 388 gpio-hog; 389 gpios = <0 GPIO_ACTIVE_LOW>; 390 input; 391 line-name = "TEMP_EVENT_MOD#"; 392 }; 393 394 mpcie-wake-hog { 395 gpio-hog; 396 gpios = <1 GPIO_ACTIVE_LOW>; 397 input; 398 line-name = "MPCIE_WAKE#"; 399 }; 400 401 /* 402 * Controls the mPCIE slot reset which is low active as 403 * reset signal. The output-low states, the signal is 404 * inactive, e.g. not in reset 405 */ 406 mpcie_rst_hog: mpcie-rst-hog { 407 gpio-hog; 408 gpios = <4 GPIO_ACTIVE_LOW>; 409 output-low; 410 line-name = "MPCIE_PERST#"; 411 }; 412 413 /* 414 * Controls the mPCIE slot WDISABLE pin which is low active 415 * as disable signal. The output-low states, the signal is 416 * inactive, e.g. not disabled 417 */ 418 mpcie_wdisable_hog: mpcie-wdisable-hog { 419 gpio-hog; 420 gpios = <5 GPIO_ACTIVE_LOW>; 421 output-low; 422 line-name = "MPCIE_WDISABLE#"; 423 }; 424 }; 425 426 expander1: gpio@71 { 427 compatible = "nxp,pca9538"; 428 reg = <0x71>; 429 gpio-controller; 430 #gpio-cells = <2>; 431 vcc-supply = <®_3v3>; 432 gpio-line-names = "ENET1_RESET#", "ENET2_RESET#", 433 "USB_RESET#", "", 434 "WLAN_PD#", "WLAN_W_DISABLE#", 435 "WLAN_PERST#", "12V_EN"; 436 437 /* 438 * Controls the WiFi card PD pin which is low active 439 * as power down signal. The output-low states, the signal 440 * is inactive, e.g. not power down 441 */ 442 wlan-pd-hog { 443 gpio-hog; 444 gpios = <4 GPIO_ACTIVE_LOW>; 445 output-low; 446 line-name = "WLAN_PD#"; 447 }; 448 449 /* 450 * Controls the WiFi card disable pin which is low active 451 * as disable signal. The output-low states, the signal 452 * is inactive, e.g. not disabled 453 */ 454 wlan-wdisable-hog { 455 gpio-hog; 456 gpios = <5 GPIO_ACTIVE_LOW>; 457 output-low; 458 line-name = "WLAN_W_DISABLE#"; 459 }; 460 461 /* 462 * Controls the WiFi card reset pin which is low active 463 * as reset signal. The output-low states, the signal 464 * is inactive, e.g. not in reset 465 */ 466 wlan-perst-hog { 467 gpio-hog; 468 gpios = <6 GPIO_ACTIVE_LOW>; 469 output-low; 470 line-name = "WLAN_PERST#"; 471 }; 472 }; 473 474 expander2: gpio@72 { 475 compatible = "nxp,pca9538"; 476 reg = <0x72>; 477 gpio-controller; 478 #gpio-cells = <2>; 479 vcc-supply = <®_3v3>; 480 gpio-line-names = "LCD_RESET#", "LCD_PWR_EN", 481 "LCD_BLT_EN", "LVDS_SHDN#", 482 "FAN_PWR_EN", "", 483 "USER_LED1", "USER_LED2"; 484 }; 485}; 486 487&lpuart1 { 488 pinctrl-names = "default"; 489 pinctrl-0 = <&pinctrl_uart1>; 490 status = "okay"; 491}; 492 493&lpuart2 { 494 pinctrl-names = "default"; 495 pinctrl-0 = <&pinctrl_uart2>; 496 linux,rs485-enabled-at-boot-time; 497 status = "okay"; 498}; 499 500&pcf85063 { 501 /* RTC_EVENT# from SoM is connected on mainboard */ 502 pinctrl-names = "default"; 503 pinctrl-0 = <&pinctrl_pcf85063>; 504 interrupt-parent = <&gpio1>; 505 interrupts = <14 IRQ_TYPE_EDGE_FALLING>; 506}; 507 508&se97_som { 509 /* TEMP_EVENT# from SoM is connected on mainboard */ 510 interrupt-parent = <&expander0>; 511 interrupts = <0 IRQ_TYPE_LEVEL_LOW>; 512}; 513 514&tpm2 { 515 pinctrl-names = "default"; 516 pinctrl-0 = <&pinctrl_tpm2>; 517 status = "okay"; 518}; 519 520&usbotg1 { 521 dr_mode = "otg"; 522 hnp-disable; 523 srp-disable; 524 adp-disable; 525 usb-role-switch; 526 disable-over-current; 527 samsung,picophy-pre-emp-curr-control = <3>; 528 samsung,picophy-dc-vol-level-adjust = <7>; 529 status = "okay"; 530 531 port { 532 typec_hs: endpoint { 533 remote-endpoint = <&typec_con_hs>; 534 }; 535 }; 536}; 537 538&usbotg2 { 539 dr_mode = "host"; 540 #address-cells = <1>; 541 #size-cells = <0>; 542 disable-over-current; 543 samsung,picophy-pre-emp-curr-control = <3>; 544 samsung,picophy-dc-vol-level-adjust = <7>; 545 status = "okay"; 546 547 hub_2_0: hub@1 { 548 compatible = "usb424,2517"; 549 reg = <1>; 550 reset-gpios = <&expander1 2 GPIO_ACTIVE_LOW>; 551 vdd-supply = <®_3v3>; 552 }; 553}; 554 555&usdhc2 { 556 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 557 pinctrl-0 = <&pinctrl_usdhc2_hs>, <&pinctrl_usdhc2_gpio>; 558 pinctrl-1 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; 559 pinctrl-2 = <&pinctrl_usdhc2_uhs>, <&pinctrl_usdhc2_gpio>; 560 cd-gpios = <&gpio3 0 GPIO_ACTIVE_LOW>; 561 vmmc-supply = <®_usdhc2_vmmc>; 562 bus-width = <4>; 563 no-sdio; 564 no-mmc; 565 disable-wp; 566 status = "okay"; 567}; 568 569&iomuxc { 570 pinctrl_eqos: eqosgrp { 571 fsl,pins = /* PD | FSEL_2 | DSE X4 */ 572 <MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x51e>, 573 /* SION | HYS | ODE | FSEL_2 | DSE X4 */ 574 <MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x4000111e>, 575 /* HYS | FSEL_0 | DSE no drive */ 576 <MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x1000>, 577 <MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x1000>, 578 <MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x1000>, 579 <MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x1000>, 580 <MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x1000>, 581 /* HYS | PD | FSEL_0 | DSE no drive */ 582 <MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x1400>, 583 /* PD | FSEL_2 | DSE X4 */ 584 <MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x51e>, 585 <MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x51e>, 586 <MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x51e>, 587 <MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x51e>, 588 <MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x51e>, 589 /* PD | FSEL_3 | DSE X3 */ 590 <MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e>; 591 }; 592 593 pinctrl_eqos_phy: eqosphygrp { 594 fsl,pins = /* HYS | FSEL_0 | DSE no drive */ 595 <MX93_PAD_CCM_CLKO1__GPIO3_IO26 0x1000>; 596 }; 597 598 pinctrl_fec: fecgrp { 599 fsl,pins = /* PD | FSEL_2 | DSE X4 */ 600 <MX93_PAD_ENET2_MDC__ENET1_MDC 0x51e>, 601 /* SION | HYS | ODE | FSEL_2 | DSE X4 */ 602 <MX93_PAD_ENET2_MDIO__ENET1_MDIO 0x4000111e>, 603 /* HYS | FSEL_0 | DSE no drive */ 604 <MX93_PAD_ENET2_RD0__ENET1_RGMII_RD0 0x1000>, 605 <MX93_PAD_ENET2_RD1__ENET1_RGMII_RD1 0x1000>, 606 <MX93_PAD_ENET2_RD2__ENET1_RGMII_RD2 0x1000>, 607 <MX93_PAD_ENET2_RD3__ENET1_RGMII_RD3 0x1000>, 608 <MX93_PAD_ENET2_RX_CTL__ENET1_RGMII_RX_CTL 0x1000>, 609 /* HYS | PD | FSEL_0 | DSE no drive */ 610 <MX93_PAD_ENET2_RXC__ENET1_RGMII_RXC 0x1400>, 611 /* PD | FSEL_2 | DSE X4 */ 612 <MX93_PAD_ENET2_TD0__ENET1_RGMII_TD0 0x51e>, 613 <MX93_PAD_ENET2_TD1__ENET1_RGMII_TD1 0x51e>, 614 <MX93_PAD_ENET2_TD2__ENET1_RGMII_TD2 0x51e>, 615 <MX93_PAD_ENET2_TD3__ENET1_RGMII_TD3 0x51e>, 616 <MX93_PAD_ENET2_TX_CTL__ENET1_RGMII_TX_CTL 0x51e>, 617 /* PD | FSEL_3 | DSE X3 */ 618 <MX93_PAD_ENET2_TXC__ENET1_RGMII_TXC 0x58e>; 619 }; 620 621 pinctrl_fec_phy: fecphygrp { 622 fsl,pins = /* HYS | FSEL_0 | DSE no drive */ 623 <MX93_PAD_CCM_CLKO2__GPIO3_IO27 0x1000>; 624 }; 625 626 pinctrl_flexcan1: flexcan1grp { 627 fsl,pins = /* HYS | PU | FSEL_0 | DSE no drive */ 628 <MX93_PAD_PDM_BIT_STREAM0__CAN1_RX 0x1200>, 629 /* PU | FSEL_3 | DSE X4 */ 630 <MX93_PAD_PDM_CLK__CAN1_TX 0x039e>; 631 }; 632 633 pinctrl_jtag: jtaggrp { 634 fsl,pins = <MX93_PAD_DAP_TCLK_SWCLK__JTAG_MUX_TCK 0x051e>, 635 <MX93_PAD_DAP_TDI__JTAG_MUX_TDI 0x1200>, 636 <MX93_PAD_DAP_TDO_TRACESWO__JTAG_MUX_TDO 0x031e>, 637 <MX93_PAD_DAP_TMS_SWDIO__JTAG_MUX_TMS 0x1200>; 638 }; 639 640 pinctrl_lpi2c3: lpi2c3grp { 641 fsl,pins = /* SION | HYS | OD | FSEL_3 | DSE X4 */ 642 <MX93_PAD_GPIO_IO28__LPI2C3_SDA 0x4000199e>, 643 <MX93_PAD_GPIO_IO29__LPI2C3_SCL 0x4000199e>; 644 }; 645 646 pinctrl_pcf85063: pcf85063grp { 647 fsl,pins = <MX93_PAD_SAI1_RXD0__GPIO1_IO14 0x1000>; 648 }; 649 650 pinctrl_pexp_irq: pexpirqgrp { 651 fsl,pins = /* HYS | FSEL_0 | No DSE */ 652 <MX93_PAD_SAI1_TXC__GPIO1_IO12 0x1000>; 653 }; 654 655 pinctrl_rgbdisp: rgbdispgrp { 656 fsl,pins = <MX93_PAD_GPIO_IO00__MEDIAMIX_DISP_CLK 0x31e>, 657 <MX93_PAD_GPIO_IO01__MEDIAMIX_DISP_DE 0x31e>, 658 <MX93_PAD_GPIO_IO02__MEDIAMIX_DISP_VSYNC 0x31e>, 659 <MX93_PAD_GPIO_IO03__MEDIAMIX_DISP_HSYNC 0x31e>, 660 <MX93_PAD_GPIO_IO04__MEDIAMIX_DISP_DATA00 0x31e>, 661 <MX93_PAD_GPIO_IO05__MEDIAMIX_DISP_DATA01 0x31e>, 662 <MX93_PAD_GPIO_IO06__MEDIAMIX_DISP_DATA02 0x31e>, 663 <MX93_PAD_GPIO_IO07__MEDIAMIX_DISP_DATA03 0x31e>, 664 <MX93_PAD_GPIO_IO08__MEDIAMIX_DISP_DATA04 0x31e>, 665 <MX93_PAD_GPIO_IO09__MEDIAMIX_DISP_DATA05 0x31e>, 666 <MX93_PAD_GPIO_IO10__MEDIAMIX_DISP_DATA06 0x31e>, 667 <MX93_PAD_GPIO_IO11__MEDIAMIX_DISP_DATA07 0x31e>, 668 <MX93_PAD_GPIO_IO12__MEDIAMIX_DISP_DATA08 0x31e>, 669 <MX93_PAD_GPIO_IO13__MEDIAMIX_DISP_DATA09 0x31e>, 670 <MX93_PAD_GPIO_IO14__MEDIAMIX_DISP_DATA10 0x31e>, 671 <MX93_PAD_GPIO_IO15__MEDIAMIX_DISP_DATA11 0x31e>, 672 <MX93_PAD_GPIO_IO16__MEDIAMIX_DISP_DATA12 0x31e>, 673 <MX93_PAD_GPIO_IO17__MEDIAMIX_DISP_DATA13 0x31e>, 674 <MX93_PAD_GPIO_IO18__MEDIAMIX_DISP_DATA14 0x31e>, 675 <MX93_PAD_GPIO_IO19__MEDIAMIX_DISP_DATA15 0x31e>, 676 <MX93_PAD_GPIO_IO20__MEDIAMIX_DISP_DATA16 0x31e>, 677 <MX93_PAD_GPIO_IO21__MEDIAMIX_DISP_DATA17 0x31e>, 678 <MX93_PAD_GPIO_IO22__MEDIAMIX_DISP_DATA18 0x31e>, 679 <MX93_PAD_GPIO_IO23__MEDIAMIX_DISP_DATA19 0x31e>, 680 <MX93_PAD_GPIO_IO24__MEDIAMIX_DISP_DATA20 0x31e>, 681 <MX93_PAD_GPIO_IO25__MEDIAMIX_DISP_DATA21 0x31e>, 682 <MX93_PAD_GPIO_IO26__MEDIAMIX_DISP_DATA22 0x31e>, 683 <MX93_PAD_GPIO_IO27__MEDIAMIX_DISP_DATA23 0x31e>; 684 }; 685 686 pinctrl_touch: touchgrp { 687 fsl,pins = /* HYS | FSEL_0 | No DSE */ 688 <MX93_PAD_SAI1_TXFS__GPIO1_IO11 0x1000>; 689 }; 690 691 pinctrl_tpm2: tpm2grp { 692 fsl,pins = <MX93_PAD_I2C2_SCL__TPM2_CH2 0x57e>; 693 }; 694 695 pinctrl_typec: typecgrp { 696 fsl,pins = /* HYS | FSEL_0 | No DSE */ 697 <MX93_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x1000>; 698 }; 699 700 pinctrl_uart1: uart1grp { 701 fsl,pins = /* HYS | FSEL_0 | No DSE */ 702 <MX93_PAD_UART1_RXD__LPUART1_RX 0x1000>, 703 /* FSEL_2 | DSE X4 */ 704 <MX93_PAD_UART1_TXD__LPUART1_TX 0x011e>; 705 }; 706 707 pinctrl_uart2: uart2grp { 708 fsl,pins = /* HYS | FSEL_0 | No DSE */ 709 <MX93_PAD_UART2_RXD__LPUART2_RX 0x1000>, 710 /* FSEL_2 | DSE X4 */ 711 <MX93_PAD_UART2_TXD__LPUART2_TX 0x011e>, 712 /* FSEL_2 | DSE X4 */ 713 <MX93_PAD_SAI1_TXD0__LPUART2_RTS_B 0x011e>; 714 }; 715 716 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 717 fsl,pins = /* HYS | FSEL_0 | No DSE */ 718 <MX93_PAD_SD2_CD_B__GPIO3_IO00 0x1000>; 719 }; 720 721 /* enable SION for data and cmd pad due to ERR052021 */ 722 pinctrl_usdhc2_hs: usdhc2hsgrp { 723 fsl,pins = /* PD | FSEL_3 | DSE X5 */ 724 <MX93_PAD_SD2_CLK__USDHC2_CLK 0x05be>, 725 /* HYS | PU | FSEL_3 | DSE X4 */ 726 <MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>, 727 /* HYS | PU | FSEL_3 | DSE X3 */ 728 <MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000138e>, 729 <MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000138e>, 730 <MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000138e>, 731 <MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000138e>, 732 /* FSEL_2 | DSE X3 */ 733 <MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>; 734 }; 735 736 /* enable SION for data and cmd pad due to ERR052021 */ 737 pinctrl_usdhc2_uhs: usdhc2uhsgrp { 738 fsl,pins = /* PD | FSEL_3 | DSE X6 */ 739 <MX93_PAD_SD2_CLK__USDHC2_CLK 0x05fe>, 740 /* HYS | PU | FSEL_3 | DSE X4 */ 741 <MX93_PAD_SD2_CMD__USDHC2_CMD 0x4000139e>, 742 <MX93_PAD_SD2_DATA0__USDHC2_DATA0 0x4000139e>, 743 <MX93_PAD_SD2_DATA1__USDHC2_DATA1 0x4000139e>, 744 <MX93_PAD_SD2_DATA2__USDHC2_DATA2 0x4000139e>, 745 <MX93_PAD_SD2_DATA3__USDHC2_DATA3 0x4000139e>, 746 /* FSEL_2 | DSE X3 */ 747 <MX93_PAD_SD2_VSELECT__USDHC2_VSELECT 0x010e>; 748 }; 749}; 750