1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025 NXP 4 */ 5 6#include "imx91-pinfunc.h" 7#include "imx91_93_common.dtsi" 8 9/{ 10 thermal-zones { 11 cpu-thermal { 12 polling-delay-passive = <250>; 13 polling-delay = <2000>; 14 thermal-sensors = <&tmu>; 15 16 trips { 17 cpu_alert: cpu-alert { 18 temperature = <80000>; 19 hysteresis = <2000>; 20 type = "passive"; 21 }; 22 23 cpu_crit: cpu-crit { 24 temperature = <90000>; 25 hysteresis = <2000>; 26 type = "critical"; 27 }; 28 }; 29 30 cooling-maps { 31 map0 { 32 trip = <&cpu_alert>; 33 cooling-device = 34 <&A55_0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; 35 }; 36 }; 37 }; 38 }; 39}; 40 41&aips1 { 42 tmu: thermal-sensor@44482000 { 43 compatible = "fsl,imx91-tmu"; 44 reg = <0x44482000 0x1000>; 45 #thermal-sensor-cells = <0>; 46 clocks = <&clk IMX93_CLK_TMC_GATE>; 47 interrupt-parent = <&gic>; 48 interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>, 49 <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>, 50 <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>; 51 interrupt-names = "thr1", "thr2", "ready"; 52 nvmem-cells = <&tmu_trim1>, <&tmu_trim2>; 53 nvmem-cell-names = "trim1", "trim2"; 54 }; 55}; 56 57&clk { 58 compatible = "fsl,imx91-ccm"; 59}; 60 61&ddr_pmu { 62 compatible = "fsl,imx91-ddr-pmu", "fsl,imx93-ddr-pmu"; 63}; 64 65&eqos { 66 clocks = <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, 67 <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>, 68 <&clk IMX91_CLK_ENET_TIMER>, 69 <&clk IMX91_CLK_ENET1_QOS_TSN>, 70 <&clk IMX91_CLK_ENET1_QOS_TSN_GATE>; 71 assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, 72 <&clk IMX91_CLK_ENET1_QOS_TSN>; 73 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 74 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; 75 assigned-clock-rates = <100000000>, <250000000>; 76}; 77 78&fec { 79 clocks = <&clk IMX91_CLK_ENET2_REGULAR_GATE>, 80 <&clk IMX91_CLK_ENET2_REGULAR_GATE>, 81 <&clk IMX91_CLK_ENET_TIMER>, 82 <&clk IMX91_CLK_ENET2_REGULAR>, 83 <&clk IMX93_CLK_DUMMY>; 84 assigned-clocks = <&clk IMX91_CLK_ENET_TIMER>, 85 <&clk IMX91_CLK_ENET2_REGULAR>; 86 assigned-clock-parents = <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>, 87 <&clk IMX93_CLK_SYS_PLL_PFD0_DIV2>; 88 assigned-clock-rates = <100000000>, <250000000>; 89}; 90 91&i3c1 { 92 clocks = <&clk IMX93_CLK_BUS_AON>, 93 <&clk IMX93_CLK_I3C1_GATE>, 94 <&clk IMX93_CLK_DUMMY>; 95}; 96 97&i3c2 { 98 clocks = <&clk IMX93_CLK_BUS_WAKEUP>, 99 <&clk IMX93_CLK_I3C2_GATE>, 100 <&clk IMX93_CLK_DUMMY>; 101}; 102 103&iomuxc { 104 compatible = "fsl,imx91-iomuxc"; 105}; 106 107&media_blk_ctrl { 108 compatible = "fsl,imx91-media-blk-ctrl", "syscon"; 109 clocks = <&clk IMX93_CLK_MEDIA_APB>, 110 <&clk IMX93_CLK_MEDIA_AXI>, 111 <&clk IMX93_CLK_NIC_MEDIA_GATE>, 112 <&clk IMX93_CLK_MEDIA_DISP_PIX>, 113 <&clk IMX93_CLK_CAM_PIX>, 114 <&clk IMX93_CLK_LCDIF_GATE>, 115 <&clk IMX93_CLK_ISI_GATE>, 116 <&clk IMX93_CLK_MIPI_CSI_GATE>; 117 clock-names = "apb", "axi", "nic", "disp", "cam", 118 "lcdif", "isi", "csi"; 119}; 120 121&ocotp { 122 tmu_trim1: tmu-trim@a0 { 123 reg = <0xa0 0x4>; 124 }; 125 126 tmu_trim2: tmu-trim@a4 { 127 reg = <0xa4 0x4>; 128 }; 129}; 130