1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2025 NXP 4 */ 5 6/dts-v1/; 7 8#include <dt-bindings/usb/pd.h> 9#include "imx91.dtsi" 10 11/ { 12 compatible = "fsl,imx91-11x11-evk", "fsl,imx91"; 13 model = "NXP i.MX91 11X11 EVK board"; 14 15 aliases { 16 ethernet0 = &fec; 17 ethernet1 = &eqos; 18 gpio0 = &gpio1; 19 gpio1 = &gpio2; 20 gpio2 = &gpio3; 21 i2c0 = &lpi2c1; 22 i2c1 = &lpi2c2; 23 i2c2 = &lpi2c3; 24 mmc0 = &usdhc1; 25 mmc1 = &usdhc2; 26 mmc2 = &usdhc3; 27 rtc0 = &bbnsm_rtc; 28 serial0 = &lpuart1; 29 serial1 = &lpuart2; 30 serial2 = &lpuart3; 31 serial3 = &lpuart4; 32 serial4 = &lpuart5; 33 }; 34 35 bt_sco_codec: bt-sco-codec { 36 compatible = "linux,bt-sco"; 37 #sound-dai-cells = <1>; 38 }; 39 40 chosen { 41 stdout-path = &lpuart1; 42 }; 43 44 reg_vref_1v8: regulator-adc-vref { 45 compatible = "regulator-fixed"; 46 regulator-max-microvolt = <1800000>; 47 regulator-min-microvolt = <1800000>; 48 regulator-name = "vref_1v8"; 49 }; 50 51 reg_audio_pwr: regulator-audio-pwr { 52 compatible = "regulator-fixed"; 53 regulator-always-on; 54 regulator-max-microvolt = <3300000>; 55 regulator-min-microvolt = <3300000>; 56 regulator-name = "audio-pwr"; 57 gpio = <&adp5585 1 GPIO_ACTIVE_HIGH>; 58 enable-active-high; 59 }; 60 61 reg_m2_pwr: regulator-m2-pwr { 62 compatible = "regulator-fixed"; 63 regulator-name = "M.2-power"; 64 regulator-min-microvolt = <3300000>; 65 regulator-max-microvolt = <3300000>; 66 gpio = <&pcal6524 13 GPIO_ACTIVE_HIGH>; 67 enable-active-high; 68 }; 69 70 reg_usdhc2_vmmc: regulator-usdhc2 { 71 compatible = "regulator-fixed"; 72 off-on-delay-us = <12000>; 73 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 74 pinctrl-names = "default"; 75 regulator-max-microvolt = <3300000>; 76 regulator-min-microvolt = <3300000>; 77 regulator-name = "VSD_3V3"; 78 gpio = <&gpio3 7 GPIO_ACTIVE_HIGH>; 79 enable-active-high; 80 }; 81 82 reg_usdhc3_vmmc: regulator-usdhc3 { 83 compatible = "regulator-fixed"; 84 regulator-name = "WLAN_EN"; 85 regulator-min-microvolt = <3300000>; 86 regulator-max-microvolt = <3300000>; 87 vin-supply = <®_m2_pwr>; 88 gpio = <&pcal6524 20 GPIO_ACTIVE_HIGH>; 89 /* 90 * IW612 wifi chip needs more delay than other wifi chips to complete 91 * the host interface initialization after power up, otherwise the 92 * internal state of IW612 may be unstable, resulting in the failure of 93 * the SDIO3.0 switch voltage. 94 */ 95 startup-delay-us = <20000>; 96 enable-active-high; 97 }; 98 99 reserved-memory { 100 ranges; 101 #address-cells = <2>; 102 #size-cells = <2>; 103 104 linux,cma { 105 compatible = "shared-dma-pool"; 106 alloc-ranges = <0 0x80000000 0 0x40000000>; 107 reusable; 108 size = <0 0x10000000>; 109 linux,cma-default; 110 }; 111 }; 112 113 sound-wm8962 { 114 compatible = "fsl,imx-audio-wm8962"; 115 model = "wm8962-audio"; 116 audio-cpu = <&sai3>; 117 audio-codec = <&wm8962>; 118 hp-det-gpio = <&pcal6524 4 GPIO_ACTIVE_HIGH>; 119 audio-routing = 120 "Headphone Jack", "HPOUTL", 121 "Headphone Jack", "HPOUTR", 122 "Ext Spk", "SPKOUTL", 123 "Ext Spk", "SPKOUTR", 124 "AMIC", "MICBIAS", 125 "IN3R", "AMIC", 126 "IN1R", "AMIC"; 127 }; 128 129 sound-bt-sco { 130 compatible = "simple-audio-card"; 131 simple-audio-card,name = "bt-sco-audio"; 132 simple-audio-card,format = "dsp_a"; 133 simple-audio-card,bitclock-inversion; 134 simple-audio-card,frame-master = <&btcpu>; 135 simple-audio-card,bitclock-master = <&btcpu>; 136 137 simple-audio-card,codec { 138 sound-dai = <&bt_sco_codec 1>; 139 }; 140 141 btcpu: simple-audio-card,cpu { 142 sound-dai = <&sai1>; 143 dai-tdm-slot-num = <2>; 144 dai-tdm-slot-width = <16>; 145 }; 146 }; 147 148 sound-micfil { 149 compatible = "fsl,imx-audio-card"; 150 model = "micfil-audio"; 151 152 pri-dai-link { 153 link-name = "micfil hifi"; 154 format = "i2s"; 155 156 cpu { 157 sound-dai = <&micfil>; 158 }; 159 }; 160 }; 161 162 sound-xcvr { 163 compatible = "fsl,imx-audio-card"; 164 model = "imx-audio-xcvr"; 165 166 pri-dai-link { 167 link-name = "XCVR PCM"; 168 169 cpu { 170 sound-dai = <&xcvr>; 171 }; 172 }; 173 }; 174 175 usdhc3_pwrseq: usdhc3_pwrseq { 176 compatible = "mmc-pwrseq-simple"; 177 reset-gpios = <&pcal6524 12 GPIO_ACTIVE_LOW>; 178 }; 179}; 180 181&adc1 { 182 vref-supply = <®_vref_1v8>; 183 status = "okay"; 184}; 185 186&eqos { 187 phy-handle = <ðphy1>; 188 phy-mode = "rgmii-id"; 189 pinctrl-0 = <&pinctrl_eqos>; 190 pinctrl-1 = <&pinctrl_eqos_sleep>; 191 pinctrl-names = "default", "sleep"; 192 status = "okay"; 193 194 mdio { 195 compatible = "snps,dwmac-mdio"; 196 #address-cells = <1>; 197 #size-cells = <0>; 198 clock-frequency = <5000000>; 199 200 ethphy1: ethernet-phy@1 { 201 reg = <1>; 202 realtek,clkout-disable; 203 }; 204 }; 205}; 206 207&fec { 208 phy-handle = <ðphy2>; 209 phy-mode = "rgmii-id"; 210 pinctrl-0 = <&pinctrl_fec>; 211 pinctrl-1 = <&pinctrl_fec_sleep>; 212 pinctrl-names = "default", "sleep"; 213 fsl,magic-packet; 214 status = "okay"; 215 216 mdio { 217 #address-cells = <1>; 218 #size-cells = <0>; 219 clock-frequency = <5000000>; 220 221 ethphy2: ethernet-phy@2 { 222 reg = <2>; 223 realtek,clkout-disable; 224 }; 225 }; 226}; 227 228&lpi2c1 { 229 clock-frequency = <400000>; 230 pinctrl-0 = <&pinctrl_lpi2c1>; 231 pinctrl-names = "default"; 232 status = "okay"; 233 234 wm8962: audio-codec@1a { 235 compatible = "wlf,wm8962"; 236 reg = <0x1a>; 237 clocks = <&clk IMX93_CLK_SAI3_GATE>; 238 AVDD-supply = <®_audio_pwr>; 239 CPVDD-supply = <®_audio_pwr>; 240 DBVDD-supply = <®_audio_pwr>; 241 DCVDD-supply = <®_audio_pwr>; 242 MICVDD-supply = <®_audio_pwr>; 243 PLLVDD-supply = <®_audio_pwr>; 244 SPKVDD1-supply = <®_audio_pwr>; 245 SPKVDD2-supply = <®_audio_pwr>; 246 gpio-cfg = < 247 0x0000 /* 0:Default */ 248 0x0000 /* 1:Default */ 249 0x0000 /* 2:FN_DMICCLK */ 250 0x0000 /* 3:Default */ 251 0x0000 /* 4:FN_DMICCDAT */ 252 0x0000 /* 5:Default */ 253 >; 254 }; 255 256 inertial-meter@6a { 257 compatible = "st,lsm6dso"; 258 reg = <0x6a>; 259 }; 260}; 261 262&lpi2c2 { 263 #address-cells = <1>; 264 #size-cells = <0>; 265 clock-frequency = <400000>; 266 pinctrl-0 = <&pinctrl_lpi2c2>; 267 pinctrl-names = "default"; 268 status = "okay"; 269 270 pcal6524: gpio@22 { 271 compatible = "nxp,pcal6524"; 272 reg = <0x22>; 273 #interrupt-cells = <2>; 274 interrupt-controller; 275 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 276 #gpio-cells = <2>; 277 gpio-controller; 278 interrupt-parent = <&gpio3>; 279 pinctrl-0 = <&pinctrl_pcal6524>; 280 pinctrl-names = "default"; 281 282 m2-pcm-level-shifter-hog { 283 gpio-hog; 284 gpios = <19 GPIO_ACTIVE_HIGH>; 285 output-high; 286 }; 287 }; 288 289 pmic@25 { 290 compatible = "nxp,pca9451a"; 291 reg = <0x25>; 292 interrupts = <11 IRQ_TYPE_EDGE_FALLING>; 293 interrupt-parent = <&pcal6524>; 294 295 regulators { 296 buck1: BUCK1 { 297 regulator-always-on; 298 regulator-boot-on; 299 regulator-max-microvolt = <2237500>; 300 regulator-min-microvolt = <650000>; 301 regulator-name = "BUCK1"; 302 regulator-ramp-delay = <3125>; 303 }; 304 305 buck2: BUCK2 { 306 regulator-always-on; 307 regulator-boot-on; 308 regulator-max-microvolt = <2187500>; 309 regulator-min-microvolt = <600000>; 310 regulator-name = "BUCK2"; 311 regulator-ramp-delay = <3125>; 312 }; 313 314 buck4: BUCK4 { 315 regulator-always-on; 316 regulator-boot-on; 317 regulator-max-microvolt = <3400000>; 318 regulator-min-microvolt = <600000>; 319 regulator-name = "BUCK4"; 320 }; 321 322 buck5: BUCK5 { 323 regulator-always-on; 324 regulator-boot-on; 325 regulator-max-microvolt = <3400000>; 326 regulator-min-microvolt = <600000>; 327 regulator-name = "BUCK5"; 328 }; 329 330 buck6: BUCK6 { 331 regulator-always-on; 332 regulator-boot-on; 333 regulator-max-microvolt = <3400000>; 334 regulator-min-microvolt = <600000>; 335 regulator-name = "BUCK6"; 336 }; 337 338 ldo1: LDO1 { 339 regulator-always-on; 340 regulator-boot-on; 341 regulator-max-microvolt = <3300000>; 342 regulator-min-microvolt = <1600000>; 343 regulator-name = "LDO1"; 344 }; 345 346 ldo4: LDO4 { 347 regulator-always-on; 348 regulator-boot-on; 349 regulator-max-microvolt = <3300000>; 350 regulator-min-microvolt = <800000>; 351 regulator-name = "LDO4"; 352 }; 353 354 ldo5: LDO5 { 355 regulator-always-on; 356 regulator-boot-on; 357 regulator-max-microvolt = <3300000>; 358 regulator-min-microvolt = <1800000>; 359 regulator-name = "LDO5"; 360 }; 361 }; 362 }; 363 364 adp5585: io-expander@34 { 365 compatible = "adi,adp5585-00", "adi,adp5585"; 366 reg = <0x34>; 367 #gpio-cells = <2>; 368 gpio-controller; 369 #pwm-cells = <3>; 370 gpio-reserved-ranges = <5 1>; 371 372 exp-sel-hog { 373 gpio-hog; 374 gpios = <4 GPIO_ACTIVE_HIGH>; 375 output-low; 376 }; 377 }; 378}; 379 380&lpi2c3 { 381 #address-cells = <1>; 382 #size-cells = <0>; 383 clock-frequency = <400000>; 384 pinctrl-0 = <&pinctrl_lpi2c3>; 385 pinctrl-names = "default"; 386 status = "okay"; 387 388 ptn5110: tcpc@50 { 389 compatible = "nxp,ptn5110", "tcpci"; 390 reg = <0x50>; 391 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 392 interrupt-parent = <&gpio3>; 393 394 typec1_con: connector { 395 compatible = "usb-c-connector"; 396 data-role = "dual"; 397 label = "USB-C"; 398 op-sink-microwatt = <15000000>; 399 power-role = "dual"; 400 self-powered; 401 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 402 PDO_VAR(5000, 20000, 3000)>; 403 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 404 try-power-role = "sink"; 405 406 ports { 407 #address-cells = <1>; 408 #size-cells = <0>; 409 410 port@0 { 411 reg = <0>; 412 413 typec1_dr_sw: endpoint { 414 remote-endpoint = <&usb1_drd_sw>; 415 }; 416 }; 417 }; 418 }; 419 }; 420 421 ptn5110_2: tcpc@51 { 422 compatible = "nxp,ptn5110", "tcpci"; 423 reg = <0x51>; 424 interrupts = <27 IRQ_TYPE_LEVEL_LOW>; 425 interrupt-parent = <&gpio3>; 426 status = "okay"; 427 428 typec2_con: connector { 429 compatible = "usb-c-connector"; 430 data-role = "dual"; 431 label = "USB-C"; 432 op-sink-microwatt = <15000000>; 433 power-role = "dual"; 434 self-powered; 435 sink-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM) 436 PDO_VAR(5000, 20000, 3000)>; 437 source-pdos = <PDO_FIXED(5000, 3000, PDO_FIXED_USB_COMM)>; 438 try-power-role = "sink"; 439 440 ports { 441 #address-cells = <1>; 442 #size-cells = <0>; 443 444 port@0 { 445 reg = <0>; 446 447 typec2_dr_sw: endpoint { 448 remote-endpoint = <&usb2_drd_sw>; 449 }; 450 }; 451 }; 452 }; 453 }; 454 455 pcf2131: rtc@53 { 456 compatible = "nxp,pcf2131"; 457 reg = <0x53>; 458 interrupts = <1 IRQ_TYPE_EDGE_FALLING>; 459 interrupt-parent = <&pcal6524>; 460 status = "okay"; 461 }; 462}; 463 464&lpuart1 { 465 pinctrl-0 = <&pinctrl_uart1>; 466 pinctrl-names = "default"; 467 status = "okay"; 468}; 469 470&lpuart5 { 471 pinctrl-0 = <&pinctrl_uart5>; 472 pinctrl-names = "default"; 473 status = "okay"; 474 475 bluetooth { 476 compatible = "nxp,88w8987-bt"; 477 }; 478}; 479 480&micfil { 481 pinctrl-names = "default", "sleep"; 482 pinctrl-0 = <&pinctrl_pdm>; 483 pinctrl-1 = <&pinctrl_pdm_sleep>; 484 assigned-clocks = <&clk IMX93_CLK_PDM>; 485 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 486 assigned-clock-rates = <49152000>; 487 status = "okay"; 488}; 489 490&sai1 { 491 pinctrl-names = "default", "sleep"; 492 pinctrl-0 = <&pinctrl_sai1>; 493 pinctrl-1 = <&pinctrl_sai1_sleep>; 494 assigned-clocks = <&clk IMX93_CLK_SAI1>; 495 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 496 assigned-clock-rates = <12288000>; 497 fsl,sai-mclk-direction-output; 498 status = "okay"; 499}; 500 501&sai3 { 502 pinctrl-names = "default", "sleep"; 503 pinctrl-0 = <&pinctrl_sai3>; 504 pinctrl-1 = <&pinctrl_sai3_sleep>; 505 assigned-clocks = <&clk IMX93_CLK_SAI3>; 506 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>; 507 assigned-clock-rates = <12288000>; 508 fsl,sai-mclk-direction-output; 509 status = "okay"; 510}; 511 512&usbotg1 { 513 adp-disable; 514 disable-over-current; 515 dr_mode = "otg"; 516 hnp-disable; 517 srp-disable; 518 usb-role-switch; 519 samsung,picophy-dc-vol-level-adjust = <7>; 520 samsung,picophy-pre-emp-curr-control = <3>; 521 status = "okay"; 522 523 port { 524 usb1_drd_sw: endpoint { 525 remote-endpoint = <&typec1_dr_sw>; 526 }; 527 }; 528}; 529 530&usbotg2 { 531 adp-disable; 532 disable-over-current; 533 dr_mode = "otg"; 534 hnp-disable; 535 srp-disable; 536 usb-role-switch; 537 samsung,picophy-dc-vol-level-adjust = <7>; 538 samsung,picophy-pre-emp-curr-control = <3>; 539 status = "okay"; 540 541 port { 542 usb2_drd_sw: endpoint { 543 remote-endpoint = <&typec2_dr_sw>; 544 }; 545 }; 546}; 547 548&usdhc1 { 549 bus-width = <8>; 550 non-removable; 551 pinctrl-0 = <&pinctrl_usdhc1>; 552 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 553 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 554 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 555 fsl,tuning-step = <1>; 556 status = "okay"; 557}; 558 559&usdhc2 { 560 bus-width = <4>; 561 cd-gpios = <&gpio3 00 GPIO_ACTIVE_LOW>; 562 no-mmc; 563 no-sdio; 564 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 565 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 566 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 567 pinctrl-3 = <&pinctrl_usdhc2_sleep>, <&pinctrl_usdhc2_gpio_sleep>; 568 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 569 vmmc-supply = <®_usdhc2_vmmc>; 570 fsl,tuning-step = <1>; 571 status = "okay"; 572}; 573 574&usdhc3 { 575 bus-width = <4>; 576 keep-power-in-suspend; 577 mmc-pwrseq = <&usdhc3_pwrseq>; 578 non-removable; 579 pinctrl-0 = <&pinctrl_usdhc3>; 580 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 581 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 582 pinctrl-3 = <&pinctrl_usdhc3_sleep>; 583 pinctrl-names = "default", "state_100mhz", "state_200mhz", "sleep"; 584 vmmc-supply = <®_usdhc3_vmmc>; 585 wakeup-source; 586 status = "okay"; 587}; 588 589&wdog3 { 590 fsl,ext-reset-output; 591 status = "okay"; 592}; 593 594&xcvr { 595 pinctrl-names = "default", "sleep"; 596 pinctrl-0 = <&pinctrl_spdif>; 597 pinctrl-1 = <&pinctrl_spdif_sleep>; 598 assigned-clocks = <&clk IMX93_CLK_SPDIF>, 599 <&clk IMX93_CLK_AUDIO_XCVR>; 600 assigned-clock-parents = <&clk IMX93_CLK_AUDIO_PLL>, 601 <&clk IMX93_CLK_SYS_PLL_PFD1_DIV2>; 602 assigned-clock-rates = <12288000>, <200000000>; 603 status = "okay"; 604}; 605 606&iomuxc { 607 pinctrl_eqos: eqosgrp { 608 fsl,pins = < 609 MX91_PAD_ENET1_MDC__ENET1_MDC 0x57e 610 MX91_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e 611 MX91_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e 612 MX91_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e 613 MX91_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e 614 MX91_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e 615 MX91_PAD_ENET1_RXC__ENET_QOS_RGMII_RXC 0x5fe 616 MX91_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e 617 MX91_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e 618 MX91_PAD_ENET1_TD1__ENET1_RGMII_TD1 0x57e 619 MX91_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e 620 MX91_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e 621 MX91_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x5fe 622 MX91_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e 623 >; 624 }; 625 626 pinctrl_eqos_sleep: eqossleepgrp { 627 fsl,pins = < 628 MX91_PAD_ENET1_MDC__GPIO4_IO0 0x31e 629 MX91_PAD_ENET1_MDIO__GPIO4_IO1 0x31e 630 MX91_PAD_ENET1_RD0__GPIO4_IO10 0x31e 631 MX91_PAD_ENET1_RD1__GPIO4_IO11 0x31e 632 MX91_PAD_ENET1_RD2__GPIO4_IO12 0x31e 633 MX91_PAD_ENET1_RD3__GPIO4_IO13 0x31e 634 MX91_PAD_ENET1_RXC__GPIO4_IO9 0x31e 635 MX91_PAD_ENET1_RX_CTL__GPIO4_IO8 0x31e 636 MX91_PAD_ENET1_TD0__GPIO4_IO5 0x31e 637 MX91_PAD_ENET1_TD1__GPIO4_IO4 0x31e 638 MX91_PAD_ENET1_TD2__GPIO4_IO3 0x31e 639 MX91_PAD_ENET1_TD3__GPIO4_IO2 0x31e 640 MX91_PAD_ENET1_TXC__GPIO4_IO7 0x31e 641 MX91_PAD_ENET1_TX_CTL__GPIO4_IO6 0x31e 642 >; 643 }; 644 645 pinctrl_fec: fecgrp { 646 fsl,pins = < 647 MX91_PAD_ENET2_MDC__ENET2_MDC 0x57e 648 MX91_PAD_ENET2_MDIO__ENET2_MDIO 0x57e 649 MX91_PAD_ENET2_RD0__ENET2_RGMII_RD0 0x57e 650 MX91_PAD_ENET2_RD1__ENET2_RGMII_RD1 0x57e 651 MX91_PAD_ENET2_RD2__ENET2_RGMII_RD2 0x57e 652 MX91_PAD_ENET2_RD3__ENET2_RGMII_RD3 0x57e 653 MX91_PAD_ENET2_RXC__ENET2_RGMII_RXC 0x5fe 654 MX91_PAD_ENET2_RX_CTL__ENET2_RGMII_RX_CTL 0x57e 655 MX91_PAD_ENET2_TD0__ENET2_RGMII_TD0 0x57e 656 MX91_PAD_ENET2_TD1__ENET2_RGMII_TD1 0x57e 657 MX91_PAD_ENET2_TD2__ENET2_RGMII_TD2 0x57e 658 MX91_PAD_ENET2_TD3__ENET2_RGMII_TD3 0x57e 659 MX91_PAD_ENET2_TXC__ENET2_RGMII_TXC 0x5fe 660 MX91_PAD_ENET2_TX_CTL__ENET2_RGMII_TX_CTL 0x57e 661 >; 662 }; 663 664 pinctrl_fec_sleep: fecsleepgrp { 665 fsl,pins = < 666 MX91_PAD_ENET2_MDC__GPIO4_IO14 0x51e 667 MX91_PAD_ENET2_MDIO__GPIO4_IO15 0x51e 668 MX91_PAD_ENET2_RD0__GPIO4_IO24 0x51e 669 MX91_PAD_ENET2_RD1__GPIO4_IO25 0x51e 670 MX91_PAD_ENET2_RD2__GPIO4_IO26 0x51e 671 MX91_PAD_ENET2_RD3__GPIO4_IO27 0x51e 672 MX91_PAD_ENET2_RXC__GPIO4_IO23 0x51e 673 MX91_PAD_ENET2_RX_CTL__GPIO4_IO22 0x51e 674 MX91_PAD_ENET2_TD0__GPIO4_IO19 0x51e 675 MX91_PAD_ENET2_TD1__GPIO4_IO18 0x51e 676 MX91_PAD_ENET2_TD2__GPIO4_IO17 0x51e 677 MX91_PAD_ENET2_TD3__GPIO4_IO16 0x51e 678 MX91_PAD_ENET2_TXC__GPIO4_IO21 0x51e 679 MX91_PAD_ENET2_TX_CTL__GPIO4_IO20 0x51e 680 >; 681 }; 682 683 pinctrl_lpi2c1: lpi2c1grp { 684 fsl,pins = < 685 MX91_PAD_I2C1_SCL__LPI2C1_SCL 0x40000b9e 686 MX91_PAD_I2C1_SDA__LPI2C1_SDA 0x40000b9e 687 >; 688 }; 689 690 pinctrl_lpi2c2: lpi2c2grp { 691 fsl,pins = < 692 MX91_PAD_I2C2_SCL__LPI2C2_SCL 0x40000b9e 693 MX91_PAD_I2C2_SDA__LPI2C2_SDA 0x40000b9e 694 >; 695 }; 696 697 pinctrl_pdm: pdmgrp { 698 fsl,pins = < 699 MX91_PAD_PDM_CLK__PDM_CLK 0x31e 700 MX91_PAD_PDM_BIT_STREAM0__PDM_BIT_STREAM0 0x31e 701 MX91_PAD_PDM_BIT_STREAM1__PDM_BIT_STREAM1 0x31e 702 >; 703 }; 704 705 pinctrl_pdm_sleep: pdmsleepgrp { 706 fsl,pins = < 707 MX91_PAD_PDM_CLK__GPIO1_IO8 0x51e 708 MX91_PAD_PDM_BIT_STREAM0__GPIO1_IO9 0x51e 709 MX91_PAD_PDM_BIT_STREAM1__GPIO1_IO10 0x51e 710 >; 711 }; 712 713 pinctrl_sai1: sai1grp { 714 fsl,pins = < 715 MX91_PAD_SAI1_TXC__SAI1_TX_BCLK 0x31e 716 MX91_PAD_SAI1_TXFS__SAI1_TX_SYNC 0x31e 717 MX91_PAD_SAI1_TXD0__SAI1_TX_DATA0 0x31e 718 MX91_PAD_SAI1_RXD0__SAI1_RX_DATA0 0x31e 719 >; 720 }; 721 722 pinctrl_sai1_sleep: sai1sleepgrp { 723 fsl,pins = < 724 MX91_PAD_SAI1_TXC__GPIO1_IO12 0x51e 725 MX91_PAD_SAI1_TXFS__GPIO1_IO11 0x51e 726 MX91_PAD_SAI1_TXD0__GPIO1_IO13 0x51e 727 MX91_PAD_SAI1_RXD0__GPIO1_IO14 0x51e 728 >; 729 }; 730 731 pinctrl_sai3: sai3grp { 732 fsl,pins = < 733 MX91_PAD_GPIO_IO16__SAI3_TX_BCLK 0x31e 734 MX91_PAD_GPIO_IO17__SAI3_MCLK 0x31e 735 MX91_PAD_GPIO_IO19__SAI3_TX_DATA0 0x31e 736 MX91_PAD_GPIO_IO20__SAI3_RX_DATA0 0x31e 737 MX91_PAD_GPIO_IO26__SAI3_TX_SYNC 0x31e 738 >; 739 }; 740 741 pinctrl_sai3_sleep: sai3sleepgrp { 742 fsl,pins = < 743 MX91_PAD_GPIO_IO16__GPIO2_IO16 0x51e 744 MX91_PAD_GPIO_IO17__GPIO2_IO17 0x51e 745 MX91_PAD_GPIO_IO19__GPIO2_IO19 0x51e 746 MX91_PAD_GPIO_IO20__GPIO2_IO20 0x51e 747 MX91_PAD_GPIO_IO26__GPIO2_IO26 0x51e 748 >; 749 }; 750 751 pinctrl_spdif: spdifgrp { 752 fsl,pins = < 753 MX91_PAD_GPIO_IO22__SPDIF_IN 0x31e 754 MX91_PAD_GPIO_IO23__SPDIF_OUT 0x31e 755 >; 756 }; 757 758 pinctrl_spdif_sleep: spdifsleepgrp { 759 fsl,pins = < 760 MX91_PAD_GPIO_IO22__GPIO2_IO22 0x51e 761 MX91_PAD_GPIO_IO23__GPIO2_IO23 0x51e 762 >; 763 }; 764 765 pinctrl_lpi2c3: lpi2c3grp { 766 fsl,pins = < 767 MX91_PAD_GPIO_IO28__LPI2C3_SDA 0x40000b9e 768 MX91_PAD_GPIO_IO29__LPI2C3_SCL 0x40000b9e 769 >; 770 }; 771 772 pinctrl_pcal6524: pcal6524grp { 773 fsl,pins = < 774 MX91_PAD_CCM_CLKO2__GPIO3_IO27 0x31e 775 >; 776 }; 777 778 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 779 fsl,pins = < 780 MX91_PAD_SD2_RESET_B__GPIO3_IO7 0x31e 781 >; 782 }; 783 784 pinctrl_uart1: uart1grp { 785 fsl,pins = < 786 MX91_PAD_UART1_RXD__LPUART1_RX 0x31e 787 MX91_PAD_UART1_TXD__LPUART1_TX 0x31e 788 >; 789 }; 790 791 pinctrl_uart5: uart5grp { 792 fsl,pins = < 793 MX91_PAD_DAP_TDO_TRACESWO__LPUART5_TX 0x31e 794 MX91_PAD_DAP_TDI__LPUART5_RX 0x31e 795 MX91_PAD_DAP_TMS_SWDIO__LPUART5_RTS_B 0x31e 796 MX91_PAD_DAP_TCLK_SWCLK__LPUART5_CTS_B 0x31e 797 >; 798 }; 799 800 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 801 fsl,pins = < 802 MX91_PAD_SD1_CLK__USDHC1_CLK 0x158e 803 MX91_PAD_SD1_CMD__USDHC1_CMD 0x138e 804 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x138e 805 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x138e 806 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x138e 807 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x138e 808 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x138e 809 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x138e 810 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x138e 811 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x138e 812 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x158e 813 >; 814 }; 815 816 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 817 fsl,pins = < 818 MX91_PAD_SD1_CLK__USDHC1_CLK 0x15fe 819 MX91_PAD_SD1_CMD__USDHC1_CMD 0x13fe 820 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe 821 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe 822 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe 823 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe 824 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe 825 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe 826 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe 827 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe 828 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe 829 >; 830 }; 831 832 pinctrl_usdhc1: usdhc1grp { 833 fsl,pins = < 834 MX91_PAD_SD1_CLK__USDHC1_CLK 0x1582 835 MX91_PAD_SD1_CMD__USDHC1_CMD 0x1382 836 MX91_PAD_SD1_DATA0__USDHC1_DATA0 0x1382 837 MX91_PAD_SD1_DATA1__USDHC1_DATA1 0x1382 838 MX91_PAD_SD1_DATA2__USDHC1_DATA2 0x1382 839 MX91_PAD_SD1_DATA3__USDHC1_DATA3 0x1382 840 MX91_PAD_SD1_DATA4__USDHC1_DATA4 0x1382 841 MX91_PAD_SD1_DATA5__USDHC1_DATA5 0x1382 842 MX91_PAD_SD1_DATA6__USDHC1_DATA6 0x1382 843 MX91_PAD_SD1_DATA7__USDHC1_DATA7 0x1382 844 MX91_PAD_SD1_STROBE__USDHC1_STROBE 0x1582 845 >; 846 }; 847 848 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 849 fsl,pins = < 850 MX91_PAD_SD2_CLK__USDHC2_CLK 0x158e 851 MX91_PAD_SD2_CMD__USDHC2_CMD 0x138e 852 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x138e 853 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x138e 854 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x138e 855 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x138e 856 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 857 >; 858 }; 859 860 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 861 fsl,pins = < 862 MX91_PAD_SD2_CLK__USDHC2_CLK 0x15fe 863 MX91_PAD_SD2_CMD__USDHC2_CMD 0x13fe 864 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x13fe 865 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x13fe 866 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x13fe 867 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x13fe 868 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 869 >; 870 }; 871 872 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 873 fsl,pins = < 874 MX91_PAD_SD2_CD_B__GPIO3_IO0 0x31e 875 >; 876 }; 877 878 pinctrl_usdhc2_gpio_sleep: usdhc2gpiosleepgrp { 879 fsl,pins = < 880 MX91_PAD_SD2_CD_B__GPIO3_IO0 0x51e 881 >; 882 }; 883 884 pinctrl_usdhc2: usdhc2grp { 885 fsl,pins = < 886 MX91_PAD_SD2_CLK__USDHC2_CLK 0x1582 887 MX91_PAD_SD2_CMD__USDHC2_CMD 0x1382 888 MX91_PAD_SD2_DATA0__USDHC2_DATA0 0x1382 889 MX91_PAD_SD2_DATA1__USDHC2_DATA1 0x1382 890 MX91_PAD_SD2_DATA2__USDHC2_DATA2 0x1382 891 MX91_PAD_SD2_DATA3__USDHC2_DATA3 0x1382 892 MX91_PAD_SD2_VSELECT__USDHC2_VSELECT 0x51e 893 >; 894 }; 895 896 pinctrl_usdhc2_sleep: usdhc2sleepgrp { 897 fsl,pins = < 898 MX91_PAD_SD2_CLK__GPIO3_IO1 0x51e 899 MX91_PAD_SD2_CMD__GPIO3_IO2 0x51e 900 MX91_PAD_SD2_DATA0__GPIO3_IO3 0x51e 901 MX91_PAD_SD2_DATA1__GPIO3_IO4 0x51e 902 MX91_PAD_SD2_DATA2__GPIO3_IO5 0x51e 903 MX91_PAD_SD2_DATA3__GPIO3_IO6 0x51e 904 MX91_PAD_SD2_VSELECT__GPIO3_IO19 0x51e 905 >; 906 }; 907 908 pinctrl_usdhc3: usdhc3grp { 909 fsl,pins = < 910 MX91_PAD_SD3_CLK__USDHC3_CLK 0x1582 911 MX91_PAD_SD3_CMD__USDHC3_CMD 0x1382 912 MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x1382 913 MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x1382 914 MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x1382 915 MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x1382 916 >; 917 }; 918 919 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 920 fsl,pins = < 921 MX91_PAD_SD3_CLK__USDHC3_CLK 0x158e 922 MX91_PAD_SD3_CMD__USDHC3_CMD 0x138e 923 MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x138e 924 MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x138e 925 MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x138e 926 MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x138e 927 >; 928 }; 929 930 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 931 fsl,pins = < 932 MX91_PAD_SD3_CLK__USDHC3_CLK 0x15fe 933 MX91_PAD_SD3_CMD__USDHC3_CMD 0x13fe 934 MX91_PAD_SD3_DATA0__USDHC3_DATA0 0x13fe 935 MX91_PAD_SD3_DATA1__USDHC3_DATA1 0x13fe 936 MX91_PAD_SD3_DATA2__USDHC3_DATA2 0x13fe 937 MX91_PAD_SD3_DATA3__USDHC3_DATA3 0x13fe 938 >; 939 }; 940 941 pinctrl_usdhc3_sleep: usdhc3-sleepgrp { 942 fsl,pins = < 943 MX91_PAD_SD3_CLK__GPIO3_IO20 0x31e 944 MX91_PAD_SD3_CMD__GPIO3_IO21 0x31e 945 MX91_PAD_SD3_DATA0__GPIO3_IO22 0x31e 946 MX91_PAD_SD3_DATA1__GPIO3_IO23 0x31e 947 MX91_PAD_SD3_DATA2__GPIO3_IO24 0x31e 948 MX91_PAD_SD3_DATA3__GPIO3_IO25 0x31e 949 >; 950 }; 951}; 952