1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2023 Gateworks Corporation 4 */ 5 6#include <dt-bindings/gpio/gpio.h> 7#include <dt-bindings/leds/common.h> 8#include <dt-bindings/phy/phy-imx8-pcie.h> 9 10/ { 11 connector { 12 compatible = "gpio-usb-b-connector", "usb-b-connector"; 13 pinctrl-names = "default"; 14 pinctrl-0 = <&pinctrl_usbcon1>; 15 type = "micro"; 16 label = "otg"; 17 id-gpios = <&gpio3 21 GPIO_ACTIVE_HIGH>; 18 19 port { 20 usb_dr_connector: endpoint { 21 remote-endpoint = <&usb3_dwc>; 22 }; 23 }; 24 }; 25 26 led-controller { 27 compatible = "gpio-leds"; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&pinctrl_gpio_leds>; 30 31 led-0 { 32 function = LED_FUNCTION_STATUS; 33 color = <LED_COLOR_ID_GREEN>; 34 gpios = <&gpio4 1 GPIO_ACTIVE_HIGH>; 35 default-state = "on"; 36 linux,default-trigger = "heartbeat"; 37 }; 38 39 led-1 { 40 function = LED_FUNCTION_STATUS; 41 color = <LED_COLOR_ID_RED>; 42 gpios = <&gpio4 5 GPIO_ACTIVE_HIGH>; 43 default-state = "off"; 44 }; 45 }; 46 47 pcie0_refclk: clock-pcie0 { 48 compatible = "fixed-clock"; 49 #clock-cells = <0>; 50 clock-frequency = <100000000>; 51 }; 52 53 pps { 54 compatible = "pps-gpio"; 55 pinctrl-names = "default"; 56 pinctrl-0 = <&pinctrl_pps>; 57 gpios = <&gpio4 3 GPIO_ACTIVE_HIGH>; 58 status = "okay"; 59 }; 60 61 reg_usb1_vbus: regulator-usb1 { 62 compatible = "regulator-fixed"; 63 pinctrl-names = "default"; 64 pinctrl-0 = <&pinctrl_reg_usb1_en>; 65 regulator-name = "usb1_vbus"; 66 gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; 67 enable-active-high; 68 regulator-min-microvolt = <5000000>; 69 regulator-max-microvolt = <5000000>; 70 }; 71 72 reg_usb2_vbus: regulator-usb2 { 73 compatible = "regulator-fixed"; 74 pinctrl-names = "default"; 75 pinctrl-0 = <&pinctrl_reg_usb2_en>; 76 regulator-name = "usb2_vbus"; 77 gpio = <&gpio4 12 GPIO_ACTIVE_HIGH>; 78 enable-active-high; 79 regulator-min-microvolt = <5000000>; 80 regulator-max-microvolt = <5000000>; 81 }; 82 83 reg_wifi_en: regulator-wifi-en { 84 compatible = "regulator-fixed"; 85 pinctrl-names = "default"; 86 pinctrl-0 = <&pinctrl_reg_wl>; 87 regulator-name = "wl"; 88 gpio = <&gpio4 19 GPIO_ACTIVE_HIGH>; 89 startup-delay-us = <100>; 90 enable-active-high; 91 regulator-min-microvolt = <3300000>; 92 regulator-max-microvolt = <3300000>; 93 }; 94 95 reg_usdhc2_vmmc: regulator-usdhc2-vmmc { 96 compatible = "regulator-fixed"; 97 pinctrl-names = "default"; 98 pinctrl-0 = <&pinctrl_usdhc2_vmmc>; 99 regulator-name = "VDD_3V3_SD"; 100 enable-active-high; 101 gpio = <&gpio2 19 0>; /* SD2_RESET */ 102 off-on-delay-us = <12000>; 103 regulator-max-microvolt = <3300000>; 104 regulator-min-microvolt = <3300000>; 105 startup-delay-us = <100>; 106 }; 107}; 108 109/* off-board header */ 110&ecspi2 { 111 pinctrl-names = "default"; 112 pinctrl-0 = <&pinctrl_spi2>; 113 cs-gpios = <&gpio5 13 GPIO_ACTIVE_LOW>, 114 <&gpio1 10 GPIO_ACTIVE_LOW>; 115 status = "okay"; 116 117 tpm@1 { 118 compatible = "atmel,attpm20p", "tcg,tpm_tis-spi"; 119 reg = <0x1>; 120 spi-max-frequency = <36000000>; 121 }; 122}; 123 124&gpio4 { 125 gpio-line-names = 126 "", "", "", "", 127 "", "", "", "", 128 "dio1", "", "", "dio0", 129 "", "", "pci_usb_sel", "", 130 "", "", "", "", 131 "", "", "rs485_en", "rs485_term", 132 "", "", "", "rs485_half", 133 "pci_wdis#", "", "", ""; 134}; 135 136&i2c2 { 137 clock-frequency = <400000>; 138 pinctrl-names = "default"; 139 pinctrl-0 = <&pinctrl_i2c2>; 140 status = "okay"; 141 142 accelerometer@19 { 143 compatible = "st,lis2de12"; 144 reg = <0x19>; 145 pinctrl-names = "default"; 146 pinctrl-0 = <&pinctrl_accel>; 147 st,drdy-int-pin = <1>; 148 interrupt-parent = <&gpio4>; 149 interrupts = <21 IRQ_TYPE_LEVEL_LOW>; 150 }; 151}; 152 153&pcie_phy { 154 fsl,refclk-pad-mode = <IMX8_PCIE_REFCLK_PAD_INPUT>; 155 fsl,clkreq-unsupported; 156 clocks = <&pcie0_refclk>; 157 clock-names = "ref"; 158 status = "okay"; 159}; 160 161&pcie { 162 pinctrl-names = "default"; 163 pinctrl-0 = <&pinctrl_pcie0>; 164 reset-gpio = <&gpio4 29 GPIO_ACTIVE_LOW>; 165 status = "okay"; 166}; 167 168/* GPS */ 169&uart1 { 170 pinctrl-names = "default"; 171 pinctrl-0 = <&pinctrl_uart1>; 172 status = "okay"; 173}; 174 175/* bluetooth HCI */ 176&uart3 { 177 pinctrl-names = "default"; 178 pinctrl-0 = <&pinctrl_uart3>, <&pinctrl_bten>; 179 cts-gpios = <&gpio5 8 GPIO_ACTIVE_LOW>; 180 rts-gpios = <&gpio5 9 GPIO_ACTIVE_LOW>; 181 status = "okay"; 182 183 bluetooth { 184 compatible = "brcm,bcm4330-bt"; 185 shutdown-gpios = <&gpio4 16 GPIO_ACTIVE_HIGH>; 186 }; 187}; 188 189/* RS232 */ 190&uart4 { 191 pinctrl-names = "default"; 192 pinctrl-0 = <&pinctrl_uart4>; 193 status = "okay"; 194}; 195 196/* USB1 - OTG */ 197&usb3_0 { 198 pinctrl-names = "default"; 199 pinctrl-0 = <&pinctrl_usb1>; 200 fsl,over-current-active-low; 201 status = "okay"; 202}; 203 204&usb3_phy0 { 205 vbus-supply = <®_usb1_vbus>; 206 status = "okay"; 207}; 208 209&usb_dwc3_0 { 210 /* dual role is implemented but not a full featured OTG */ 211 adp-disable; 212 hnp-disable; 213 srp-disable; 214 dr_mode = "otg"; 215 usb-role-switch; 216 role-switch-default-mode = "peripheral"; 217 status = "okay"; 218 219 port { 220 usb3_dwc: endpoint { 221 remote-endpoint = <&usb_dr_connector>; 222 }; 223 }; 224}; 225 226/* USB2 - USB3.0 Hub */ 227&usb3_1 { 228 fsl,permanently-attached; 229 fsl,disable-port-power-control; 230 status = "okay"; 231}; 232 233&usb3_phy1 { 234 vbus-supply = <®_usb2_vbus>; 235 status = "okay"; 236}; 237 238&usb_dwc3_1 { 239 dr_mode = "host"; 240 status = "okay"; 241}; 242 243/* SDIO WiFi */ 244&usdhc1 { 245 pinctrl-names = "default"; 246 pinctrl-0 = <&pinctrl_usdhc1>; 247 bus-width = <4>; 248 non-removable; 249 vmmc-supply = <®_wifi_en>; 250 status = "okay"; 251}; 252 253/* microSD */ 254&usdhc2 { 255 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 256 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 257 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 258 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 259 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 260 bus-width = <4>; 261 vmmc-supply = <®_usdhc2_vmmc>; 262 status = "okay"; 263}; 264 265&iomuxc { 266 pinctrl-names = "default"; 267 pinctrl-0 = <&pinctrl_hog>; 268 269 pinctrl_hog: hoggrp { 270 fsl,pins = < 271 MX8MP_IOMUXC_SAI1_RXD6__GPIO4_IO08 0x40000146 /* DIO1 */ 272 MX8MP_IOMUXC_SAI1_TXC__GPIO4_IO11 0x40000146 /* DIO0 */ 273 MX8MP_IOMUXC_SAI1_TXD2__GPIO4_IO14 0x40000106 /* PCIE_USBSEL */ 274 MX8MP_IOMUXC_SAI2_MCLK__GPIO4_IO27 0x40000106 /* RS485_HALF */ 275 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x40000106 /* RS485_EN */ 276 MX8MP_IOMUXC_SAI2_RXD0__GPIO4_IO23 0x40000106 /* RS485_TERM */ 277 MX8MP_IOMUXC_SAI3_RXFS__GPIO4_IO28 0x40000106 /* PCIE_WDIS# */ 278 >; 279 }; 280 281 pinctrl_accel: accelgrp { 282 fsl,pins = < 283 MX8MP_IOMUXC_SAI2_RXFS__GPIO4_IO21 0x150 /* IRQ */ 284 >; 285 }; 286 287 pinctrl_bten: btengrp { 288 fsl,pins = < 289 MX8MP_IOMUXC_SAI1_TXD4__GPIO4_IO16 0x146 290 >; 291 }; 292 293 pinctrl_gpio_leds: gpioledgrp { 294 fsl,pins = < 295 MX8MP_IOMUXC_SAI1_RXC__GPIO4_IO01 0x6 /* LEDG */ 296 MX8MP_IOMUXC_SAI1_RXD3__GPIO4_IO05 0x6 /* LEDR */ 297 >; 298 }; 299 300 pinctrl_pcie0: pcie0grp { 301 fsl,pins = < 302 MX8MP_IOMUXC_SAI3_RXC__GPIO4_IO29 0x106 303 >; 304 }; 305 306 pinctrl_pps: ppsgrp { 307 fsl,pins = < 308 MX8MP_IOMUXC_SAI1_RXD1__GPIO4_IO03 0x146 309 >; 310 }; 311 312 pinctrl_reg_wl: regwlgrp { 313 fsl,pins = < 314 MX8MP_IOMUXC_SAI1_TXD7__GPIO4_IO19 0x146 315 >; 316 }; 317 318 pinctrl_reg_usb1_en: regusb1grp { 319 fsl,pins = < 320 MX8MP_IOMUXC_GPIO1_IO12__GPIO1_IO12 0x146 /* USB1_EN */ 321 >; 322 }; 323 324 pinctrl_usb1: usb1grp { 325 fsl,pins = < 326 MX8MP_IOMUXC_GPIO1_IO13__USB1_OTG_OC 0x140 /* USB1_FLT# */ 327 >; 328 }; 329 330 pinctrl_usbcon1: usbcon1grp { 331 fsl,pins = < 332 MX8MP_IOMUXC_SAI5_RXD0__GPIO3_IO21 0x140 /* USB1_ID */ 333 >; 334 }; 335 336 pinctrl_reg_usb2_en: regusb2grp { 337 fsl,pins = < 338 MX8MP_IOMUXC_SAI1_TXD0__GPIO4_IO12 0x146 /* USBHUB_RST# */ 339 >; 340 }; 341 342 pinctrl_spi2: spi2grp { 343 fsl,pins = < 344 MX8MP_IOMUXC_ECSPI2_SCLK__ECSPI2_SCLK 0x140 345 MX8MP_IOMUXC_ECSPI2_MOSI__ECSPI2_MOSI 0x140 346 MX8MP_IOMUXC_ECSPI2_MISO__ECSPI2_MISO 0x140 347 MX8MP_IOMUXC_ECSPI2_SS0__GPIO5_IO13 0x140 348 >; 349 }; 350 351 pinctrl_uart1: uart1grp { 352 fsl,pins = < 353 MX8MP_IOMUXC_UART1_RXD__UART1_DCE_RX 0x140 354 MX8MP_IOMUXC_UART1_TXD__UART1_DCE_TX 0x140 355 >; 356 }; 357 358 pinctrl_uart3: uart3grp { 359 fsl,pins = < 360 MX8MP_IOMUXC_UART3_RXD__UART3_DCE_RX 0x140 361 MX8MP_IOMUXC_UART3_TXD__UART3_DCE_TX 0x140 362 MX8MP_IOMUXC_ECSPI1_MISO__GPIO5_IO08 0x140 363 MX8MP_IOMUXC_ECSPI1_SS0__GPIO5_IO09 0x140 364 >; 365 }; 366 367 pinctrl_uart4: uart4grp { 368 fsl,pins = < 369 MX8MP_IOMUXC_UART4_RXD__UART4_DCE_RX 0x140 370 MX8MP_IOMUXC_UART4_TXD__UART4_DCE_TX 0x140 371 >; 372 }; 373 374 pinctrl_usdhc1: usdhc1grp { 375 fsl,pins = < 376 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 377 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 378 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 379 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 380 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 381 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 382 >; 383 }; 384 385 pinctrl_usdhc2: usdhc2grp { 386 fsl,pins = < 387 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 388 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 389 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 390 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 391 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 392 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 393 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 394 >; 395 }; 396 397 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 398 fsl,pins = < 399 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 400 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 401 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 402 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 403 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 404 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 405 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 406 >; 407 }; 408 409 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 410 fsl,pins = < 411 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 412 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 413 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 414 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 415 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 416 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 417 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc1 418 >; 419 }; 420 421 pinctrl_usdhc2_vmmc: usdhc2-vmmc-grp { 422 fsl,pins = < 423 MX8MP_IOMUXC_SD2_RESET_B__USDHC2_RESET_B 0x1d0 424 >; 425 }; 426 427 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 428 fsl,pins = < 429 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 430 >; 431 }; 432}; 433