1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2019 NXP 4 */ 5 6/dts-v1/; 7 8#include "imx8mp.dtsi" 9 10/ { 11 model = "NXP i.MX8MPlus FRDM board"; 12 compatible = "fsl,imx8mp-frdm", "fsl,imx8mp"; 13 14 chosen { 15 stdout-path = &uart2; 16 }; 17 18 gpio-leds { 19 compatible = "gpio-leds"; 20 21 led-0 { 22 label = "red"; 23 gpios = <&pcal6416_0 13 GPIO_ACTIVE_HIGH>; 24 default-state = "off"; 25 }; 26 27 led-1 { 28 label = "green"; 29 gpios = <&pcal6416_0 14 GPIO_ACTIVE_HIGH>; 30 default-state = "on"; 31 }; 32 33 led-2 { 34 label = "blue"; 35 gpios = <&pcal6416_0 15 GPIO_ACTIVE_HIGH>; 36 default-state = "off"; 37 }; 38 }; 39 40 memory@40000000 { 41 device_type = "memory"; 42 reg = <0x0 0x40000000 0 0xc0000000>, 43 <0x1 0x00000000 0 0x40000000>; 44 }; 45 46 native-hdmi-connector { 47 compatible = "hdmi-connector"; 48 label = "HDMI OUT"; 49 type = "a"; 50 51 port { 52 hdmi_in: endpoint { 53 remote-endpoint = <&hdmi_tx_out>; 54 }; 55 }; 56 }; 57 58 reg_usdhc2_vmmc: regulator-sd { 59 compatible = "regulator-fixed"; 60 pinctrl-names = "default"; 61 pinctrl-0 = <&pinctrl_reg_usdhc2_vmmc>; 62 regulator-name = "VSD_3V3"; 63 regulator-min-microvolt = <3300000>; 64 regulator-max-microvolt = <3300000>; 65 gpio = <&gpio2 19 GPIO_ACTIVE_HIGH>; 66 enable-active-high; 67 }; 68 69 reg_usb_vbus: regulator-vbus { 70 compatible = "regulator-fixed"; 71 regulator-name = "USB_VBUS"; 72 regulator-min-microvolt = <5000000>; 73 regulator-max-microvolt = <5000000>; 74 gpio = <&pcal6416_1 5 GPIO_ACTIVE_HIGH>; 75 enable-active-high; 76 }; 77 78 reg_usdhc1_vmmc: regulator-wifi-vmmc { 79 compatible = "regulator-fixed"; 80 regulator-name = "WLAN_EN"; 81 regulator-min-microvolt = <3300000>; 82 regulator-max-microvolt = <3300000>; 83 gpio = <&pcal6416_1 10 GPIO_ACTIVE_HIGH>; 84 /* 85 * IW612 wifi chip needs more delay than other wifi chips to complete 86 * the host interface initialization after power up, otherwise the 87 * internal state of IW612 may be unstable, resulting in the failure of 88 * the SDIO3.0 switch voltage. 89 */ 90 enable-active-high; 91 startup-delay-us = <20000>; 92 }; 93 94 reg_usdhc1_vqmmc: regulator-wifi-vqmmc { 95 compatible = "regulator-fixed"; 96 regulator-name = "regulator-wifi-vqmmc"; 97 regulator-min-microvolt = <1800000>; 98 regulator-max-microvolt = <1800000>; 99 enable-active-high; 100 }; 101 102 sdio_pwrseq: usdhc1-pwrseq { 103 compatible = "mmc-pwrseq-simple"; 104 reset-gpios = <&gpio2 10 GPIO_ACTIVE_LOW>; 105 }; 106}; 107 108&A53_0 { 109 cpu-supply = <®_arm>; 110}; 111 112&A53_1 { 113 cpu-supply = <®_arm>; 114}; 115 116&A53_2 { 117 cpu-supply = <®_arm>; 118}; 119 120&A53_3 { 121 cpu-supply = <®_arm>; 122}; 123 124&eqos { 125 pinctrl-names = "default"; 126 pinctrl-0 = <&pinctrl_eqos>; 127 phy-mode = "rgmii-id"; 128 phy-handle = <ðphy0>; 129 snps,force_thresh_dma_mode; 130 snps,mtl-tx-config = <&mtl_tx_setup>; 131 snps,mtl-rx-config = <&mtl_rx_setup>; 132 status = "okay"; 133 134 mdio { 135 compatible = "snps,dwmac-mdio"; 136 #address-cells = <1>; 137 #size-cells = <0>; 138 139 ethphy0: ethernet-phy@2 { 140 compatible = "ethernet-phy-ieee802.3-c22"; 141 reg = <2>; 142 pinctrl-names = "default"; 143 pinctrl-0 = <&pinctrl_eqos_phy>; 144 reset-gpios = <&gpio4 22 GPIO_ACTIVE_LOW>; 145 reset-assert-us = <10000>; 146 reset-deassert-us = <80000>; 147 }; 148 }; 149 150 mtl_tx_setup: tx-queues-config { 151 snps,tx-queues-to-use = <5>; 152 153 queue0 { 154 snps,dcb-algorithm; 155 snps,priority = <0x1>; 156 }; 157 158 queue1 { 159 snps,dcb-algorithm; 160 snps,priority = <0x2>; 161 }; 162 163 queue2 { 164 snps,dcb-algorithm; 165 snps,priority = <0x4>; 166 }; 167 168 queue3 { 169 snps,dcb-algorithm; 170 snps,priority = <0x8>; 171 }; 172 173 queue4 { 174 snps,dcb-algorithm; 175 snps,priority = <0xf0>; 176 }; 177 }; 178 179 mtl_rx_setup: rx-queues-config { 180 snps,rx-queues-to-use = <5>; 181 snps,rx-sched-sp; 182 183 queue0 { 184 snps,dcb-algorithm; 185 snps,priority = <0x1>; 186 snps,map-to-dma-channel = <0>; 187 }; 188 189 queue1 { 190 snps,dcb-algorithm; 191 snps,priority = <0x2>; 192 snps,map-to-dma-channel = <1>; 193 }; 194 195 queue2 { 196 snps,dcb-algorithm; 197 snps,priority = <0x4>; 198 snps,map-to-dma-channel = <2>; 199 }; 200 201 queue3 { 202 snps,dcb-algorithm; 203 snps,priority = <0x8>; 204 snps,map-to-dma-channel = <3>; 205 }; 206 207 queue4 { 208 snps,dcb-algorithm; 209 snps,priority = <0xf0>; 210 snps,map-to-dma-channel = <4>; 211 }; 212 }; 213}; 214 215&fec { 216 pinctrl-names = "default"; 217 pinctrl-0 = <&pinctrl_fec>; 218 phy-mode = "rgmii-id"; 219 phy-handle = <ðphy1>; 220 fsl,magic-packet; 221 status = "okay"; 222 223 mdio { 224 #address-cells = <1>; 225 #size-cells = <0>; 226 227 ethphy1: ethernet-phy@1 { 228 compatible = "ethernet-phy-ieee802.3-c22"; 229 reg = <1>; 230 pinctrl-names = "default"; 231 pinctrl-0 = <&pinctrl_fec_phy>; 232 eee-broken-1000t; 233 reset-gpios = <&gpio4 2 GPIO_ACTIVE_LOW>; 234 reset-assert-us = <10000>; 235 reset-deassert-us = <80000>; 236 realtek,aldps-enable; 237 realtek,clkout-disable; 238 }; 239 }; 240}; 241 242&hdmi_pvi { 243 status = "okay"; 244}; 245 246&hdmi_tx { 247 pinctrl-names = "default"; 248 pinctrl-0 = <&pinctrl_hdmi>; 249 status = "okay"; 250 251 ports { 252 port@1 { 253 hdmi_tx_out: endpoint { 254 remote-endpoint = <&hdmi_in>; 255 }; 256 }; 257 }; 258}; 259 260&hdmi_tx_phy { 261 status = "okay"; 262}; 263 264&i2c1 { 265 clock-frequency = <400000>; 266 pinctrl-names = "default"; 267 pinctrl-0 = <&pinctrl_i2c1>; 268 status = "okay"; 269 270 pmic@25 { 271 compatible = "nxp,pca9450c"; 272 reg = <0x25>; 273 pinctrl-names = "default"; 274 pinctrl-0 = <&pinctrl_pmic>; 275 interrupt-parent = <&gpio1>; 276 interrupts = <3 IRQ_TYPE_LEVEL_LOW>; 277 278 regulators { 279 BUCK1 { 280 regulator-name = "BUCK1"; 281 regulator-min-microvolt = <720000>; 282 regulator-max-microvolt = <1000000>; 283 regulator-boot-on; 284 regulator-always-on; 285 regulator-ramp-delay = <3125>; 286 }; 287 288 reg_arm: BUCK2 { 289 regulator-name = "BUCK2"; 290 regulator-min-microvolt = <720000>; 291 regulator-max-microvolt = <1025000>; 292 regulator-boot-on; 293 regulator-always-on; 294 regulator-ramp-delay = <3125>; 295 nxp,dvs-run-voltage = <950000>; 296 nxp,dvs-standby-voltage = <850000>; 297 }; 298 299 BUCK4 { 300 regulator-name = "BUCK4"; 301 regulator-min-microvolt = <3000000>; 302 regulator-max-microvolt = <3600000>; 303 regulator-boot-on; 304 regulator-always-on; 305 }; 306 307 reg_buck5: BUCK5 { 308 regulator-name = "BUCK5"; 309 regulator-min-microvolt = <1650000>; 310 regulator-max-microvolt = <1950000>; 311 regulator-boot-on; 312 regulator-always-on; 313 }; 314 315 BUCK6 { 316 regulator-name = "BUCK6"; 317 regulator-min-microvolt = <1045000>; 318 regulator-max-microvolt = <1155000>; 319 regulator-boot-on; 320 regulator-always-on; 321 }; 322 323 LDO1 { 324 regulator-name = "LDO1"; 325 regulator-min-microvolt = <1650000>; 326 regulator-max-microvolt = <1950000>; 327 regulator-boot-on; 328 regulator-always-on; 329 }; 330 331 LDO3 { 332 regulator-name = "LDO3"; 333 regulator-min-microvolt = <1710000>; 334 regulator-max-microvolt = <1890000>; 335 regulator-boot-on; 336 regulator-always-on; 337 }; 338 339 LDO5 { 340 regulator-name = "LDO5"; 341 regulator-min-microvolt = <1800000>; 342 regulator-max-microvolt = <3300000>; 343 regulator-boot-on; 344 regulator-always-on; 345 }; 346 }; 347 }; 348 349 pcal6416_0: gpio@20 { 350 compatible = "nxp,pcal6416"; 351 reg = <0x20>; 352 gpio-controller; 353 #gpio-cells = <2>; 354 interrupt-controller; 355 #interrupt-cells = <2>; 356 pinctrl-names = "default"; 357 pinctrl-0 = <&pinctrl_pcal6416_0_int>; 358 interrupt-parent = <&gpio3>; 359 interrupts = <16 IRQ_TYPE_LEVEL_LOW>; 360 gpio-line-names = "CSI1_nRST", 361 "CSI2_nRST", 362 "DSI_CTP_RST", 363 "EXT_PWREN1", 364 "CAN_STBY", 365 "EXP_P0_5", 366 "EXP_P0_6", 367 "P0_7", 368 "LVDS0_BLT_EN", 369 "LVDS1_BLT_EN", 370 "LVDS0_CTP_RST", 371 "LVDS1_CTP_RST", 372 "SPK_PWREN", 373 "RLED_GPIO", 374 "GLED_GPIO", 375 "BLED_GPIO"; 376 }; 377 378 pcal6416_1: gpio@21 { 379 compatible = "nxp,pcal6416"; 380 reg = <0x21>; 381 gpio-controller; 382 #gpio-cells = <2>; 383 interrupt-controller; 384 #interrupt-cells = <2>; 385 pinctrl-names = "default"; 386 pinctrl-0 = <&pinctrl_pcal6416_1_int>; 387 interrupt-parent = <&gpio2>; 388 interrupts = <11 IRQ_TYPE_LEVEL_LOW>; 389 gpio-line-names = "P0_0", 390 "P0_1", 391 "AUD_nINT", 392 "RTC_nINTA", 393 "USB1_SS_SEL", 394 "USB2_PWR_EN", 395 "SPI_EXP_SEL", 396 "P0_7", 397 "W2_HOST_WAKE_SD_3V3", 398 "W2_HOST_WAKE_BT_3V3", 399 "EXP_WIFI_BT_PDN_3V3", 400 "EXP_BT_RST_3V3", 401 "W2_RST_IND_3V3", 402 "SPI_nINT_3V3", 403 "KEYM_PCIE_nWAKE", 404 "P1_7"; 405 }; 406}; 407 408&i2c2 { 409 clock-frequency = <400000>; 410 pinctrl-names = "default"; 411 pinctrl-0 = <&pinctrl_i2c2>; 412 status = "okay"; 413}; 414 415&i2c3 { 416 clock-frequency = <400000>; 417 pinctrl-names = "default"; 418 pinctrl-0 = <&pinctrl_i2c3>; 419 status = "okay"; 420}; 421 422&lcdif3 { 423 status = "okay"; 424}; 425 426&snvs_pwrkey { 427 status = "okay"; 428}; 429 430&uart2 { 431 pinctrl-names = "default"; 432 pinctrl-0 = <&pinctrl_uart2>; 433 status = "okay"; 434}; 435 436&uart3 { 437 pinctrl-names = "default"; 438 pinctrl-0 = <&pinctrl_uart3>; 439 assigned-clocks = <&clk IMX8MP_CLK_UART3>; 440 assigned-clock-parents = <&clk IMX8MP_SYS_PLL1_80M>; 441 uart-has-rtscts; 442 status = "okay"; 443}; 444 445&usb3_0 { 446 status = "okay"; 447}; 448 449&usb3_1 { 450 status = "okay"; 451}; 452 453&usb3_phy0 { 454 status = "okay"; 455}; 456 457&usb3_phy1 { 458 vbus-supply = <®_usb_vbus>; 459 status = "okay"; 460}; 461 462&usb_dwc3_1 { 463 dr_mode = "host"; 464 status = "okay"; 465}; 466 467&usdhc1 { 468 assigned-clocks = <&clk IMX8MP_CLK_USDHC1>; 469 assigned-clock-rates = <200000000>; 470 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 471 pinctrl-0 = <&pinctrl_usdhc1>; 472 pinctrl-1 = <&pinctrl_usdhc1_100mhz>; 473 pinctrl-2 = <&pinctrl_usdhc1_200mhz>; 474 mmc-pwrseq = <&sdio_pwrseq>; 475 vmmc-supply = <®_usdhc1_vmmc>; 476 vqmmc-supply = <®_usdhc1_vqmmc>; 477 bus-width = <4>; 478 non-removable; 479 no-sd; 480 no-mmc; 481 status = "okay"; 482}; 483 484&usdhc2 { 485 assigned-clocks = <&clk IMX8MP_CLK_USDHC2>; 486 assigned-clock-rates = <400000000>; 487 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 488 pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; 489 pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; 490 pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; 491 cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; 492 vmmc-supply = <®_usdhc2_vmmc>; 493 bus-width = <4>; 494 status = "okay"; 495}; 496 497&usdhc3 { 498 assigned-clocks = <&clk IMX8MP_CLK_USDHC3>; 499 assigned-clock-rates = <400000000>; 500 pinctrl-names = "default", "state_100mhz", "state_200mhz"; 501 pinctrl-0 = <&pinctrl_usdhc3>; 502 pinctrl-1 = <&pinctrl_usdhc3_100mhz>; 503 pinctrl-2 = <&pinctrl_usdhc3_200mhz>; 504 bus-width = <8>; 505 non-removable; 506 status = "okay"; 507}; 508 509&iomuxc { 510 pinctrl-names = "default"; 511 pinctrl-0 = <&pinctrl_hog>; 512 513 pinctrl_eqos: eqosgrp { 514 fsl,pins = < 515 MX8MP_IOMUXC_ENET_MDC__ENET_QOS_MDC 0x2 516 MX8MP_IOMUXC_ENET_MDIO__ENET_QOS_MDIO 0x2 517 MX8MP_IOMUXC_ENET_RD0__ENET_QOS_RGMII_RD0 0x90 518 MX8MP_IOMUXC_ENET_RD1__ENET_QOS_RGMII_RD1 0x90 519 MX8MP_IOMUXC_ENET_RD2__ENET_QOS_RGMII_RD2 0x90 520 MX8MP_IOMUXC_ENET_RD3__ENET_QOS_RGMII_RD3 0x90 521 MX8MP_IOMUXC_ENET_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x90 522 MX8MP_IOMUXC_ENET_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x90 523 MX8MP_IOMUXC_ENET_TD0__ENET_QOS_RGMII_TD0 0x16 524 MX8MP_IOMUXC_ENET_TD1__ENET_QOS_RGMII_TD1 0x16 525 MX8MP_IOMUXC_ENET_TD2__ENET_QOS_RGMII_TD2 0x16 526 MX8MP_IOMUXC_ENET_TD3__ENET_QOS_RGMII_TD3 0x16 527 MX8MP_IOMUXC_ENET_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x16 528 MX8MP_IOMUXC_ENET_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x16 529 >; 530 }; 531 532 pinctrl_eqos_phy: eqosphygrp { 533 fsl,pins = < 534 MX8MP_IOMUXC_SAI2_RXC__GPIO4_IO22 0x10 535 >; 536 }; 537 538 pinctrl_fec: fecgrp { 539 fsl,pins = < 540 MX8MP_IOMUXC_SAI1_RXD2__ENET1_MDC 0x2 541 MX8MP_IOMUXC_SAI1_RXD3__ENET1_MDIO 0x2 542 MX8MP_IOMUXC_SAI1_RXD4__ENET1_RGMII_RD0 0x90 543 MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x90 544 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x90 545 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x90 546 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x90 547 MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x90 548 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x16 549 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x16 550 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x16 551 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x16 552 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x16 553 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x16 554 >; 555 }; 556 557 pinctrl_fec_phy: fecphygrp { 558 fsl,pins = < 559 MX8MP_IOMUXC_SAI1_RXD0__GPIO4_IO02 0x10 560 >; 561 }; 562 563 pinctrl_hdmi: hdmigrp { 564 fsl,pins = < 565 MX8MP_IOMUXC_HDMI_CEC__HDMIMIX_HDMI_CEC 0x10 566 >; 567 }; 568 569 pinctrl_hog: hoggrp { 570 fsl,pins = < 571 /* Pin might be required by multiple drivers 572 * (e. g. HDMI Audio and HDMI TX) 573 */ 574 MX8MP_IOMUXC_HDMI_HPD__HDMIMIX_HDMI_HPD 0x40000010 575 >; 576 }; 577 578 pinctrl_i2c1: i2c1grp { 579 fsl,pins = < 580 MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) 581 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) 582 >; 583 }; 584 585 pinctrl_i2c2: i2c2grp { 586 fsl,pins = < 587 MX8MP_IOMUXC_I2C2_SCL__I2C2_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) 588 MX8MP_IOMUXC_I2C2_SDA__I2C2_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) 589 >; 590 }; 591 592 pinctrl_i2c3: i2c3grp { 593 fsl,pins = < 594 MX8MP_IOMUXC_I2C3_SCL__I2C3_SCL (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) 595 MX8MP_IOMUXC_I2C3_SDA__I2C3_SDA (MX8MP_DSE_X4 | MX8MP_I2C_DEFAULT) 596 >; 597 }; 598 599 pinctrl_pmic: pmicgrp { 600 fsl,pins = < 601 MX8MP_IOMUXC_GPIO1_IO03__GPIO1_IO03 602 (MX8MP_PULL_UP | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 603 >; 604 }; 605 606 pinctrl_pcal6416_0_int: pcal6416-0-int-grp { 607 fsl,pins = < 608 MX8MP_IOMUXC_NAND_READY_B__GPIO3_IO16 609 (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 610 >; 611 }; 612 613 pinctrl_pcal6416_1_int: pcal6416-1-int-grp { 614 fsl,pins = < 615 MX8MP_IOMUXC_SD1_STROBE__GPIO2_IO11 616 (MX8MP_DSE_X6 | MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 617 618 >; 619 }; 620 621 pinctrl_reg_usdhc2_vmmc: regusdhc2vmmcgrp { 622 fsl,pins = < 623 MX8MP_IOMUXC_SD2_RESET_B__GPIO2_IO19 0x40 624 >; 625 }; 626 627 pinctrl_uart2: uart2grp { 628 fsl,pins = < 629 MX8MP_IOMUXC_UART2_RXD__UART2_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 630 MX8MP_IOMUXC_UART2_TXD__UART2_DCE_TX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 631 632 >; 633 }; 634 635 pinctrl_uart3: uart3grp { 636 fsl,pins = < 637 MX8MP_IOMUXC_ECSPI1_SCLK__UART3_DCE_RX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 638 MX8MP_IOMUXC_ECSPI1_MOSI__UART3_DCE_TX (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 639 MX8MP_IOMUXC_ECSPI1_SS0__UART3_DCE_RTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 640 MX8MP_IOMUXC_ECSPI1_MISO__UART3_DCE_CTS (MX8MP_PULL_UP | MX8MP_PULL_ENABLE) 641 >; 642 }; 643 644 pinctrl_usdhc1: usdhc1grp { 645 fsl,pins = < 646 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x190 647 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d0 648 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d0 649 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d0 650 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d0 651 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d0 652 >; 653 }; 654 655 pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { 656 fsl,pins = < 657 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x194 658 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d4 659 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d4 660 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d4 661 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d4 662 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d4 663 >; 664 }; 665 666 pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { 667 fsl,pins = < 668 MX8MP_IOMUXC_SD1_CLK__USDHC1_CLK 0x196 669 MX8MP_IOMUXC_SD1_CMD__USDHC1_CMD 0x1d6 670 MX8MP_IOMUXC_SD1_DATA0__USDHC1_DATA0 0x1d6 671 MX8MP_IOMUXC_SD1_DATA1__USDHC1_DATA1 0x1d6 672 MX8MP_IOMUXC_SD1_DATA2__USDHC1_DATA2 0x1d6 673 MX8MP_IOMUXC_SD1_DATA3__USDHC1_DATA3 0x1d6 674 >; 675 }; 676 677 pinctrl_usdhc2: usdhc2grp { 678 fsl,pins = < 679 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x190 680 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d0 681 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d0 682 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d0 683 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d0 684 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d0 685 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 686 >; 687 }; 688 689 pinctrl_usdhc2_100mhz: usdhc2-100mhzgrp { 690 fsl,pins = < 691 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x194 692 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d4 693 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d4 694 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d4 695 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d4 696 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d4 697 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 698 >; 699 }; 700 701 pinctrl_usdhc2_200mhz: usdhc2-200mhzgrp { 702 fsl,pins = < 703 MX8MP_IOMUXC_SD2_CLK__USDHC2_CLK 0x196 704 MX8MP_IOMUXC_SD2_CMD__USDHC2_CMD 0x1d6 705 MX8MP_IOMUXC_SD2_DATA0__USDHC2_DATA0 0x1d6 706 MX8MP_IOMUXC_SD2_DATA1__USDHC2_DATA1 0x1d6 707 MX8MP_IOMUXC_SD2_DATA2__USDHC2_DATA2 0x1d6 708 MX8MP_IOMUXC_SD2_DATA3__USDHC2_DATA3 0x1d6 709 MX8MP_IOMUXC_GPIO1_IO04__USDHC2_VSELECT 0xc0 710 >; 711 }; 712 713 pinctrl_usdhc2_gpio: usdhc2gpiogrp { 714 fsl,pins = < 715 MX8MP_IOMUXC_SD2_CD_B__GPIO2_IO12 0x1c4 716 >; 717 }; 718 719 pinctrl_usdhc3: usdhc3grp { 720 fsl,pins = < 721 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 722 (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 723 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 724 (MX8MP_FSEL_FAST | MX8MP_PULL_UP | 725 MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 726 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 MX8MP_USDHC_DATA_DEFAULT 727 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 MX8MP_USDHC_DATA_DEFAULT 728 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 MX8MP_USDHC_DATA_DEFAULT 729 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 MX8MP_USDHC_DATA_DEFAULT 730 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 MX8MP_USDHC_DATA_DEFAULT 731 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 MX8MP_USDHC_DATA_DEFAULT 732 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 MX8MP_USDHC_DATA_DEFAULT 733 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 MX8MP_USDHC_DATA_DEFAULT 734 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 735 (MX8MP_FSEL_FAST | MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 736 >; 737 }; 738 739 pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { 740 fsl,pins = < 741 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 742 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | 743 MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 744 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 745 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 746 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 747 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 748 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 749 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 750 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 751 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 752 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 753 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 754 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 755 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 756 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 757 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 758 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 759 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 760 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 761 (MX8MP_DSE_X2 | MX8MP_USDHC_DATA_DEFAULT) 762 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 763 (MX8MP_DSE_X2 | MX8MP_FSEL_FAST | 764 MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 765 >; 766 }; 767 768 pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { 769 fsl,pins = < 770 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 771 (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | 772 MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 773 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 774 (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | MX8MP_PULL_UP | 775 MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 776 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 777 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 778 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 779 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 780 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 781 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 782 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 783 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 784 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 785 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 786 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 787 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 788 MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 789 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 790 MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 791 (MX8MP_DSE_X6 | MX8MP_USDHC_DATA_DEFAULT) 792 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 793 (MX8MP_DSE_X6 | MX8MP_FSEL_FAST | 794 MX8MP_HYS_SCHMITT | MX8MP_PULL_ENABLE) 795 >; 796 }; 797}; 798