1// SPDX-License-Identifier: (GPL-2.0+ OR MIT) 2/* 3 * Copyright 2021 BSH 4 */ 5 6/ { 7 backlight: backlight { 8 compatible = "pwm-backlight"; 9 pwms = <&pwm1 0 700000 0>; /* 700000 ns = 1337Hz */ 10 brightness-levels = <0 100>; 11 num-interpolated-steps = <100>; 12 default-brightness-level = <50>; 13 status = "okay"; 14 }; 15 16 reg_3v3_dvdd: regulator-3v3-O3 { 17 compatible = "regulator-fixed"; 18 pinctrl-names = "default"; 19 pinctrl-0 = <&pinctrl_dvdd>; 20 regulator-name = "3v3-dvdd-supply"; 21 regulator-min-microvolt = <3300000>; 22 regulator-max-microvolt = <3300000>; 23 gpio = <&gpio1 7 GPIO_ACTIVE_LOW>; 24 }; 25 26 reg_v3v3_avdd: regulator-3v3-O2 { 27 compatible = "regulator-fixed"; 28 pinctrl-names = "default"; 29 pinctrl-0 = <&pinctrl_avdd>; 30 regulator-name = "3v3-avdd-supply"; 31 regulator-min-microvolt = <3300000>; 32 regulator-max-microvolt = <3300000>; 33 gpio = <&gpio1 5 GPIO_ACTIVE_LOW>; 34 }; 35}; 36 37&pwm1 { 38 pinctrl-names = "default"; 39 pinctrl-0 = <&pinctrl_bl>; 40 status = "okay"; 41}; 42 43&lcdif { 44 assigned-clocks = <&clk IMX8MN_VIDEO_PLL1>; 45 assigned-clock-rates = <594000000>; 46 status = "okay"; 47}; 48 49&pgc_dispmix { 50 assigned-clocks = <&clk IMX8MN_CLK_DISP_AXI>, <&clk IMX8MN_CLK_DISP_APB>; 51 assigned-clock-parents = <&clk IMX8MN_SYS_PLL2_1000M>, <&clk IMX8MN_SYS_PLL1_800M>; 52 assigned-clock-rates = <500000000>, <200000000>; 53}; 54 55&mipi_dsi { 56 #address-cells = <1>; 57 #size-cells = <0>; 58 samsung,esc-clock-frequency = <20000000>; 59 samsung,pll-clock-frequency = <12000000>; 60 status = "okay"; 61 62 panel@0 { 63 compatible = "sharp,ls068b3sx02", "syna,r63353"; 64 pinctrl-names = "default"; 65 pinctrl-0 = <&pinctrl_panel>; 66 reg = <0>; 67 68 backlight = <&backlight>; 69 dvdd-supply = <®_3v3_dvdd>; 70 avdd-supply = <®_v3v3_avdd>; 71 reset-gpios = <&gpio4 29 GPIO_ACTIVE_HIGH>; 72 73 port { 74 panel_in: endpoint { 75 remote-endpoint = <&mipi_dsi_out>; 76 }; 77 }; 78 79 }; 80 81 ports { 82 port@1 { 83 reg = <1>; 84 85 mipi_dsi_out: endpoint { 86 remote-endpoint = <&panel_in>; 87 }; 88 }; 89 }; 90}; 91 92&gpu { 93 status = "okay"; 94}; 95 96&iomuxc { 97 pinctrl_avdd: avddgrp { 98 fsl,pins = < 99 MX8MN_IOMUXC_GPIO1_IO05_GPIO1_IO5 0x16 /* VDD 3V3_VO2 */ 100 >; 101 }; 102 103 /* This is for both PWM and voltage regulators for display */ 104 pinctrl_bl: blgrp { 105 fsl,pins = < 106 MX8MN_IOMUXC_GPIO1_IO01_PWM1_OUT 0x16 107 >; 108 }; 109 110 pinctrl_dvdd: dvddgrp { 111 fsl,pins = < 112 MX8MN_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x16 /* VDD 3V3_VO3 */ 113 >; 114 }; 115 116 pinctrl_panel: panelgrp { 117 fsl,pins = < 118 MX8MN_IOMUXC_SAI3_RXC_GPIO4_IO29 0x16 /* panel reset */ 119 >; 120 }; 121}; 122