12846c905SEmmanuel Vadot// SPDX-License-Identifier: GPL-2.0+ 22846c905SEmmanuel Vadot/* 32846c905SEmmanuel Vadot * Copyright (c) 2024 Blaize, Inc. All rights reserved. 42846c905SEmmanuel Vadot */ 52846c905SEmmanuel Vadot 62846c905SEmmanuel Vadot/dts-v1/; 72846c905SEmmanuel Vadot 82846c905SEmmanuel Vadot#include "blaize-blzp1600-som.dtsi" 92846c905SEmmanuel Vadot 102846c905SEmmanuel Vadot/ { 112846c905SEmmanuel Vadot model = "Blaize BLZP1600 SoM1600P CB2 Development Board"; 122846c905SEmmanuel Vadot 132846c905SEmmanuel Vadot compatible = "blaize,blzp1600-cb2", "blaize,blzp1600"; 142846c905SEmmanuel Vadot 152846c905SEmmanuel Vadot aliases { 162846c905SEmmanuel Vadot serial0 = &uart0; 172846c905SEmmanuel Vadot }; 182846c905SEmmanuel Vadot 192846c905SEmmanuel Vadot chosen { 202846c905SEmmanuel Vadot stdout-path = "serial0:115200"; 212846c905SEmmanuel Vadot }; 222846c905SEmmanuel Vadot}; 232846c905SEmmanuel Vadot 242846c905SEmmanuel Vadot&i2c0 { 252846c905SEmmanuel Vadot clock-frequency = <100000>; 262846c905SEmmanuel Vadot status = "okay"; 272846c905SEmmanuel Vadot}; 282846c905SEmmanuel Vadot 292846c905SEmmanuel Vadot&i2c1 { 302846c905SEmmanuel Vadot clock-frequency = <100000>; 312846c905SEmmanuel Vadot status = "okay"; 322846c905SEmmanuel Vadot}; 332846c905SEmmanuel Vadot 342846c905SEmmanuel Vadot&i2c3 { 352846c905SEmmanuel Vadot clock-frequency = <100000>; 362846c905SEmmanuel Vadot status = "okay"; 372846c905SEmmanuel Vadot 382846c905SEmmanuel Vadot gpio_expander: gpio@74 { 392846c905SEmmanuel Vadot compatible = "ti,tca9539"; 402846c905SEmmanuel Vadot reg = <0x74>; 412846c905SEmmanuel Vadot gpio-controller; 422846c905SEmmanuel Vadot #gpio-cells = <2>; 432846c905SEmmanuel Vadot gpio-line-names = "RSP_PIN_7", /* GPIO_0 */ 442846c905SEmmanuel Vadot "RSP_PIN_11", /* GPIO_1 */ 452846c905SEmmanuel Vadot "RSP_PIN_13", /* GPIO_2 */ 462846c905SEmmanuel Vadot "RSP_PIN_15", /* GPIO_3 */ 472846c905SEmmanuel Vadot "RSP_PIN_27", /* GPIO_4 */ 482846c905SEmmanuel Vadot "RSP_PIN_29", /* GPIO_5 */ 492846c905SEmmanuel Vadot "RSP_PIN_31", /* GPIO_6 */ 502846c905SEmmanuel Vadot "RSP_PIN_33", /* GPIO_7 */ 512846c905SEmmanuel Vadot "RSP_PIN_37", /* GPIO_8 */ 522846c905SEmmanuel Vadot "RSP_PIN_16", /* GPIO_9 */ 532846c905SEmmanuel Vadot "RSP_PIN_18", /* GPIO_10 */ 542846c905SEmmanuel Vadot "RSP_PIN_22", /* GPIO_11 */ 552846c905SEmmanuel Vadot "RSP_PIN_28", /* GPIO_12 */ 562846c905SEmmanuel Vadot "RSP_PIN_32", /* GPIO_13 */ 572846c905SEmmanuel Vadot "RSP_PIN_36", /* GPIO_14 */ 582846c905SEmmanuel Vadot "TP31"; /* GPIO_15 */ 592846c905SEmmanuel Vadot }; 602846c905SEmmanuel Vadot 612846c905SEmmanuel Vadot gpio_expander_m2: gpio@75 { 622846c905SEmmanuel Vadot compatible = "ti,tca9539"; 632846c905SEmmanuel Vadot reg = <0x75>; 642846c905SEmmanuel Vadot gpio-controller; 652846c905SEmmanuel Vadot #gpio-cells = <2>; 662846c905SEmmanuel Vadot gpio-line-names = "M2_W_DIS1_N", /* GPIO_0 */ 672846c905SEmmanuel Vadot "M2_W_DIS2_N", /* GPIO_1 */ 682846c905SEmmanuel Vadot "M2_UART_WAKE_N", /* GPIO_2 */ 692846c905SEmmanuel Vadot "M2_COEX3", /* GPIO_3 */ 702846c905SEmmanuel Vadot "M2_COEX_RXD", /* GPIO_4 */ 712846c905SEmmanuel Vadot "M2_COEX_TXD", /* GPIO_5 */ 722846c905SEmmanuel Vadot "M2_VENDOR_PIN40", /* GPIO_6 */ 732846c905SEmmanuel Vadot "M2_VENDOR_PIN42", /* GPIO_7 */ 742846c905SEmmanuel Vadot "M2_VENDOR_PIN38", /* GPIO_8 */ 752846c905SEmmanuel Vadot "M2_SDIO_RST_N", /* GPIO_9 */ 762846c905SEmmanuel Vadot "M2_SDIO_WAKE_N", /* GPIO_10 */ 772846c905SEmmanuel Vadot "M2_PETN1", /* GPIO_11 */ 782846c905SEmmanuel Vadot "M2_PERP1", /* GPIO_12 */ 792846c905SEmmanuel Vadot "M2_PERN1", /* GPIO_13 */ 802846c905SEmmanuel Vadot "UIM_SWP", /* GPIO_14 */ 812846c905SEmmanuel Vadot "UART1_TO_RSP"; /* GPIO_15 */ 822846c905SEmmanuel Vadot }; 832846c905SEmmanuel Vadot}; 84*ae5de77eSEmmanuel Vadot 85*ae5de77eSEmmanuel Vadot&gpio0 { 86*ae5de77eSEmmanuel Vadot status = "okay"; 87*ae5de77eSEmmanuel Vadot gpio-line-names = "PERST_N", /* GPIO_0 */ 88*ae5de77eSEmmanuel Vadot "LM96063_ALERT_N", /* GPIO_1 */ 89*ae5de77eSEmmanuel Vadot "INA3221_PV", /* GPIO_2 */ 90*ae5de77eSEmmanuel Vadot "INA3221_CRIT", /* GPIO_3 */ 91*ae5de77eSEmmanuel Vadot "INA3221_WARN", /* GPIO_4 */ 92*ae5de77eSEmmanuel Vadot "INA3221_TC", /* GPIO_5 */ 93*ae5de77eSEmmanuel Vadot "QSPI0_RST_N", /* GPIO_6 */ 94*ae5de77eSEmmanuel Vadot "LM96063_TCRIT_N", /* GPIO_7 */ 95*ae5de77eSEmmanuel Vadot "DSI_TCH_INT", /* GPIO_8 */ 96*ae5de77eSEmmanuel Vadot "DSI_RST", /* GPIO_9 */ 97*ae5de77eSEmmanuel Vadot "DSI_BL", /* GPIO_10 */ 98*ae5de77eSEmmanuel Vadot "DSI_INT", /* GPIO_11 */ 99*ae5de77eSEmmanuel Vadot "ETH_RST", /* GPIO_12 */ 100*ae5de77eSEmmanuel Vadot "CSI0_RST", /* GPIO_13 */ 101*ae5de77eSEmmanuel Vadot "CSI0_PWDN", /* GPIO_14 */ 102*ae5de77eSEmmanuel Vadot "CSI1_RST", /* GPIO_15 */ 103*ae5de77eSEmmanuel Vadot "CSI1_PWDN", /* GPIO_16 */ 104*ae5de77eSEmmanuel Vadot "CSI2_RST", /* GPIO_17 */ 105*ae5de77eSEmmanuel Vadot "CSI2_PWDN", /* GPIO_18 */ 106*ae5de77eSEmmanuel Vadot "CSI3_RST", /* GPIO_19 */ 107*ae5de77eSEmmanuel Vadot "CSI3_PWDN", /* GPIO_20 */ 108*ae5de77eSEmmanuel Vadot "ADAC_RST", /* GPIO_21 */ 109*ae5de77eSEmmanuel Vadot "SD_SW_VDD", /* GPIO_22 */ 110*ae5de77eSEmmanuel Vadot "SD_PON_VDD", /* GPIO_23 */ 111*ae5de77eSEmmanuel Vadot "GPIO_EXP_INT", /* GPIO_24 */ 112*ae5de77eSEmmanuel Vadot "BOARD_ID_0", /* GPIO_25 */ 113*ae5de77eSEmmanuel Vadot "SDIO1_SW_VDD", /* GPIO_26 */ 114*ae5de77eSEmmanuel Vadot "SDIO1_PON_VDD", /* GPIO_27 */ 115*ae5de77eSEmmanuel Vadot "SDIO2_SW_VDD", /* GPIO_28 */ 116*ae5de77eSEmmanuel Vadot "SDIO2_PON_VDD", /* GPIO_29 */ 117*ae5de77eSEmmanuel Vadot "BOARD_ID_1", /* GPIO_30 */ 118*ae5de77eSEmmanuel Vadot "BOARD_ID_2"; /* GPIO_31 */ 119*ae5de77eSEmmanuel Vadot}; 120