1*c66ec88fSEmmanuel Vadot /* SPDX-License-Identifier: GPL-2.0-only */ 2*c66ec88fSEmmanuel Vadot /* 3*c66ec88fSEmmanuel Vadot * Copyright (C) 2019 Glider bvba 4*c66ec88fSEmmanuel Vadot */ 5*c66ec88fSEmmanuel Vadot #ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__ 6*c66ec88fSEmmanuel Vadot #define __DT_BINDINGS_POWER_R8A77961_SYSC_H__ 7*c66ec88fSEmmanuel Vadot 8*c66ec88fSEmmanuel Vadot /* 9*c66ec88fSEmmanuel Vadot * These power domain indices match the numbers of the interrupt bits 10*c66ec88fSEmmanuel Vadot * representing the power areas in the various Interrupt Registers 11*c66ec88fSEmmanuel Vadot * (e.g. SYSCISR, Interrupt Status Register) 12*c66ec88fSEmmanuel Vadot */ 13*c66ec88fSEmmanuel Vadot 14*c66ec88fSEmmanuel Vadot #define R8A77961_PD_CA57_CPU0 0 15*c66ec88fSEmmanuel Vadot #define R8A77961_PD_CA57_CPU1 1 16*c66ec88fSEmmanuel Vadot #define R8A77961_PD_CA53_CPU0 5 17*c66ec88fSEmmanuel Vadot #define R8A77961_PD_CA53_CPU1 6 18*c66ec88fSEmmanuel Vadot #define R8A77961_PD_CA53_CPU2 7 19*c66ec88fSEmmanuel Vadot #define R8A77961_PD_CA53_CPU3 8 20*c66ec88fSEmmanuel Vadot #define R8A77961_PD_CA57_SCU 12 21*c66ec88fSEmmanuel Vadot #define R8A77961_PD_CR7 13 22*c66ec88fSEmmanuel Vadot #define R8A77961_PD_A3VC 14 23*c66ec88fSEmmanuel Vadot #define R8A77961_PD_3DG_A 17 24*c66ec88fSEmmanuel Vadot #define R8A77961_PD_3DG_B 18 25*c66ec88fSEmmanuel Vadot #define R8A77961_PD_CA53_SCU 21 26*c66ec88fSEmmanuel Vadot #define R8A77961_PD_A3IR 24 27*c66ec88fSEmmanuel Vadot #define R8A77961_PD_A2VC1 26 28*c66ec88fSEmmanuel Vadot 29*c66ec88fSEmmanuel Vadot /* Always-on power area */ 30*c66ec88fSEmmanuel Vadot #define R8A77961_PD_ALWAYS_ON 32 31*c66ec88fSEmmanuel Vadot 32*c66ec88fSEmmanuel Vadot #endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */ 33