1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2019 Glider bvba 4 */ 5 #ifndef __DT_BINDINGS_POWER_R8A77961_SYSC_H__ 6 #define __DT_BINDINGS_POWER_R8A77961_SYSC_H__ 7 8 /* 9 * These power domain indices match the numbers of the interrupt bits 10 * representing the power areas in the various Interrupt Registers 11 * (e.g. SYSCISR, Interrupt Status Register) 12 */ 13 14 #define R8A77961_PD_CA57_CPU0 0 15 #define R8A77961_PD_CA57_CPU1 1 16 #define R8A77961_PD_CA53_CPU0 5 17 #define R8A77961_PD_CA53_CPU1 6 18 #define R8A77961_PD_CA53_CPU2 7 19 #define R8A77961_PD_CA53_CPU3 8 20 #define R8A77961_PD_CA57_SCU 12 21 #define R8A77961_PD_CR7 13 22 #define R8A77961_PD_A3VC 14 23 #define R8A77961_PD_3DG_A 17 24 #define R8A77961_PD_3DG_B 18 25 #define R8A77961_PD_CA53_SCU 21 26 #define R8A77961_PD_A3IR 24 27 #define R8A77961_PD_A2VC1 26 28 29 /* Always-on power area */ 30 #define R8A77961_PD_ALWAYS_ON 32 31 32 #endif /* __DT_BINDINGS_POWER_R8A77961_SYSC_H__ */ 33