1* FSL MPIC Message Registers 2 3This binding specifies what properties must be available in the device tree 4representation of the message register blocks found in some FSL MPIC 5implementations. 6 7Required properties: 8 9 - compatible: Specifies the compatibility list for the message register 10 block. The type shall be <string-list> and the value shall be of the form 11 "fsl,mpic-v<version>-msgr", where <version> is the version number of 12 the MPIC containing the message registers. 13 14 - reg: Specifies the base physical address(s) and size(s) of the 15 message register block's addressable register space. The type shall be 16 <prop-encoded-array>. 17 18 - interrupts: Specifies a list of interrupt-specifiers which are available 19 for receiving interrupts. Interrupt-specifier consists of two cells: first 20 cell is interrupt-number and second cell is level-sense. The type shall be 21 <prop-encoded-array>. 22 23Optional properties: 24 25 - mpic-msgr-receive-mask: Specifies what registers in the containing block 26 are allowed to receive interrupts. The value is a bit mask where a set 27 bit at bit 'n' indicates that message register 'n' can receive interrupts. 28 Note that "bit 'n'" is numbered from LSB for PPC hardware. The type shall 29 be <u32>. If not present, then all of the message registers in the block 30 are available. 31 32Aliases: 33 34 An alias should be created for every message register block. They are not 35 required, though. However, a particular implementation of this binding 36 may require aliases to be present. Aliases are of the form 37 'mpic-msgr-block<n>', where <n> is an integer specifying the block's number. 38 Numbers shall start at 0. 39 40Example: 41 42 aliases { 43 mpic-msgr-block0 = &mpic_msgr_block0; 44 mpic-msgr-block1 = &mpic_msgr_block1; 45 }; 46 47 mpic_msgr_block0: mpic-msgr-block@41400 { 48 compatible = "fsl,mpic-v3.1-msgr"; 49 reg = <0x41400 0x200>; 50 // Message registers 0 and 2 in this block can receive interrupts on 51 // sources 0xb0 and 0xb2, respectively. 52 interrupts = <0xb0 2 0xb2 2>; 53 mpic-msgr-receive-mask = <0x5>; 54 }; 55 56 mpic_msgr_block1: mpic-msgr-block@42400 { 57 compatible = "fsl,mpic-v3.1-msgr"; 58 reg = <0x42400 0x200>; 59 // Message registers 0 and 2 in this block can receive interrupts on 60 // sources 0xb4 and 0xb6, respectively. 61 interrupts = <0xb4 2 0xb6 2>; 62 mpic-msgr-receive-mask = <0x5>; 63 }; 64