1# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause 2%YAML 1.2 3--- 4$id: http://devicetree.org/schemas/pinctrl/brcm,bcm11351-pinctrl.yaml# 5$schema: http://devicetree.org/meta-schemas/core.yaml# 6 7title: Broadcom BCM281xx pin controller 8 9maintainers: 10 - Florian Fainelli <florian.fainelli@broadcom.com> 11 - Ray Jui <rjui@broadcom.com> 12 - Scott Branden <sbranden@broadcom.com> 13 14allOf: 15 - $ref: pinctrl.yaml# 16 17properties: 18 compatible: 19 const: brcm,bcm11351-pinctrl 20 21 reg: 22 maxItems: 1 23 24patternProperties: 25 '-pins$': 26 type: object 27 additionalProperties: false 28 29 patternProperties: 30 '-grp[0-9]$': 31 type: object 32 unevaluatedProperties: false 33 34 properties: 35 pins: 36 description: 37 Specifies the name(s) of one or more pins to be configured by 38 this node. 39 items: 40 enum: [ adcsync, bat_rm, bsc1_scl, bsc1_sda, bsc2_scl, bsc2_sda, 41 classgpwr, clk_cx8, clkout_0, clkout_1, clkout_2, 42 clkout_3, clkreq_in_0, clkreq_in_1, cws_sys_req1, 43 cws_sys_req2, cws_sys_req3, digmic1_clk, digmic1_dq, 44 digmic2_clk, digmic2_dq, gpen13, gpen14, gpen15, gpio00, 45 gpio01, gpio02, gpio03, gpio04, gpio05, gpio06, gpio07, 46 gpio08, gpio09, gpio10, gpio11, gpio12, gpio13, gpio14, 47 gps_pablank, gps_tmark, hdmi_scl, hdmi_sda, ic_dm, ic_dp, 48 kp_col_ip_0, kp_col_ip_1, kp_col_ip_2, kp_col_ip_3, 49 kp_row_op_0, kp_row_op_1, kp_row_op_2, kp_row_op_3, 50 lcd_b_0, lcd_b_1, lcd_b_2, lcd_b_3, lcd_b_4, lcd_b_5, 51 lcd_b_6, lcd_b_7, lcd_g_0, lcd_g_1, lcd_g_2, lcd_g_3, 52 lcd_g_4, lcd_g_5, lcd_g_6, lcd_g_7, lcd_hsync, lcd_oe, 53 lcd_pclk, lcd_r_0, lcd_r_1, lcd_r_2, lcd_r_3, lcd_r_4, 54 lcd_r_5, lcd_r_6, lcd_r_7, lcd_vsync, mdmgpio0, mdmgpio1, 55 mdmgpio2, mdmgpio3, mdmgpio4, mdmgpio5, mdmgpio6, 56 mdmgpio7, mdmgpio8, mphi_data_0, mphi_data_1, mphi_data_2, 57 mphi_data_3, mphi_data_4, mphi_data_5, mphi_data_6, 58 mphi_data_7, mphi_data_8, mphi_data_9, mphi_data_10, 59 mphi_data_11, mphi_data_12, mphi_data_13, mphi_data_14, 60 mphi_data_15, mphi_ha0, mphi_hat0, mphi_hat1, mphi_hce0_n, 61 mphi_hce1_n, mphi_hrd_n, mphi_hwr_n, mphi_run0, mphi_run1, 62 mtx_scan_clk, mtx_scan_data, nand_ad_0, nand_ad_1, 63 nand_ad_2, nand_ad_3, nand_ad_4, nand_ad_5, nand_ad_6, 64 nand_ad_7, nand_ale, nand_cen_0, nand_cen_1, nand_cle, 65 nand_oen, nand_rdy_0, nand_rdy_1, nand_wen, nand_wp, pc1, 66 pc2, pmu_int, pmu_scl, pmu_sda, rfst2g_mtsloten3g, 67 rgmii_0_rx_ctl, rgmii_0_rxc, rgmii_0_rxd_0, rgmii_0_rxd_1, 68 rgmii_0_rxd_2, rgmii_0_rxd_3, rgmii_0_tx_ctl, rgmii_0_txc, 69 rgmii_0_txd_0, rgmii_0_txd_1, rgmii_0_txd_2, 70 rgmii_0_txd_3, rgmii_1_rx_ctl, rgmii_1_rxc, rgmii_1_rxd_0, 71 rgmii_1_rxd_1, rgmii_1_rxd_2, rgmii_1_rxd_3, 72 rgmii_1_tx_ctl, rgmii_1_txc, rgmii_1_txd_0, rgmii_1_txd_1, 73 rgmii_1_txd_2, rgmii_1_txd_3, rgmii_gpio_0, rgmii_gpio_1, 74 rgmii_gpio_2, rgmii_gpio_3, rtxdata2g_txdata3g1, 75 rtxen2g_txdata3g2, rxdata3g0, rxdata3g1, rxdata3g2, 76 sdio1_clk, sdio1_cmd, sdio1_data_0, sdio1_data_1, 77 sdio1_data_2, sdio1_data_3, sdio4_clk, sdio4_cmd, 78 sdio4_data_0, sdio4_data_1, sdio4_data_2, sdio4_data_3, 79 sim_clk, sim_data, sim_det, sim_resetn, sim2_clk, 80 sim2_data, sim2_det, sim2_resetn, sri_c, sri_d, sri_e, 81 ssp_extclk, ssp0_clk, ssp0_fs, ssp0_rxd, ssp0_txd, 82 ssp2_clk, ssp2_fs_0, ssp2_fs_1, ssp2_fs_2, ssp2_fs_3, 83 ssp2_rxd_0, ssp2_rxd_1, ssp2_txd_0, ssp2_txd_1, ssp3_clk, 84 ssp3_fs, ssp3_rxd, ssp3_txd, ssp4_clk, ssp4_fs, ssp4_rxd, 85 ssp4_txd, ssp5_clk, ssp5_fs, ssp5_rxd, ssp5_txd, ssp6_clk, 86 ssp6_fs, ssp6_rxd, ssp6_txd, stat_1, stat_2, sysclken, 87 traceclk, tracedt00, tracedt01, tracedt02, tracedt03, 88 tracedt04, tracedt05, tracedt06, tracedt07, tracedt08 89 tracedt09, tracedt10, tracedt11, tracedt12, tracedt13 90 tracedt14, tracedt15, txdata3g0, txpwrind, uartb1_ucts, 91 uartb1_urts, uartb1_urxd, uartb1_utxd, uartb2_urxd, 92 uartb2_utxd, uartb3_ucts, uartb3_urts, uartb3_urxd, 93 uartb3_utxd, uartb4_ucts, uartb4_urts, uartb4_urxd, 94 uartb4_utxd, vc_cam1_scl, vc_cam1_sda, vc_cam2_scl, 95 vc_cam2_sda, vc_cam3_scl, vc_cam3_sda ] 96 97 function: 98 description: 99 Specifies the pin mux selection. 100 enum: [ alt1, alt2, alt3, alt4 ] 101 102 slew-rate: 103 description: | 104 Meaning depends on configured pin mux: 105 *_scl or *_sda: 106 0: Standard (100 kbps) & Fast (400 kbps) mode 107 1: Highspeed (3.4 Mbps) mode 108 ic_dm or ic_dp: 109 0: normal slew rate 110 1: fast slew rate 111 Otherwise: 112 0: fast slew rate 113 1: normal slew rate 114 115 bias-disable: true 116 input-disable: true 117 input-enable: true 118 119 required: 120 - pins 121 122 allOf: 123 - $ref: pincfg-node.yaml# 124 125 # Optional properties for standard pins 126 - if: 127 properties: 128 pins: 129 contains: 130 enum: [ adcsync, bat_rm, classgpwr, clk_cx8, clkout_0, 131 clkout_1, clkout_2, clkout_3, clkreq_in_0, 132 clkreq_in_1, cws_sys_req1, cws_sys_req2, 133 cws_sys_req3, digmic1_clk, digmic1_dq, digmic2_clk, 134 digmic2_dq, gpen13, gpen14, gpen15, gpio00, gpio01, 135 gpio02, gpio03, gpio04, gpio05, gpio06, gpio07, 136 gpio08, gpio09, gpio10, gpio11, gpio12, gpio13, 137 gpio14, gps_pablank, gps_tmark, ic_dm, ic_dp, 138 kp_col_ip_0, kp_col_ip_1, kp_col_ip_2, kp_col_ip_3, 139 kp_row_op_0, kp_row_op_1, kp_row_op_2, kp_row_op_3, 140 lcd_b_0, lcd_b_1, lcd_b_2, lcd_b_3, lcd_b_4, lcd_b_5, 141 lcd_b_6, lcd_b_7, lcd_g_0, lcd_g_1, lcd_g_2, lcd_g_3, 142 lcd_g_4, lcd_g_5, lcd_g_6, lcd_g_7, lcd_hsync, 143 lcd_oe, lcd_pclk, lcd_r_0, lcd_r_1, lcd_r_2, 144 lcd_r_3, lcd_r_4, lcd_r_5, lcd_r_6, lcd_r_7, 145 lcd_vsync, mdmgpio0, mdmgpio1, mdmgpio2, mdmgpio3, 146 mdmgpio4, mdmgpio5, mdmgpio6, mdmgpio7, mdmgpio8, 147 mphi_data_0, mphi_data_1, mphi_data_2, mphi_data_3, 148 mphi_data_4, mphi_data_5, mphi_data_6, mphi_data_7, 149 mphi_data_8, mphi_data_9, mphi_data_10, 150 mphi_data_11, mphi_data_12, mphi_data_13, 151 mphi_data_14, mphi_data_15, mphi_ha0, mphi_hat0, 152 mphi_hat1, mphi_hce0_n, mphi_hce1_n, mphi_hrd_n, 153 mphi_hwr_n, mphi_run0, mphi_run1, mtx_scan_clk, 154 mtx_scan_data, nand_ad_0, nand_ad_1, nand_ad_2, 155 nand_ad_3, nand_ad_4, nand_ad_5, nand_ad_6, 156 nand_ad_7, nand_ale, nand_cen_0, nand_cen_1, 157 nand_cle, nand_oen, nand_rdy_0, nand_rdy_1, 158 nand_wen, nand_wp, pc1, pc2, pmu_int, 159 rfst2g_mtsloten3g, rgmii_0_rx_ctl, rgmii_0_rxc, 160 rgmii_0_rxd_0, rgmii_0_rxd_1, rgmii_0_rxd_2, 161 rgmii_0_rxd_3, rgmii_0_tx_ctl, rgmii_0_txc, 162 rgmii_0_txd_0, rgmii_0_txd_1, rgmii_0_txd_2, 163 rgmii_0_txd_3, rgmii_1_rx_ctl, rgmii_1_rxc, 164 rgmii_1_rxd_0, rgmii_1_rxd_1, rgmii_1_rxd_2, 165 rgmii_1_rxd_3, rgmii_1_tx_ctl, rgmii_1_txc, 166 rgmii_1_txd_0, rgmii_1_txd_1, rgmii_1_txd_2, 167 rgmii_1_txd_3, rgmii_gpio_0, rgmii_gpio_1, 168 rgmii_gpio_2, rgmii_gpio_3, rtxdata2g_txdata3g1, 169 rtxen2g_txdata3g2, rxdata3g0, rxdata3g1, rxdata3g2, 170 sdio1_clk, sdio1_cmd, sdio1_data_0, sdio1_data_1, 171 sdio1_data_2, sdio1_data_3, sdio4_clk, sdio4_cmd, 172 sdio4_data_0, sdio4_data_1, sdio4_data_2, 173 sdio4_data_3, sim_clk, sim_data, sim_det, 174 sim_resetn, sim2_clk, sim2_data, sim2_det, 175 sim2_resetn, sri_c, sri_d, sri_e, ssp_extclk, 176 ssp0_clk, ssp0_fs, ssp0_rxd, ssp0_txd, ssp2_clk, 177 ssp2_fs_0, ssp2_fs_1, ssp2_fs_2, ssp2_fs_3, 178 ssp2_rxd_0, ssp2_rxd_1, ssp2_txd_0, ssp2_txd_1, 179 ssp3_clk, ssp3_fs, ssp3_rxd, ssp3_txd, ssp4_clk, 180 ssp4_fs, ssp4_rxd, ssp4_txd, ssp5_clk, ssp5_fs, 181 ssp5_rxd, ssp5_txd, ssp6_clk, ssp6_fs, ssp6_rxd, 182 ssp6_txd, stat_1, stat_2, sysclken, traceclk, 183 tracedt00, tracedt01, tracedt02, tracedt03, 184 tracedt04, tracedt05, tracedt06, tracedt07, 185 tracedt08, tracedt09, tracedt10, tracedt11, 186 tracedt12, tracedt13, tracedt14, tracedt15, 187 txdata3g0, txpwrind, uartb1_ucts, uartb1_urts, 188 uartb1_urxd, uartb1_utxd, uartb2_urxd, uartb2_utxd, 189 uartb3_ucts, uartb3_urts, uartb3_urxd, uartb3_utxd, 190 uartb4_ucts, uartb4_urts, uartb4_urxd, uartb4_utxd ] 191 then: 192 properties: 193 drive-strength: 194 enum: [ 2, 4, 6, 8, 10, 12, 14, 16 ] 195 196 bias-disable: true 197 bias-pull-up: true 198 bias-pull-down: true 199 input-schmitt-enable: true 200 input-schmitt-disable: true 201 202 # Optional properties for I2C pins 203 - if: 204 properties: 205 pins: 206 contains: 207 enum: [ bsc1_scl, bsc1_sda, bsc2_scl, bsc2_sda, pmu_scl, 208 pmu_sda, vc_cam1_scl, vc_cam1_sda, vc_cam2_scl, 209 vc_cam2_sda, vc_cam3_scl, vc_cam3_sda ] 210 then: 211 properties: 212 bias-pull-up: 213 description: 214 There are 3 pull-up resistors (1.2k, 1.8k, 2.7k) available 215 in parallel for I2C pins. 216 enum: [ 568, 720, 831, 1080, 1200, 1800, 2700 ] 217 218 bias-disable: true 219 220required: 221 - compatible 222 - reg 223 224unevaluatedProperties: false 225 226examples: 227 - | 228 pinctrl@35004800 { 229 compatible = "brcm,bcm11351-pinctrl"; 230 reg = <0x35004800 0x430>; 231 232 dev-a-active-pins { 233 /* group node defining 1 standard pin */ 234 std-grp0 { 235 pins = "gpio00"; 236 function = "alt1"; 237 input-schmitt-enable; 238 bias-disable; 239 slew-rate = <1>; 240 drive-strength = <4>; 241 }; 242 243 /* group node defining 2 I2C pins */ 244 i2c-grp0 { 245 pins = "bsc1_scl", "bsc1_sda"; 246 function = "alt2"; 247 bias-pull-up = <720>; 248 input-enable; 249 }; 250 251 /* group node defining 2 HDMI pins */ 252 hdmi-grp0 { 253 pins = "hdmi_scl", "hdmi_sda"; 254 function = "alt3"; 255 slew-rate = <1>; 256 }; 257 }; 258 }; 259... 260