xref: /freebsd/sys/contrib/device-tree/Bindings/phy/qcom,sc8280xp-qmp-ufs-phy.yaml (revision 8d13bc63c0e1d50bc9e47ac1f26329c999bfecf0) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,sc8280xp-qmp-ufs-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (UFS, SC8280XP)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    enum:
19      - qcom,msm8996-qmp-ufs-phy
20      - qcom,msm8998-qmp-ufs-phy
21      - qcom,sa8775p-qmp-ufs-phy
22      - qcom,sc7280-qmp-ufs-phy
23      - qcom,sc8180x-qmp-ufs-phy
24      - qcom,sc8280xp-qmp-ufs-phy
25      - qcom,sdm845-qmp-ufs-phy
26      - qcom,sm6115-qmp-ufs-phy
27      - qcom,sm6125-qmp-ufs-phy
28      - qcom,sm6350-qmp-ufs-phy
29      - qcom,sm7150-qmp-ufs-phy
30      - qcom,sm8150-qmp-ufs-phy
31      - qcom,sm8250-qmp-ufs-phy
32      - qcom,sm8350-qmp-ufs-phy
33      - qcom,sm8450-qmp-ufs-phy
34      - qcom,sm8550-qmp-ufs-phy
35      - qcom,sm8650-qmp-ufs-phy
36
37  reg:
38    maxItems: 1
39
40  clocks:
41    minItems: 1
42    maxItems: 3
43
44  clock-names:
45    minItems: 1
46    items:
47      - const: ref
48      - const: ref_aux
49      - const: qref
50
51  power-domains:
52    maxItems: 1
53
54  resets:
55    maxItems: 1
56
57  reset-names:
58    items:
59      - const: ufsphy
60
61  vdda-phy-supply: true
62
63  vdda-pll-supply: true
64
65  "#clock-cells":
66    const: 1
67
68  "#phy-cells":
69    const: 0
70
71required:
72  - compatible
73  - reg
74  - clocks
75  - clock-names
76  - power-domains
77  - resets
78  - reset-names
79  - vdda-phy-supply
80  - vdda-pll-supply
81  - "#phy-cells"
82
83allOf:
84  - if:
85      properties:
86        compatible:
87          contains:
88            enum:
89              - qcom,sa8775p-qmp-ufs-phy
90              - qcom,sc7280-qmp-ufs-phy
91              - qcom,sm8450-qmp-ufs-phy
92    then:
93      properties:
94        clocks:
95          minItems: 3
96        clock-names:
97          minItems: 3
98
99  - if:
100      properties:
101        compatible:
102          contains:
103            enum:
104              - qcom,msm8998-qmp-ufs-phy
105              - qcom,sc8180x-qmp-ufs-phy
106              - qcom,sc8280xp-qmp-ufs-phy
107              - qcom,sdm845-qmp-ufs-phy
108              - qcom,sm6115-qmp-ufs-phy
109              - qcom,sm6125-qmp-ufs-phy
110              - qcom,sm6350-qmp-ufs-phy
111              - qcom,sm7150-qmp-ufs-phy
112              - qcom,sm8150-qmp-ufs-phy
113              - qcom,sm8250-qmp-ufs-phy
114              - qcom,sm8350-qmp-ufs-phy
115              - qcom,sm8550-qmp-ufs-phy
116              - qcom,sm8650-qmp-ufs-phy
117    then:
118      properties:
119        clocks:
120          maxItems: 2
121        clock-names:
122          maxItems: 2
123
124  - if:
125      properties:
126        compatible:
127          contains:
128            enum:
129              - qcom,msm8996-qmp-ufs-phy
130    then:
131      properties:
132        clocks:
133          maxItems: 1
134        clock-names:
135          maxItems: 1
136
137additionalProperties: false
138
139examples:
140  - |
141    #include <dt-bindings/clock/qcom,gcc-sc8280xp.h>
142
143    ufs_mem_phy: phy@1d87000 {
144        compatible = "qcom,sc8280xp-qmp-ufs-phy";
145        reg = <0x01d87000 0x1000>;
146
147        clocks = <&gcc GCC_UFS_REF_CLKREF_CLK>, <&gcc GCC_UFS_PHY_PHY_AUX_CLK>;
148        clock-names = "ref", "ref_aux";
149
150        power-domains = <&gcc UFS_PHY_GDSC>;
151
152        resets = <&ufs_mem_hc 0>;
153        reset-names = "ufsphy";
154
155        vdda-phy-supply = <&vreg_l6b>;
156        vdda-pll-supply = <&vreg_l3b>;
157
158        #phy-cells = <0>;
159    };
160