xref: /freebsd/sys/contrib/device-tree/Bindings/phy/qcom,msm8998-qmp-pcie-phy.yaml (revision aa1a8ff2d6dbc51ef058f46f3db5a8bb77967145) 
1# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/phy/qcom,msm8998-qmp-pcie-phy.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm QMP PHY controller (PCIe, MSM8998)
8
9maintainers:
10  - Vinod Koul <vkoul@kernel.org>
11
12description:
13  The QMP PHY controller supports physical layer functionality for a number of
14  controllers on Qualcomm chipsets, such as, PCIe, UFS, and USB.
15
16properties:
17  compatible:
18    const: qcom,msm8998-qmp-pcie-phy
19
20  reg:
21    items:
22      - description: serdes
23
24  clocks:
25    maxItems: 4
26
27  clock-names:
28    items:
29      - const: aux
30      - const: cfg_ahb
31      - const: ref
32      - const: pipe
33
34  resets:
35    maxItems: 2
36
37  reset-names:
38    items:
39      - const: phy
40      - const: common
41
42  vdda-phy-supply: true
43
44  vdda-pll-supply: true
45
46  "#clock-cells":
47    const: 0
48
49  clock-output-names:
50    maxItems: 1
51
52  "#phy-cells":
53    const: 0
54
55required:
56  - compatible
57  - reg
58  - clocks
59  - clock-names
60  - resets
61  - reset-names
62  - vdda-phy-supply
63  - vdda-pll-supply
64  - "#clock-cells"
65  - clock-output-names
66  - "#phy-cells"
67
68additionalProperties: false
69
70examples:
71  - |
72    #include <dt-bindings/clock/qcom,gcc-msm8998.h>
73
74    phy@1c18000 {
75        compatible = "qcom,msm8998-qmp-pcie-phy";
76        reg = <0x01c06000 0x1000>;
77
78        clocks = <&gcc GCC_PCIE_PHY_AUX_CLK>,
79                 <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
80                 <&gcc GCC_PCIE_CLKREF_CLK>,
81                 <&gcc GCC_PCIE_0_PIPE_CLK>;
82        clock-names = "aux",
83                      "cfg_ahb",
84                      "ref",
85                      "pipe";
86
87        clock-output-names = "pcie_0_pipe_clk_src";
88        #clock-cells = <0>;
89
90        #phy-cells = <0>;
91
92        resets = <&gcc GCC_PCIE_0_PHY_BCR>, <&gcc GCC_PCIE_PHY_BCR>;
93        reset-names = "phy", "common";
94
95        vdda-phy-supply = <&vreg_l1a_0p875>;
96        vdda-pll-supply = <&vreg_l2a_1p2>;
97    };
98