xref: /freebsd/sys/contrib/device-tree/Bindings/pci/qcom,pcie-sdx55.yaml (revision 0cd4430a9320c916a84617b6bbf400f5c64a09c7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-sdx55.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDX55 PCI Express Root Complex
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Manivannan Sadhasivam <mani@kernel.org>
12
13properties:
14  compatible:
15    enum:
16      - qcom,pcie-sdx55
17
18  reg:
19    minItems: 5
20    maxItems: 6
21
22  reg-names:
23    minItems: 5
24    items:
25      - const: parf
26      - const: dbi
27      - const: elbi
28      - const: atu
29      - const: config
30      - const: mhi
31
32  clocks:
33    maxItems: 7
34
35  clock-names:
36    items:
37      - const: pipe
38      - const: aux
39      - const: cfg
40      - const: bus_master # Master AXI clock
41      - const: bus_slave # Slave AXI clock
42      - const: slave_q2a
43      - const: sleep
44
45  interrupts:
46    maxItems: 8
47
48  interrupt-names:
49    items:
50      - const: msi
51      - const: msi2
52      - const: msi3
53      - const: msi4
54      - const: msi5
55      - const: msi6
56      - const: msi7
57      - const: msi8
58
59  resets:
60    maxItems: 1
61
62  reset-names:
63    items:
64      - const: pci
65
66required:
67  - power-domains
68  - resets
69  - reset-names
70
71allOf:
72  - $ref: qcom,pcie-common.yaml#
73
74unevaluatedProperties: false
75
76examples:
77  - |
78    #include <dt-bindings/clock/qcom,gcc-sdx55.h>
79    #include <dt-bindings/gpio/gpio.h>
80    #include <dt-bindings/interrupt-controller/arm-gic.h>
81
82    pcie@1c00000 {
83        compatible = "qcom,pcie-sdx55";
84        reg = <0x01c00000 0x3000>,
85              <0x40000000 0xf1d>,
86              <0x40000f20 0xc8>,
87              <0x40001000 0x1000>,
88              <0x40100000 0x100000>;
89        reg-names = "parf",
90                    "dbi",
91                    "elbi",
92                    "atu",
93                    "config";
94        ranges = <0x01000000 0x0 0x00000000 0x40200000 0x0 0x100000>,
95                 <0x02000000 0x0 0x40300000 0x40300000 0x0 0x3fd00000>;
96
97        device_type = "pci";
98        linux,pci-domain = <0>;
99        bus-range = <0x00 0xff>;
100        num-lanes = <1>;
101
102        #address-cells = <3>;
103        #size-cells = <2>;
104
105        interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>,
106                     <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
107                     <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
108                     <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
109                     <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>,
110                     <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>,
111                     <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>,
112                     <GIC_SPI 126 IRQ_TYPE_LEVEL_HIGH>;
113        interrupt-names = "msi",
114                          "msi2",
115                          "msi3",
116                          "msi4",
117                          "msi5",
118                          "msi6",
119                          "msi7",
120                          "msi8";
121        #interrupt-cells = <1>;
122        interrupt-map-mask = <0 0 0 0x7>;
123        interrupt-map = <0 0 0 1 &intc GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
124                        <0 0 0 2 &intc GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
125                        <0 0 0 3 &intc GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
126                        <0 0 0 4 &intc GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
127
128        clocks = <&gcc GCC_PCIE_PIPE_CLK>,
129                 <&gcc GCC_PCIE_AUX_CLK>,
130                 <&gcc GCC_PCIE_CFG_AHB_CLK>,
131                 <&gcc GCC_PCIE_MSTR_AXI_CLK>,
132                 <&gcc GCC_PCIE_SLV_AXI_CLK>,
133                 <&gcc GCC_PCIE_SLV_Q2A_AXI_CLK>,
134                 <&gcc GCC_PCIE_SLEEP_CLK>;
135        clock-names = "pipe",
136                      "aux",
137                      "cfg",
138                      "bus_master",
139                      "bus_slave",
140                      "slave_q2a",
141                      "sleep";
142
143        assigned-clocks = <&gcc GCC_PCIE_AUX_CLK>;
144        assigned-clock-rates = <19200000>;
145
146        iommu-map = <0x0 &apps_smmu 0x0200 0x1>,
147                    <0x100 &apps_smmu 0x0201 0x1>,
148                    <0x200 &apps_smmu 0x0202 0x1>,
149                    <0x300 &apps_smmu 0x0203 0x1>,
150                    <0x400 &apps_smmu 0x0204 0x1>;
151
152        power-domains = <&gcc PCIE_GDSC>;
153
154        phys = <&pcie_phy>;
155        phy-names = "pciephy";
156
157        resets = <&gcc GCC_PCIE_BCR>;
158        reset-names = "pci";
159
160        perst-gpios = <&tlmm 57 GPIO_ACTIVE_LOW>;
161        wake-gpios = <&tlmm 53 GPIO_ACTIVE_HIGH>;
162
163        pcie@0 {
164            device_type = "pci";
165            reg = <0x0 0x0 0x0 0x0 0x0>;
166            bus-range = <0x01 0xff>;
167
168            #address-cells = <3>;
169            #size-cells = <2>;
170            ranges;
171        };
172    };
173