xref: /freebsd/sys/contrib/device-tree/Bindings/pci/qcom,pcie-sdm845.yaml (revision 0cd4430a9320c916a84617b6bbf400f5c64a09c7) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/qcom,pcie-sdm845.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Qualcomm SDM845 PCI Express Root Complex
8
9maintainers:
10  - Bjorn Andersson <andersson@kernel.org>
11  - Manivannan Sadhasivam <mani@kernel.org>
12
13properties:
14  compatible:
15    enum:
16      - qcom,pcie-sdm845
17
18  reg:
19    minItems: 4
20    maxItems: 5
21
22  reg-names:
23    minItems: 4
24    items:
25      - const: parf
26      - const: dbi
27      - const: elbi
28      - const: config
29      - const: mhi
30
31  clocks:
32    minItems: 7
33    maxItems: 8
34
35  clock-names:
36    minItems: 7
37    items:
38      - const: pipe
39      - const: aux
40      - const: cfg
41      - const: bus_master # Master AXI clock
42      - const: bus_slave # Slave AXI clock
43      - const: slave_q2a
44      - enum: [ ref, tbu ]
45      - const: tbu
46
47  interrupts:
48    minItems: 8
49    maxItems: 9
50
51  interrupt-names:
52    minItems: 8
53    items:
54      - const: msi0
55      - const: msi1
56      - const: msi2
57      - const: msi3
58      - const: msi4
59      - const: msi5
60      - const: msi6
61      - const: msi7
62      - const: global
63
64  resets:
65    maxItems: 1
66
67  reset-names:
68    items:
69      - const: pci
70
71required:
72  - power-domains
73  - resets
74  - reset-names
75
76allOf:
77  - $ref: qcom,pcie-common.yaml#
78
79unevaluatedProperties: false
80
81examples:
82  - |
83    #include <dt-bindings/clock/qcom,gcc-sdm845.h>
84    #include <dt-bindings/gpio/gpio.h>
85    #include <dt-bindings/interrupt-controller/arm-gic.h>
86
87    soc {
88        #address-cells = <2>;
89        #size-cells = <2>;
90
91        pcie@1c00000 {
92            compatible = "qcom,pcie-sdm845";
93            reg = <0x0 0x01c00000 0x0 0x2000>,
94                  <0x0 0x60000000 0x0 0xf1d>,
95                  <0x0 0x60000f20 0x0 0xa8>,
96                  <0x0 0x60100000 0x0 0x100000>,
97                  <0x0 0x01c07000 0x0 0x1000>;
98            reg-names = "parf", "dbi", "elbi", "config", "mhi";
99            ranges = <0x01000000 0x0 0x00000000 0x0 0x60200000 0x0 0x100000>,
100                     <0x02000000 0x0 0x60300000 0x0 0x60300000 0x0 0xd00000>;
101
102            device_type = "pci";
103            linux,pci-domain = <0>;
104            bus-range = <0x00 0xff>;
105            num-lanes = <1>;
106
107            #address-cells = <3>;
108            #size-cells = <2>;
109
110            clocks = <&gcc GCC_PCIE_0_PIPE_CLK>,
111                     <&gcc GCC_PCIE_0_AUX_CLK>,
112                     <&gcc GCC_PCIE_0_CFG_AHB_CLK>,
113                     <&gcc GCC_PCIE_0_MSTR_AXI_CLK>,
114                     <&gcc GCC_PCIE_0_SLV_AXI_CLK>,
115                     <&gcc GCC_PCIE_0_SLV_Q2A_AXI_CLK>,
116                     <&gcc GCC_AGGRE_NOC_PCIE_TBU_CLK>;
117            clock-names = "pipe",
118                          "aux",
119                          "cfg",
120                          "bus_master",
121                          "bus_slave",
122                          "slave_q2a",
123                          "tbu";
124
125            interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>,
126                         <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>,
127                         <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>,
128                         <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH>,
129                         <GIC_SPI 145 IRQ_TYPE_LEVEL_HIGH>,
130                         <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>,
131                         <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>,
132                         <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>,
133                         <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>;
134            interrupt-names = "msi0",
135                              "msi1",
136                              "msi2",
137                              "msi3",
138                              "msi4",
139                              "msi5",
140                              "msi6",
141                              "msi7",
142                              "global";
143            #interrupt-cells = <1>;
144            interrupt-map-mask = <0 0 0 0x7>;
145            interrupt-map = <0 0 0 1 &intc 0 0 GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, /* int_a */
146                            <0 0 0 2 &intc 0 0 GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, /* int_b */
147                            <0 0 0 3 &intc 0 0 GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, /* int_c */
148                            <0 0 0 4 &intc 0 0 GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>; /* int_d */
149
150            iommu-map = <0x0 &apps_smmu 0x1c10 0x1>,
151                        <0x100 &apps_smmu 0x1c11 0x1>,
152                        <0x200 &apps_smmu 0x1c12 0x1>,
153                        <0x300 &apps_smmu 0x1c13 0x1>,
154                        <0x400 &apps_smmu 0x1c14 0x1>,
155                        <0x500 &apps_smmu 0x1c15 0x1>,
156                        <0x600 &apps_smmu 0x1c16 0x1>,
157                        <0x700 &apps_smmu 0x1c17 0x1>,
158                        <0x800 &apps_smmu 0x1c18 0x1>,
159                        <0x900 &apps_smmu 0x1c19 0x1>,
160                        <0xa00 &apps_smmu 0x1c1a 0x1>,
161                        <0xb00 &apps_smmu 0x1c1b 0x1>,
162                        <0xc00 &apps_smmu 0x1c1c 0x1>,
163                        <0xd00 &apps_smmu 0x1c1d 0x1>,
164                        <0xe00 &apps_smmu 0x1c1e 0x1>,
165                        <0xf00 &apps_smmu 0x1c1f 0x1>;
166
167            power-domains = <&gcc PCIE_0_GDSC>;
168
169            phys = <&pcie0_phy>;
170            phy-names = "pciephy";
171
172            resets = <&gcc GCC_PCIE_0_BCR>;
173            reset-names = "pci";
174
175            perst-gpios = <&tlmm 35 GPIO_ACTIVE_LOW>;
176            wake-gpios = <&tlmm 134 GPIO_ACTIVE_HIGH>;
177
178            vddpe-3v3-supply = <&pcie0_3p3v_dual>;
179
180            pcie@0 {
181                device_type = "pci";
182                reg = <0x0 0x0 0x0 0x0 0x0>;
183                bus-range = <0x01 0xff>;
184
185                #address-cells = <3>;
186                #size-cells = <2>;
187                ranges;
188            };
189        };
190    };
191