xref: /freebsd/sys/contrib/device-tree/Bindings/pci/mbvl,gpex40-pcie.yaml (revision 2846c90520eb4cc74e24d586a0ea0f4a0006bc73) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/pci/mbvl,gpex40-pcie.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: Mobiveil AXI PCIe Host Bridge
8
9maintainers:
10  - Frank Li <Frank Li@nxp.com>
11
12description:
13  Mobiveil's GPEX 4.0 is a PCIe Gen4 host bridge IP. This configurable IP
14  has up to 8 outbound and inbound windows for address translation.
15
16  NXP Layerscape PCIe Gen4 controller (Deprecated) base on Mobiveil's GPEX 4.0.
17
18properties:
19  compatible:
20    enum:
21      - fsl,lx2160a-pcie
22      - mbvl,gpex40-pcie
23
24  reg:
25    items:
26      - description: PCIe controller registers
27      - description: Bridge config registers
28      - description: GPIO registers to control slot power
29      - description: MSI registers
30    minItems: 2
31
32  reg-names:
33    items:
34      - const: csr_axi_slave
35      - const: config_axi_slave
36      - const: gpio_slave
37      - const: apb_csr
38    minItems: 2
39
40  apio-wins:
41    $ref: /schemas/types.yaml#/definitions/uint32
42    description: |
43      number of requested APIO outbound windows
44        1. Config window
45        2. Memory window
46    default: 2
47    maximum: 256
48
49  ppio-wins:
50    $ref: /schemas/types.yaml#/definitions/uint32
51    description: number of requested PPIO inbound windows
52    default: 1
53    maximum: 256
54
55  interrupt-controller: true
56
57  "#interrupt-cells":
58    const: 1
59
60  interrupts:
61    minItems: 1
62    maxItems: 3
63
64  interrupt-names:
65    minItems: 1
66    maxItems: 3
67
68  dma-coherent: true
69
70  msi-parent: true
71
72required:
73  - compatible
74  - reg
75  - reg-names
76
77allOf:
78  - $ref: /schemas/pci/pci-host-bridge.yaml#
79  - if:
80      properties:
81        compatible:
82          enum:
83            - fsl,lx2160a-pcie
84    then:
85      properties:
86        reg:
87          maxItems: 2
88
89        reg-names:
90          maxItems: 2
91
92        interrupts:
93          minItems: 3
94
95        interrupt-names:
96          items:
97            - const: aer
98            - const: pme
99            - const: intr
100    else:
101      properties:
102        dma-coherent: false
103        msi-parent: false
104        interrupts:
105          maxItems: 1
106        interrupt-names: false
107
108unevaluatedProperties: false
109
110examples:
111  - |
112    #include <dt-bindings/interrupt-controller/arm-gic.h>
113
114    pcie@b0000000 {
115        compatible = "mbvl,gpex40-pcie";
116        reg = <0xb0000000 0x00010000>,
117              <0xa0000000 0x00001000>,
118              <0xff000000 0x00200000>,
119              <0xb0010000 0x00001000>;
120        reg-names = "csr_axi_slave",
121                    "config_axi_slave",
122                    "gpio_slave",
123                    "apb_csr";
124        ranges = <0x83000000 0 0x00000000 0xa8000000 0 0x8000000>;
125        #address-cells = <3>;
126        #size-cells = <2>;
127        device_type = "pci";
128        apio-wins = <2>;
129        ppio-wins = <1>;
130        bus-range = <0x00 0xff>;
131        interrupt-controller;
132        #interrupt-cells = <1>;
133        interrupt-parent = <&gic>;
134        interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
135        interrupt-map-mask = <0 0 0 7>;
136        interrupt-map = <0 0 0 0 &pci_express 0>,
137                        <0 0 0 1 &pci_express 1>,
138                        <0 0 0 2 &pci_express 2>,
139                        <0 0 0 3 &pci_express 3>;
140    };
141
142  - |
143    #include <dt-bindings/interrupt-controller/arm-gic.h>
144
145    soc {
146        #address-cells = <2>;
147        #size-cells = <2>;
148        pcie@3400000 {
149            compatible = "fsl,lx2160a-pcie";
150            reg = <0x00 0x03400000 0x0 0x00100000   /* controller registers */
151                   0x80 0x00000000 0x0 0x00001000>; /* configuration space */
152            reg-names = "csr_axi_slave", "config_axi_slave";
153            ranges = <0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>;
154            interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* AER interrupt */
155                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */
156                         <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; /* controller interrupt */
157            interrupt-names = "aer", "pme", "intr";
158            #address-cells = <3>;
159            #size-cells = <2>;
160            device_type = "pci";
161            apio-wins = <8>;
162            ppio-wins = <8>;
163            dma-coherent;
164            bus-range = <0x00 0xff>;
165            msi-parent = <&its>;
166            #interrupt-cells = <1>;
167            interrupt-map-mask = <0 0 0 7>;
168            interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>,
169                            <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>,
170                            <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>,
171                            <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>;
172        };
173    };
174