xref: /freebsd/sys/contrib/device-tree/Bindings/net/mediatek,net.yaml (revision f126890ac5386406dadf7c4cfa9566cbb56537c5) 
1# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2%YAML 1.2
3---
4$id: http://devicetree.org/schemas/net/mediatek,net.yaml#
5$schema: http://devicetree.org/meta-schemas/core.yaml#
6
7title: MediaTek Frame Engine Ethernet controller
8
9maintainers:
10  - Lorenzo Bianconi <lorenzo@kernel.org>
11  - Felix Fietkau <nbd@nbd.name>
12
13description:
14  The frame engine ethernet controller can be found on MediaTek SoCs. These SoCs
15  have dual GMAC ports.
16
17properties:
18  compatible:
19    enum:
20      - mediatek,mt2701-eth
21      - mediatek,mt7623-eth
22      - mediatek,mt7622-eth
23      - mediatek,mt7629-eth
24      - mediatek,mt7981-eth
25      - mediatek,mt7986-eth
26      - ralink,rt5350-eth
27
28  reg:
29    maxItems: 1
30
31  clocks: true
32  clock-names: true
33
34  interrupts:
35    minItems: 3
36    maxItems: 4
37
38  power-domains:
39    maxItems: 1
40
41  resets:
42    maxItems: 3
43
44  reset-names:
45    items:
46      - const: fe
47      - const: gmac
48      - const: ppe
49
50  mediatek,ethsys:
51    $ref: /schemas/types.yaml#/definitions/phandle
52    description:
53      Phandle to the syscon node that handles the port setup.
54
55  cci-control-port: true
56
57  mediatek,hifsys:
58    $ref: /schemas/types.yaml#/definitions/phandle
59    description:
60      Phandle to the mediatek hifsys controller used to provide various clocks
61      and reset to the system.
62
63  mediatek,sgmiisys:
64    $ref: /schemas/types.yaml#/definitions/phandle-array
65    minItems: 1
66    maxItems: 2
67    items:
68      maxItems: 1
69    description:
70      A list of phandle to the syscon node that handles the SGMII setup which is required for
71      those SoCs equipped with SGMII.
72
73  mediatek,wed:
74    $ref: /schemas/types.yaml#/definitions/phandle-array
75    minItems: 2
76    maxItems: 2
77    items:
78      maxItems: 1
79    description:
80      List of phandles to wireless ethernet dispatch nodes.
81
82  mediatek,wed-pcie:
83    $ref: /schemas/types.yaml#/definitions/phandle
84    description:
85      Phandle to the mediatek wed-pcie controller.
86
87  dma-coherent: true
88
89  mdio-bus:
90    $ref: mdio.yaml#
91    unevaluatedProperties: false
92
93  "#address-cells":
94    const: 1
95
96  "#size-cells":
97    const: 0
98
99allOf:
100  - $ref: ethernet-controller.yaml#
101  - if:
102      properties:
103        compatible:
104          contains:
105            enum:
106              - mediatek,mt2701-eth
107              - mediatek,mt7623-eth
108    then:
109      properties:
110        interrupts:
111          maxItems: 3
112
113        clocks:
114          minItems: 4
115          maxItems: 4
116
117        clock-names:
118          items:
119            - const: ethif
120            - const: esw
121            - const: gp1
122            - const: gp2
123
124        mediatek,pctl:
125          $ref: /schemas/types.yaml#/definitions/phandle
126          description:
127            Phandle to the syscon node that handles the ports slew rate and
128            driver current.
129
130        mediatek,wed: false
131
132        mediatek,wed-pcie: false
133
134  - if:
135      properties:
136        compatible:
137          contains:
138            const: mediatek,mt7622-eth
139    then:
140      properties:
141        interrupts:
142          maxItems: 3
143
144        clocks:
145          minItems: 11
146          maxItems: 11
147
148        clock-names:
149          items:
150            - const: ethif
151            - const: esw
152            - const: gp0
153            - const: gp1
154            - const: gp2
155            - const: sgmii_tx250m
156            - const: sgmii_rx250m
157            - const: sgmii_cdr_ref
158            - const: sgmii_cdr_fb
159            - const: sgmii_ck
160            - const: eth2pll
161
162        mediatek,sgmiisys:
163          minItems: 1
164          maxItems: 1
165
166        mediatek,pcie-mirror:
167          $ref: /schemas/types.yaml#/definitions/phandle
168          description:
169            Phandle to the mediatek pcie-mirror controller.
170
171        mediatek,wed-pcie: false
172
173  - if:
174      properties:
175        compatible:
176          contains:
177            const: mediatek,mt7629-eth
178    then:
179      properties:
180        interrupts:
181          maxItems: 3
182
183        clocks:
184          minItems: 17
185          maxItems: 17
186
187        clock-names:
188          items:
189            - const: ethif
190            - const: sgmiitop
191            - const: esw
192            - const: gp0
193            - const: gp1
194            - const: gp2
195            - const: fe
196            - const: sgmii_tx250m
197            - const: sgmii_rx250m
198            - const: sgmii_cdr_ref
199            - const: sgmii_cdr_fb
200            - const: sgmii2_tx250m
201            - const: sgmii2_rx250m
202            - const: sgmii2_cdr_ref
203            - const: sgmii2_cdr_fb
204            - const: sgmii_ck
205            - const: eth2pll
206
207        mediatek,infracfg:
208          $ref: /schemas/types.yaml#/definitions/phandle
209          description:
210            Phandle to the syscon node that handles the path from GMAC to
211            PHY variants.
212
213        mediatek,sgmiisys:
214          minItems: 2
215          maxItems: 2
216
217        mediatek,wed: false
218
219        mediatek,wed-pcie: false
220
221  - if:
222      properties:
223        compatible:
224          contains:
225            const: mediatek,mt7981-eth
226    then:
227      properties:
228        interrupts:
229          minItems: 4
230
231        clocks:
232          minItems: 15
233          maxItems: 15
234
235        clock-names:
236          items:
237            - const: fe
238            - const: gp2
239            - const: gp1
240            - const: wocpu0
241            - const: sgmii_ck
242            - const: sgmii_tx250m
243            - const: sgmii_rx250m
244            - const: sgmii_cdr_ref
245            - const: sgmii_cdr_fb
246            - const: sgmii2_tx250m
247            - const: sgmii2_rx250m
248            - const: sgmii2_cdr_ref
249            - const: sgmii2_cdr_fb
250            - const: netsys0
251            - const: netsys1
252
253        mediatek,sgmiisys:
254          minItems: 2
255          maxItems: 2
256
257  - if:
258      properties:
259        compatible:
260          contains:
261            const: mediatek,mt7986-eth
262    then:
263      properties:
264        interrupts:
265          minItems: 4
266
267        clocks:
268          minItems: 15
269          maxItems: 15
270
271        clock-names:
272          items:
273            - const: fe
274            - const: gp2
275            - const: gp1
276            - const: wocpu1
277            - const: wocpu0
278            - const: sgmii_tx250m
279            - const: sgmii_rx250m
280            - const: sgmii_cdr_ref
281            - const: sgmii_cdr_fb
282            - const: sgmii2_tx250m
283            - const: sgmii2_rx250m
284            - const: sgmii2_cdr_ref
285            - const: sgmii2_cdr_fb
286            - const: netsys0
287            - const: netsys1
288
289        mediatek,sgmiisys:
290          minItems: 2
291          maxItems: 2
292
293patternProperties:
294  "^mac@[0-1]$":
295    type: object
296    unevaluatedProperties: false
297    allOf:
298      - $ref: ethernet-controller.yaml#
299    description:
300      Ethernet MAC node
301    properties:
302      compatible:
303        const: mediatek,eth-mac
304
305      reg:
306        maxItems: 1
307
308    required:
309      - reg
310      - compatible
311
312required:
313  - compatible
314  - reg
315  - interrupts
316  - clocks
317  - clock-names
318  - mediatek,ethsys
319
320unevaluatedProperties: false
321
322examples:
323  - |
324    #include <dt-bindings/interrupt-controller/arm-gic.h>
325    #include <dt-bindings/interrupt-controller/irq.h>
326    #include <dt-bindings/clock/mt7622-clk.h>
327    #include <dt-bindings/power/mt7622-power.h>
328
329    soc {
330      #address-cells = <2>;
331      #size-cells = <2>;
332
333      ethernet: ethernet@1b100000 {
334        compatible = "mediatek,mt7622-eth";
335        reg = <0 0x1b100000 0 0x20000>;
336        interrupts = <GIC_SPI 223 IRQ_TYPE_LEVEL_LOW>,
337                     <GIC_SPI 224 IRQ_TYPE_LEVEL_LOW>,
338                     <GIC_SPI 225 IRQ_TYPE_LEVEL_LOW>;
339        clocks = <&topckgen CLK_TOP_ETH_SEL>,
340                 <&ethsys CLK_ETH_ESW_EN>,
341                 <&ethsys CLK_ETH_GP0_EN>,
342                 <&ethsys CLK_ETH_GP1_EN>,
343                 <&ethsys CLK_ETH_GP2_EN>,
344                 <&sgmiisys CLK_SGMII_TX250M_EN>,
345                 <&sgmiisys CLK_SGMII_RX250M_EN>,
346                 <&sgmiisys CLK_SGMII_CDR_REF>,
347                 <&sgmiisys CLK_SGMII_CDR_FB>,
348                 <&topckgen CLK_TOP_SGMIIPLL>,
349                 <&apmixedsys CLK_APMIXED_ETH2PLL>;
350        clock-names = "ethif", "esw", "gp0", "gp1", "gp2",
351                      "sgmii_tx250m", "sgmii_rx250m",
352                      "sgmii_cdr_ref", "sgmii_cdr_fb", "sgmii_ck",
353                      "eth2pll";
354        power-domains = <&scpsys MT7622_POWER_DOMAIN_ETHSYS>;
355        mediatek,ethsys = <&ethsys>;
356        mediatek,sgmiisys = <&sgmiisys>;
357        cci-control-port = <&cci_control2>;
358        mediatek,pcie-mirror = <&pcie_mirror>;
359        mediatek,hifsys = <&hifsys>;
360        dma-coherent;
361
362        #address-cells = <1>;
363        #size-cells = <0>;
364
365        mdio0: mdio-bus {
366          #address-cells = <1>;
367          #size-cells = <0>;
368
369          phy0: ethernet-phy@0 {
370            reg = <0>;
371          };
372
373          phy1: ethernet-phy@1 {
374            reg = <1>;
375          };
376        };
377
378        gmac0: mac@0 {
379          compatible = "mediatek,eth-mac";
380          phy-mode = "rgmii";
381          phy-handle = <&phy0>;
382          reg = <0>;
383        };
384
385        gmac1: mac@1 {
386          compatible = "mediatek,eth-mac";
387          phy-mode = "rgmii";
388          phy-handle = <&phy1>;
389          reg = <1>;
390        };
391      };
392    };
393
394  - |
395    #include <dt-bindings/interrupt-controller/arm-gic.h>
396    #include <dt-bindings/interrupt-controller/irq.h>
397    #include <dt-bindings/clock/mt7622-clk.h>
398
399    soc {
400      #address-cells = <2>;
401      #size-cells = <2>;
402
403      eth: ethernet@15100000 {
404        #define CLK_ETH_FE_EN               0
405        #define CLK_ETH_WOCPU1_EN           3
406        #define CLK_ETH_WOCPU0_EN           4
407        #define CLK_TOP_NETSYS_SEL          43
408        #define CLK_TOP_NETSYS_500M_SEL     44
409        #define CLK_TOP_NETSYS_2X_SEL       46
410        #define CLK_TOP_SGM_325M_SEL        47
411        #define CLK_APMIXED_NET2PLL         1
412        #define CLK_APMIXED_SGMPLL          3
413
414        compatible = "mediatek,mt7986-eth";
415        reg = <0 0x15100000 0 0x80000>;
416        interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>,
417                     <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>,
418                     <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>,
419                     <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>;
420        clocks = <&ethsys CLK_ETH_FE_EN>,
421                 <&ethsys CLK_ETH_GP2_EN>,
422                 <&ethsys CLK_ETH_GP1_EN>,
423                 <&ethsys CLK_ETH_WOCPU1_EN>,
424                 <&ethsys CLK_ETH_WOCPU0_EN>,
425                 <&sgmiisys0 CLK_SGMII_TX250M_EN>,
426                 <&sgmiisys0 CLK_SGMII_RX250M_EN>,
427                 <&sgmiisys0 CLK_SGMII_CDR_REF>,
428                 <&sgmiisys0 CLK_SGMII_CDR_FB>,
429                 <&sgmiisys1 CLK_SGMII_TX250M_EN>,
430                 <&sgmiisys1 CLK_SGMII_RX250M_EN>,
431                 <&sgmiisys1 CLK_SGMII_CDR_REF>,
432                 <&sgmiisys1 CLK_SGMII_CDR_FB>,
433                 <&topckgen CLK_TOP_NETSYS_SEL>,
434                 <&topckgen CLK_TOP_NETSYS_SEL>;
435        clock-names = "fe", "gp2", "gp1", "wocpu1", "wocpu0",
436                      "sgmii_tx250m", "sgmii_rx250m",
437                      "sgmii_cdr_ref", "sgmii_cdr_fb",
438                      "sgmii2_tx250m", "sgmii2_rx250m",
439                      "sgmii2_cdr_ref", "sgmii2_cdr_fb",
440                      "netsys0", "netsys1";
441        mediatek,ethsys = <&ethsys>;
442        mediatek,sgmiisys = <&sgmiisys0>, <&sgmiisys1>;
443        assigned-clocks = <&topckgen CLK_TOP_NETSYS_2X_SEL>,
444                          <&topckgen CLK_TOP_SGM_325M_SEL>;
445        assigned-clock-parents = <&apmixedsys CLK_APMIXED_NET2PLL>,
446                                 <&apmixedsys CLK_APMIXED_SGMPLL>;
447
448        #address-cells = <1>;
449        #size-cells = <0>;
450
451        mdio: mdio-bus {
452          #address-cells = <1>;
453          #size-cells = <0>;
454
455          phy5: ethernet-phy@0 {
456            compatible = "ethernet-phy-id67c9.de0a";
457            phy-mode = "2500base-x";
458            reset-gpios = <&pio 6 1>;
459            reset-deassert-us = <20000>;
460            reg = <5>;
461          };
462
463          phy6: ethernet-phy@1 {
464            compatible = "ethernet-phy-id67c9.de0a";
465            phy-mode = "2500base-x";
466            reg = <6>;
467          };
468        };
469
470        mac0: mac@0 {
471          compatible = "mediatek,eth-mac";
472          phy-mode = "2500base-x";
473          phy-handle = <&phy5>;
474          reg = <0>;
475        };
476
477        mac1: mac@1 {
478          compatible = "mediatek,eth-mac";
479          phy-mode = "2500base-x";
480          phy-handle = <&phy6>;
481          reg = <1>;
482        };
483      };
484    };
485